1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include "rvu_struct.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 20 /* PCI device IDs */ 21 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 22 23 /* Subsystem Device ID */ 24 #define PCI_SUBSYS_DEVID_96XX 0xB200 25 26 /* PCI BAR nos */ 27 #define PCI_AF_REG_BAR_NUM 0 28 #define PCI_PF_REG_BAR_NUM 2 29 #define PCI_MBOX_BAR_NUM 4 30 31 #define NAME_SIZE 32 32 #define MAX_NIX_BLKS 2 33 34 /* PF_FUNC */ 35 #define RVU_PFVF_PF_SHIFT 10 36 #define RVU_PFVF_PF_MASK 0x3F 37 #define RVU_PFVF_FUNC_SHIFT 0 38 #define RVU_PFVF_FUNC_MASK 0x3FF 39 40 #ifdef CONFIG_DEBUG_FS 41 struct dump_ctx { 42 int lf; 43 int id; 44 bool all; 45 }; 46 47 struct rvu_debugfs { 48 struct dentry *root; 49 struct dentry *cgx_root; 50 struct dentry *cgx; 51 struct dentry *lmac; 52 struct dentry *npa; 53 struct dentry *nix; 54 struct dentry *npc; 55 struct dump_ctx npa_aura_ctx; 56 struct dump_ctx npa_pool_ctx; 57 struct dump_ctx nix_cq_ctx; 58 struct dump_ctx nix_rq_ctx; 59 struct dump_ctx nix_sq_ctx; 60 int npa_qsize_id; 61 int nix_qsize_id; 62 }; 63 #endif 64 65 struct rvu_work { 66 struct work_struct work; 67 struct rvu *rvu; 68 int num_msgs; 69 int up_num_msgs; 70 }; 71 72 struct rsrc_bmap { 73 unsigned long *bmap; /* Pointer to resource bitmap */ 74 u16 max; /* Max resource id or count */ 75 }; 76 77 struct rvu_block { 78 struct rsrc_bmap lf; 79 struct admin_queue *aq; /* NIX/NPA AQ */ 80 u16 *fn_map; /* LF to pcifunc mapping */ 81 bool multislot; 82 bool implemented; 83 u8 addr; /* RVU_BLOCK_ADDR_E */ 84 u8 type; /* RVU_BLOCK_TYPE_E */ 85 u8 lfshift; 86 u64 lookup_reg; 87 u64 pf_lfcnt_reg; 88 u64 vf_lfcnt_reg; 89 u64 lfcfg_reg; 90 u64 msixcfg_reg; 91 u64 lfreset_reg; 92 unsigned char name[NAME_SIZE]; 93 }; 94 95 struct nix_mcast { 96 struct qmem *mce_ctx; 97 struct qmem *mcast_buf; 98 int replay_pkind; 99 int next_free_mce; 100 struct mutex mce_lock; /* Serialize MCE updates */ 101 }; 102 103 struct nix_mce_list { 104 struct hlist_head head; 105 int count; 106 int max; 107 }; 108 109 /* layer metadata to uniquely identify a packet header field */ 110 struct npc_layer_mdata { 111 u8 lid; 112 u8 ltype; 113 u8 hdr; 114 u8 key; 115 u8 len; 116 }; 117 118 /* Structure to represent a field present in the 119 * generated key. A key field may present anywhere and can 120 * be of any size in the generated key. Once this structure 121 * is populated for fields of interest then field's presence 122 * and location (if present) can be known. 123 */ 124 struct npc_key_field { 125 /* Masks where all set bits indicate position 126 * of a field in the key 127 */ 128 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 129 /* Number of words in the key a field spans. If a field is 130 * of 16 bytes and key offset is 4 then the field will use 131 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 132 * nr_kws will be 3(KW0, KW1 and KW2). 133 */ 134 int nr_kws; 135 /* used by packet header fields */ 136 struct npc_layer_mdata layer_mdata; 137 }; 138 139 struct npc_mcam { 140 struct rsrc_bmap counters; 141 struct mutex lock; /* MCAM entries and counters update lock */ 142 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 143 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 144 u16 bmap_entries; /* Number of unreserved MCAM entries */ 145 u16 bmap_fcnt; /* MCAM entries free count */ 146 u16 *entry2pfvf_map; 147 u16 *entry2cntr_map; 148 u16 *cntr2pfvf_map; 149 u16 *cntr_refcnt; 150 u16 *entry2target_pffunc; 151 u8 keysize; /* MCAM keysize 112/224/448 bits */ 152 u8 banks; /* Number of MCAM banks */ 153 u8 banks_per_entry;/* Number of keywords in key */ 154 u16 banksize; /* Number of MCAM entries in each bank */ 155 u16 total_entries; /* Total number of MCAM entries */ 156 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 157 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 158 u16 lprio_count; 159 u16 lprio_start; 160 u16 hprio_count; 161 u16 hprio_end; 162 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 163 /* fields present in the generated key */ 164 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 165 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 166 u64 tx_features; 167 u64 rx_features; 168 struct list_head mcam_rules; 169 }; 170 171 /* Structure for per RVU func info ie PF/VF */ 172 struct rvu_pfvf { 173 bool npalf; /* Only one NPALF per RVU_FUNC */ 174 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 175 u16 sso; 176 u16 ssow; 177 u16 cptlfs; 178 u16 timlfs; 179 u16 cpt1_lfs; 180 u8 cgx_lmac; 181 182 /* Block LF's MSIX vector info */ 183 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 184 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 185 u16 *msix_lfmap; /* Vector to block LF mapping */ 186 187 /* NPA contexts */ 188 struct qmem *aura_ctx; 189 struct qmem *pool_ctx; 190 struct qmem *npa_qints_ctx; 191 unsigned long *aura_bmap; 192 unsigned long *pool_bmap; 193 194 /* NIX contexts */ 195 struct qmem *rq_ctx; 196 struct qmem *sq_ctx; 197 struct qmem *cq_ctx; 198 struct qmem *rss_ctx; 199 struct qmem *cq_ints_ctx; 200 struct qmem *nix_qints_ctx; 201 unsigned long *sq_bmap; 202 unsigned long *rq_bmap; 203 unsigned long *cq_bmap; 204 205 u16 rx_chan_base; 206 u16 tx_chan_base; 207 u8 rx_chan_cnt; /* total number of RX channels */ 208 u8 tx_chan_cnt; /* total number of TX channels */ 209 u16 maxlen; 210 u16 minlen; 211 212 u8 pf_set_vf_cfg; 213 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 214 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 215 216 /* Broadcast pkt replication info */ 217 u16 bcast_mce_idx; 218 struct nix_mce_list bcast_mce_list; 219 220 struct rvu_npc_mcam_rule *def_ucast_rule; 221 222 bool cgx_in_use; /* this PF/VF using CGX? */ 223 int cgx_users; /* number of cgx users - used only by PFs */ 224 225 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 226 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 227 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 228 }; 229 230 struct nix_txsch { 231 struct rsrc_bmap schq; 232 u8 lvl; 233 #define NIX_TXSCHQ_FREE BIT_ULL(1) 234 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 235 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 236 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 237 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 238 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 239 u32 *pfvf_map; 240 }; 241 242 struct nix_mark_format { 243 u8 total; 244 u8 in_use; 245 u32 *cfg; 246 }; 247 248 struct npc_pkind { 249 struct rsrc_bmap rsrc; 250 u32 *pfchan_map; 251 }; 252 253 struct nix_flowkey { 254 #define NIX_FLOW_KEY_ALG_MAX 32 255 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 256 int in_use; 257 }; 258 259 struct nix_lso { 260 u8 total; 261 u8 in_use; 262 }; 263 264 struct nix_txvlan { 265 #define NIX_TX_VTAG_DEF_MAX 0x400 266 struct rsrc_bmap rsrc; 267 u16 *entry2pfvf_map; 268 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 269 }; 270 271 struct nix_hw { 272 int blkaddr; 273 struct rvu *rvu; 274 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 275 struct nix_mcast mcast; 276 struct nix_flowkey flowkey; 277 struct nix_mark_format mark_format; 278 struct nix_lso lso; 279 struct nix_txvlan txvlan; 280 }; 281 282 /* RVU block's capabilities or functionality, 283 * which vary by silicon version/skew. 284 */ 285 struct hw_cap { 286 /* Transmit side supported functionality */ 287 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 288 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 289 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 290 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 291 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 292 bool nix_shaping; /* Is shaping and coloring supported */ 293 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 294 bool nix_rx_multicast; /* Rx packet replication support */ 295 }; 296 297 struct rvu_hwinfo { 298 u8 total_pfs; /* MAX RVU PFs HW supports */ 299 u16 total_vfs; /* Max RVU VFs HW supports */ 300 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 301 u8 cgx; 302 u8 lmac_per_cgx; 303 u8 cgx_links; 304 u8 lbk_links; 305 u8 sdp_links; 306 u8 npc_kpus; /* No of parser units */ 307 u8 npc_pkinds; /* No of port kinds */ 308 u8 npc_intfs; /* No of interfaces */ 309 u8 npc_kpu_entries; /* No of KPU entries */ 310 u16 npc_counters; /* No of match stats counters */ 311 bool npc_ext_set; /* Extended register set */ 312 313 struct hw_cap cap; 314 struct rvu_block block[BLK_COUNT]; /* Block info */ 315 struct nix_hw *nix; 316 struct rvu *rvu; 317 struct npc_pkind pkind; 318 struct npc_mcam mcam; 319 }; 320 321 struct mbox_wq_info { 322 struct otx2_mbox mbox; 323 struct rvu_work *mbox_wrk; 324 325 struct otx2_mbox mbox_up; 326 struct rvu_work *mbox_wrk_up; 327 328 struct workqueue_struct *mbox_wq; 329 }; 330 331 struct rvu_fwdata { 332 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 333 #define RVU_FWDATA_VERSION 0x0001 334 u32 header_magic; 335 u32 version; /* version id */ 336 337 /* MAC address */ 338 #define PF_MACNUM_MAX 32 339 #define VF_MACNUM_MAX 256 340 u64 pf_macs[PF_MACNUM_MAX]; 341 u64 vf_macs[VF_MACNUM_MAX]; 342 u64 sclk; 343 u64 rclk; 344 u64 mcam_addr; 345 u64 mcam_sz; 346 u64 msixtr_base; 347 #define FWDATA_RESERVED_MEM 1023 348 u64 reserved[FWDATA_RESERVED_MEM]; 349 }; 350 351 struct ptp; 352 353 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 354 * source where it came from. 355 */ 356 struct npc_kpu_profile_adapter { 357 const char *name; 358 u64 version; 359 const struct npc_lt_def_cfg *lt_def; 360 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 361 const struct npc_kpu_profile *kpu; /* array[kpus] */ 362 struct npc_mcam_kex *mkex; 363 size_t pkinds; 364 size_t kpus; 365 }; 366 367 struct rvu { 368 void __iomem *afreg_base; 369 void __iomem *pfreg_base; 370 struct pci_dev *pdev; 371 struct device *dev; 372 struct rvu_hwinfo *hw; 373 struct rvu_pfvf *pf; 374 struct rvu_pfvf *hwvf; 375 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 376 int vfs; /* Number of VFs attached to RVU */ 377 int nix_blkaddr[MAX_NIX_BLKS]; 378 379 /* Mbox */ 380 struct mbox_wq_info afpf_wq_info; 381 struct mbox_wq_info afvf_wq_info; 382 383 /* PF FLR */ 384 struct rvu_work *flr_wrk; 385 struct workqueue_struct *flr_wq; 386 struct mutex flr_lock; /* Serialize FLRs */ 387 388 /* MSI-X */ 389 u16 num_vec; 390 char *irq_name; 391 bool *irq_allocated; 392 dma_addr_t msix_base_iova; 393 u64 msixtr_base_phy; /* Register reset value */ 394 395 /* CGX */ 396 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 397 u8 cgx_mapped_pfs; 398 u8 cgx_cnt_max; /* CGX port count max */ 399 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 400 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 401 * every cgx lmac port 402 */ 403 unsigned long pf_notify_bmap; /* Flags for PF notification */ 404 void **cgx_idmap; /* cgx id to cgx data map table */ 405 struct work_struct cgx_evh_work; 406 struct workqueue_struct *cgx_evh_wq; 407 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 408 struct list_head cgx_evq_head; /* cgx event queue head */ 409 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 410 411 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 412 413 /* Firmware data */ 414 struct rvu_fwdata *fwdata; 415 416 /* NPC KPU data */ 417 struct npc_kpu_profile_adapter kpu; 418 419 struct ptp *ptp; 420 421 #ifdef CONFIG_DEBUG_FS 422 struct rvu_debugfs rvu_dbg; 423 #endif 424 }; 425 426 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 427 { 428 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 429 } 430 431 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 432 { 433 return readq(rvu->afreg_base + ((block << 28) | offset)); 434 } 435 436 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 437 { 438 writeq(val, rvu->pfreg_base + offset); 439 } 440 441 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 442 { 443 return readq(rvu->pfreg_base + offset); 444 } 445 446 /* Silicon revisions */ 447 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 448 { 449 struct pci_dev *pdev = rvu->pdev; 450 451 return (pdev->revision == 0x00) && 452 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 453 } 454 455 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 456 { 457 struct pci_dev *pdev = rvu->pdev; 458 459 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 460 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 461 } 462 463 /* Function Prototypes 464 * RVU 465 */ 466 static inline int is_afvf(u16 pcifunc) 467 { 468 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 469 } 470 471 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 472 { 473 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 474 (rvu->fwdata->version == RVU_FWDATA_VERSION); 475 } 476 477 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 478 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 479 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 480 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 481 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 482 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 483 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 484 int rvu_get_pf(u16 pcifunc); 485 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 486 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 487 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 488 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 489 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 490 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 491 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 492 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 493 int rvu_get_num_lbk_chans(void); 494 495 /* RVU HW reg validation */ 496 enum regmap_block { 497 TXSCHQ_HWREGMAP = 0, 498 MAX_HWREGMAP, 499 }; 500 501 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 502 503 /* NPA/NIX AQ APIs */ 504 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 505 int qsize, int inst_size, int res_size); 506 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 507 508 /* CGX APIs */ 509 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 510 { 511 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 512 } 513 514 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 515 { 516 *cgx_id = (map >> 4) & 0xF; 517 *lmac_id = (map & 0xF); 518 } 519 520 #define M(_name, _id, fn_name, req, rsp) \ 521 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 522 MBOX_MESSAGES 523 #undef M 524 525 int rvu_cgx_init(struct rvu *rvu); 526 int rvu_cgx_exit(struct rvu *rvu); 527 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 528 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 529 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 530 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 531 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 532 int rxtxflag, u64 *stat); 533 /* NPA APIs */ 534 int rvu_npa_init(struct rvu *rvu); 535 void rvu_npa_freemem(struct rvu *rvu); 536 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 537 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 538 struct npa_aq_enq_rsp *rsp); 539 540 /* NIX APIs */ 541 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 542 int rvu_nix_init(struct rvu *rvu); 543 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 544 int blkaddr, u32 cfg); 545 void rvu_nix_freemem(struct rvu *rvu); 546 int rvu_get_nixlf_count(struct rvu *rvu); 547 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 548 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 549 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); 550 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 551 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 552 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 553 554 /* NPC APIs */ 555 int rvu_npc_init(struct rvu *rvu); 556 void rvu_npc_freemem(struct rvu *rvu); 557 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 558 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 559 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 560 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 561 int nixlf, u64 chan, u8 *mac_addr); 562 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 563 int nixlf, u64 chan, bool allmulti); 564 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 565 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 566 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 567 int nixlf, u64 chan); 568 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable); 569 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 570 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 571 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 572 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 573 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 574 int group, int alg_idx, int mcam_index); 575 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 576 int blkaddr, int *alloc_cnt, 577 int *enable_cnt); 578 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 579 int blkaddr, int *alloc_cnt, 580 int *enable_cnt); 581 bool is_npc_intf_tx(u8 intf); 582 bool is_npc_intf_rx(u8 intf); 583 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 584 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 585 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel); 586 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 587 const char *npc_get_field_name(u8 hdr); 588 bool rvu_npc_write_default_rule(struct rvu *rvu, int blkaddr, int nixlf, 589 u16 pcifunc, u8 intf, struct mcam_entry *entry, 590 int *entry_index); 591 int npc_get_bank(struct npc_mcam *mcam, int index); 592 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 593 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 594 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 595 int blkaddr, int index, bool enable); 596 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 597 int blkaddr, u16 src, struct mcam_entry *entry, 598 u8 *intf, u8 *ena); 599 600 #ifdef CONFIG_DEBUG_FS 601 void rvu_dbg_init(struct rvu *rvu); 602 void rvu_dbg_exit(struct rvu *rvu); 603 #else 604 static inline void rvu_dbg_init(struct rvu *rvu) {} 605 static inline void rvu_dbg_exit(struct rvu *rvu) {} 606 #endif 607 #endif /* RVU_H */ 608