1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 #include "ptp.h" 21 22 /* PCI device IDs */ 23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 25 26 /* Subsystem Device ID */ 27 #define PCI_SUBSYS_DEVID_98XX 0xB100 28 #define PCI_SUBSYS_DEVID_96XX 0xB200 29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 33 34 /* PCI BAR nos */ 35 #define PCI_AF_REG_BAR_NUM 0 36 #define PCI_PF_REG_BAR_NUM 2 37 #define PCI_MBOX_BAR_NUM 4 38 39 #define NAME_SIZE 32 40 #define MAX_NIX_BLKS 2 41 #define MAX_CPT_BLKS 2 42 43 /* PF_FUNC */ 44 #define RVU_PFVF_PF_SHIFT 10 45 #define RVU_PFVF_PF_MASK 0x3F 46 #define RVU_PFVF_FUNC_SHIFT 0 47 #define RVU_PFVF_FUNC_MASK 0x3FF 48 49 #ifdef CONFIG_DEBUG_FS 50 struct dump_ctx { 51 int lf; 52 int id; 53 bool all; 54 }; 55 56 struct cpt_ctx { 57 int blkaddr; 58 struct rvu *rvu; 59 }; 60 61 struct rvu_debugfs { 62 struct dentry *root; 63 struct dentry *cgx_root; 64 struct dentry *cgx; 65 struct dentry *lmac; 66 struct dentry *npa; 67 struct dentry *nix; 68 struct dentry *npc; 69 struct dentry *cpt; 70 struct dentry *mcs_root; 71 struct dentry *mcs; 72 struct dentry *mcs_rx; 73 struct dentry *mcs_tx; 74 struct dump_ctx npa_aura_ctx; 75 struct dump_ctx npa_pool_ctx; 76 struct dump_ctx nix_cq_ctx; 77 struct dump_ctx nix_rq_ctx; 78 struct dump_ctx nix_sq_ctx; 79 struct dump_ctx nix_tm_ctx; 80 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 81 int npa_qsize_id; 82 int nix_qsize_id; 83 }; 84 #endif 85 86 struct rvu_work { 87 struct work_struct work; 88 struct rvu *rvu; 89 int num_msgs; 90 int up_num_msgs; 91 }; 92 93 struct rsrc_bmap { 94 unsigned long *bmap; /* Pointer to resource bitmap */ 95 u16 max; /* Max resource id or count */ 96 }; 97 98 struct rvu_block { 99 struct rsrc_bmap lf; 100 struct admin_queue *aq; /* NIX/NPA AQ */ 101 u16 *fn_map; /* LF to pcifunc mapping */ 102 bool multislot; 103 bool implemented; 104 u8 addr; /* RVU_BLOCK_ADDR_E */ 105 u8 type; /* RVU_BLOCK_TYPE_E */ 106 u8 lfshift; 107 u64 lookup_reg; 108 u64 pf_lfcnt_reg; 109 u64 vf_lfcnt_reg; 110 u64 lfcfg_reg; 111 u64 msixcfg_reg; 112 u64 lfreset_reg; 113 unsigned char name[NAME_SIZE]; 114 struct rvu *rvu; 115 u64 cpt_flt_eng_map[3]; 116 u64 cpt_rcvrd_eng_map[3]; 117 }; 118 119 struct nix_mcast { 120 struct qmem *mce_ctx; 121 struct qmem *mcast_buf; 122 int replay_pkind; 123 struct rsrc_bmap mce_counter[2]; 124 /* Counters for both ingress and egress mcast lists */ 125 struct mutex mce_lock; /* Serialize MCE updates */ 126 }; 127 128 struct nix_mce_list { 129 struct hlist_head head; 130 int count; 131 int max; 132 }; 133 134 struct nix_mcast_grp_elem { 135 struct nix_mce_list mcast_mce_list; 136 u32 mcast_grp_idx; 137 u32 pcifunc; 138 int mcam_index; 139 int mce_start_index; 140 struct list_head list; 141 u8 dir; 142 }; 143 144 struct nix_mcast_grp { 145 struct list_head mcast_grp_head; 146 int count; 147 int next_grp_index; 148 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 149 }; 150 151 /* layer metadata to uniquely identify a packet header field */ 152 struct npc_layer_mdata { 153 u8 lid; 154 u8 ltype; 155 u8 hdr; 156 u8 key; 157 u8 len; 158 }; 159 160 /* Structure to represent a field present in the 161 * generated key. A key field may present anywhere and can 162 * be of any size in the generated key. Once this structure 163 * is populated for fields of interest then field's presence 164 * and location (if present) can be known. 165 */ 166 struct npc_key_field { 167 /* Masks where all set bits indicate position 168 * of a field in the key 169 */ 170 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 171 /* Number of words in the key a field spans. If a field is 172 * of 16 bytes and key offset is 4 then the field will use 173 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 174 * nr_kws will be 3(KW0, KW1 and KW2). 175 */ 176 int nr_kws; 177 /* used by packet header fields */ 178 struct npc_layer_mdata layer_mdata; 179 }; 180 181 struct npc_mcam { 182 struct rsrc_bmap counters; 183 struct mutex lock; /* MCAM entries and counters update lock */ 184 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 185 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 186 u16 bmap_entries; /* Number of unreserved MCAM entries */ 187 u16 bmap_fcnt; /* MCAM entries free count */ 188 u16 *entry2pfvf_map; 189 u16 *entry2cntr_map; 190 u16 *cntr2pfvf_map; 191 u16 *cntr_refcnt; 192 u16 *entry2target_pffunc; 193 u8 keysize; /* MCAM keysize 112/224/448 bits */ 194 u8 banks; /* Number of MCAM banks */ 195 u8 banks_per_entry;/* Number of keywords in key */ 196 u16 banksize; /* Number of MCAM entries in each bank */ 197 u16 total_entries; /* Total number of MCAM entries */ 198 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 199 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 200 u16 lprio_count; 201 u16 lprio_start; 202 u16 hprio_count; 203 u16 hprio_end; 204 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 205 /* fields present in the generated key */ 206 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 207 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 208 u64 tx_features; 209 u64 rx_features; 210 struct list_head mcam_rules; 211 }; 212 213 /* Structure for per RVU func info ie PF/VF */ 214 struct rvu_pfvf { 215 bool npalf; /* Only one NPALF per RVU_FUNC */ 216 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 217 u16 sso; 218 u16 ssow; 219 u16 cptlfs; 220 u16 timlfs; 221 u16 cpt1_lfs; 222 u8 cgx_lmac; 223 224 /* Block LF's MSIX vector info */ 225 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 226 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 227 u16 *msix_lfmap; /* Vector to block LF mapping */ 228 229 /* NPA contexts */ 230 struct qmem *aura_ctx; 231 struct qmem *pool_ctx; 232 struct qmem *npa_qints_ctx; 233 unsigned long *aura_bmap; 234 unsigned long *pool_bmap; 235 236 /* NIX contexts */ 237 struct qmem *rq_ctx; 238 struct qmem *sq_ctx; 239 struct qmem *cq_ctx; 240 struct qmem *rss_ctx; 241 struct qmem *cq_ints_ctx; 242 struct qmem *nix_qints_ctx; 243 unsigned long *sq_bmap; 244 unsigned long *rq_bmap; 245 unsigned long *cq_bmap; 246 247 u16 rx_chan_base; 248 u16 tx_chan_base; 249 u8 rx_chan_cnt; /* total number of RX channels */ 250 u8 tx_chan_cnt; /* total number of TX channels */ 251 u16 maxlen; 252 u16 minlen; 253 254 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 255 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 256 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 257 258 /* Broadcast/Multicast/Promisc pkt replication info */ 259 u16 bcast_mce_idx; 260 u16 mcast_mce_idx; 261 u16 promisc_mce_idx; 262 struct nix_mce_list bcast_mce_list; 263 struct nix_mce_list mcast_mce_list; 264 struct nix_mce_list promisc_mce_list; 265 bool use_mce_list; 266 267 struct rvu_npc_mcam_rule *def_ucast_rule; 268 269 bool cgx_in_use; /* this PF/VF using CGX? */ 270 int cgx_users; /* number of cgx users - used only by PFs */ 271 272 int intf_mode; 273 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 274 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 275 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 276 u8 lbkid; /* NIX0/1 lbk link ID */ 277 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 278 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 279 unsigned long flags; 280 struct sdp_node_info *sdp_info; 281 }; 282 283 enum rvu_pfvf_flags { 284 NIXLF_INITIALIZED = 0, 285 PF_SET_VF_MAC, 286 PF_SET_VF_CFG, 287 PF_SET_VF_TRUSTED, 288 }; 289 290 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 291 292 struct nix_bp { 293 struct rsrc_bmap bpids; /* free bpids bitmap */ 294 u16 cgx_bpid_cnt; 295 u16 sdp_bpid_cnt; 296 u16 free_pool_base; 297 u16 *fn_map; /* pcifunc mapping */ 298 u8 *intf_map; /* interface type map */ 299 u8 *ref_cnt; 300 }; 301 302 struct nix_txsch { 303 struct rsrc_bmap schq; 304 u8 lvl; 305 #define NIX_TXSCHQ_FREE BIT_ULL(1) 306 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 307 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 308 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 309 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 310 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 311 u32 *pfvf_map; 312 }; 313 314 struct nix_mark_format { 315 u8 total; 316 u8 in_use; 317 u32 *cfg; 318 }; 319 320 /* smq(flush) to tl1 cir/pir info */ 321 struct nix_smq_tree_ctx { 322 u16 schq; 323 u64 cir_off; 324 u64 cir_val; 325 u64 pir_off; 326 u64 pir_val; 327 }; 328 329 /* smq flush context */ 330 struct nix_smq_flush_ctx { 331 int smq; 332 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 333 }; 334 335 struct npc_pkind { 336 struct rsrc_bmap rsrc; 337 u32 *pfchan_map; 338 }; 339 340 struct nix_flowkey { 341 #define NIX_FLOW_KEY_ALG_MAX 32 342 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 343 int in_use; 344 }; 345 346 struct nix_lso { 347 u8 total; 348 u8 in_use; 349 }; 350 351 struct nix_txvlan { 352 #define NIX_TX_VTAG_DEF_MAX 0x400 353 struct rsrc_bmap rsrc; 354 u16 *entry2pfvf_map; 355 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 356 }; 357 358 struct nix_ipolicer { 359 struct rsrc_bmap band_prof; 360 u16 *pfvf_map; 361 u16 *match_id; 362 u16 *ref_count; 363 }; 364 365 struct nix_hw { 366 int blkaddr; 367 struct rvu *rvu; 368 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 369 struct nix_mcast mcast; 370 struct nix_mcast_grp mcast_grp; 371 struct nix_flowkey flowkey; 372 struct nix_mark_format mark_format; 373 struct nix_lso lso; 374 struct nix_txvlan txvlan; 375 struct nix_ipolicer *ipolicer; 376 struct nix_bp bp; 377 u64 *tx_credits; 378 u8 cc_mcs_cnt; 379 }; 380 381 /* RVU block's capabilities or functionality, 382 * which vary by silicon version/skew. 383 */ 384 struct hw_cap { 385 /* Transmit side supported functionality */ 386 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 387 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 388 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 389 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 390 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 391 bool nix_shaping; /* Is shaping and coloring supported */ 392 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 393 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 394 bool nix_rx_multicast; /* Rx packet replication support */ 395 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 396 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 397 bool programmable_chans; /* Channels programmable ? */ 398 bool ipolicer; 399 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 400 bool npc_hash_extract; /* Hash extract enabled ? */ 401 bool npc_exact_match_enabled; /* Exact match supported ? */ 402 bool cpt_rxc; /* Is CPT-RXC supported */ 403 }; 404 405 struct rvu_hwinfo { 406 u8 total_pfs; /* MAX RVU PFs HW supports */ 407 u16 total_vfs; /* Max RVU VFs HW supports */ 408 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 409 u8 cgx; 410 u8 lmac_per_cgx; 411 u16 cgx_chan_base; /* CGX base channel number */ 412 u16 lbk_chan_base; /* LBK base channel number */ 413 u16 sdp_chan_base; /* SDP base channel number */ 414 u16 cpt_chan_base; /* CPT base channel number */ 415 u8 cgx_links; 416 u8 lbk_links; 417 u8 sdp_links; 418 u8 cpt_links; /* Number of CPT links */ 419 u8 npc_kpus; /* No of parser units */ 420 u8 npc_pkinds; /* No of port kinds */ 421 u8 npc_intfs; /* No of interfaces */ 422 u8 npc_kpu_entries; /* No of KPU entries */ 423 u16 npc_counters; /* No of match stats counters */ 424 u32 lbk_bufsize; /* FIFO size supported by LBK */ 425 bool npc_ext_set; /* Extended register set */ 426 u64 npc_stat_ena; /* Match stats enable bit */ 427 428 struct hw_cap cap; 429 struct rvu_block block[BLK_COUNT]; /* Block info */ 430 struct nix_hw *nix; 431 struct rvu *rvu; 432 struct npc_pkind pkind; 433 struct npc_mcam mcam; 434 struct npc_exact_table *table; 435 }; 436 437 struct mbox_wq_info { 438 struct otx2_mbox mbox; 439 struct rvu_work *mbox_wrk; 440 441 struct otx2_mbox mbox_up; 442 struct rvu_work *mbox_wrk_up; 443 444 struct workqueue_struct *mbox_wq; 445 }; 446 447 struct channel_fwdata { 448 struct sdp_node_info info; 449 u8 valid; 450 #define RVU_CHANL_INFO_RESERVED 379 451 u8 reserved[RVU_CHANL_INFO_RESERVED]; 452 }; 453 454 struct rvu_fwdata { 455 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 456 #define RVU_FWDATA_VERSION 0x0001 457 u32 header_magic; 458 u32 version; /* version id */ 459 460 /* MAC address */ 461 #define PF_MACNUM_MAX 32 462 #define VF_MACNUM_MAX 256 463 u64 pf_macs[PF_MACNUM_MAX]; 464 u64 vf_macs[VF_MACNUM_MAX]; 465 u64 sclk; 466 u64 rclk; 467 u64 mcam_addr; 468 u64 mcam_sz; 469 u64 msixtr_base; 470 u32 ptp_ext_clk_rate; 471 u32 ptp_ext_tstamp; 472 struct channel_fwdata channel_data; 473 #define FWDATA_RESERVED_MEM 958 474 u64 reserved[FWDATA_RESERVED_MEM]; 475 #define CGX_MAX 9 476 #define CGX_LMACS_MAX 4 477 #define CGX_LMACS_USX 8 478 #define FWDATA_CGX_LMAC_OFFSET 10536 479 union { 480 struct cgx_lmac_fwdata_s 481 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 482 struct cgx_lmac_fwdata_s 483 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 484 }; 485 /* Do not add new fields below this line */ 486 }; 487 488 struct ptp; 489 490 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 491 * source where it came from. 492 */ 493 struct npc_kpu_profile_adapter { 494 const char *name; 495 u64 version; 496 const struct npc_lt_def_cfg *lt_def; 497 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 498 const struct npc_kpu_profile *kpu; /* array[kpus] */ 499 struct npc_mcam_kex *mkex; 500 struct npc_mcam_kex_hash *mkex_hash; 501 bool custom; 502 size_t pkinds; 503 size_t kpus; 504 }; 505 506 #define RVU_SWITCH_LBK_CHAN 63 507 508 struct rvu_switch { 509 struct mutex switch_lock; /* Serialize flow installation */ 510 u32 used_entries; 511 u16 *entry2pcifunc; 512 u16 mode; 513 u16 start_entry; 514 }; 515 516 struct rvu { 517 void __iomem *afreg_base; 518 void __iomem *pfreg_base; 519 struct pci_dev *pdev; 520 struct device *dev; 521 struct rvu_hwinfo *hw; 522 struct rvu_pfvf *pf; 523 struct rvu_pfvf *hwvf; 524 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 525 struct mutex alias_lock; /* Serialize bar2 alias access */ 526 int vfs; /* Number of VFs attached to RVU */ 527 u16 vf_devid; /* VF devices id */ 528 int nix_blkaddr[MAX_NIX_BLKS]; 529 530 /* Mbox */ 531 struct mbox_wq_info afpf_wq_info; 532 struct mbox_wq_info afvf_wq_info; 533 534 /* PF FLR */ 535 struct rvu_work *flr_wrk; 536 struct workqueue_struct *flr_wq; 537 struct mutex flr_lock; /* Serialize FLRs */ 538 539 /* MSI-X */ 540 u16 num_vec; 541 char *irq_name; 542 bool *irq_allocated; 543 dma_addr_t msix_base_iova; 544 u64 msixtr_base_phy; /* Register reset value */ 545 546 /* CGX */ 547 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 548 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 549 u8 cgx_mapped_pfs; 550 u8 cgx_cnt_max; /* CGX port count max */ 551 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 552 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 553 * every cgx lmac port 554 */ 555 unsigned long pf_notify_bmap; /* Flags for PF notification */ 556 void **cgx_idmap; /* cgx id to cgx data map table */ 557 struct work_struct cgx_evh_work; 558 struct workqueue_struct *cgx_evh_wq; 559 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 560 struct list_head cgx_evq_head; /* cgx event queue head */ 561 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 562 563 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 564 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 565 566 /* Firmware data */ 567 struct rvu_fwdata *fwdata; 568 void *kpu_fwdata; 569 size_t kpu_fwdata_sz; 570 void __iomem *kpu_prfl_addr; 571 572 /* NPC KPU data */ 573 struct npc_kpu_profile_adapter kpu; 574 575 struct ptp *ptp; 576 577 int mcs_blk_cnt; 578 int cpt_pf_num; 579 580 #ifdef CONFIG_DEBUG_FS 581 struct rvu_debugfs rvu_dbg; 582 #endif 583 struct rvu_devlink *rvu_dl; 584 585 /* RVU switch implementation over NPC with DMAC rules */ 586 struct rvu_switch rswitch; 587 588 struct work_struct mcs_intr_work; 589 struct workqueue_struct *mcs_intr_wq; 590 struct list_head mcs_intrq_head; 591 /* mcs interrupt queue lock */ 592 spinlock_t mcs_intrq_lock; 593 /* CPT interrupt lock */ 594 spinlock_t cpt_intr_lock; 595 596 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 597 }; 598 599 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 600 { 601 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 602 } 603 604 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 605 { 606 return readq(rvu->afreg_base + ((block << 28) | offset)); 607 } 608 609 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 610 { 611 writeq(val, rvu->pfreg_base + offset); 612 } 613 614 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 615 { 616 return readq(rvu->pfreg_base + offset); 617 } 618 619 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 620 { 621 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 622 * write operation. 623 */ 624 rvu_write64(rvu, block, offset, val); 625 rvu_read64(rvu, block, offset); 626 /* Barrier to ensure read completes before accessing LF registers */ 627 mb(); 628 } 629 630 /* Silicon revisions */ 631 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 632 { 633 struct pci_dev *pdev = rvu->pdev; 634 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 635 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 636 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 637 (pdev->revision == 0x14)); 638 } 639 640 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 641 { 642 struct pci_dev *pdev = rvu->pdev; 643 644 return (pdev->revision == 0x00); 645 } 646 647 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 648 { 649 struct pci_dev *pdev = rvu->pdev; 650 651 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 652 } 653 654 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 655 { 656 struct pci_dev *pdev = rvu->pdev; 657 658 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 659 } 660 661 /* REVID for PCIe devices. 662 * Bits 0..1: minor pass, bit 3..2: major pass 663 * bits 7..4: midr id 664 */ 665 #define PCI_REVISION_ID_96XX 0x00 666 #define PCI_REVISION_ID_95XX 0x10 667 #define PCI_REVISION_ID_95XXN 0x20 668 #define PCI_REVISION_ID_98XX 0x30 669 #define PCI_REVISION_ID_95XXMM 0x40 670 #define PCI_REVISION_ID_95XXO 0xE0 671 672 static inline bool is_rvu_otx2(struct rvu *rvu) 673 { 674 struct pci_dev *pdev = rvu->pdev; 675 676 u8 midr = pdev->revision & 0xF0; 677 678 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 679 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 680 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 681 } 682 683 static inline bool is_cnf10ka_a0(struct rvu *rvu) 684 { 685 struct pci_dev *pdev = rvu->pdev; 686 687 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 688 (pdev->revision & 0x0F) == 0x0) 689 return true; 690 return false; 691 } 692 693 static inline bool is_cn10ka_a0(struct rvu *rvu) 694 { 695 struct pci_dev *pdev = rvu->pdev; 696 697 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 698 (pdev->revision & 0x0F) == 0x0) 699 return true; 700 return false; 701 } 702 703 static inline bool is_cn10ka_a1(struct rvu *rvu) 704 { 705 struct pci_dev *pdev = rvu->pdev; 706 707 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 708 (pdev->revision & 0x0F) == 0x1) 709 return true; 710 return false; 711 } 712 713 static inline bool is_cn10kb(struct rvu *rvu) 714 { 715 struct pci_dev *pdev = rvu->pdev; 716 717 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) 718 return true; 719 return false; 720 } 721 722 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 723 { 724 u64 npc_const3; 725 726 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 727 if (!(npc_const3 & BIT_ULL(62))) 728 return false; 729 730 return true; 731 } 732 733 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 734 u8 lmacid, u8 chan) 735 { 736 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 737 u16 cgx_chans = nix_const & 0xFFULL; 738 struct rvu_hwinfo *hw = rvu->hw; 739 740 if (!hw->cap.programmable_chans) 741 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 742 743 return rvu->hw->cgx_chan_base + 744 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 745 } 746 747 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 748 u8 chan) 749 { 750 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 751 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 752 struct rvu_hwinfo *hw = rvu->hw; 753 754 if (!hw->cap.programmable_chans) 755 return NIX_CHAN_LBK_CHX(lbkid, chan); 756 757 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 758 } 759 760 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 761 { 762 struct rvu_hwinfo *hw = rvu->hw; 763 764 if (!hw->cap.programmable_chans) 765 return NIX_CHAN_SDP_CHX(chan); 766 767 return hw->sdp_chan_base + chan; 768 } 769 770 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 771 { 772 return rvu->hw->cpt_chan_base + chan; 773 } 774 775 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 776 { 777 struct pci_dev *pdev = rvu->pdev; 778 779 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 780 return true; 781 782 return false; 783 } 784 785 /* Function Prototypes 786 * RVU 787 */ 788 #define RVU_LBK_VF_DEVID 0xA0F8 789 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 790 { 791 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 792 (rvu->vf_devid == RVU_LBK_VF_DEVID)); 793 } 794 795 static inline bool is_vf(u16 pcifunc) 796 { 797 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 798 } 799 800 /* check if PF_FUNC is AF */ 801 static inline bool is_pffunc_af(u16 pcifunc) 802 { 803 return !pcifunc; 804 } 805 806 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 807 { 808 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 809 (rvu->fwdata->version == RVU_FWDATA_VERSION); 810 } 811 812 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 813 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 814 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 815 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 816 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 817 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 818 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 819 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 820 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 821 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 822 int rvu_get_pf(u16 pcifunc); 823 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 824 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 825 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 826 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 827 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 828 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 829 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 830 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 831 int rvu_get_num_lbk_chans(void); 832 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 833 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 834 u16 global_slot, u16 *slot_in_block); 835 836 /* RVU HW reg validation */ 837 enum regmap_block { 838 TXSCHQ_HWREGMAP = 0, 839 MAX_HWREGMAP, 840 }; 841 842 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 843 844 /* NPA/NIX AQ APIs */ 845 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 846 int qsize, int inst_size, int res_size); 847 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 848 849 /* SDP APIs */ 850 int rvu_sdp_init(struct rvu *rvu); 851 bool is_sdp_pfvf(u16 pcifunc); 852 bool is_sdp_pf(u16 pcifunc); 853 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 854 855 /* CGX APIs */ 856 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 857 { 858 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 859 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 860 } 861 862 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 863 { 864 *cgx_id = (map >> 4) & 0xF; 865 *lmac_id = (map & 0xF); 866 } 867 868 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 869 { 870 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 871 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 872 } 873 874 #define M(_name, _id, fn_name, req, rsp) \ 875 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 876 MBOX_MESSAGES 877 #undef M 878 879 int rvu_cgx_init(struct rvu *rvu); 880 int rvu_cgx_exit(struct rvu *rvu); 881 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 882 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 883 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 884 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 885 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 886 int rxtxflag, u64 *stat); 887 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 888 889 /* NPA APIs */ 890 int rvu_npa_init(struct rvu *rvu); 891 void rvu_npa_freemem(struct rvu *rvu); 892 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 893 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 894 struct npa_aq_enq_rsp *rsp); 895 896 /* NIX APIs */ 897 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 898 int rvu_nix_init(struct rvu *rvu); 899 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 900 int blkaddr, u32 cfg); 901 void rvu_nix_freemem(struct rvu *rvu); 902 int rvu_get_nixlf_count(struct rvu *rvu); 903 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 904 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 905 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 906 struct nix_mce_list *mce_list, 907 int mce_idx, int mcam_index, bool add); 908 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 909 struct nix_mce_list **mce_list, int *mce_idx); 910 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 911 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 912 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 913 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 914 struct nix_hw **nix_hw, int *blkaddr); 915 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 916 u16 rq_idx, u16 match_id); 917 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 918 struct nix_cn10k_aq_enq_req *aq_req, 919 struct nix_cn10k_aq_enq_rsp *aq_rsp, 920 u16 pcifunc, u8 ctype, u32 qidx); 921 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 922 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 923 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 924 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 925 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 926 struct nix_txsch *txsch, bool enable); 927 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 928 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 929 u32 mcast_grp_idx); 930 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 931 u32 mcast_grp_idx, u16 mcam_index); 932 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 933 934 /* NPC APIs */ 935 void rvu_npc_freemem(struct rvu *rvu); 936 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 937 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 938 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 939 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 940 int nixlf, u64 chan, u8 *mac_addr); 941 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 942 int nixlf, u64 chan, u8 chan_cnt); 943 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 944 bool enable); 945 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 946 int nixlf, u64 chan); 947 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 948 bool enable); 949 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 950 u64 chan); 951 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 952 bool enable); 953 954 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 955 int nixlf, int type, bool enable); 956 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 957 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 958 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 959 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 960 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 961 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 962 int group, int alg_idx, int mcam_index); 963 964 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 965 int blkaddr, int *alloc_cnt, 966 int *enable_cnt); 967 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 968 int blkaddr, int *alloc_cnt, 969 int *enable_cnt); 970 bool is_npc_intf_tx(u8 intf); 971 bool is_npc_intf_rx(u8 intf); 972 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 973 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 974 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 975 const char *npc_get_field_name(u8 hdr); 976 int npc_get_bank(struct npc_mcam *mcam, int index); 977 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 978 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 979 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 980 int blkaddr, int index, bool enable); 981 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 982 int blkaddr, int index); 983 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 984 int blkaddr, int index, u64 cfg); 985 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 986 int blkaddr, u16 src, struct mcam_entry *entry, 987 u8 *intf, u8 *ena); 988 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 989 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 990 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 991 void *rvu_first_cgx_pdata(struct rvu *rvu); 992 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 993 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 994 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 995 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 996 u16 pfc_en); 997 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 998 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 999 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 1000 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 1001 int type); 1002 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 1003 int index); 1004 int rvu_npc_init(struct rvu *rvu); 1005 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1006 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1007 u64 bcast_mcast_val, u64 bcast_mcast_mask); 1008 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 1009 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 1010 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 1011 void npc_mcam_rsrcs_deinit(struct rvu *rvu); 1012 1013 /* CPT APIs */ 1014 int rvu_cpt_register_interrupts(struct rvu *rvu); 1015 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 1016 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 1017 int slot); 1018 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 1019 int rvu_cpt_init(struct rvu *rvu); 1020 1021 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 1022 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 1023 1024 /* CN10K RVU */ 1025 int rvu_set_channels_base(struct rvu *rvu); 1026 void rvu_program_channels(struct rvu *rvu); 1027 1028 /* CN10K NIX */ 1029 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 1030 1031 /* CN10K RVU - LMT*/ 1032 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 1033 void rvu_apr_block_cn10k_init(struct rvu *rvu); 1034 1035 #ifdef CONFIG_DEBUG_FS 1036 void rvu_dbg_init(struct rvu *rvu); 1037 void rvu_dbg_exit(struct rvu *rvu); 1038 #else 1039 static inline void rvu_dbg_init(struct rvu *rvu) {} 1040 static inline void rvu_dbg_exit(struct rvu *rvu) {} 1041 #endif 1042 1043 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1044 1045 /* RVU Switch */ 1046 void rvu_switch_enable(struct rvu *rvu); 1047 void rvu_switch_disable(struct rvu *rvu); 1048 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 1049 1050 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1051 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1052 u8 shift_dir); 1053 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1054 1055 /* CN10K MCS */ 1056 int rvu_mcs_init(struct rvu *rvu); 1057 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1058 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1059 void rvu_mcs_exit(struct rvu *rvu); 1060 1061 #endif /* RVU_H */ 1062