xref: /linux/drivers/net/ethernet/marvell/octeontx2/af/rvu.h (revision 8fc4e4aa2bfca8d32e8bc2a01526ea2da450e6cb)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef RVU_H
12 #define RVU_H
13 
14 #include <linux/pci.h>
15 #include <net/devlink.h>
16 
17 #include "rvu_struct.h"
18 #include "rvu_devlink.h"
19 #include "common.h"
20 #include "mbox.h"
21 #include "npc.h"
22 #include "rvu_reg.h"
23 
24 /* PCI device IDs */
25 #define	PCI_DEVID_OCTEONTX2_RVU_AF		0xA065
26 #define	PCI_DEVID_OCTEONTX2_LBK			0xA061
27 
28 /* Subsystem Device ID */
29 #define PCI_SUBSYS_DEVID_96XX                  0xB200
30 #define PCI_SUBSYS_DEVID_CN10K_A	       0xB900
31 
32 /* PCI BAR nos */
33 #define	PCI_AF_REG_BAR_NUM			0
34 #define	PCI_PF_REG_BAR_NUM			2
35 #define	PCI_MBOX_BAR_NUM			4
36 
37 #define NAME_SIZE				32
38 #define MAX_NIX_BLKS				2
39 #define MAX_CPT_BLKS				2
40 
41 /* PF_FUNC */
42 #define RVU_PFVF_PF_SHIFT	10
43 #define RVU_PFVF_PF_MASK	0x3F
44 #define RVU_PFVF_FUNC_SHIFT	0
45 #define RVU_PFVF_FUNC_MASK	0x3FF
46 
47 #ifdef CONFIG_DEBUG_FS
48 struct dump_ctx {
49 	int	lf;
50 	int	id;
51 	bool	all;
52 };
53 
54 struct cpt_ctx {
55 	int blkaddr;
56 	struct rvu *rvu;
57 };
58 
59 struct rvu_debugfs {
60 	struct dentry *root;
61 	struct dentry *cgx_root;
62 	struct dentry *cgx;
63 	struct dentry *lmac;
64 	struct dentry *npa;
65 	struct dentry *nix;
66 	struct dentry *npc;
67 	struct dentry *cpt;
68 	struct dump_ctx npa_aura_ctx;
69 	struct dump_ctx npa_pool_ctx;
70 	struct dump_ctx nix_cq_ctx;
71 	struct dump_ctx nix_rq_ctx;
72 	struct dump_ctx nix_sq_ctx;
73 	struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
74 	int npa_qsize_id;
75 	int nix_qsize_id;
76 };
77 #endif
78 
79 struct rvu_work {
80 	struct	work_struct work;
81 	struct	rvu *rvu;
82 	int num_msgs;
83 	int up_num_msgs;
84 };
85 
86 struct rsrc_bmap {
87 	unsigned long *bmap;	/* Pointer to resource bitmap */
88 	u16  max;		/* Max resource id or count */
89 };
90 
91 struct rvu_block {
92 	struct rsrc_bmap	lf;
93 	struct admin_queue	*aq; /* NIX/NPA AQ */
94 	u16  *fn_map; /* LF to pcifunc mapping */
95 	bool multislot;
96 	bool implemented;
97 	u8   addr;  /* RVU_BLOCK_ADDR_E */
98 	u8   type;  /* RVU_BLOCK_TYPE_E */
99 	u8   lfshift;
100 	u64  lookup_reg;
101 	u64  pf_lfcnt_reg;
102 	u64  vf_lfcnt_reg;
103 	u64  lfcfg_reg;
104 	u64  msixcfg_reg;
105 	u64  lfreset_reg;
106 	unsigned char name[NAME_SIZE];
107 };
108 
109 struct nix_mcast {
110 	struct qmem	*mce_ctx;
111 	struct qmem	*mcast_buf;
112 	int		replay_pkind;
113 	int		next_free_mce;
114 	struct mutex	mce_lock; /* Serialize MCE updates */
115 };
116 
117 struct nix_mce_list {
118 	struct hlist_head	head;
119 	int			count;
120 	int			max;
121 };
122 
123 /* layer metadata to uniquely identify a packet header field */
124 struct npc_layer_mdata {
125 	u8 lid;
126 	u8 ltype;
127 	u8 hdr;
128 	u8 key;
129 	u8 len;
130 };
131 
132 /* Structure to represent a field present in the
133  * generated key. A key field may present anywhere and can
134  * be of any size in the generated key. Once this structure
135  * is populated for fields of interest then field's presence
136  * and location (if present) can be known.
137  */
138 struct npc_key_field {
139 	/* Masks where all set bits indicate position
140 	 * of a field in the key
141 	 */
142 	u64 kw_mask[NPC_MAX_KWS_IN_KEY];
143 	/* Number of words in the key a field spans. If a field is
144 	 * of 16 bytes and key offset is 4 then the field will use
145 	 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
146 	 * nr_kws will be 3(KW0, KW1 and KW2).
147 	 */
148 	int nr_kws;
149 	/* used by packet header fields */
150 	struct npc_layer_mdata layer_mdata;
151 };
152 
153 struct npc_mcam {
154 	struct rsrc_bmap counters;
155 	struct mutex	lock;	/* MCAM entries and counters update lock */
156 	unsigned long	*bmap;		/* bitmap, 0 => bmap_entries */
157 	unsigned long	*bmap_reverse;	/* Reverse bitmap, bmap_entries => 0 */
158 	u16	bmap_entries;	/* Number of unreserved MCAM entries */
159 	u16	bmap_fcnt;	/* MCAM entries free count */
160 	u16	*entry2pfvf_map;
161 	u16	*entry2cntr_map;
162 	u16	*cntr2pfvf_map;
163 	u16	*cntr_refcnt;
164 	u16	*entry2target_pffunc;
165 	u8	keysize;	/* MCAM keysize 112/224/448 bits */
166 	u8	banks;		/* Number of MCAM banks */
167 	u8	banks_per_entry;/* Number of keywords in key */
168 	u16	banksize;	/* Number of MCAM entries in each bank */
169 	u16	total_entries;	/* Total number of MCAM entries */
170 	u16	nixlf_offset;	/* Offset of nixlf rsvd uncast entries */
171 	u16	pf_offset;	/* Offset of PF's rsvd bcast, promisc entries */
172 	u16	lprio_count;
173 	u16	lprio_start;
174 	u16	hprio_count;
175 	u16	hprio_end;
176 	u16     rx_miss_act_cntr; /* Counter for RX MISS action */
177 	/* fields present in the generated key */
178 	struct npc_key_field	tx_key_fields[NPC_KEY_FIELDS_MAX];
179 	struct npc_key_field	rx_key_fields[NPC_KEY_FIELDS_MAX];
180 	u64	tx_features;
181 	u64	rx_features;
182 	struct list_head mcam_rules;
183 };
184 
185 /* Structure for per RVU func info ie PF/VF */
186 struct rvu_pfvf {
187 	bool		npalf; /* Only one NPALF per RVU_FUNC */
188 	bool		nixlf; /* Only one NIXLF per RVU_FUNC */
189 	u16		sso;
190 	u16		ssow;
191 	u16		cptlfs;
192 	u16		timlfs;
193 	u16		cpt1_lfs;
194 	u8		cgx_lmac;
195 
196 	/* Block LF's MSIX vector info */
197 	struct rsrc_bmap msix;      /* Bitmap for MSIX vector alloc */
198 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
199 	u16		 *msix_lfmap; /* Vector to block LF mapping */
200 
201 	/* NPA contexts */
202 	struct qmem	*aura_ctx;
203 	struct qmem	*pool_ctx;
204 	struct qmem	*npa_qints_ctx;
205 	unsigned long	*aura_bmap;
206 	unsigned long	*pool_bmap;
207 
208 	/* NIX contexts */
209 	struct qmem	*rq_ctx;
210 	struct qmem	*sq_ctx;
211 	struct qmem	*cq_ctx;
212 	struct qmem	*rss_ctx;
213 	struct qmem	*cq_ints_ctx;
214 	struct qmem	*nix_qints_ctx;
215 	unsigned long	*sq_bmap;
216 	unsigned long	*rq_bmap;
217 	unsigned long	*cq_bmap;
218 
219 	u16		rx_chan_base;
220 	u16		tx_chan_base;
221 	u8              rx_chan_cnt; /* total number of RX channels */
222 	u8              tx_chan_cnt; /* total number of TX channels */
223 	u16		maxlen;
224 	u16		minlen;
225 
226 	u8		pf_set_vf_cfg;
227 	u8		mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
228 	u8		default_mac[ETH_ALEN]; /* MAC address from FWdata */
229 
230 	/* Broadcast pkt replication info */
231 	u16			bcast_mce_idx;
232 	struct nix_mce_list	bcast_mce_list;
233 
234 	struct rvu_npc_mcam_rule *def_ucast_rule;
235 
236 	bool	cgx_in_use; /* this PF/VF using CGX? */
237 	int	cgx_users;  /* number of cgx users - used only by PFs */
238 
239 	u8	nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
240 	u8	nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
241 	u8	nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
242 };
243 
244 struct nix_txsch {
245 	struct rsrc_bmap schq;
246 	u8   lvl;
247 #define NIX_TXSCHQ_FREE		      BIT_ULL(1)
248 #define NIX_TXSCHQ_CFG_DONE	      BIT_ULL(0)
249 #define TXSCH_MAP_FUNC(__pfvf_map)    ((__pfvf_map) & 0xFFFF)
250 #define TXSCH_MAP_FLAGS(__pfvf_map)   ((__pfvf_map) >> 16)
251 #define TXSCH_MAP(__func, __flags)    (((__func) & 0xFFFF) | ((__flags) << 16))
252 #define TXSCH_SET_FLAG(__pfvf_map, flag)    ((__pfvf_map) | ((flag) << 16))
253 	u32  *pfvf_map;
254 };
255 
256 struct nix_mark_format {
257 	u8 total;
258 	u8 in_use;
259 	u32 *cfg;
260 };
261 
262 struct npc_pkind {
263 	struct rsrc_bmap rsrc;
264 	u32	*pfchan_map;
265 };
266 
267 struct nix_flowkey {
268 #define NIX_FLOW_KEY_ALG_MAX 32
269 	u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
270 	int in_use;
271 };
272 
273 struct nix_lso {
274 	u8 total;
275 	u8 in_use;
276 };
277 
278 struct nix_txvlan {
279 #define NIX_TX_VTAG_DEF_MAX 0x400
280 	struct rsrc_bmap rsrc;
281 	u16 *entry2pfvf_map;
282 	struct mutex rsrc_lock; /* Serialize resource alloc/free */
283 };
284 
285 struct nix_hw {
286 	int blkaddr;
287 	struct rvu *rvu;
288 	struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
289 	struct nix_mcast mcast;
290 	struct nix_flowkey flowkey;
291 	struct nix_mark_format mark_format;
292 	struct nix_lso lso;
293 	struct nix_txvlan txvlan;
294 };
295 
296 /* RVU block's capabilities or functionality,
297  * which vary by silicon version/skew.
298  */
299 struct hw_cap {
300 	/* Transmit side supported functionality */
301 	u8	nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
302 	u16	nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
303 	u16	nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
304 	u16	nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
305 	bool	nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
306 	bool	nix_shaping;		 /* Is shaping and coloring supported */
307 	bool	nix_tx_link_bp;		 /* Can link backpressure TL queues ? */
308 	bool	nix_rx_multicast;	 /* Rx packet replication support */
309 	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
310 	bool	programmable_chans; /* Channels programmable ? */
311 };
312 
313 struct rvu_hwinfo {
314 	u8	total_pfs;   /* MAX RVU PFs HW supports */
315 	u16	total_vfs;   /* Max RVU VFs HW supports */
316 	u16	max_vfs_per_pf; /* Max VFs that can be attached to a PF */
317 	u8	cgx;
318 	u8	lmac_per_cgx;
319 	u16	cgx_chan_base;	/* CGX base channel number */
320 	u16	lbk_chan_base;	/* LBK base channel number */
321 	u16	sdp_chan_base;	/* SDP base channel number */
322 	u16	cpt_chan_base;	/* CPT base channel number */
323 	u8	cgx_links;
324 	u8	lbk_links;
325 	u8	sdp_links;
326 	u8	cpt_links;	/* Number of CPT links */
327 	u8	npc_kpus;          /* No of parser units */
328 	u8	npc_pkinds;        /* No of port kinds */
329 	u8	npc_intfs;         /* No of interfaces */
330 	u8	npc_kpu_entries;   /* No of KPU entries */
331 	u16	npc_counters;	   /* No of match stats counters */
332 	u32	lbk_bufsize;	   /* FIFO size supported by LBK */
333 	bool	npc_ext_set;	   /* Extended register set */
334 
335 	struct hw_cap    cap;
336 	struct rvu_block block[BLK_COUNT]; /* Block info */
337 	struct nix_hw    *nix;
338 	struct rvu	 *rvu;
339 	struct npc_pkind pkind;
340 	struct npc_mcam  mcam;
341 };
342 
343 struct mbox_wq_info {
344 	struct otx2_mbox mbox;
345 	struct rvu_work *mbox_wrk;
346 
347 	struct otx2_mbox mbox_up;
348 	struct rvu_work *mbox_wrk_up;
349 
350 	struct workqueue_struct *mbox_wq;
351 };
352 
353 struct rvu_fwdata {
354 #define RVU_FWDATA_HEADER_MAGIC	0xCFDA	/* Custom Firmware Data*/
355 #define RVU_FWDATA_VERSION	0x0001
356 	u32 header_magic;
357 	u32 version;		/* version id */
358 
359 	/* MAC address */
360 #define PF_MACNUM_MAX	32
361 #define VF_MACNUM_MAX	256
362 	u64 pf_macs[PF_MACNUM_MAX];
363 	u64 vf_macs[VF_MACNUM_MAX];
364 	u64 sclk;
365 	u64 rclk;
366 	u64 mcam_addr;
367 	u64 mcam_sz;
368 	u64 msixtr_base;
369 #define FWDATA_RESERVED_MEM 1023
370 	u64 reserved[FWDATA_RESERVED_MEM];
371 #define CGX_MAX         5
372 #define CGX_LMACS_MAX   4
373 	struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
374 	/* Do not add new fields below this line */
375 };
376 
377 struct ptp;
378 
379 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
380  * source where it came from.
381  */
382 struct npc_kpu_profile_adapter {
383 	const char			*name;
384 	u64				version;
385 	const struct npc_lt_def_cfg	*lt_def;
386 	const struct npc_kpu_profile_action	*ikpu; /* array[pkinds] */
387 	const struct npc_kpu_profile	*kpu; /* array[kpus] */
388 	struct npc_mcam_kex		*mkex;
389 	size_t				pkinds;
390 	size_t				kpus;
391 };
392 
393 struct rvu {
394 	void __iomem		*afreg_base;
395 	void __iomem		*pfreg_base;
396 	struct pci_dev		*pdev;
397 	struct device		*dev;
398 	struct rvu_hwinfo       *hw;
399 	struct rvu_pfvf		*pf;
400 	struct rvu_pfvf		*hwvf;
401 	struct mutex		rsrc_lock; /* Serialize resource alloc/free */
402 	int			vfs; /* Number of VFs attached to RVU */
403 	int			nix_blkaddr[MAX_NIX_BLKS];
404 
405 	/* Mbox */
406 	struct mbox_wq_info	afpf_wq_info;
407 	struct mbox_wq_info	afvf_wq_info;
408 
409 	/* PF FLR */
410 	struct rvu_work		*flr_wrk;
411 	struct workqueue_struct *flr_wq;
412 	struct mutex		flr_lock; /* Serialize FLRs */
413 
414 	/* MSI-X */
415 	u16			num_vec;
416 	char			*irq_name;
417 	bool			*irq_allocated;
418 	dma_addr_t		msix_base_iova;
419 	u64			msixtr_base_phy; /* Register reset value */
420 
421 	/* CGX */
422 #define PF_CGXMAP_BASE		1 /* PF 0 is reserved for RVU PF */
423 	u8			cgx_mapped_pfs;
424 	u8			cgx_cnt_max;	 /* CGX port count max */
425 	u8			*pf2cgxlmac_map; /* pf to cgx_lmac map */
426 	u16			*cgxlmac2pf_map; /* bitmap of mapped pfs for
427 						  * every cgx lmac port
428 						  */
429 	unsigned long		pf_notify_bmap; /* Flags for PF notification */
430 	void			**cgx_idmap; /* cgx id to cgx data map table */
431 	struct			work_struct cgx_evh_work;
432 	struct			workqueue_struct *cgx_evh_wq;
433 	spinlock_t		cgx_evq_lock; /* cgx event queue lock */
434 	struct list_head	cgx_evq_head; /* cgx event queue head */
435 	struct mutex		cgx_cfg_lock; /* serialize cgx configuration */
436 
437 	char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
438 
439 	/* Firmware data */
440 	struct rvu_fwdata	*fwdata;
441 
442 	/* NPC KPU data */
443 	struct npc_kpu_profile_adapter kpu;
444 
445 	struct ptp		*ptp;
446 
447 #ifdef CONFIG_DEBUG_FS
448 	struct rvu_debugfs	rvu_dbg;
449 #endif
450 	struct rvu_devlink	*rvu_dl;
451 };
452 
453 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
454 {
455 	writeq(val, rvu->afreg_base + ((block << 28) | offset));
456 }
457 
458 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
459 {
460 	return readq(rvu->afreg_base + ((block << 28) | offset));
461 }
462 
463 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
464 {
465 	writeq(val, rvu->pfreg_base + offset);
466 }
467 
468 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
469 {
470 	return readq(rvu->pfreg_base + offset);
471 }
472 
473 /* Silicon revisions */
474 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
475 {
476 	struct pci_dev *pdev = rvu->pdev;
477 
478 	return (pdev->revision == 0x00) &&
479 		(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
480 }
481 
482 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
483 {
484 	struct pci_dev *pdev = rvu->pdev;
485 
486 	return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) &&
487 		(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
488 }
489 
490 /* REVID for PCIe devices.
491  * Bits 0..1: minor pass, bit 3..2: major pass
492  * bits 7..4: midr id
493  */
494 #define PCI_REVISION_ID_96XX		0x00
495 #define PCI_REVISION_ID_95XX		0x10
496 #define PCI_REVISION_ID_LOKI		0x20
497 #define PCI_REVISION_ID_98XX		0x30
498 #define PCI_REVISION_ID_95XXMM		0x40
499 
500 static inline bool is_rvu_otx2(struct rvu *rvu)
501 {
502 	struct pci_dev *pdev = rvu->pdev;
503 
504 	u8 midr = pdev->revision & 0xF0;
505 
506 	return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
507 		midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX ||
508 		midr == PCI_REVISION_ID_95XXMM);
509 }
510 
511 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
512 				   u8 lmacid, u8 chan)
513 {
514 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
515 	u16 cgx_chans = nix_const & 0xFFULL;
516 	struct rvu_hwinfo *hw = rvu->hw;
517 
518 	if (!hw->cap.programmable_chans)
519 		return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
520 
521 	return rvu->hw->cgx_chan_base +
522 		(cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
523 }
524 
525 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
526 				   u8 chan)
527 {
528 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
529 	u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
530 	struct rvu_hwinfo *hw = rvu->hw;
531 
532 	if (!hw->cap.programmable_chans)
533 		return NIX_CHAN_LBK_CHX(lbkid, chan);
534 
535 	return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
536 }
537 
538 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
539 {
540 	return rvu->hw->cpt_chan_base + chan;
541 }
542 
543 /* Function Prototypes
544  * RVU
545  */
546 static inline int is_afvf(u16 pcifunc)
547 {
548 	return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
549 }
550 
551 /* check if PF_FUNC is AF */
552 static inline bool is_pffunc_af(u16 pcifunc)
553 {
554 	return !pcifunc;
555 }
556 
557 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
558 {
559 	return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
560 		(rvu->fwdata->version == RVU_FWDATA_VERSION);
561 }
562 
563 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
564 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
565 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
566 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
567 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
568 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
569 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
570 int rvu_get_pf(u16 pcifunc);
571 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
572 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
573 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
574 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
575 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
576 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
577 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
578 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
579 int rvu_get_num_lbk_chans(void);
580 
581 /* RVU HW reg validation */
582 enum regmap_block {
583 	TXSCHQ_HWREGMAP = 0,
584 	MAX_HWREGMAP,
585 };
586 
587 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
588 
589 /* NPA/NIX AQ APIs */
590 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
591 		 int qsize, int inst_size, int res_size);
592 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
593 
594 /* CGX APIs */
595 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
596 {
597 	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
598 }
599 
600 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
601 {
602 	*cgx_id = (map >> 4) & 0xF;
603 	*lmac_id = (map & 0xF);
604 }
605 
606 #define M(_name, _id, fn_name, req, rsp)				\
607 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
608 MBOX_MESSAGES
609 #undef M
610 
611 int rvu_cgx_init(struct rvu *rvu);
612 int rvu_cgx_exit(struct rvu *rvu);
613 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
614 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
615 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
616 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
617 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
618 			   int rxtxflag, u64 *stat);
619 /* NPA APIs */
620 int rvu_npa_init(struct rvu *rvu);
621 void rvu_npa_freemem(struct rvu *rvu);
622 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
623 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
624 			struct npa_aq_enq_rsp *rsp);
625 
626 /* NIX APIs */
627 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
628 int rvu_nix_init(struct rvu *rvu);
629 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
630 				int blkaddr, u32 cfg);
631 void rvu_nix_freemem(struct rvu *rvu);
632 int rvu_get_nixlf_count(struct rvu *rvu);
633 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
634 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
635 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
636 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
637 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
638 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
639 
640 /* NPC APIs */
641 int rvu_npc_init(struct rvu *rvu);
642 void rvu_npc_freemem(struct rvu *rvu);
643 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
644 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
645 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
646 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
647 				 int nixlf, u64 chan, u8 *mac_addr);
648 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
649 				   int nixlf, u64 chan, u8 chan_cnt,
650 				   bool allmulti);
651 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
652 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
653 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
654 				       int nixlf, u64 chan);
655 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable);
656 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
657 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
658 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
659 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
660 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
661 				    int group, int alg_idx, int mcam_index);
662 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
663 				       int blkaddr, int *alloc_cnt,
664 				       int *enable_cnt);
665 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
666 					 int blkaddr, int *alloc_cnt,
667 					 int *enable_cnt);
668 bool is_npc_intf_tx(u8 intf);
669 bool is_npc_intf_rx(u8 intf);
670 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
671 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
672 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel);
673 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
674 const char *npc_get_field_name(u8 hdr);
675 int npc_get_bank(struct npc_mcam *mcam, int index);
676 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
677 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
678 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
679 			   int blkaddr, int index, bool enable);
680 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
681 			 int blkaddr, u16 src, struct mcam_entry *entry,
682 			 u8 *intf, u8 *ena);
683 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
684 u32  rvu_cgx_get_fifolen(struct rvu *rvu);
685 void *rvu_first_cgx_pdata(struct rvu *rvu);
686 
687 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
688 			     int type);
689 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
690 			   int index);
691 
692 /* CPT APIs */
693 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot);
694 
695 /* CN10K RVU */
696 int rvu_set_channels_base(struct rvu *rvu);
697 void rvu_program_channels(struct rvu *rvu);
698 
699 #ifdef CONFIG_DEBUG_FS
700 void rvu_dbg_init(struct rvu *rvu);
701 void rvu_dbg_exit(struct rvu *rvu);
702 #else
703 static inline void rvu_dbg_init(struct rvu *rvu) {}
704 static inline void rvu_dbg_exit(struct rvu *rvu) {}
705 #endif
706 #endif /* RVU_H */
707