1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include "rvu_struct.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 20 /* PCI device IDs */ 21 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 22 23 /* Subsystem Device ID */ 24 #define PCI_SUBSYS_DEVID_96XX 0xB200 25 26 /* PCI BAR nos */ 27 #define PCI_AF_REG_BAR_NUM 0 28 #define PCI_PF_REG_BAR_NUM 2 29 #define PCI_MBOX_BAR_NUM 4 30 31 #define NAME_SIZE 32 32 #define MAX_NIX_BLKS 2 33 34 /* PF_FUNC */ 35 #define RVU_PFVF_PF_SHIFT 10 36 #define RVU_PFVF_PF_MASK 0x3F 37 #define RVU_PFVF_FUNC_SHIFT 0 38 #define RVU_PFVF_FUNC_MASK 0x3FF 39 40 #ifdef CONFIG_DEBUG_FS 41 struct dump_ctx { 42 int lf; 43 int id; 44 bool all; 45 }; 46 47 struct rvu_debugfs { 48 struct dentry *root; 49 struct dentry *cgx_root; 50 struct dentry *cgx; 51 struct dentry *lmac; 52 struct dentry *npa; 53 struct dentry *nix; 54 struct dentry *npc; 55 struct dentry *cpt; 56 struct dump_ctx npa_aura_ctx; 57 struct dump_ctx npa_pool_ctx; 58 struct dump_ctx nix_cq_ctx; 59 struct dump_ctx nix_rq_ctx; 60 struct dump_ctx nix_sq_ctx; 61 int npa_qsize_id; 62 int nix_qsize_id; 63 }; 64 #endif 65 66 struct rvu_work { 67 struct work_struct work; 68 struct rvu *rvu; 69 int num_msgs; 70 int up_num_msgs; 71 }; 72 73 struct rsrc_bmap { 74 unsigned long *bmap; /* Pointer to resource bitmap */ 75 u16 max; /* Max resource id or count */ 76 }; 77 78 struct rvu_block { 79 struct rsrc_bmap lf; 80 struct admin_queue *aq; /* NIX/NPA AQ */ 81 u16 *fn_map; /* LF to pcifunc mapping */ 82 bool multislot; 83 bool implemented; 84 u8 addr; /* RVU_BLOCK_ADDR_E */ 85 u8 type; /* RVU_BLOCK_TYPE_E */ 86 u8 lfshift; 87 u64 lookup_reg; 88 u64 pf_lfcnt_reg; 89 u64 vf_lfcnt_reg; 90 u64 lfcfg_reg; 91 u64 msixcfg_reg; 92 u64 lfreset_reg; 93 unsigned char name[NAME_SIZE]; 94 }; 95 96 struct nix_mcast { 97 struct qmem *mce_ctx; 98 struct qmem *mcast_buf; 99 int replay_pkind; 100 int next_free_mce; 101 struct mutex mce_lock; /* Serialize MCE updates */ 102 }; 103 104 struct nix_mce_list { 105 struct hlist_head head; 106 int count; 107 int max; 108 }; 109 110 /* layer metadata to uniquely identify a packet header field */ 111 struct npc_layer_mdata { 112 u8 lid; 113 u8 ltype; 114 u8 hdr; 115 u8 key; 116 u8 len; 117 }; 118 119 /* Structure to represent a field present in the 120 * generated key. A key field may present anywhere and can 121 * be of any size in the generated key. Once this structure 122 * is populated for fields of interest then field's presence 123 * and location (if present) can be known. 124 */ 125 struct npc_key_field { 126 /* Masks where all set bits indicate position 127 * of a field in the key 128 */ 129 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 130 /* Number of words in the key a field spans. If a field is 131 * of 16 bytes and key offset is 4 then the field will use 132 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 133 * nr_kws will be 3(KW0, KW1 and KW2). 134 */ 135 int nr_kws; 136 /* used by packet header fields */ 137 struct npc_layer_mdata layer_mdata; 138 }; 139 140 struct npc_mcam { 141 struct rsrc_bmap counters; 142 struct mutex lock; /* MCAM entries and counters update lock */ 143 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 144 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 145 u16 bmap_entries; /* Number of unreserved MCAM entries */ 146 u16 bmap_fcnt; /* MCAM entries free count */ 147 u16 *entry2pfvf_map; 148 u16 *entry2cntr_map; 149 u16 *cntr2pfvf_map; 150 u16 *cntr_refcnt; 151 u16 *entry2target_pffunc; 152 u8 keysize; /* MCAM keysize 112/224/448 bits */ 153 u8 banks; /* Number of MCAM banks */ 154 u8 banks_per_entry;/* Number of keywords in key */ 155 u16 banksize; /* Number of MCAM entries in each bank */ 156 u16 total_entries; /* Total number of MCAM entries */ 157 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 158 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 159 u16 lprio_count; 160 u16 lprio_start; 161 u16 hprio_count; 162 u16 hprio_end; 163 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 164 /* fields present in the generated key */ 165 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 166 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 167 u64 tx_features; 168 u64 rx_features; 169 struct list_head mcam_rules; 170 }; 171 172 /* Structure for per RVU func info ie PF/VF */ 173 struct rvu_pfvf { 174 bool npalf; /* Only one NPALF per RVU_FUNC */ 175 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 176 u16 sso; 177 u16 ssow; 178 u16 cptlfs; 179 u16 timlfs; 180 u16 cpt1_lfs; 181 u8 cgx_lmac; 182 183 /* Block LF's MSIX vector info */ 184 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 185 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 186 u16 *msix_lfmap; /* Vector to block LF mapping */ 187 188 /* NPA contexts */ 189 struct qmem *aura_ctx; 190 struct qmem *pool_ctx; 191 struct qmem *npa_qints_ctx; 192 unsigned long *aura_bmap; 193 unsigned long *pool_bmap; 194 195 /* NIX contexts */ 196 struct qmem *rq_ctx; 197 struct qmem *sq_ctx; 198 struct qmem *cq_ctx; 199 struct qmem *rss_ctx; 200 struct qmem *cq_ints_ctx; 201 struct qmem *nix_qints_ctx; 202 unsigned long *sq_bmap; 203 unsigned long *rq_bmap; 204 unsigned long *cq_bmap; 205 206 u16 rx_chan_base; 207 u16 tx_chan_base; 208 u8 rx_chan_cnt; /* total number of RX channels */ 209 u8 tx_chan_cnt; /* total number of TX channels */ 210 u16 maxlen; 211 u16 minlen; 212 213 u8 pf_set_vf_cfg; 214 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 215 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 216 217 /* Broadcast pkt replication info */ 218 u16 bcast_mce_idx; 219 struct nix_mce_list bcast_mce_list; 220 221 struct rvu_npc_mcam_rule *def_ucast_rule; 222 223 bool cgx_in_use; /* this PF/VF using CGX? */ 224 int cgx_users; /* number of cgx users - used only by PFs */ 225 226 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 227 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 228 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 229 }; 230 231 struct nix_txsch { 232 struct rsrc_bmap schq; 233 u8 lvl; 234 #define NIX_TXSCHQ_FREE BIT_ULL(1) 235 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 236 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 237 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 238 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 239 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 240 u32 *pfvf_map; 241 }; 242 243 struct nix_mark_format { 244 u8 total; 245 u8 in_use; 246 u32 *cfg; 247 }; 248 249 struct npc_pkind { 250 struct rsrc_bmap rsrc; 251 u32 *pfchan_map; 252 }; 253 254 struct nix_flowkey { 255 #define NIX_FLOW_KEY_ALG_MAX 32 256 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 257 int in_use; 258 }; 259 260 struct nix_lso { 261 u8 total; 262 u8 in_use; 263 }; 264 265 struct nix_txvlan { 266 #define NIX_TX_VTAG_DEF_MAX 0x400 267 struct rsrc_bmap rsrc; 268 u16 *entry2pfvf_map; 269 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 270 }; 271 272 struct nix_hw { 273 int blkaddr; 274 struct rvu *rvu; 275 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 276 struct nix_mcast mcast; 277 struct nix_flowkey flowkey; 278 struct nix_mark_format mark_format; 279 struct nix_lso lso; 280 struct nix_txvlan txvlan; 281 }; 282 283 /* RVU block's capabilities or functionality, 284 * which vary by silicon version/skew. 285 */ 286 struct hw_cap { 287 /* Transmit side supported functionality */ 288 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 289 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 290 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 291 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 292 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 293 bool nix_shaping; /* Is shaping and coloring supported */ 294 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 295 bool nix_rx_multicast; /* Rx packet replication support */ 296 }; 297 298 struct rvu_hwinfo { 299 u8 total_pfs; /* MAX RVU PFs HW supports */ 300 u16 total_vfs; /* Max RVU VFs HW supports */ 301 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 302 u8 cgx; 303 u8 lmac_per_cgx; 304 u8 cgx_links; 305 u8 lbk_links; 306 u8 sdp_links; 307 u8 npc_kpus; /* No of parser units */ 308 u8 npc_pkinds; /* No of port kinds */ 309 u8 npc_intfs; /* No of interfaces */ 310 u8 npc_kpu_entries; /* No of KPU entries */ 311 u16 npc_counters; /* No of match stats counters */ 312 bool npc_ext_set; /* Extended register set */ 313 314 struct hw_cap cap; 315 struct rvu_block block[BLK_COUNT]; /* Block info */ 316 struct nix_hw *nix; 317 struct rvu *rvu; 318 struct npc_pkind pkind; 319 struct npc_mcam mcam; 320 }; 321 322 struct mbox_wq_info { 323 struct otx2_mbox mbox; 324 struct rvu_work *mbox_wrk; 325 326 struct otx2_mbox mbox_up; 327 struct rvu_work *mbox_wrk_up; 328 329 struct workqueue_struct *mbox_wq; 330 }; 331 332 struct rvu_fwdata { 333 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 334 #define RVU_FWDATA_VERSION 0x0001 335 u32 header_magic; 336 u32 version; /* version id */ 337 338 /* MAC address */ 339 #define PF_MACNUM_MAX 32 340 #define VF_MACNUM_MAX 256 341 u64 pf_macs[PF_MACNUM_MAX]; 342 u64 vf_macs[VF_MACNUM_MAX]; 343 u64 sclk; 344 u64 rclk; 345 u64 mcam_addr; 346 u64 mcam_sz; 347 u64 msixtr_base; 348 #define FWDATA_RESERVED_MEM 1023 349 u64 reserved[FWDATA_RESERVED_MEM]; 350 }; 351 352 struct ptp; 353 354 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 355 * source where it came from. 356 */ 357 struct npc_kpu_profile_adapter { 358 const char *name; 359 u64 version; 360 const struct npc_lt_def_cfg *lt_def; 361 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 362 const struct npc_kpu_profile *kpu; /* array[kpus] */ 363 struct npc_mcam_kex *mkex; 364 size_t pkinds; 365 size_t kpus; 366 }; 367 368 struct rvu { 369 void __iomem *afreg_base; 370 void __iomem *pfreg_base; 371 struct pci_dev *pdev; 372 struct device *dev; 373 struct rvu_hwinfo *hw; 374 struct rvu_pfvf *pf; 375 struct rvu_pfvf *hwvf; 376 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 377 int vfs; /* Number of VFs attached to RVU */ 378 int nix_blkaddr[MAX_NIX_BLKS]; 379 380 /* Mbox */ 381 struct mbox_wq_info afpf_wq_info; 382 struct mbox_wq_info afvf_wq_info; 383 384 /* PF FLR */ 385 struct rvu_work *flr_wrk; 386 struct workqueue_struct *flr_wq; 387 struct mutex flr_lock; /* Serialize FLRs */ 388 389 /* MSI-X */ 390 u16 num_vec; 391 char *irq_name; 392 bool *irq_allocated; 393 dma_addr_t msix_base_iova; 394 u64 msixtr_base_phy; /* Register reset value */ 395 396 /* CGX */ 397 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 398 u8 cgx_mapped_pfs; 399 u8 cgx_cnt_max; /* CGX port count max */ 400 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 401 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 402 * every cgx lmac port 403 */ 404 unsigned long pf_notify_bmap; /* Flags for PF notification */ 405 void **cgx_idmap; /* cgx id to cgx data map table */ 406 struct work_struct cgx_evh_work; 407 struct workqueue_struct *cgx_evh_wq; 408 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 409 struct list_head cgx_evq_head; /* cgx event queue head */ 410 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 411 412 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 413 414 /* Firmware data */ 415 struct rvu_fwdata *fwdata; 416 417 /* NPC KPU data */ 418 struct npc_kpu_profile_adapter kpu; 419 420 struct ptp *ptp; 421 422 #ifdef CONFIG_DEBUG_FS 423 struct rvu_debugfs rvu_dbg; 424 #endif 425 }; 426 427 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 428 { 429 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 430 } 431 432 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 433 { 434 return readq(rvu->afreg_base + ((block << 28) | offset)); 435 } 436 437 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 438 { 439 writeq(val, rvu->pfreg_base + offset); 440 } 441 442 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 443 { 444 return readq(rvu->pfreg_base + offset); 445 } 446 447 /* Silicon revisions */ 448 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 449 { 450 struct pci_dev *pdev = rvu->pdev; 451 452 return (pdev->revision == 0x00) && 453 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 454 } 455 456 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 457 { 458 struct pci_dev *pdev = rvu->pdev; 459 460 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 461 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 462 } 463 464 /* Function Prototypes 465 * RVU 466 */ 467 static inline int is_afvf(u16 pcifunc) 468 { 469 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 470 } 471 472 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 473 { 474 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 475 (rvu->fwdata->version == RVU_FWDATA_VERSION); 476 } 477 478 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 479 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 480 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 481 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 482 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 483 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 484 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 485 int rvu_get_pf(u16 pcifunc); 486 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 487 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 488 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 489 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 490 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 491 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 492 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 493 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 494 int rvu_get_num_lbk_chans(void); 495 496 /* RVU HW reg validation */ 497 enum regmap_block { 498 TXSCHQ_HWREGMAP = 0, 499 MAX_HWREGMAP, 500 }; 501 502 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 503 504 /* NPA/NIX AQ APIs */ 505 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 506 int qsize, int inst_size, int res_size); 507 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 508 509 /* CGX APIs */ 510 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 511 { 512 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 513 } 514 515 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 516 { 517 *cgx_id = (map >> 4) & 0xF; 518 *lmac_id = (map & 0xF); 519 } 520 521 #define M(_name, _id, fn_name, req, rsp) \ 522 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 523 MBOX_MESSAGES 524 #undef M 525 526 int rvu_cgx_init(struct rvu *rvu); 527 int rvu_cgx_exit(struct rvu *rvu); 528 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 529 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 530 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 531 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 532 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 533 int rxtxflag, u64 *stat); 534 /* NPA APIs */ 535 int rvu_npa_init(struct rvu *rvu); 536 void rvu_npa_freemem(struct rvu *rvu); 537 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 538 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 539 struct npa_aq_enq_rsp *rsp); 540 541 /* NIX APIs */ 542 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 543 int rvu_nix_init(struct rvu *rvu); 544 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 545 int blkaddr, u32 cfg); 546 void rvu_nix_freemem(struct rvu *rvu); 547 int rvu_get_nixlf_count(struct rvu *rvu); 548 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 549 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 550 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); 551 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 552 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 553 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 554 555 /* NPC APIs */ 556 int rvu_npc_init(struct rvu *rvu); 557 void rvu_npc_freemem(struct rvu *rvu); 558 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 559 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 560 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 561 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 562 int nixlf, u64 chan, u8 *mac_addr); 563 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 564 int nixlf, u64 chan, bool allmulti); 565 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 566 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 567 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 568 int nixlf, u64 chan); 569 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable); 570 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 571 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 572 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 573 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 574 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 575 int group, int alg_idx, int mcam_index); 576 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 577 int blkaddr, int *alloc_cnt, 578 int *enable_cnt); 579 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 580 int blkaddr, int *alloc_cnt, 581 int *enable_cnt); 582 bool is_npc_intf_tx(u8 intf); 583 bool is_npc_intf_rx(u8 intf); 584 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 585 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 586 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel); 587 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 588 const char *npc_get_field_name(u8 hdr); 589 bool rvu_npc_write_default_rule(struct rvu *rvu, int blkaddr, int nixlf, 590 u16 pcifunc, u8 intf, struct mcam_entry *entry, 591 int *entry_index); 592 int npc_get_bank(struct npc_mcam *mcam, int index); 593 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 594 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 595 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 596 int blkaddr, int index, bool enable); 597 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 598 int blkaddr, u16 src, struct mcam_entry *entry, 599 u8 *intf, u8 *ena); 600 601 #ifdef CONFIG_DEBUG_FS 602 void rvu_dbg_init(struct rvu *rvu); 603 void rvu_dbg_exit(struct rvu *rvu); 604 #else 605 static inline void rvu_dbg_init(struct rvu *rvu) {} 606 static inline void rvu_dbg_exit(struct rvu *rvu) {} 607 #endif 608 #endif /* RVU_H */ 609