1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 #include "mcs.h" 20 21 #include "rvu_trace.h" 22 #include "rvu_npc_hash.h" 23 24 #define DRV_NAME "rvu_af" 25 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 26 27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 28 struct rvu_block *block, int lf); 29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 32 33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 34 int type, int num, 35 void (mbox_handler)(struct work_struct *), 36 void (mbox_up_handler)(struct work_struct *)); 37 enum { 38 TYPE_AFVF, 39 TYPE_AFPF, 40 }; 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->cap.npc_hash_extract = false; 72 hw->cap.npc_exact_match_enabled = false; 73 hw->rvu = rvu; 74 75 if (is_rvu_pre_96xx_C0(rvu)) { 76 hw->cap.nix_fixed_txschq_mapping = true; 77 hw->cap.nix_txsch_per_cgx_lmac = 4; 78 hw->cap.nix_txsch_per_lbk_lmac = 132; 79 hw->cap.nix_txsch_per_sdp_lmac = 76; 80 hw->cap.nix_shaping = false; 81 hw->cap.nix_tx_link_bp = false; 82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 83 hw->cap.nix_rx_multicast = false; 84 } 85 if (!is_rvu_pre_96xx_C0(rvu)) 86 hw->cap.nix_shaper_toggle_wait = true; 87 88 if (!is_rvu_otx2(rvu)) 89 hw->cap.per_pf_mbox_regs = true; 90 91 if (is_rvu_npc_hash_extract_en(rvu)) 92 hw->cap.npc_hash_extract = true; 93 } 94 95 /* Poll a RVU block's register 'offset', for a 'zero' 96 * or 'nonzero' at bits specified by 'mask' 97 */ 98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 99 { 100 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 101 bool twice = false; 102 void __iomem *reg; 103 u64 reg_val; 104 105 reg = rvu->afreg_base + ((block << 28) | offset); 106 again: 107 reg_val = readq(reg); 108 if (zero && !(reg_val & mask)) 109 return 0; 110 if (!zero && (reg_val & mask)) 111 return 0; 112 if (time_before(jiffies, timeout)) { 113 usleep_range(1, 5); 114 goto again; 115 } 116 /* In scenarios where CPU is scheduled out before checking 117 * 'time_before' (above) and gets scheduled in such that 118 * jiffies are beyond timeout value, then check again if HW is 119 * done with the operation in the meantime. 120 */ 121 if (!twice) { 122 twice = true; 123 goto again; 124 } 125 return -EBUSY; 126 } 127 128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 129 { 130 int id; 131 132 if (!rsrc->bmap) 133 return -EINVAL; 134 135 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 136 if (id >= rsrc->max) 137 return -ENOSPC; 138 139 __set_bit(id, rsrc->bmap); 140 141 return id; 142 } 143 144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 145 { 146 int start; 147 148 if (!rsrc->bmap) 149 return -EINVAL; 150 151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 152 if (start >= rsrc->max) 153 return -ENOSPC; 154 155 bitmap_set(rsrc->bmap, start, nrsrc); 156 return start; 157 } 158 159 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 160 { 161 if (!rsrc->bmap) 162 return; 163 if (start >= rsrc->max) 164 return; 165 166 bitmap_clear(rsrc->bmap, start, nrsrc); 167 } 168 169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 170 { 171 int start; 172 173 if (!rsrc->bmap) 174 return false; 175 176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 177 if (start >= rsrc->max) 178 return false; 179 180 return true; 181 } 182 183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 184 { 185 if (!rsrc->bmap) 186 return; 187 188 __clear_bit(id, rsrc->bmap); 189 } 190 191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 192 { 193 int used; 194 195 if (!rsrc->bmap) 196 return 0; 197 198 used = bitmap_weight(rsrc->bmap, rsrc->max); 199 return (rsrc->max - used); 200 } 201 202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 203 { 204 if (!rsrc->bmap) 205 return false; 206 207 return !test_bit(id, rsrc->bmap); 208 } 209 210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 211 { 212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 213 sizeof(long), GFP_KERNEL); 214 if (!rsrc->bmap) 215 return -ENOMEM; 216 return 0; 217 } 218 219 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 220 { 221 kfree(rsrc->bmap); 222 } 223 224 /* Get block LF's HW index from a PF_FUNC's block slot number */ 225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 226 { 227 u16 match = 0; 228 int lf; 229 230 mutex_lock(&rvu->rsrc_lock); 231 for (lf = 0; lf < block->lf.max; lf++) { 232 if (block->fn_map[lf] == pcifunc) { 233 if (slot == match) { 234 mutex_unlock(&rvu->rsrc_lock); 235 return lf; 236 } 237 match++; 238 } 239 } 240 mutex_unlock(&rvu->rsrc_lock); 241 return -ENODEV; 242 } 243 244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 245 * Some silicon variants of OcteonTX2 supports 246 * multiple blocks of same type. 247 * 248 * @pcifunc has to be zero when no LF is yet attached. 249 * 250 * For a pcifunc if LFs are attached from multiple blocks of same type, then 251 * return blkaddr of first encountered block. 252 */ 253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 254 { 255 int devnum, blkaddr = -ENODEV; 256 u64 cfg, reg; 257 bool is_pf; 258 259 switch (blktype) { 260 case BLKTYPE_NPC: 261 blkaddr = BLKADDR_NPC; 262 goto exit; 263 case BLKTYPE_NPA: 264 blkaddr = BLKADDR_NPA; 265 goto exit; 266 case BLKTYPE_NIX: 267 /* For now assume NIX0 */ 268 if (!pcifunc) { 269 blkaddr = BLKADDR_NIX0; 270 goto exit; 271 } 272 break; 273 case BLKTYPE_SSO: 274 blkaddr = BLKADDR_SSO; 275 goto exit; 276 case BLKTYPE_SSOW: 277 blkaddr = BLKADDR_SSOW; 278 goto exit; 279 case BLKTYPE_TIM: 280 blkaddr = BLKADDR_TIM; 281 goto exit; 282 case BLKTYPE_CPT: 283 /* For now assume CPT0 */ 284 if (!pcifunc) { 285 blkaddr = BLKADDR_CPT0; 286 goto exit; 287 } 288 break; 289 } 290 291 /* Check if this is a RVU PF or VF */ 292 if (pcifunc & RVU_PFVF_FUNC_MASK) { 293 is_pf = false; 294 devnum = rvu_get_hwvf(rvu, pcifunc); 295 } else { 296 is_pf = true; 297 devnum = rvu_get_pf(pcifunc); 298 } 299 300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 301 * 'BLKADDR_NIX1'. 302 */ 303 if (blktype == BLKTYPE_NIX) { 304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 305 RVU_PRIV_HWVFX_NIXX_CFG(0); 306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 307 if (cfg) { 308 blkaddr = BLKADDR_NIX0; 309 goto exit; 310 } 311 312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 313 RVU_PRIV_HWVFX_NIXX_CFG(1); 314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 315 if (cfg) 316 blkaddr = BLKADDR_NIX1; 317 } 318 319 if (blktype == BLKTYPE_CPT) { 320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 321 RVU_PRIV_HWVFX_CPTX_CFG(0); 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 323 if (cfg) { 324 blkaddr = BLKADDR_CPT0; 325 goto exit; 326 } 327 328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 329 RVU_PRIV_HWVFX_CPTX_CFG(1); 330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 331 if (cfg) 332 blkaddr = BLKADDR_CPT1; 333 } 334 335 exit: 336 if (is_block_implemented(rvu->hw, blkaddr)) 337 return blkaddr; 338 return -ENODEV; 339 } 340 341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 342 struct rvu_block *block, u16 pcifunc, 343 u16 lf, bool attach) 344 { 345 int devnum, num_lfs = 0; 346 bool is_pf; 347 u64 reg; 348 349 if (lf >= block->lf.max) { 350 dev_err(&rvu->pdev->dev, 351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 352 __func__, lf, block->name, block->lf.max); 353 return; 354 } 355 356 /* Check if this is for a RVU PF or VF */ 357 if (pcifunc & RVU_PFVF_FUNC_MASK) { 358 is_pf = false; 359 devnum = rvu_get_hwvf(rvu, pcifunc); 360 } else { 361 is_pf = true; 362 devnum = rvu_get_pf(pcifunc); 363 } 364 365 block->fn_map[lf] = attach ? pcifunc : 0; 366 367 switch (block->addr) { 368 case BLKADDR_NPA: 369 pfvf->npalf = attach ? true : false; 370 num_lfs = pfvf->npalf; 371 break; 372 case BLKADDR_NIX0: 373 case BLKADDR_NIX1: 374 pfvf->nixlf = attach ? true : false; 375 num_lfs = pfvf->nixlf; 376 break; 377 case BLKADDR_SSO: 378 attach ? pfvf->sso++ : pfvf->sso--; 379 num_lfs = pfvf->sso; 380 break; 381 case BLKADDR_SSOW: 382 attach ? pfvf->ssow++ : pfvf->ssow--; 383 num_lfs = pfvf->ssow; 384 break; 385 case BLKADDR_TIM: 386 attach ? pfvf->timlfs++ : pfvf->timlfs--; 387 num_lfs = pfvf->timlfs; 388 break; 389 case BLKADDR_CPT0: 390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 391 num_lfs = pfvf->cptlfs; 392 break; 393 case BLKADDR_CPT1: 394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 395 num_lfs = pfvf->cpt1_lfs; 396 break; 397 } 398 399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 401 } 402 403 inline int rvu_get_pf(u16 pcifunc) 404 { 405 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 406 } 407 408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 409 { 410 u64 cfg; 411 412 /* Get numVFs attached to this PF and first HWVF */ 413 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 414 if (numvfs) 415 *numvfs = (cfg >> 12) & 0xFF; 416 if (hwvf) 417 *hwvf = cfg & 0xFFF; 418 } 419 420 int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 421 { 422 int pf, func; 423 u64 cfg; 424 425 pf = rvu_get_pf(pcifunc); 426 func = pcifunc & RVU_PFVF_FUNC_MASK; 427 428 /* Get first HWVF attached to this PF */ 429 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 430 431 return ((cfg & 0xFFF) + func - 1); 432 } 433 434 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 435 { 436 /* Check if it is a PF or VF */ 437 if (pcifunc & RVU_PFVF_FUNC_MASK) 438 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 439 else 440 return &rvu->pf[rvu_get_pf(pcifunc)]; 441 } 442 443 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 444 { 445 int pf, vf, nvfs; 446 u64 cfg; 447 448 pf = rvu_get_pf(pcifunc); 449 if (pf >= rvu->hw->total_pfs) 450 return false; 451 452 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 453 return true; 454 455 /* Check if VF is within number of VFs attached to this PF */ 456 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 457 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 458 nvfs = (cfg >> 12) & 0xFF; 459 if (vf >= nvfs) 460 return false; 461 462 return true; 463 } 464 465 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 466 { 467 struct rvu_block *block; 468 469 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 470 return false; 471 472 block = &hw->block[blkaddr]; 473 return block->implemented; 474 } 475 476 static void rvu_check_block_implemented(struct rvu *rvu) 477 { 478 struct rvu_hwinfo *hw = rvu->hw; 479 struct rvu_block *block; 480 int blkid; 481 u64 cfg; 482 483 /* For each block check if 'implemented' bit is set */ 484 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 485 block = &hw->block[blkid]; 486 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 487 if (cfg & BIT_ULL(11)) 488 block->implemented = true; 489 } 490 } 491 492 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 493 { 494 rvu_write64(rvu, BLKADDR_RVUM, 495 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 496 RVU_BLK_RVUM_REVID); 497 } 498 499 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 500 { 501 rvu_write64(rvu, BLKADDR_RVUM, 502 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 503 } 504 505 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 506 { 507 int err; 508 509 if (!block->implemented) 510 return 0; 511 512 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 513 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 514 true); 515 return err; 516 } 517 518 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 519 { 520 struct rvu_block *block = &rvu->hw->block[blkaddr]; 521 int err; 522 523 if (!block->implemented) 524 return; 525 526 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 527 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 528 if (err) { 529 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); 530 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) 531 ; 532 } 533 } 534 535 static void rvu_reset_all_blocks(struct rvu *rvu) 536 { 537 /* Do a HW reset of all RVU blocks */ 538 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 539 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 543 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 544 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 545 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 546 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 547 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 548 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 549 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 550 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 551 } 552 553 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 554 { 555 struct rvu_pfvf *pfvf; 556 u64 cfg; 557 int lf; 558 559 for (lf = 0; lf < block->lf.max; lf++) { 560 cfg = rvu_read64(rvu, block->addr, 561 block->lfcfg_reg | (lf << block->lfshift)); 562 if (!(cfg & BIT_ULL(63))) 563 continue; 564 565 /* Set this resource as being used */ 566 __set_bit(lf, block->lf.bmap); 567 568 /* Get, to whom this LF is attached */ 569 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 570 rvu_update_rsrc_map(rvu, pfvf, block, 571 (cfg >> 8) & 0xFFFF, lf, true); 572 573 /* Set start MSIX vector for this LF within this PF/VF */ 574 rvu_set_msix_offset(rvu, pfvf, block, lf); 575 } 576 } 577 578 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 579 { 580 int min_vecs; 581 582 if (!vf) 583 goto check_pf; 584 585 if (!nvecs) { 586 dev_warn(rvu->dev, 587 "PF%d:VF%d is configured with zero msix vectors, %d\n", 588 pf, vf - 1, nvecs); 589 } 590 return; 591 592 check_pf: 593 if (pf == 0) 594 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 595 else 596 min_vecs = RVU_PF_INT_VEC_CNT; 597 598 if (!(nvecs < min_vecs)) 599 return; 600 dev_warn(rvu->dev, 601 "PF%d is configured with too few vectors, %d, min is %d\n", 602 pf, nvecs, min_vecs); 603 } 604 605 static int rvu_setup_msix_resources(struct rvu *rvu) 606 { 607 struct rvu_hwinfo *hw = rvu->hw; 608 int pf, vf, numvfs, hwvf, err; 609 int nvecs, offset, max_msix; 610 struct rvu_pfvf *pfvf; 611 u64 cfg, phy_addr; 612 dma_addr_t iova; 613 614 for (pf = 0; pf < hw->total_pfs; pf++) { 615 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 616 /* If PF is not enabled, nothing to do */ 617 if (!((cfg >> 20) & 0x01)) 618 continue; 619 620 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 621 622 pfvf = &rvu->pf[pf]; 623 /* Get num of MSIX vectors attached to this PF */ 624 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 625 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 626 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 627 628 /* Alloc msix bitmap for this PF */ 629 err = rvu_alloc_bitmap(&pfvf->msix); 630 if (err) 631 return err; 632 633 /* Allocate memory for MSIX vector to RVU block LF mapping */ 634 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 635 sizeof(u16), GFP_KERNEL); 636 if (!pfvf->msix_lfmap) 637 return -ENOMEM; 638 639 /* For PF0 (AF) firmware will set msix vector offsets for 640 * AF, block AF and PF0_INT vectors, so jump to VFs. 641 */ 642 if (!pf) 643 goto setup_vfmsix; 644 645 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 646 * These are allocated on driver init and never freed, 647 * so no need to set 'msix_lfmap' for these. 648 */ 649 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 650 nvecs = (cfg >> 12) & 0xFF; 651 cfg &= ~0x7FFULL; 652 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 653 rvu_write64(rvu, BLKADDR_RVUM, 654 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 655 setup_vfmsix: 656 /* Alloc msix bitmap for VFs */ 657 for (vf = 0; vf < numvfs; vf++) { 658 pfvf = &rvu->hwvf[hwvf + vf]; 659 /* Get num of MSIX vectors attached to this VF */ 660 cfg = rvu_read64(rvu, BLKADDR_RVUM, 661 RVU_PRIV_PFX_MSIX_CFG(pf)); 662 pfvf->msix.max = (cfg & 0xFFF) + 1; 663 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 664 665 /* Alloc msix bitmap for this VF */ 666 err = rvu_alloc_bitmap(&pfvf->msix); 667 if (err) 668 return err; 669 670 pfvf->msix_lfmap = 671 devm_kcalloc(rvu->dev, pfvf->msix.max, 672 sizeof(u16), GFP_KERNEL); 673 if (!pfvf->msix_lfmap) 674 return -ENOMEM; 675 676 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 677 * These are allocated on driver init and never freed, 678 * so no need to set 'msix_lfmap' for these. 679 */ 680 cfg = rvu_read64(rvu, BLKADDR_RVUM, 681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 682 nvecs = (cfg >> 12) & 0xFF; 683 cfg &= ~0x7FFULL; 684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 685 rvu_write64(rvu, BLKADDR_RVUM, 686 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 687 cfg | offset); 688 } 689 } 690 691 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 692 * create an IOMMU mapping for the physical address configured by 693 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 694 */ 695 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 696 max_msix = cfg & 0xFFFFF; 697 if (rvu->fwdata && rvu->fwdata->msixtr_base) 698 phy_addr = rvu->fwdata->msixtr_base; 699 else 700 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 701 702 iova = dma_map_resource(rvu->dev, phy_addr, 703 max_msix * PCI_MSIX_ENTRY_SIZE, 704 DMA_BIDIRECTIONAL, 0); 705 706 if (dma_mapping_error(rvu->dev, iova)) 707 return -ENOMEM; 708 709 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 710 rvu->msix_base_iova = iova; 711 rvu->msixtr_base_phy = phy_addr; 712 713 return 0; 714 } 715 716 static void rvu_reset_msix(struct rvu *rvu) 717 { 718 /* Restore msixtr base register */ 719 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 720 rvu->msixtr_base_phy); 721 } 722 723 static void rvu_free_hw_resources(struct rvu *rvu) 724 { 725 struct rvu_hwinfo *hw = rvu->hw; 726 struct rvu_block *block; 727 struct rvu_pfvf *pfvf; 728 int id, max_msix; 729 u64 cfg; 730 731 rvu_npa_freemem(rvu); 732 rvu_npc_freemem(rvu); 733 rvu_nix_freemem(rvu); 734 735 /* Free block LF bitmaps */ 736 for (id = 0; id < BLK_COUNT; id++) { 737 block = &hw->block[id]; 738 kfree(block->lf.bmap); 739 } 740 741 /* Free MSIX bitmaps */ 742 for (id = 0; id < hw->total_pfs; id++) { 743 pfvf = &rvu->pf[id]; 744 kfree(pfvf->msix.bmap); 745 } 746 747 for (id = 0; id < hw->total_vfs; id++) { 748 pfvf = &rvu->hwvf[id]; 749 kfree(pfvf->msix.bmap); 750 } 751 752 /* Unmap MSIX vector base IOVA mapping */ 753 if (!rvu->msix_base_iova) 754 return; 755 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 756 max_msix = cfg & 0xFFFFF; 757 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 758 max_msix * PCI_MSIX_ENTRY_SIZE, 759 DMA_BIDIRECTIONAL, 0); 760 761 rvu_reset_msix(rvu); 762 mutex_destroy(&rvu->rsrc_lock); 763 } 764 765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 766 { 767 struct rvu_hwinfo *hw = rvu->hw; 768 int pf, vf, numvfs, hwvf; 769 struct rvu_pfvf *pfvf; 770 u64 *mac; 771 772 for (pf = 0; pf < hw->total_pfs; pf++) { 773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 774 if (!pf) 775 goto lbkvf; 776 777 if (!is_pf_cgxmapped(rvu, pf)) 778 continue; 779 /* Assign MAC address to PF */ 780 pfvf = &rvu->pf[pf]; 781 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 782 mac = &rvu->fwdata->pf_macs[pf]; 783 if (*mac) 784 u64_to_ether_addr(*mac, pfvf->mac_addr); 785 else 786 eth_random_addr(pfvf->mac_addr); 787 } else { 788 eth_random_addr(pfvf->mac_addr); 789 } 790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 791 792 lbkvf: 793 /* Assign MAC address to VFs*/ 794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 795 for (vf = 0; vf < numvfs; vf++, hwvf++) { 796 pfvf = &rvu->hwvf[hwvf]; 797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 798 mac = &rvu->fwdata->vf_macs[hwvf]; 799 if (*mac) 800 u64_to_ether_addr(*mac, pfvf->mac_addr); 801 else 802 eth_random_addr(pfvf->mac_addr); 803 } else { 804 eth_random_addr(pfvf->mac_addr); 805 } 806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 807 } 808 } 809 } 810 811 static int rvu_fwdata_init(struct rvu *rvu) 812 { 813 u64 fwdbase; 814 int err; 815 816 /* Get firmware data base address */ 817 err = cgx_get_fwdata_base(&fwdbase); 818 if (err) 819 goto fail; 820 821 BUILD_BUG_ON(offsetof(struct rvu_fwdata, cgx_fw_data) > FWDATA_CGX_LMAC_OFFSET); 822 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 823 if (!rvu->fwdata) 824 goto fail; 825 if (!is_rvu_fwdata_valid(rvu)) { 826 dev_err(rvu->dev, 827 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 828 iounmap(rvu->fwdata); 829 rvu->fwdata = NULL; 830 return -EINVAL; 831 } 832 return 0; 833 fail: 834 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 835 return -EIO; 836 } 837 838 static void rvu_fwdata_exit(struct rvu *rvu) 839 { 840 if (rvu->fwdata) 841 iounmap(rvu->fwdata); 842 } 843 844 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 845 { 846 struct rvu_hwinfo *hw = rvu->hw; 847 struct rvu_block *block; 848 int blkid; 849 u64 cfg; 850 851 /* Init NIX LF's bitmap */ 852 block = &hw->block[blkaddr]; 853 if (!block->implemented) 854 return 0; 855 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 856 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 857 block->lf.max = cfg & 0xFFF; 858 block->addr = blkaddr; 859 block->type = BLKTYPE_NIX; 860 block->lfshift = 8; 861 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 862 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 863 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 864 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 865 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 866 block->lfreset_reg = NIX_AF_LF_RST; 867 block->rvu = rvu; 868 sprintf(block->name, "NIX%d", blkid); 869 rvu->nix_blkaddr[blkid] = blkaddr; 870 return rvu_alloc_bitmap(&block->lf); 871 } 872 873 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 874 { 875 struct rvu_hwinfo *hw = rvu->hw; 876 struct rvu_block *block; 877 int blkid; 878 u64 cfg; 879 880 /* Init CPT LF's bitmap */ 881 block = &hw->block[blkaddr]; 882 if (!block->implemented) 883 return 0; 884 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 885 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 886 block->lf.max = cfg & 0xFF; 887 block->addr = blkaddr; 888 block->type = BLKTYPE_CPT; 889 block->multislot = true; 890 block->lfshift = 3; 891 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 892 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 893 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 894 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 895 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 896 block->lfreset_reg = CPT_AF_LF_RST; 897 block->rvu = rvu; 898 sprintf(block->name, "CPT%d", blkid); 899 return rvu_alloc_bitmap(&block->lf); 900 } 901 902 static void rvu_get_lbk_bufsize(struct rvu *rvu) 903 { 904 struct pci_dev *pdev = NULL; 905 void __iomem *base; 906 u64 lbk_const; 907 908 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 909 PCI_DEVID_OCTEONTX2_LBK, pdev); 910 if (!pdev) 911 return; 912 913 base = pci_ioremap_bar(pdev, 0); 914 if (!base) 915 goto err_put; 916 917 lbk_const = readq(base + LBK_CONST); 918 919 /* cache fifo size */ 920 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 921 922 iounmap(base); 923 err_put: 924 pci_dev_put(pdev); 925 } 926 927 static int rvu_setup_hw_resources(struct rvu *rvu) 928 { 929 struct rvu_hwinfo *hw = rvu->hw; 930 struct rvu_block *block; 931 int blkid, err; 932 u64 cfg; 933 934 /* Get HW supported max RVU PF & VF count */ 935 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 936 hw->total_pfs = (cfg >> 32) & 0xFF; 937 hw->total_vfs = (cfg >> 20) & 0xFFF; 938 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 939 940 if (!is_rvu_otx2(rvu)) 941 rvu_apr_block_cn10k_init(rvu); 942 943 /* Init NPA LF's bitmap */ 944 block = &hw->block[BLKADDR_NPA]; 945 if (!block->implemented) 946 goto nix; 947 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 948 block->lf.max = (cfg >> 16) & 0xFFF; 949 block->addr = BLKADDR_NPA; 950 block->type = BLKTYPE_NPA; 951 block->lfshift = 8; 952 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 953 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 954 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 955 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 956 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 957 block->lfreset_reg = NPA_AF_LF_RST; 958 block->rvu = rvu; 959 sprintf(block->name, "NPA"); 960 err = rvu_alloc_bitmap(&block->lf); 961 if (err) { 962 dev_err(rvu->dev, 963 "%s: Failed to allocate NPA LF bitmap\n", __func__); 964 return err; 965 } 966 967 nix: 968 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 969 if (err) { 970 dev_err(rvu->dev, 971 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 972 return err; 973 } 974 975 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 976 if (err) { 977 dev_err(rvu->dev, 978 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 979 return err; 980 } 981 982 /* Init SSO group's bitmap */ 983 block = &hw->block[BLKADDR_SSO]; 984 if (!block->implemented) 985 goto ssow; 986 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 987 block->lf.max = cfg & 0xFFFF; 988 block->addr = BLKADDR_SSO; 989 block->type = BLKTYPE_SSO; 990 block->multislot = true; 991 block->lfshift = 3; 992 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 993 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 994 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 995 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 996 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 997 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 998 block->rvu = rvu; 999 sprintf(block->name, "SSO GROUP"); 1000 err = rvu_alloc_bitmap(&block->lf); 1001 if (err) { 1002 dev_err(rvu->dev, 1003 "%s: Failed to allocate SSO LF bitmap\n", __func__); 1004 return err; 1005 } 1006 1007 ssow: 1008 /* Init SSO workslot's bitmap */ 1009 block = &hw->block[BLKADDR_SSOW]; 1010 if (!block->implemented) 1011 goto tim; 1012 block->lf.max = (cfg >> 56) & 0xFF; 1013 block->addr = BLKADDR_SSOW; 1014 block->type = BLKTYPE_SSOW; 1015 block->multislot = true; 1016 block->lfshift = 3; 1017 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1018 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1019 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1020 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1021 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1022 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1023 block->rvu = rvu; 1024 sprintf(block->name, "SSOWS"); 1025 err = rvu_alloc_bitmap(&block->lf); 1026 if (err) { 1027 dev_err(rvu->dev, 1028 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1029 return err; 1030 } 1031 1032 tim: 1033 /* Init TIM LF's bitmap */ 1034 block = &hw->block[BLKADDR_TIM]; 1035 if (!block->implemented) 1036 goto cpt; 1037 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1038 block->lf.max = cfg & 0xFFFF; 1039 block->addr = BLKADDR_TIM; 1040 block->type = BLKTYPE_TIM; 1041 block->multislot = true; 1042 block->lfshift = 3; 1043 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1044 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1045 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1046 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1047 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1048 block->lfreset_reg = TIM_AF_LF_RST; 1049 block->rvu = rvu; 1050 sprintf(block->name, "TIM"); 1051 err = rvu_alloc_bitmap(&block->lf); 1052 if (err) { 1053 dev_err(rvu->dev, 1054 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1055 return err; 1056 } 1057 1058 cpt: 1059 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1060 if (err) { 1061 dev_err(rvu->dev, 1062 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1063 return err; 1064 } 1065 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1066 if (err) { 1067 dev_err(rvu->dev, 1068 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1069 return err; 1070 } 1071 1072 /* Allocate memory for PFVF data */ 1073 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1074 sizeof(struct rvu_pfvf), GFP_KERNEL); 1075 if (!rvu->pf) { 1076 dev_err(rvu->dev, 1077 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1078 return -ENOMEM; 1079 } 1080 1081 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1082 sizeof(struct rvu_pfvf), GFP_KERNEL); 1083 if (!rvu->hwvf) { 1084 dev_err(rvu->dev, 1085 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1086 return -ENOMEM; 1087 } 1088 1089 mutex_init(&rvu->rsrc_lock); 1090 1091 rvu_fwdata_init(rvu); 1092 1093 err = rvu_setup_msix_resources(rvu); 1094 if (err) { 1095 dev_err(rvu->dev, 1096 "%s: Failed to setup MSIX resources\n", __func__); 1097 return err; 1098 } 1099 1100 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1101 block = &hw->block[blkid]; 1102 if (!block->lf.bmap) 1103 continue; 1104 1105 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1106 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1107 sizeof(u16), GFP_KERNEL); 1108 if (!block->fn_map) { 1109 err = -ENOMEM; 1110 goto msix_err; 1111 } 1112 1113 /* Scan all blocks to check if low level firmware has 1114 * already provisioned any of the resources to a PF/VF. 1115 */ 1116 rvu_scan_block(rvu, block); 1117 } 1118 1119 err = rvu_set_channels_base(rvu); 1120 if (err) 1121 goto msix_err; 1122 1123 err = rvu_npc_init(rvu); 1124 if (err) { 1125 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1126 goto npc_err; 1127 } 1128 1129 err = rvu_cgx_init(rvu); 1130 if (err) { 1131 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1132 goto cgx_err; 1133 } 1134 1135 err = rvu_npc_exact_init(rvu); 1136 if (err) { 1137 dev_err(rvu->dev, "failed to initialize exact match table\n"); 1138 return err; 1139 } 1140 1141 /* Assign MACs for CGX mapped functions */ 1142 rvu_setup_pfvf_macaddress(rvu); 1143 1144 err = rvu_npa_init(rvu); 1145 if (err) { 1146 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1147 goto npa_err; 1148 } 1149 1150 rvu_get_lbk_bufsize(rvu); 1151 1152 err = rvu_nix_init(rvu); 1153 if (err) { 1154 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1155 goto nix_err; 1156 } 1157 1158 err = rvu_sdp_init(rvu); 1159 if (err) { 1160 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1161 goto nix_err; 1162 } 1163 1164 rvu_program_channels(rvu); 1165 cgx_start_linkup(rvu); 1166 1167 err = rvu_mcs_init(rvu); 1168 if (err) { 1169 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); 1170 goto nix_err; 1171 } 1172 1173 err = rvu_cpt_init(rvu); 1174 if (err) { 1175 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__); 1176 goto mcs_err; 1177 } 1178 1179 return 0; 1180 1181 mcs_err: 1182 rvu_mcs_exit(rvu); 1183 nix_err: 1184 rvu_nix_freemem(rvu); 1185 npa_err: 1186 rvu_npa_freemem(rvu); 1187 cgx_err: 1188 rvu_cgx_exit(rvu); 1189 npc_err: 1190 rvu_npc_freemem(rvu); 1191 rvu_fwdata_exit(rvu); 1192 msix_err: 1193 rvu_reset_msix(rvu); 1194 return err; 1195 } 1196 1197 /* NPA and NIX admin queue APIs */ 1198 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1199 { 1200 if (!aq) 1201 return; 1202 1203 qmem_free(rvu->dev, aq->inst); 1204 qmem_free(rvu->dev, aq->res); 1205 devm_kfree(rvu->dev, aq); 1206 } 1207 1208 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1209 int qsize, int inst_size, int res_size) 1210 { 1211 struct admin_queue *aq; 1212 int err; 1213 1214 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1215 if (!*ad_queue) 1216 return -ENOMEM; 1217 aq = *ad_queue; 1218 1219 /* Alloc memory for instructions i.e AQ */ 1220 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1221 if (err) { 1222 devm_kfree(rvu->dev, aq); 1223 return err; 1224 } 1225 1226 /* Alloc memory for results */ 1227 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1228 if (err) { 1229 rvu_aq_free(rvu, aq); 1230 return err; 1231 } 1232 1233 spin_lock_init(&aq->lock); 1234 return 0; 1235 } 1236 1237 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1238 struct ready_msg_rsp *rsp) 1239 { 1240 if (rvu->fwdata) { 1241 rsp->rclk_freq = rvu->fwdata->rclk; 1242 rsp->sclk_freq = rvu->fwdata->sclk; 1243 } 1244 return 0; 1245 } 1246 1247 /* Get current count of a RVU block's LF/slots 1248 * provisioned to a given RVU func. 1249 */ 1250 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1251 { 1252 switch (blkaddr) { 1253 case BLKADDR_NPA: 1254 return pfvf->npalf ? 1 : 0; 1255 case BLKADDR_NIX0: 1256 case BLKADDR_NIX1: 1257 return pfvf->nixlf ? 1 : 0; 1258 case BLKADDR_SSO: 1259 return pfvf->sso; 1260 case BLKADDR_SSOW: 1261 return pfvf->ssow; 1262 case BLKADDR_TIM: 1263 return pfvf->timlfs; 1264 case BLKADDR_CPT0: 1265 return pfvf->cptlfs; 1266 case BLKADDR_CPT1: 1267 return pfvf->cpt1_lfs; 1268 } 1269 return 0; 1270 } 1271 1272 /* Return true if LFs of block type are attached to pcifunc */ 1273 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1274 { 1275 switch (blktype) { 1276 case BLKTYPE_NPA: 1277 return pfvf->npalf ? 1 : 0; 1278 case BLKTYPE_NIX: 1279 return pfvf->nixlf ? 1 : 0; 1280 case BLKTYPE_SSO: 1281 return !!pfvf->sso; 1282 case BLKTYPE_SSOW: 1283 return !!pfvf->ssow; 1284 case BLKTYPE_TIM: 1285 return !!pfvf->timlfs; 1286 case BLKTYPE_CPT: 1287 return pfvf->cptlfs || pfvf->cpt1_lfs; 1288 } 1289 1290 return false; 1291 } 1292 1293 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1294 { 1295 struct rvu_pfvf *pfvf; 1296 1297 if (!is_pf_func_valid(rvu, pcifunc)) 1298 return false; 1299 1300 pfvf = rvu_get_pfvf(rvu, pcifunc); 1301 1302 /* Check if this PFFUNC has a LF of type blktype attached */ 1303 if (!is_blktype_attached(pfvf, blktype)) 1304 return false; 1305 1306 return true; 1307 } 1308 1309 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1310 int pcifunc, int slot) 1311 { 1312 u64 val; 1313 1314 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1315 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1316 /* Wait for the lookup to finish */ 1317 /* TODO: put some timeout here */ 1318 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1319 ; 1320 1321 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1322 1323 /* Check LF valid bit */ 1324 if (!(val & (1ULL << 12))) 1325 return -1; 1326 1327 return (val & 0xFFF); 1328 } 1329 1330 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1331 u16 global_slot, u16 *slot_in_block) 1332 { 1333 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1334 int numlfs, total_lfs = 0, nr_blocks = 0; 1335 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1336 struct rvu_block *block; 1337 int blkaddr; 1338 u16 start_slot; 1339 1340 if (!is_blktype_attached(pfvf, blktype)) 1341 return -ENODEV; 1342 1343 /* Get all the block addresses from which LFs are attached to 1344 * the given pcifunc in num_blkaddr[]. 1345 */ 1346 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1347 block = &rvu->hw->block[blkaddr]; 1348 if (block->type != blktype) 1349 continue; 1350 if (!is_block_implemented(rvu->hw, blkaddr)) 1351 continue; 1352 1353 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1354 if (numlfs) { 1355 total_lfs += numlfs; 1356 num_blkaddr[nr_blocks] = blkaddr; 1357 nr_blocks++; 1358 } 1359 } 1360 1361 if (global_slot >= total_lfs) 1362 return -ENODEV; 1363 1364 /* Based on the given global slot number retrieve the 1365 * correct block address out of all attached block 1366 * addresses and slot number in that block. 1367 */ 1368 total_lfs = 0; 1369 blkaddr = -ENODEV; 1370 for (i = 0; i < nr_blocks; i++) { 1371 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1372 total_lfs += numlfs; 1373 if (global_slot < total_lfs) { 1374 blkaddr = num_blkaddr[i]; 1375 start_slot = total_lfs - numlfs; 1376 *slot_in_block = global_slot - start_slot; 1377 break; 1378 } 1379 } 1380 1381 return blkaddr; 1382 } 1383 1384 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1385 { 1386 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1387 struct rvu_hwinfo *hw = rvu->hw; 1388 struct rvu_block *block; 1389 int slot, lf, num_lfs; 1390 int blkaddr; 1391 1392 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1393 if (blkaddr < 0) 1394 return; 1395 1396 1397 block = &hw->block[blkaddr]; 1398 1399 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1400 if (!num_lfs) 1401 return; 1402 1403 for (slot = 0; slot < num_lfs; slot++) { 1404 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1405 if (lf < 0) /* This should never happen */ 1406 continue; 1407 1408 if (blktype == BLKTYPE_NIX) { 1409 rvu_nix_reset_mac(pfvf, pcifunc); 1410 rvu_npc_clear_ucast_entry(rvu, pcifunc, lf); 1411 } 1412 /* Disable the LF */ 1413 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1414 (lf << block->lfshift), 0x00ULL); 1415 1416 /* Update SW maintained mapping info as well */ 1417 rvu_update_rsrc_map(rvu, pfvf, block, 1418 pcifunc, lf, false); 1419 1420 /* Free the resource */ 1421 rvu_free_rsrc(&block->lf, lf); 1422 1423 /* Clear MSIX vector offset for this LF */ 1424 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1425 } 1426 } 1427 1428 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1429 u16 pcifunc) 1430 { 1431 struct rvu_hwinfo *hw = rvu->hw; 1432 bool detach_all = true; 1433 struct rvu_block *block; 1434 int blkid; 1435 1436 mutex_lock(&rvu->rsrc_lock); 1437 1438 /* Check for partial resource detach */ 1439 if (detach && detach->partial) 1440 detach_all = false; 1441 1442 /* Check for RVU block's LFs attached to this func, 1443 * if so, detach them. 1444 */ 1445 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1446 block = &hw->block[blkid]; 1447 if (!block->lf.bmap) 1448 continue; 1449 if (!detach_all && detach) { 1450 if (blkid == BLKADDR_NPA && !detach->npalf) 1451 continue; 1452 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1453 continue; 1454 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1455 continue; 1456 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1457 continue; 1458 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1459 continue; 1460 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1461 continue; 1462 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1463 continue; 1464 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1465 continue; 1466 } 1467 rvu_detach_block(rvu, pcifunc, block->type); 1468 } 1469 1470 mutex_unlock(&rvu->rsrc_lock); 1471 return 0; 1472 } 1473 1474 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1475 struct rsrc_detach *detach, 1476 struct msg_rsp *rsp) 1477 { 1478 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1479 } 1480 1481 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1482 { 1483 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1484 int blkaddr = BLKADDR_NIX0, vf; 1485 struct rvu_pfvf *pf; 1486 1487 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1488 1489 /* All CGX mapped PFs are set with assigned NIX block during init */ 1490 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1491 blkaddr = pf->nix_blkaddr; 1492 } else if (is_lbk_vf(rvu, pcifunc)) { 1493 vf = pcifunc - 1; 1494 /* Assign NIX based on VF number. All even numbered VFs get 1495 * NIX0 and odd numbered gets NIX1 1496 */ 1497 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1498 /* NIX1 is not present on all silicons */ 1499 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1500 blkaddr = BLKADDR_NIX0; 1501 } 1502 1503 /* if SDP1 then the blkaddr is NIX1 */ 1504 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1505 blkaddr = BLKADDR_NIX1; 1506 1507 switch (blkaddr) { 1508 case BLKADDR_NIX1: 1509 pfvf->nix_blkaddr = BLKADDR_NIX1; 1510 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1511 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1512 break; 1513 case BLKADDR_NIX0: 1514 default: 1515 pfvf->nix_blkaddr = BLKADDR_NIX0; 1516 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1517 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1518 break; 1519 } 1520 1521 return pfvf->nix_blkaddr; 1522 } 1523 1524 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1525 u16 pcifunc, struct rsrc_attach *attach) 1526 { 1527 int blkaddr; 1528 1529 switch (blktype) { 1530 case BLKTYPE_NIX: 1531 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1532 break; 1533 case BLKTYPE_CPT: 1534 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1535 return rvu_get_blkaddr(rvu, blktype, 0); 1536 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1537 BLKADDR_CPT0; 1538 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1539 return -ENODEV; 1540 break; 1541 default: 1542 return rvu_get_blkaddr(rvu, blktype, 0); 1543 } 1544 1545 if (is_block_implemented(rvu->hw, blkaddr)) 1546 return blkaddr; 1547 1548 return -ENODEV; 1549 } 1550 1551 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1552 int num_lfs, struct rsrc_attach *attach) 1553 { 1554 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1555 struct rvu_hwinfo *hw = rvu->hw; 1556 struct rvu_block *block; 1557 int slot, lf; 1558 int blkaddr; 1559 u64 cfg; 1560 1561 if (!num_lfs) 1562 return; 1563 1564 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1565 if (blkaddr < 0) 1566 return; 1567 1568 block = &hw->block[blkaddr]; 1569 if (!block->lf.bmap) 1570 return; 1571 1572 for (slot = 0; slot < num_lfs; slot++) { 1573 /* Allocate the resource */ 1574 lf = rvu_alloc_rsrc(&block->lf); 1575 if (lf < 0) 1576 return; 1577 1578 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1579 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1580 (lf << block->lfshift), cfg); 1581 rvu_update_rsrc_map(rvu, pfvf, block, 1582 pcifunc, lf, true); 1583 1584 /* Set start MSIX vector for this LF within this PF/VF */ 1585 rvu_set_msix_offset(rvu, pfvf, block, lf); 1586 } 1587 } 1588 1589 static int rvu_check_rsrc_availability(struct rvu *rvu, 1590 struct rsrc_attach *req, u16 pcifunc) 1591 { 1592 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1593 int free_lfs, mappedlfs, blkaddr; 1594 struct rvu_hwinfo *hw = rvu->hw; 1595 struct rvu_block *block; 1596 1597 /* Only one NPA LF can be attached */ 1598 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1599 block = &hw->block[BLKADDR_NPA]; 1600 free_lfs = rvu_rsrc_free_count(&block->lf); 1601 if (!free_lfs) 1602 goto fail; 1603 } else if (req->npalf) { 1604 dev_err(&rvu->pdev->dev, 1605 "Func 0x%x: Invalid req, already has NPA\n", 1606 pcifunc); 1607 return -EINVAL; 1608 } 1609 1610 /* Only one NIX LF can be attached */ 1611 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1612 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1613 pcifunc, req); 1614 if (blkaddr < 0) 1615 return blkaddr; 1616 block = &hw->block[blkaddr]; 1617 free_lfs = rvu_rsrc_free_count(&block->lf); 1618 if (!free_lfs) 1619 goto fail; 1620 } else if (req->nixlf) { 1621 dev_err(&rvu->pdev->dev, 1622 "Func 0x%x: Invalid req, already has NIX\n", 1623 pcifunc); 1624 return -EINVAL; 1625 } 1626 1627 if (req->sso) { 1628 block = &hw->block[BLKADDR_SSO]; 1629 /* Is request within limits ? */ 1630 if (req->sso > block->lf.max) { 1631 dev_err(&rvu->pdev->dev, 1632 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1633 pcifunc, req->sso, block->lf.max); 1634 return -EINVAL; 1635 } 1636 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1637 free_lfs = rvu_rsrc_free_count(&block->lf); 1638 /* Check if additional resources are available */ 1639 if (req->sso > mappedlfs && 1640 ((req->sso - mappedlfs) > free_lfs)) 1641 goto fail; 1642 } 1643 1644 if (req->ssow) { 1645 block = &hw->block[BLKADDR_SSOW]; 1646 if (req->ssow > block->lf.max) { 1647 dev_err(&rvu->pdev->dev, 1648 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1649 pcifunc, req->ssow, block->lf.max); 1650 return -EINVAL; 1651 } 1652 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1653 free_lfs = rvu_rsrc_free_count(&block->lf); 1654 if (req->ssow > mappedlfs && 1655 ((req->ssow - mappedlfs) > free_lfs)) 1656 goto fail; 1657 } 1658 1659 if (req->timlfs) { 1660 block = &hw->block[BLKADDR_TIM]; 1661 if (req->timlfs > block->lf.max) { 1662 dev_err(&rvu->pdev->dev, 1663 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1664 pcifunc, req->timlfs, block->lf.max); 1665 return -EINVAL; 1666 } 1667 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1668 free_lfs = rvu_rsrc_free_count(&block->lf); 1669 if (req->timlfs > mappedlfs && 1670 ((req->timlfs - mappedlfs) > free_lfs)) 1671 goto fail; 1672 } 1673 1674 if (req->cptlfs) { 1675 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1676 pcifunc, req); 1677 if (blkaddr < 0) 1678 return blkaddr; 1679 block = &hw->block[blkaddr]; 1680 if (req->cptlfs > block->lf.max) { 1681 dev_err(&rvu->pdev->dev, 1682 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1683 pcifunc, req->cptlfs, block->lf.max); 1684 return -EINVAL; 1685 } 1686 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1687 free_lfs = rvu_rsrc_free_count(&block->lf); 1688 if (req->cptlfs > mappedlfs && 1689 ((req->cptlfs - mappedlfs) > free_lfs)) 1690 goto fail; 1691 } 1692 1693 return 0; 1694 1695 fail: 1696 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1697 return -ENOSPC; 1698 } 1699 1700 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1701 struct rsrc_attach *attach) 1702 { 1703 int blkaddr, num_lfs; 1704 1705 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1706 attach->hdr.pcifunc, attach); 1707 if (blkaddr < 0) 1708 return false; 1709 1710 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1711 blkaddr); 1712 /* Requester already has LFs from given block ? */ 1713 return !!num_lfs; 1714 } 1715 1716 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1717 struct rsrc_attach *attach, 1718 struct msg_rsp *rsp) 1719 { 1720 u16 pcifunc = attach->hdr.pcifunc; 1721 int err; 1722 1723 /* If first request, detach all existing attached resources */ 1724 if (!attach->modify) 1725 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1726 1727 mutex_lock(&rvu->rsrc_lock); 1728 1729 /* Check if the request can be accommodated */ 1730 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1731 if (err) 1732 goto exit; 1733 1734 /* Now attach the requested resources */ 1735 if (attach->npalf) 1736 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1737 1738 if (attach->nixlf) 1739 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1740 1741 if (attach->sso) { 1742 /* RVU func doesn't know which exact LF or slot is attached 1743 * to it, it always sees as slot 0,1,2. So for a 'modify' 1744 * request, simply detach all existing attached LFs/slots 1745 * and attach a fresh. 1746 */ 1747 if (attach->modify) 1748 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1749 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1750 attach->sso, attach); 1751 } 1752 1753 if (attach->ssow) { 1754 if (attach->modify) 1755 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1756 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1757 attach->ssow, attach); 1758 } 1759 1760 if (attach->timlfs) { 1761 if (attach->modify) 1762 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1763 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1764 attach->timlfs, attach); 1765 } 1766 1767 if (attach->cptlfs) { 1768 if (attach->modify && 1769 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1770 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1771 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1772 attach->cptlfs, attach); 1773 } 1774 1775 exit: 1776 mutex_unlock(&rvu->rsrc_lock); 1777 return err; 1778 } 1779 1780 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1781 int blkaddr, int lf) 1782 { 1783 u16 vec; 1784 1785 if (lf < 0) 1786 return MSIX_VECTOR_INVALID; 1787 1788 for (vec = 0; vec < pfvf->msix.max; vec++) { 1789 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1790 return vec; 1791 } 1792 return MSIX_VECTOR_INVALID; 1793 } 1794 1795 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1796 struct rvu_block *block, int lf) 1797 { 1798 u16 nvecs, vec, offset; 1799 u64 cfg; 1800 1801 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1802 (lf << block->lfshift)); 1803 nvecs = (cfg >> 12) & 0xFF; 1804 1805 /* Check and alloc MSIX vectors, must be contiguous */ 1806 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1807 return; 1808 1809 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1810 1811 /* Config MSIX offset in LF */ 1812 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1813 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1814 1815 /* Update the bitmap as well */ 1816 for (vec = 0; vec < nvecs; vec++) 1817 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1818 } 1819 1820 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1821 struct rvu_block *block, int lf) 1822 { 1823 u16 nvecs, vec, offset; 1824 u64 cfg; 1825 1826 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1827 (lf << block->lfshift)); 1828 nvecs = (cfg >> 12) & 0xFF; 1829 1830 /* Clear MSIX offset in LF */ 1831 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1832 (lf << block->lfshift), cfg & ~0x7FFULL); 1833 1834 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1835 1836 /* Update the mapping */ 1837 for (vec = 0; vec < nvecs; vec++) 1838 pfvf->msix_lfmap[offset + vec] = 0; 1839 1840 /* Free the same in MSIX bitmap */ 1841 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1842 } 1843 1844 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1845 struct msix_offset_rsp *rsp) 1846 { 1847 struct rvu_hwinfo *hw = rvu->hw; 1848 u16 pcifunc = req->hdr.pcifunc; 1849 struct rvu_pfvf *pfvf; 1850 int lf, slot, blkaddr; 1851 1852 pfvf = rvu_get_pfvf(rvu, pcifunc); 1853 if (!pfvf->msix.bmap) 1854 return 0; 1855 1856 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1857 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1858 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1859 1860 /* Get BLKADDR from which LFs are attached to pcifunc */ 1861 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1862 if (blkaddr < 0) { 1863 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1864 } else { 1865 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1866 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1867 } 1868 1869 rsp->sso = pfvf->sso; 1870 for (slot = 0; slot < rsp->sso; slot++) { 1871 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1872 rsp->sso_msixoff[slot] = 1873 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1874 } 1875 1876 rsp->ssow = pfvf->ssow; 1877 for (slot = 0; slot < rsp->ssow; slot++) { 1878 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1879 rsp->ssow_msixoff[slot] = 1880 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1881 } 1882 1883 rsp->timlfs = pfvf->timlfs; 1884 for (slot = 0; slot < rsp->timlfs; slot++) { 1885 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1886 rsp->timlf_msixoff[slot] = 1887 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1888 } 1889 1890 rsp->cptlfs = pfvf->cptlfs; 1891 for (slot = 0; slot < rsp->cptlfs; slot++) { 1892 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1893 rsp->cptlf_msixoff[slot] = 1894 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1895 } 1896 1897 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1898 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1899 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1900 rsp->cpt1_lf_msixoff[slot] = 1901 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1902 } 1903 1904 return 0; 1905 } 1906 1907 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1908 struct free_rsrcs_rsp *rsp) 1909 { 1910 struct rvu_hwinfo *hw = rvu->hw; 1911 struct rvu_block *block; 1912 struct nix_txsch *txsch; 1913 struct nix_hw *nix_hw; 1914 1915 mutex_lock(&rvu->rsrc_lock); 1916 1917 block = &hw->block[BLKADDR_NPA]; 1918 rsp->npa = rvu_rsrc_free_count(&block->lf); 1919 1920 block = &hw->block[BLKADDR_NIX0]; 1921 rsp->nix = rvu_rsrc_free_count(&block->lf); 1922 1923 block = &hw->block[BLKADDR_NIX1]; 1924 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1925 1926 block = &hw->block[BLKADDR_SSO]; 1927 rsp->sso = rvu_rsrc_free_count(&block->lf); 1928 1929 block = &hw->block[BLKADDR_SSOW]; 1930 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1931 1932 block = &hw->block[BLKADDR_TIM]; 1933 rsp->tim = rvu_rsrc_free_count(&block->lf); 1934 1935 block = &hw->block[BLKADDR_CPT0]; 1936 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1937 1938 block = &hw->block[BLKADDR_CPT1]; 1939 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1940 1941 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1942 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1943 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1944 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1945 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1946 /* NIX1 */ 1947 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1948 goto out; 1949 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1950 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1951 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1952 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1953 } else { 1954 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1955 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1956 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1957 rvu_rsrc_free_count(&txsch->schq); 1958 1959 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1960 rsp->schq[NIX_TXSCH_LVL_TL4] = 1961 rvu_rsrc_free_count(&txsch->schq); 1962 1963 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1964 rsp->schq[NIX_TXSCH_LVL_TL3] = 1965 rvu_rsrc_free_count(&txsch->schq); 1966 1967 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1968 rsp->schq[NIX_TXSCH_LVL_TL2] = 1969 rvu_rsrc_free_count(&txsch->schq); 1970 1971 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1972 goto out; 1973 1974 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1975 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1976 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1977 rvu_rsrc_free_count(&txsch->schq); 1978 1979 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1980 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1981 rvu_rsrc_free_count(&txsch->schq); 1982 1983 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1984 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1985 rvu_rsrc_free_count(&txsch->schq); 1986 1987 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1988 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1989 rvu_rsrc_free_count(&txsch->schq); 1990 } 1991 1992 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1993 out: 1994 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1995 mutex_unlock(&rvu->rsrc_lock); 1996 1997 return 0; 1998 } 1999 2000 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 2001 struct msg_rsp *rsp) 2002 { 2003 u16 pcifunc = req->hdr.pcifunc; 2004 u16 vf, numvfs; 2005 u64 cfg; 2006 2007 vf = pcifunc & RVU_PFVF_FUNC_MASK; 2008 cfg = rvu_read64(rvu, BLKADDR_RVUM, 2009 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 2010 numvfs = (cfg >> 12) & 0xFF; 2011 2012 if (vf && vf <= numvfs) 2013 __rvu_flr_handler(rvu, pcifunc); 2014 else 2015 return RVU_INVALID_VF_ID; 2016 2017 return 0; 2018 } 2019 2020 int rvu_ndc_sync(struct rvu *rvu, int lfblkaddr, int lfidx, u64 lfoffset) 2021 { 2022 /* Sync cached info for this LF in NDC to LLC/DRAM */ 2023 rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx); 2024 return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true); 2025 } 2026 2027 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2028 struct get_hw_cap_rsp *rsp) 2029 { 2030 struct rvu_hwinfo *hw = rvu->hw; 2031 2032 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 2033 rsp->nix_shaping = hw->cap.nix_shaping; 2034 rsp->npc_hash_extract = hw->cap.npc_hash_extract; 2035 2036 if (rvu->mcs_blk_cnt) 2037 rsp->hw_caps = HW_CAP_MACSEC; 2038 2039 return 0; 2040 } 2041 2042 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 2043 struct msg_rsp *rsp) 2044 { 2045 struct rvu_hwinfo *hw = rvu->hw; 2046 u16 pcifunc = req->hdr.pcifunc; 2047 struct rvu_pfvf *pfvf; 2048 int blkaddr, nixlf; 2049 u16 target; 2050 2051 /* Only PF can add VF permissions */ 2052 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_lbk_vf(rvu, pcifunc)) 2053 return -EOPNOTSUPP; 2054 2055 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2056 pfvf = rvu_get_pfvf(rvu, target); 2057 2058 if (req->flags & RESET_VF_PERM) { 2059 pfvf->flags &= RVU_CLEAR_VF_PERM; 2060 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2061 (req->flags & VF_TRUSTED)) { 2062 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2063 /* disable multicast and promisc entries */ 2064 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2065 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2066 if (blkaddr < 0) 2067 return 0; 2068 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2069 target, 0); 2070 if (nixlf < 0) 2071 return 0; 2072 npc_enadis_default_mce_entry(rvu, target, nixlf, 2073 NIXLF_ALLMULTI_ENTRY, 2074 false); 2075 npc_enadis_default_mce_entry(rvu, target, nixlf, 2076 NIXLF_PROMISC_ENTRY, 2077 false); 2078 } 2079 } 2080 2081 return 0; 2082 } 2083 2084 int rvu_mbox_handler_ndc_sync_op(struct rvu *rvu, 2085 struct ndc_sync_op *req, 2086 struct msg_rsp *rsp) 2087 { 2088 struct rvu_hwinfo *hw = rvu->hw; 2089 u16 pcifunc = req->hdr.pcifunc; 2090 int err, lfidx, lfblkaddr; 2091 2092 if (req->npa_lf_sync) { 2093 /* Get NPA LF data */ 2094 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); 2095 if (lfblkaddr < 0) 2096 return NPA_AF_ERR_AF_LF_INVALID; 2097 2098 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2099 if (lfidx < 0) 2100 return NPA_AF_ERR_AF_LF_INVALID; 2101 2102 /* Sync NPA NDC */ 2103 err = rvu_ndc_sync(rvu, lfblkaddr, 2104 lfidx, NPA_AF_NDC_SYNC); 2105 if (err) 2106 dev_err(rvu->dev, 2107 "NDC-NPA sync failed for LF %u\n", lfidx); 2108 } 2109 2110 if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync) 2111 return 0; 2112 2113 /* Get NIX LF data */ 2114 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2115 if (lfblkaddr < 0) 2116 return NIX_AF_ERR_AF_LF_INVALID; 2117 2118 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2119 if (lfidx < 0) 2120 return NIX_AF_ERR_AF_LF_INVALID; 2121 2122 if (req->nix_lf_tx_sync) { 2123 /* Sync NIX TX NDC */ 2124 err = rvu_ndc_sync(rvu, lfblkaddr, 2125 lfidx, NIX_AF_NDC_TX_SYNC); 2126 if (err) 2127 dev_err(rvu->dev, 2128 "NDC-NIX-TX sync fail for LF %u\n", lfidx); 2129 } 2130 2131 if (req->nix_lf_rx_sync) { 2132 /* Sync NIX RX NDC */ 2133 err = rvu_ndc_sync(rvu, lfblkaddr, 2134 lfidx, NIX_AF_NDC_RX_SYNC); 2135 if (err) 2136 dev_err(rvu->dev, 2137 "NDC-NIX-RX sync failed for LF %u\n", lfidx); 2138 } 2139 2140 return 0; 2141 } 2142 2143 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2144 struct mbox_msghdr *req) 2145 { 2146 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2147 2148 /* Check if valid, if not reply with a invalid msg */ 2149 if (req->sig != OTX2_MBOX_REQ_SIG) 2150 goto bad_message; 2151 2152 switch (req->id) { 2153 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2154 case _id: { \ 2155 struct _rsp_type *rsp; \ 2156 int err; \ 2157 \ 2158 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2159 mbox, devid, \ 2160 sizeof(struct _rsp_type)); \ 2161 /* some handlers should complete even if reply */ \ 2162 /* could not be allocated */ \ 2163 if (!rsp && \ 2164 _id != MBOX_MSG_DETACH_RESOURCES && \ 2165 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2166 _id != MBOX_MSG_VF_FLR) \ 2167 return -ENOMEM; \ 2168 if (rsp) { \ 2169 rsp->hdr.id = _id; \ 2170 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2171 rsp->hdr.pcifunc = req->pcifunc; \ 2172 rsp->hdr.rc = 0; \ 2173 } \ 2174 \ 2175 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2176 (struct _req_type *)req, \ 2177 rsp); \ 2178 if (rsp && err) \ 2179 rsp->hdr.rc = err; \ 2180 \ 2181 trace_otx2_msg_process(mbox->pdev, _id, err, req->pcifunc); \ 2182 return rsp ? err : -ENOMEM; \ 2183 } 2184 MBOX_MESSAGES 2185 #undef M 2186 2187 bad_message: 2188 default: 2189 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2190 return -ENODEV; 2191 } 2192 } 2193 2194 static void __rvu_mbox_handler(struct rvu_work *mwork, int type, bool poll) 2195 { 2196 struct rvu *rvu = mwork->rvu; 2197 int offset, err, id, devid; 2198 struct otx2_mbox_dev *mdev; 2199 struct mbox_hdr *req_hdr; 2200 struct mbox_msghdr *msg; 2201 struct mbox_wq_info *mw; 2202 struct otx2_mbox *mbox; 2203 2204 switch (type) { 2205 case TYPE_AFPF: 2206 mw = &rvu->afpf_wq_info; 2207 break; 2208 case TYPE_AFVF: 2209 mw = &rvu->afvf_wq_info; 2210 break; 2211 default: 2212 return; 2213 } 2214 2215 devid = mwork - mw->mbox_wrk; 2216 mbox = &mw->mbox; 2217 mdev = &mbox->dev[devid]; 2218 2219 /* Process received mbox messages */ 2220 req_hdr = mdev->mbase + mbox->rx_start; 2221 if (mw->mbox_wrk[devid].num_msgs == 0) 2222 return; 2223 2224 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2225 2226 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2227 msg = mdev->mbase + offset; 2228 2229 /* Set which PF/VF sent this message based on mbox IRQ */ 2230 switch (type) { 2231 case TYPE_AFPF: 2232 msg->pcifunc &= 2233 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2234 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2235 break; 2236 case TYPE_AFVF: 2237 msg->pcifunc &= 2238 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2239 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2240 break; 2241 } 2242 2243 err = rvu_process_mbox_msg(mbox, devid, msg); 2244 if (!err) { 2245 offset = mbox->rx_start + msg->next_msgoff; 2246 continue; 2247 } 2248 2249 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2250 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2251 err, otx2_mbox_id2name(msg->id), 2252 msg->id, rvu_get_pf(msg->pcifunc), 2253 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2254 else 2255 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2256 err, otx2_mbox_id2name(msg->id), 2257 msg->id, devid); 2258 } 2259 mw->mbox_wrk[devid].num_msgs = 0; 2260 2261 if (poll) 2262 otx2_mbox_wait_for_zero(mbox, devid); 2263 2264 /* Send mbox responses to VF/PF */ 2265 otx2_mbox_msg_send(mbox, devid); 2266 } 2267 2268 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2269 { 2270 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2271 struct rvu *rvu = mwork->rvu; 2272 2273 mutex_lock(&rvu->mbox_lock); 2274 __rvu_mbox_handler(mwork, TYPE_AFPF, true); 2275 mutex_unlock(&rvu->mbox_lock); 2276 } 2277 2278 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2279 { 2280 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2281 2282 __rvu_mbox_handler(mwork, TYPE_AFVF, false); 2283 } 2284 2285 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2286 { 2287 struct rvu *rvu = mwork->rvu; 2288 struct otx2_mbox_dev *mdev; 2289 struct mbox_hdr *rsp_hdr; 2290 struct mbox_msghdr *msg; 2291 struct mbox_wq_info *mw; 2292 struct otx2_mbox *mbox; 2293 int offset, id, devid; 2294 2295 switch (type) { 2296 case TYPE_AFPF: 2297 mw = &rvu->afpf_wq_info; 2298 break; 2299 case TYPE_AFVF: 2300 mw = &rvu->afvf_wq_info; 2301 break; 2302 default: 2303 return; 2304 } 2305 2306 devid = mwork - mw->mbox_wrk_up; 2307 mbox = &mw->mbox_up; 2308 mdev = &mbox->dev[devid]; 2309 2310 rsp_hdr = mdev->mbase + mbox->rx_start; 2311 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2312 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2313 return; 2314 } 2315 2316 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2317 2318 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2319 msg = mdev->mbase + offset; 2320 2321 if (msg->id >= MBOX_MSG_MAX) { 2322 dev_err(rvu->dev, 2323 "Mbox msg with unknown ID 0x%x\n", msg->id); 2324 goto end; 2325 } 2326 2327 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2328 dev_err(rvu->dev, 2329 "Mbox msg with wrong signature %x, ID 0x%x\n", 2330 msg->sig, msg->id); 2331 goto end; 2332 } 2333 2334 switch (msg->id) { 2335 case MBOX_MSG_CGX_LINK_EVENT: 2336 break; 2337 default: 2338 if (msg->rc) 2339 dev_err(rvu->dev, 2340 "Mbox msg response has err %d, ID 0x%x\n", 2341 msg->rc, msg->id); 2342 break; 2343 } 2344 end: 2345 offset = mbox->rx_start + msg->next_msgoff; 2346 mdev->msgs_acked++; 2347 } 2348 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2349 2350 otx2_mbox_reset(mbox, devid); 2351 } 2352 2353 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2354 { 2355 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2356 2357 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2358 } 2359 2360 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2361 { 2362 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2363 2364 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2365 } 2366 2367 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2368 int num, int type, unsigned long *pf_bmap) 2369 { 2370 struct rvu_hwinfo *hw = rvu->hw; 2371 int region; 2372 u64 bar4; 2373 2374 /* For cn10k platform VF mailbox regions of a PF follows after the 2375 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2376 * RVU_PF_VF_BAR4_ADDR register. 2377 */ 2378 if (type == TYPE_AFVF) { 2379 for (region = 0; region < num; region++) { 2380 if (!test_bit(region, pf_bmap)) 2381 continue; 2382 2383 if (hw->cap.per_pf_mbox_regs) { 2384 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2385 RVU_AF_PFX_BAR4_ADDR(0)) + 2386 MBOX_SIZE; 2387 bar4 += region * MBOX_SIZE; 2388 } else { 2389 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2390 bar4 += region * MBOX_SIZE; 2391 } 2392 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2393 if (!mbox_addr[region]) 2394 goto error; 2395 } 2396 return 0; 2397 } 2398 2399 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2400 * PF registers. Whereas for Octeontx2 it is read from 2401 * RVU_AF_PF_BAR4_ADDR register. 2402 */ 2403 for (region = 0; region < num; region++) { 2404 if (!test_bit(region, pf_bmap)) 2405 continue; 2406 2407 if (hw->cap.per_pf_mbox_regs) { 2408 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2409 RVU_AF_PFX_BAR4_ADDR(region)); 2410 } else { 2411 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2412 RVU_AF_PF_BAR4_ADDR); 2413 bar4 += region * MBOX_SIZE; 2414 } 2415 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2416 if (!mbox_addr[region]) 2417 goto error; 2418 } 2419 return 0; 2420 2421 error: 2422 while (region--) 2423 iounmap((void __iomem *)mbox_addr[region]); 2424 return -ENOMEM; 2425 } 2426 2427 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2428 int type, int num, 2429 void (mbox_handler)(struct work_struct *), 2430 void (mbox_up_handler)(struct work_struct *)) 2431 { 2432 int err = -EINVAL, i, dir, dir_up; 2433 void __iomem *reg_base; 2434 struct rvu_work *mwork; 2435 unsigned long *pf_bmap; 2436 void **mbox_regions; 2437 const char *name; 2438 u64 cfg; 2439 2440 pf_bmap = bitmap_zalloc(num, GFP_KERNEL); 2441 if (!pf_bmap) 2442 return -ENOMEM; 2443 2444 /* RVU VFs */ 2445 if (type == TYPE_AFVF) 2446 bitmap_set(pf_bmap, 0, num); 2447 2448 if (type == TYPE_AFPF) { 2449 /* Mark enabled PFs in bitmap */ 2450 for (i = 0; i < num; i++) { 2451 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i)); 2452 if (cfg & BIT_ULL(20)) 2453 set_bit(i, pf_bmap); 2454 } 2455 } 2456 2457 mutex_init(&rvu->mbox_lock); 2458 2459 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2460 if (!mbox_regions) { 2461 err = -ENOMEM; 2462 goto free_bitmap; 2463 } 2464 2465 switch (type) { 2466 case TYPE_AFPF: 2467 name = "rvu_afpf_mailbox"; 2468 dir = MBOX_DIR_AFPF; 2469 dir_up = MBOX_DIR_AFPF_UP; 2470 reg_base = rvu->afreg_base; 2471 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap); 2472 if (err) 2473 goto free_regions; 2474 break; 2475 case TYPE_AFVF: 2476 name = "rvu_afvf_mailbox"; 2477 dir = MBOX_DIR_PFVF; 2478 dir_up = MBOX_DIR_PFVF_UP; 2479 reg_base = rvu->pfreg_base; 2480 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap); 2481 if (err) 2482 goto free_regions; 2483 break; 2484 default: 2485 goto free_regions; 2486 } 2487 2488 mw->mbox_wq = alloc_workqueue("%s", 2489 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2490 num, name); 2491 if (!mw->mbox_wq) { 2492 err = -ENOMEM; 2493 goto unmap_regions; 2494 } 2495 2496 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2497 sizeof(struct rvu_work), GFP_KERNEL); 2498 if (!mw->mbox_wrk) { 2499 err = -ENOMEM; 2500 goto exit; 2501 } 2502 2503 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2504 sizeof(struct rvu_work), GFP_KERNEL); 2505 if (!mw->mbox_wrk_up) { 2506 err = -ENOMEM; 2507 goto exit; 2508 } 2509 2510 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2511 reg_base, dir, num, pf_bmap); 2512 if (err) 2513 goto exit; 2514 2515 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2516 reg_base, dir_up, num, pf_bmap); 2517 if (err) 2518 goto exit; 2519 2520 for (i = 0; i < num; i++) { 2521 if (!test_bit(i, pf_bmap)) 2522 continue; 2523 2524 mwork = &mw->mbox_wrk[i]; 2525 mwork->rvu = rvu; 2526 INIT_WORK(&mwork->work, mbox_handler); 2527 2528 mwork = &mw->mbox_wrk_up[i]; 2529 mwork->rvu = rvu; 2530 INIT_WORK(&mwork->work, mbox_up_handler); 2531 } 2532 goto free_regions; 2533 2534 exit: 2535 destroy_workqueue(mw->mbox_wq); 2536 unmap_regions: 2537 while (num--) 2538 iounmap((void __iomem *)mbox_regions[num]); 2539 free_regions: 2540 kfree(mbox_regions); 2541 free_bitmap: 2542 bitmap_free(pf_bmap); 2543 return err; 2544 } 2545 2546 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2547 { 2548 struct otx2_mbox *mbox = &mw->mbox; 2549 struct otx2_mbox_dev *mdev; 2550 int devid; 2551 2552 if (mw->mbox_wq) { 2553 destroy_workqueue(mw->mbox_wq); 2554 mw->mbox_wq = NULL; 2555 } 2556 2557 for (devid = 0; devid < mbox->ndevs; devid++) { 2558 mdev = &mbox->dev[devid]; 2559 if (mdev->hwbase) 2560 iounmap((void __iomem *)mdev->hwbase); 2561 } 2562 2563 otx2_mbox_destroy(&mw->mbox); 2564 otx2_mbox_destroy(&mw->mbox_up); 2565 } 2566 2567 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2568 int mdevs, u64 intr) 2569 { 2570 struct otx2_mbox_dev *mdev; 2571 struct otx2_mbox *mbox; 2572 struct mbox_hdr *hdr; 2573 int i; 2574 2575 for (i = first; i < mdevs; i++) { 2576 /* start from 0 */ 2577 if (!(intr & BIT_ULL(i - first))) 2578 continue; 2579 2580 mbox = &mw->mbox; 2581 mdev = &mbox->dev[i]; 2582 hdr = mdev->mbase + mbox->rx_start; 2583 2584 /*The hdr->num_msgs is set to zero immediately in the interrupt 2585 * handler to ensure that it holds a correct value next time 2586 * when the interrupt handler is called. 2587 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2588 * pf>mbox.up_num_msgs holds the data for use in 2589 * pfaf_mbox_up_handler. 2590 */ 2591 2592 if (hdr->num_msgs) { 2593 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2594 hdr->num_msgs = 0; 2595 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2596 } 2597 mbox = &mw->mbox_up; 2598 mdev = &mbox->dev[i]; 2599 hdr = mdev->mbase + mbox->rx_start; 2600 if (hdr->num_msgs) { 2601 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2602 hdr->num_msgs = 0; 2603 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2604 } 2605 } 2606 } 2607 2608 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) 2609 { 2610 struct rvu *rvu = (struct rvu *)rvu_irq; 2611 u64 intr; 2612 2613 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2614 /* Clear interrupts */ 2615 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2616 if (intr) 2617 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2618 2619 /* Sync with mbox memory region */ 2620 rmb(); 2621 2622 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2623 2624 return IRQ_HANDLED; 2625 } 2626 2627 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2628 { 2629 struct rvu *rvu = (struct rvu *)rvu_irq; 2630 int vfs = rvu->vfs; 2631 u64 intr; 2632 2633 /* Sync with mbox memory region */ 2634 rmb(); 2635 2636 /* Handle VF interrupts */ 2637 if (vfs > 64) { 2638 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2639 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2640 2641 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2642 vfs = 64; 2643 } 2644 2645 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2646 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2647 if (intr) 2648 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2649 2650 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2651 2652 return IRQ_HANDLED; 2653 } 2654 2655 static void rvu_enable_mbox_intr(struct rvu *rvu) 2656 { 2657 struct rvu_hwinfo *hw = rvu->hw; 2658 2659 /* Clear spurious irqs, if any */ 2660 rvu_write64(rvu, BLKADDR_RVUM, 2661 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2662 2663 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2664 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2665 INTR_MASK(hw->total_pfs) & ~1ULL); 2666 } 2667 2668 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2669 { 2670 struct rvu_block *block; 2671 int slot, lf, num_lfs; 2672 int err; 2673 2674 block = &rvu->hw->block[blkaddr]; 2675 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2676 block->addr); 2677 if (!num_lfs) 2678 return; 2679 for (slot = 0; slot < num_lfs; slot++) { 2680 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2681 if (lf < 0) 2682 continue; 2683 2684 /* Cleanup LF and reset it */ 2685 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2686 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2687 else if (block->addr == BLKADDR_NPA) 2688 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2689 else if ((block->addr == BLKADDR_CPT0) || 2690 (block->addr == BLKADDR_CPT1)) 2691 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, 2692 slot); 2693 2694 err = rvu_lf_reset(rvu, block, lf); 2695 if (err) { 2696 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2697 block->addr, lf); 2698 } 2699 } 2700 } 2701 2702 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2703 { 2704 if (rvu_npc_exact_has_match_table(rvu)) 2705 rvu_npc_exact_reset(rvu, pcifunc); 2706 2707 mutex_lock(&rvu->flr_lock); 2708 /* Reset order should reflect inter-block dependencies: 2709 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2710 * 2. Flush and reset SSO/SSOW 2711 * 3. Cleanup pools (NPA) 2712 */ 2713 2714 /* Free allocated BPIDs */ 2715 rvu_nix_flr_free_bpids(rvu, pcifunc); 2716 2717 /* Free multicast/mirror node associated with the 'pcifunc' */ 2718 rvu_nix_mcast_flr_free_entries(rvu, pcifunc); 2719 2720 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2721 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2722 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2723 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2724 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2725 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2726 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2727 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2728 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2729 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2730 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM 2731 * entries, check and free the MCAM entries explicitly to avoid leak. 2732 * Since LF is detached use LF number as -1. 2733 */ 2734 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); 2735 rvu_mac_reset(rvu, pcifunc); 2736 2737 if (rvu->mcs_blk_cnt) 2738 rvu_mcs_flr_handler(rvu, pcifunc); 2739 2740 mutex_unlock(&rvu->flr_lock); 2741 } 2742 2743 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2744 { 2745 int reg = 0; 2746 2747 /* pcifunc = 0(PF0) | (vf + 1) */ 2748 __rvu_flr_handler(rvu, vf + 1); 2749 2750 if (vf >= 64) { 2751 reg = 1; 2752 vf = vf - 64; 2753 } 2754 2755 /* Signal FLR finish and enable IRQ */ 2756 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2757 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2758 } 2759 2760 static void rvu_flr_handler(struct work_struct *work) 2761 { 2762 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2763 struct rvu *rvu = flrwork->rvu; 2764 u16 pcifunc, numvfs, vf; 2765 u64 cfg; 2766 int pf; 2767 2768 pf = flrwork - rvu->flr_wrk; 2769 if (pf >= rvu->hw->total_pfs) { 2770 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2771 return; 2772 } 2773 2774 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2775 numvfs = (cfg >> 12) & 0xFF; 2776 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2777 2778 for (vf = 0; vf < numvfs; vf++) 2779 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2780 2781 __rvu_flr_handler(rvu, pcifunc); 2782 2783 /* Signal FLR finish */ 2784 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2785 2786 /* Enable interrupt */ 2787 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2788 } 2789 2790 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2791 { 2792 int dev, vf, reg = 0; 2793 u64 intr; 2794 2795 if (start_vf >= 64) 2796 reg = 1; 2797 2798 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2799 if (!intr) 2800 return; 2801 2802 for (vf = 0; vf < numvfs; vf++) { 2803 if (!(intr & BIT_ULL(vf))) 2804 continue; 2805 /* Clear and disable the interrupt */ 2806 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2807 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2808 2809 dev = vf + start_vf + rvu->hw->total_pfs; 2810 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2811 } 2812 } 2813 2814 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2815 { 2816 struct rvu *rvu = (struct rvu *)rvu_irq; 2817 u64 intr; 2818 u8 pf; 2819 2820 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2821 if (!intr) 2822 goto afvf_flr; 2823 2824 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2825 if (intr & (1ULL << pf)) { 2826 /* clear interrupt */ 2827 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2828 BIT_ULL(pf)); 2829 /* Disable the interrupt */ 2830 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2831 BIT_ULL(pf)); 2832 /* PF is already dead do only AF related operations */ 2833 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2834 } 2835 } 2836 2837 afvf_flr: 2838 rvu_afvf_queue_flr_work(rvu, 0, 64); 2839 if (rvu->vfs > 64) 2840 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2841 2842 return IRQ_HANDLED; 2843 } 2844 2845 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2846 { 2847 int vf; 2848 2849 /* Nothing to be done here other than clearing the 2850 * TRPEND bit. 2851 */ 2852 for (vf = 0; vf < 64; vf++) { 2853 if (intr & (1ULL << vf)) { 2854 /* clear the trpend due to ME(master enable) */ 2855 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2856 /* clear interrupt */ 2857 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2858 } 2859 } 2860 } 2861 2862 /* Handles ME interrupts from VFs of AF */ 2863 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2864 { 2865 struct rvu *rvu = (struct rvu *)rvu_irq; 2866 int vfset; 2867 u64 intr; 2868 2869 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2870 2871 for (vfset = 0; vfset <= 1; vfset++) { 2872 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2873 if (intr) 2874 rvu_me_handle_vfset(rvu, vfset, intr); 2875 } 2876 2877 return IRQ_HANDLED; 2878 } 2879 2880 /* Handles ME interrupts from PFs */ 2881 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2882 { 2883 struct rvu *rvu = (struct rvu *)rvu_irq; 2884 u64 intr; 2885 u8 pf; 2886 2887 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2888 2889 /* Nothing to be done here other than clearing the 2890 * TRPEND bit. 2891 */ 2892 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2893 if (intr & (1ULL << pf)) { 2894 /* clear the trpend due to ME(master enable) */ 2895 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2896 BIT_ULL(pf)); 2897 /* clear interrupt */ 2898 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2899 BIT_ULL(pf)); 2900 } 2901 } 2902 2903 return IRQ_HANDLED; 2904 } 2905 2906 static void rvu_unregister_interrupts(struct rvu *rvu) 2907 { 2908 int irq; 2909 2910 rvu_cpt_unregister_interrupts(rvu); 2911 2912 /* Disable the Mbox interrupt */ 2913 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2914 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2915 2916 /* Disable the PF FLR interrupt */ 2917 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2918 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2919 2920 /* Disable the PF ME interrupt */ 2921 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2922 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2923 2924 for (irq = 0; irq < rvu->num_vec; irq++) { 2925 if (rvu->irq_allocated[irq]) { 2926 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2927 rvu->irq_allocated[irq] = false; 2928 } 2929 } 2930 2931 pci_free_irq_vectors(rvu->pdev); 2932 rvu->num_vec = 0; 2933 } 2934 2935 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2936 { 2937 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2938 int offset; 2939 2940 pfvf = &rvu->pf[0]; 2941 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2942 2943 /* Make sure there are enough MSIX vectors configured so that 2944 * VF interrupts can be handled. Offset equal to zero means 2945 * that PF vectors are not configured and overlapping AF vectors. 2946 */ 2947 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2948 offset; 2949 } 2950 2951 static int rvu_register_interrupts(struct rvu *rvu) 2952 { 2953 int ret, offset, pf_vec_start; 2954 2955 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2956 2957 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2958 NAME_SIZE, GFP_KERNEL); 2959 if (!rvu->irq_name) 2960 return -ENOMEM; 2961 2962 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2963 sizeof(bool), GFP_KERNEL); 2964 if (!rvu->irq_allocated) 2965 return -ENOMEM; 2966 2967 /* Enable MSI-X */ 2968 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2969 rvu->num_vec, PCI_IRQ_MSIX); 2970 if (ret < 0) { 2971 dev_err(rvu->dev, 2972 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2973 rvu->num_vec, ret); 2974 return ret; 2975 } 2976 2977 /* Register mailbox interrupt handler */ 2978 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2979 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2980 rvu_mbox_pf_intr_handler, 0, 2981 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2982 if (ret) { 2983 dev_err(rvu->dev, 2984 "RVUAF: IRQ registration failed for mbox irq\n"); 2985 goto fail; 2986 } 2987 2988 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2989 2990 /* Enable mailbox interrupts from all PFs */ 2991 rvu_enable_mbox_intr(rvu); 2992 2993 /* Register FLR interrupt handler */ 2994 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2995 "RVUAF FLR"); 2996 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2997 rvu_flr_intr_handler, 0, 2998 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2999 rvu); 3000 if (ret) { 3001 dev_err(rvu->dev, 3002 "RVUAF: IRQ registration failed for FLR\n"); 3003 goto fail; 3004 } 3005 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 3006 3007 /* Enable FLR interrupt for all PFs*/ 3008 rvu_write64(rvu, BLKADDR_RVUM, 3009 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 3010 3011 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 3012 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3013 3014 /* Register ME interrupt handler */ 3015 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3016 "RVUAF ME"); 3017 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 3018 rvu_me_pf_intr_handler, 0, 3019 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3020 rvu); 3021 if (ret) { 3022 dev_err(rvu->dev, 3023 "RVUAF: IRQ registration failed for ME\n"); 3024 } 3025 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 3026 3027 /* Clear TRPEND bit for all PF */ 3028 rvu_write64(rvu, BLKADDR_RVUM, 3029 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 3030 /* Enable ME interrupt for all PFs*/ 3031 rvu_write64(rvu, BLKADDR_RVUM, 3032 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 3033 3034 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 3035 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3036 3037 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 3038 return 0; 3039 3040 /* Get PF MSIX vectors offset. */ 3041 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 3042 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 3043 3044 /* Register MBOX0 interrupt. */ 3045 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 3046 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 3047 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3048 rvu_mbox_intr_handler, 0, 3049 &rvu->irq_name[offset * NAME_SIZE], 3050 rvu); 3051 if (ret) 3052 dev_err(rvu->dev, 3053 "RVUAF: IRQ registration failed for Mbox0\n"); 3054 3055 rvu->irq_allocated[offset] = true; 3056 3057 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 3058 * simply increment current offset by 1. 3059 */ 3060 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 3061 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 3062 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3063 rvu_mbox_intr_handler, 0, 3064 &rvu->irq_name[offset * NAME_SIZE], 3065 rvu); 3066 if (ret) 3067 dev_err(rvu->dev, 3068 "RVUAF: IRQ registration failed for Mbox1\n"); 3069 3070 rvu->irq_allocated[offset] = true; 3071 3072 /* Register FLR interrupt handler for AF's VFs */ 3073 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 3074 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 3075 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3076 rvu_flr_intr_handler, 0, 3077 &rvu->irq_name[offset * NAME_SIZE], rvu); 3078 if (ret) { 3079 dev_err(rvu->dev, 3080 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 3081 goto fail; 3082 } 3083 rvu->irq_allocated[offset] = true; 3084 3085 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 3086 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 3087 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3088 rvu_flr_intr_handler, 0, 3089 &rvu->irq_name[offset * NAME_SIZE], rvu); 3090 if (ret) { 3091 dev_err(rvu->dev, 3092 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 3093 goto fail; 3094 } 3095 rvu->irq_allocated[offset] = true; 3096 3097 /* Register ME interrupt handler for AF's VFs */ 3098 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 3099 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 3100 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3101 rvu_me_vf_intr_handler, 0, 3102 &rvu->irq_name[offset * NAME_SIZE], rvu); 3103 if (ret) { 3104 dev_err(rvu->dev, 3105 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 3106 goto fail; 3107 } 3108 rvu->irq_allocated[offset] = true; 3109 3110 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 3111 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 3112 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3113 rvu_me_vf_intr_handler, 0, 3114 &rvu->irq_name[offset * NAME_SIZE], rvu); 3115 if (ret) { 3116 dev_err(rvu->dev, 3117 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 3118 goto fail; 3119 } 3120 rvu->irq_allocated[offset] = true; 3121 3122 ret = rvu_cpt_register_interrupts(rvu); 3123 if (ret) 3124 goto fail; 3125 3126 return 0; 3127 3128 fail: 3129 rvu_unregister_interrupts(rvu); 3130 return ret; 3131 } 3132 3133 static void rvu_flr_wq_destroy(struct rvu *rvu) 3134 { 3135 if (rvu->flr_wq) { 3136 destroy_workqueue(rvu->flr_wq); 3137 rvu->flr_wq = NULL; 3138 } 3139 } 3140 3141 static int rvu_flr_init(struct rvu *rvu) 3142 { 3143 int dev, num_devs; 3144 u64 cfg; 3145 int pf; 3146 3147 /* Enable FLR for all PFs*/ 3148 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 3149 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 3150 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 3151 cfg | BIT_ULL(22)); 3152 } 3153 3154 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr", 3155 WQ_HIGHPRI | WQ_MEM_RECLAIM); 3156 if (!rvu->flr_wq) 3157 return -ENOMEM; 3158 3159 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 3160 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 3161 sizeof(struct rvu_work), GFP_KERNEL); 3162 if (!rvu->flr_wrk) { 3163 destroy_workqueue(rvu->flr_wq); 3164 return -ENOMEM; 3165 } 3166 3167 for (dev = 0; dev < num_devs; dev++) { 3168 rvu->flr_wrk[dev].rvu = rvu; 3169 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 3170 } 3171 3172 mutex_init(&rvu->flr_lock); 3173 3174 return 0; 3175 } 3176 3177 static void rvu_disable_afvf_intr(struct rvu *rvu) 3178 { 3179 int vfs = rvu->vfs; 3180 3181 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3182 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3183 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3184 if (vfs <= 64) 3185 return; 3186 3187 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3188 INTR_MASK(vfs - 64)); 3189 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3190 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3191 } 3192 3193 static void rvu_enable_afvf_intr(struct rvu *rvu) 3194 { 3195 int vfs = rvu->vfs; 3196 3197 /* Clear any pending interrupts and enable AF VF interrupts for 3198 * the first 64 VFs. 3199 */ 3200 /* Mbox */ 3201 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3202 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3203 3204 /* FLR */ 3205 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3206 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3207 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3208 3209 /* Same for remaining VFs, if any. */ 3210 if (vfs <= 64) 3211 return; 3212 3213 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3214 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3215 INTR_MASK(vfs - 64)); 3216 3217 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3218 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3219 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3220 } 3221 3222 int rvu_get_num_lbk_chans(void) 3223 { 3224 struct pci_dev *pdev; 3225 void __iomem *base; 3226 int ret = -EIO; 3227 3228 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3229 NULL); 3230 if (!pdev) 3231 goto err; 3232 3233 base = pci_ioremap_bar(pdev, 0); 3234 if (!base) 3235 goto err_put; 3236 3237 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3238 ret = (readq(base + 0x10) >> 32) & 0xffff; 3239 iounmap(base); 3240 err_put: 3241 pci_dev_put(pdev); 3242 err: 3243 return ret; 3244 } 3245 3246 static int rvu_enable_sriov(struct rvu *rvu) 3247 { 3248 struct pci_dev *pdev = rvu->pdev; 3249 int err, chans, vfs; 3250 int pos = 0; 3251 3252 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3253 dev_warn(&pdev->dev, 3254 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3255 return 0; 3256 } 3257 3258 /* Get RVU VFs device id */ 3259 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 3260 if (!pos) 3261 return 0; 3262 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid); 3263 3264 chans = rvu_get_num_lbk_chans(); 3265 if (chans < 0) 3266 return chans; 3267 3268 vfs = pci_sriov_get_totalvfs(pdev); 3269 3270 /* Limit VFs in case we have more VFs than LBK channels available. */ 3271 if (vfs > chans) 3272 vfs = chans; 3273 3274 if (!vfs) 3275 return 0; 3276 3277 /* LBK channel number 63 is used for switching packets between 3278 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3279 */ 3280 if (vfs > 62) 3281 vfs = 62; 3282 3283 /* Save VFs number for reference in VF interrupts handlers. 3284 * Since interrupts might start arriving during SRIOV enablement 3285 * ordinary API cannot be used to get number of enabled VFs. 3286 */ 3287 rvu->vfs = vfs; 3288 3289 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3290 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3291 if (err) 3292 return err; 3293 3294 rvu_enable_afvf_intr(rvu); 3295 /* Make sure IRQs are enabled before SRIOV. */ 3296 mb(); 3297 3298 err = pci_enable_sriov(pdev, vfs); 3299 if (err) { 3300 rvu_disable_afvf_intr(rvu); 3301 rvu_mbox_destroy(&rvu->afvf_wq_info); 3302 return err; 3303 } 3304 3305 return 0; 3306 } 3307 3308 static void rvu_disable_sriov(struct rvu *rvu) 3309 { 3310 rvu_disable_afvf_intr(rvu); 3311 rvu_mbox_destroy(&rvu->afvf_wq_info); 3312 pci_disable_sriov(rvu->pdev); 3313 } 3314 3315 static void rvu_update_module_params(struct rvu *rvu) 3316 { 3317 const char *default_pfl_name = "default"; 3318 3319 strscpy(rvu->mkex_pfl_name, 3320 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3321 strscpy(rvu->kpu_pfl_name, 3322 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3323 } 3324 3325 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3326 { 3327 struct device *dev = &pdev->dev; 3328 struct rvu *rvu; 3329 int err; 3330 3331 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3332 if (!rvu) 3333 return -ENOMEM; 3334 3335 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3336 if (!rvu->hw) { 3337 devm_kfree(dev, rvu); 3338 return -ENOMEM; 3339 } 3340 3341 pci_set_drvdata(pdev, rvu); 3342 rvu->pdev = pdev; 3343 rvu->dev = &pdev->dev; 3344 3345 err = pci_enable_device(pdev); 3346 if (err) { 3347 dev_err(dev, "Failed to enable PCI device\n"); 3348 goto err_freemem; 3349 } 3350 3351 err = pci_request_regions(pdev, DRV_NAME); 3352 if (err) { 3353 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3354 goto err_disable_device; 3355 } 3356 3357 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3358 if (err) { 3359 dev_err(dev, "DMA mask config failed, abort\n"); 3360 goto err_release_regions; 3361 } 3362 3363 pci_set_master(pdev); 3364 3365 rvu->ptp = ptp_get(); 3366 if (IS_ERR(rvu->ptp)) { 3367 err = PTR_ERR(rvu->ptp); 3368 if (err) 3369 goto err_release_regions; 3370 rvu->ptp = NULL; 3371 } 3372 3373 /* Map Admin function CSRs */ 3374 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3375 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3376 if (!rvu->afreg_base || !rvu->pfreg_base) { 3377 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3378 err = -ENOMEM; 3379 goto err_put_ptp; 3380 } 3381 3382 /* Store module params in rvu structure */ 3383 rvu_update_module_params(rvu); 3384 3385 /* Check which blocks the HW supports */ 3386 rvu_check_block_implemented(rvu); 3387 3388 rvu_reset_all_blocks(rvu); 3389 3390 rvu_setup_hw_capabilities(rvu); 3391 3392 err = rvu_setup_hw_resources(rvu); 3393 if (err) 3394 goto err_put_ptp; 3395 3396 /* Init mailbox btw AF and PFs */ 3397 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3398 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3399 rvu_afpf_mbox_up_handler); 3400 if (err) { 3401 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3402 goto err_hwsetup; 3403 } 3404 3405 err = rvu_flr_init(rvu); 3406 if (err) { 3407 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3408 goto err_mbox; 3409 } 3410 3411 err = rvu_register_interrupts(rvu); 3412 if (err) { 3413 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3414 goto err_flr; 3415 } 3416 3417 err = rvu_register_dl(rvu); 3418 if (err) { 3419 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3420 goto err_irq; 3421 } 3422 3423 rvu_setup_rvum_blk_revid(rvu); 3424 3425 /* Enable AF's VFs (if any) */ 3426 err = rvu_enable_sriov(rvu); 3427 if (err) { 3428 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3429 goto err_dl; 3430 } 3431 3432 /* Initialize debugfs */ 3433 rvu_dbg_init(rvu); 3434 3435 mutex_init(&rvu->rswitch.switch_lock); 3436 3437 if (rvu->fwdata) 3438 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3439 rvu->fwdata->ptp_ext_tstamp); 3440 3441 return 0; 3442 err_dl: 3443 rvu_unregister_dl(rvu); 3444 err_irq: 3445 rvu_unregister_interrupts(rvu); 3446 err_flr: 3447 rvu_flr_wq_destroy(rvu); 3448 err_mbox: 3449 rvu_mbox_destroy(&rvu->afpf_wq_info); 3450 err_hwsetup: 3451 rvu_cgx_exit(rvu); 3452 rvu_fwdata_exit(rvu); 3453 rvu_mcs_exit(rvu); 3454 rvu_reset_all_blocks(rvu); 3455 rvu_free_hw_resources(rvu); 3456 rvu_clear_rvum_blk_revid(rvu); 3457 err_put_ptp: 3458 ptp_put(rvu->ptp); 3459 err_release_regions: 3460 pci_release_regions(pdev); 3461 err_disable_device: 3462 pci_disable_device(pdev); 3463 err_freemem: 3464 pci_set_drvdata(pdev, NULL); 3465 devm_kfree(&pdev->dev, rvu->hw); 3466 devm_kfree(dev, rvu); 3467 return err; 3468 } 3469 3470 static void rvu_remove(struct pci_dev *pdev) 3471 { 3472 struct rvu *rvu = pci_get_drvdata(pdev); 3473 3474 rvu_dbg_exit(rvu); 3475 rvu_unregister_dl(rvu); 3476 rvu_unregister_interrupts(rvu); 3477 rvu_flr_wq_destroy(rvu); 3478 rvu_cgx_exit(rvu); 3479 rvu_fwdata_exit(rvu); 3480 rvu_mcs_exit(rvu); 3481 rvu_mbox_destroy(&rvu->afpf_wq_info); 3482 rvu_disable_sriov(rvu); 3483 rvu_reset_all_blocks(rvu); 3484 rvu_free_hw_resources(rvu); 3485 rvu_clear_rvum_blk_revid(rvu); 3486 ptp_put(rvu->ptp); 3487 pci_release_regions(pdev); 3488 pci_disable_device(pdev); 3489 pci_set_drvdata(pdev, NULL); 3490 3491 devm_kfree(&pdev->dev, rvu->hw); 3492 devm_kfree(&pdev->dev, rvu); 3493 } 3494 3495 static struct pci_driver rvu_driver = { 3496 .name = DRV_NAME, 3497 .id_table = rvu_id_table, 3498 .probe = rvu_probe, 3499 .remove = rvu_remove, 3500 }; 3501 3502 static int __init rvu_init_module(void) 3503 { 3504 int err; 3505 3506 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3507 3508 err = pci_register_driver(&cgx_driver); 3509 if (err < 0) 3510 return err; 3511 3512 err = pci_register_driver(&ptp_driver); 3513 if (err < 0) 3514 goto ptp_err; 3515 3516 err = pci_register_driver(&mcs_driver); 3517 if (err < 0) 3518 goto mcs_err; 3519 3520 err = pci_register_driver(&rvu_driver); 3521 if (err < 0) 3522 goto rvu_err; 3523 3524 return 0; 3525 rvu_err: 3526 pci_unregister_driver(&mcs_driver); 3527 mcs_err: 3528 pci_unregister_driver(&ptp_driver); 3529 ptp_err: 3530 pci_unregister_driver(&cgx_driver); 3531 3532 return err; 3533 } 3534 3535 static void __exit rvu_cleanup_module(void) 3536 { 3537 pci_unregister_driver(&rvu_driver); 3538 pci_unregister_driver(&mcs_driver); 3539 pci_unregister_driver(&ptp_driver); 3540 pci_unregister_driver(&cgx_driver); 3541 } 3542 3543 module_init(rvu_init_module); 3544 module_exit(rvu_cleanup_module); 3545