1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 #include "ptp.h" 22 23 #include "rvu_trace.h" 24 25 #define DRV_NAME "octeontx2-af" 26 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 27 28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 29 30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 33 struct rvu_block *block, int lf); 34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 35 36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 37 int type, int num, 38 void (mbox_handler)(struct work_struct *), 39 void (mbox_up_handler)(struct work_struct *)); 40 enum { 41 TYPE_AFVF, 42 TYPE_AFPF, 43 }; 44 45 /* Supported devices */ 46 static const struct pci_device_id rvu_id_table[] = { 47 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 48 { 0, } /* end of table */ 49 }; 50 51 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 52 MODULE_DESCRIPTION(DRV_STRING); 53 MODULE_LICENSE("GPL v2"); 54 MODULE_DEVICE_TABLE(pci, rvu_id_table); 55 56 static char *mkex_profile; /* MKEX profile name */ 57 module_param(mkex_profile, charp, 0000); 58 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 59 60 static void rvu_setup_hw_capabilities(struct rvu *rvu) 61 { 62 struct rvu_hwinfo *hw = rvu->hw; 63 64 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 65 hw->cap.nix_fixed_txschq_mapping = false; 66 hw->cap.nix_shaping = true; 67 hw->cap.nix_tx_link_bp = true; 68 hw->cap.nix_rx_multicast = true; 69 hw->rvu = rvu; 70 71 if (is_rvu_96xx_B0(rvu)) { 72 hw->cap.nix_fixed_txschq_mapping = true; 73 hw->cap.nix_txsch_per_cgx_lmac = 4; 74 hw->cap.nix_txsch_per_lbk_lmac = 132; 75 hw->cap.nix_txsch_per_sdp_lmac = 76; 76 hw->cap.nix_shaping = false; 77 hw->cap.nix_tx_link_bp = false; 78 if (is_rvu_96xx_A0(rvu)) 79 hw->cap.nix_rx_multicast = false; 80 } 81 } 82 83 /* Poll a RVU block's register 'offset', for a 'zero' 84 * or 'nonzero' at bits specified by 'mask' 85 */ 86 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 87 { 88 unsigned long timeout = jiffies + usecs_to_jiffies(10000); 89 void __iomem *reg; 90 u64 reg_val; 91 92 reg = rvu->afreg_base + ((block << 28) | offset); 93 again: 94 reg_val = readq(reg); 95 if (zero && !(reg_val & mask)) 96 return 0; 97 if (!zero && (reg_val & mask)) 98 return 0; 99 if (time_before(jiffies, timeout)) { 100 usleep_range(1, 5); 101 goto again; 102 } 103 return -EBUSY; 104 } 105 106 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 107 { 108 int id; 109 110 if (!rsrc->bmap) 111 return -EINVAL; 112 113 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 114 if (id >= rsrc->max) 115 return -ENOSPC; 116 117 __set_bit(id, rsrc->bmap); 118 119 return id; 120 } 121 122 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 123 { 124 int start; 125 126 if (!rsrc->bmap) 127 return -EINVAL; 128 129 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 130 if (start >= rsrc->max) 131 return -ENOSPC; 132 133 bitmap_set(rsrc->bmap, start, nrsrc); 134 return start; 135 } 136 137 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 138 { 139 if (!rsrc->bmap) 140 return; 141 if (start >= rsrc->max) 142 return; 143 144 bitmap_clear(rsrc->bmap, start, nrsrc); 145 } 146 147 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 148 { 149 int start; 150 151 if (!rsrc->bmap) 152 return false; 153 154 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 155 if (start >= rsrc->max) 156 return false; 157 158 return true; 159 } 160 161 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 162 { 163 if (!rsrc->bmap) 164 return; 165 166 __clear_bit(id, rsrc->bmap); 167 } 168 169 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 170 { 171 int used; 172 173 if (!rsrc->bmap) 174 return 0; 175 176 used = bitmap_weight(rsrc->bmap, rsrc->max); 177 return (rsrc->max - used); 178 } 179 180 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 181 { 182 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 183 sizeof(long), GFP_KERNEL); 184 if (!rsrc->bmap) 185 return -ENOMEM; 186 return 0; 187 } 188 189 /* Get block LF's HW index from a PF_FUNC's block slot number */ 190 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 191 { 192 u16 match = 0; 193 int lf; 194 195 mutex_lock(&rvu->rsrc_lock); 196 for (lf = 0; lf < block->lf.max; lf++) { 197 if (block->fn_map[lf] == pcifunc) { 198 if (slot == match) { 199 mutex_unlock(&rvu->rsrc_lock); 200 return lf; 201 } 202 match++; 203 } 204 } 205 mutex_unlock(&rvu->rsrc_lock); 206 return -ENODEV; 207 } 208 209 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 210 * Some silicon variants of OcteonTX2 supports 211 * multiple blocks of same type. 212 * 213 * @pcifunc has to be zero when no LF is yet attached. 214 * 215 * For a pcifunc if LFs are attached from multiple blocks of same type, then 216 * return blkaddr of first encountered block. 217 */ 218 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 219 { 220 int devnum, blkaddr = -ENODEV; 221 u64 cfg, reg; 222 bool is_pf; 223 224 switch (blktype) { 225 case BLKTYPE_NPC: 226 blkaddr = BLKADDR_NPC; 227 goto exit; 228 case BLKTYPE_NPA: 229 blkaddr = BLKADDR_NPA; 230 goto exit; 231 case BLKTYPE_NIX: 232 /* For now assume NIX0 */ 233 if (!pcifunc) { 234 blkaddr = BLKADDR_NIX0; 235 goto exit; 236 } 237 break; 238 case BLKTYPE_SSO: 239 blkaddr = BLKADDR_SSO; 240 goto exit; 241 case BLKTYPE_SSOW: 242 blkaddr = BLKADDR_SSOW; 243 goto exit; 244 case BLKTYPE_TIM: 245 blkaddr = BLKADDR_TIM; 246 goto exit; 247 case BLKTYPE_CPT: 248 /* For now assume CPT0 */ 249 if (!pcifunc) { 250 blkaddr = BLKADDR_CPT0; 251 goto exit; 252 } 253 break; 254 } 255 256 /* Check if this is a RVU PF or VF */ 257 if (pcifunc & RVU_PFVF_FUNC_MASK) { 258 is_pf = false; 259 devnum = rvu_get_hwvf(rvu, pcifunc); 260 } else { 261 is_pf = true; 262 devnum = rvu_get_pf(pcifunc); 263 } 264 265 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 266 * 'BLKADDR_NIX1'. 267 */ 268 if (blktype == BLKTYPE_NIX) { 269 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 270 RVU_PRIV_HWVFX_NIXX_CFG(0); 271 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 272 if (cfg) { 273 blkaddr = BLKADDR_NIX0; 274 goto exit; 275 } 276 277 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 278 RVU_PRIV_HWVFX_NIXX_CFG(1); 279 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 280 if (cfg) 281 blkaddr = BLKADDR_NIX1; 282 } 283 284 if (blktype == BLKTYPE_CPT) { 285 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 286 RVU_PRIV_HWVFX_CPTX_CFG(0); 287 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 288 if (cfg) { 289 blkaddr = BLKADDR_CPT0; 290 goto exit; 291 } 292 293 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 294 RVU_PRIV_HWVFX_CPTX_CFG(1); 295 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 296 if (cfg) 297 blkaddr = BLKADDR_CPT1; 298 } 299 300 exit: 301 if (is_block_implemented(rvu->hw, blkaddr)) 302 return blkaddr; 303 return -ENODEV; 304 } 305 306 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 307 struct rvu_block *block, u16 pcifunc, 308 u16 lf, bool attach) 309 { 310 int devnum, num_lfs = 0; 311 bool is_pf; 312 u64 reg; 313 314 if (lf >= block->lf.max) { 315 dev_err(&rvu->pdev->dev, 316 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 317 __func__, lf, block->name, block->lf.max); 318 return; 319 } 320 321 /* Check if this is for a RVU PF or VF */ 322 if (pcifunc & RVU_PFVF_FUNC_MASK) { 323 is_pf = false; 324 devnum = rvu_get_hwvf(rvu, pcifunc); 325 } else { 326 is_pf = true; 327 devnum = rvu_get_pf(pcifunc); 328 } 329 330 block->fn_map[lf] = attach ? pcifunc : 0; 331 332 switch (block->addr) { 333 case BLKADDR_NPA: 334 pfvf->npalf = attach ? true : false; 335 num_lfs = pfvf->npalf; 336 break; 337 case BLKADDR_NIX0: 338 case BLKADDR_NIX1: 339 pfvf->nixlf = attach ? true : false; 340 num_lfs = pfvf->nixlf; 341 break; 342 case BLKADDR_SSO: 343 attach ? pfvf->sso++ : pfvf->sso--; 344 num_lfs = pfvf->sso; 345 break; 346 case BLKADDR_SSOW: 347 attach ? pfvf->ssow++ : pfvf->ssow--; 348 num_lfs = pfvf->ssow; 349 break; 350 case BLKADDR_TIM: 351 attach ? pfvf->timlfs++ : pfvf->timlfs--; 352 num_lfs = pfvf->timlfs; 353 break; 354 case BLKADDR_CPT0: 355 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 356 num_lfs = pfvf->cptlfs; 357 break; 358 case BLKADDR_CPT1: 359 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 360 num_lfs = pfvf->cpt1_lfs; 361 break; 362 } 363 364 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 365 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 366 } 367 368 inline int rvu_get_pf(u16 pcifunc) 369 { 370 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 371 } 372 373 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 374 { 375 u64 cfg; 376 377 /* Get numVFs attached to this PF and first HWVF */ 378 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 379 *numvfs = (cfg >> 12) & 0xFF; 380 *hwvf = cfg & 0xFFF; 381 } 382 383 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 384 { 385 int pf, func; 386 u64 cfg; 387 388 pf = rvu_get_pf(pcifunc); 389 func = pcifunc & RVU_PFVF_FUNC_MASK; 390 391 /* Get first HWVF attached to this PF */ 392 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 393 394 return ((cfg & 0xFFF) + func - 1); 395 } 396 397 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 398 { 399 /* Check if it is a PF or VF */ 400 if (pcifunc & RVU_PFVF_FUNC_MASK) 401 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 402 else 403 return &rvu->pf[rvu_get_pf(pcifunc)]; 404 } 405 406 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 407 { 408 int pf, vf, nvfs; 409 u64 cfg; 410 411 pf = rvu_get_pf(pcifunc); 412 if (pf >= rvu->hw->total_pfs) 413 return false; 414 415 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 416 return true; 417 418 /* Check if VF is within number of VFs attached to this PF */ 419 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 420 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 421 nvfs = (cfg >> 12) & 0xFF; 422 if (vf >= nvfs) 423 return false; 424 425 return true; 426 } 427 428 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 429 { 430 struct rvu_block *block; 431 432 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 433 return false; 434 435 block = &hw->block[blkaddr]; 436 return block->implemented; 437 } 438 439 static void rvu_check_block_implemented(struct rvu *rvu) 440 { 441 struct rvu_hwinfo *hw = rvu->hw; 442 struct rvu_block *block; 443 int blkid; 444 u64 cfg; 445 446 /* For each block check if 'implemented' bit is set */ 447 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 448 block = &hw->block[blkid]; 449 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 450 if (cfg & BIT_ULL(11)) 451 block->implemented = true; 452 } 453 } 454 455 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 456 { 457 rvu_write64(rvu, BLKADDR_RVUM, 458 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 459 RVU_BLK_RVUM_REVID); 460 } 461 462 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 463 { 464 rvu_write64(rvu, BLKADDR_RVUM, 465 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 466 } 467 468 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 469 { 470 int err; 471 472 if (!block->implemented) 473 return 0; 474 475 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 476 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 477 true); 478 return err; 479 } 480 481 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 482 { 483 struct rvu_block *block = &rvu->hw->block[blkaddr]; 484 485 if (!block->implemented) 486 return; 487 488 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 489 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 490 } 491 492 static void rvu_reset_all_blocks(struct rvu *rvu) 493 { 494 /* Do a HW reset of all RVU blocks */ 495 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 496 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 497 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 498 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 499 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 500 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 501 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 502 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 503 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 504 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 505 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 506 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 507 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 508 } 509 510 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 511 { 512 struct rvu_pfvf *pfvf; 513 u64 cfg; 514 int lf; 515 516 for (lf = 0; lf < block->lf.max; lf++) { 517 cfg = rvu_read64(rvu, block->addr, 518 block->lfcfg_reg | (lf << block->lfshift)); 519 if (!(cfg & BIT_ULL(63))) 520 continue; 521 522 /* Set this resource as being used */ 523 __set_bit(lf, block->lf.bmap); 524 525 /* Get, to whom this LF is attached */ 526 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 527 rvu_update_rsrc_map(rvu, pfvf, block, 528 (cfg >> 8) & 0xFFFF, lf, true); 529 530 /* Set start MSIX vector for this LF within this PF/VF */ 531 rvu_set_msix_offset(rvu, pfvf, block, lf); 532 } 533 } 534 535 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 536 { 537 int min_vecs; 538 539 if (!vf) 540 goto check_pf; 541 542 if (!nvecs) { 543 dev_warn(rvu->dev, 544 "PF%d:VF%d is configured with zero msix vectors, %d\n", 545 pf, vf - 1, nvecs); 546 } 547 return; 548 549 check_pf: 550 if (pf == 0) 551 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 552 else 553 min_vecs = RVU_PF_INT_VEC_CNT; 554 555 if (!(nvecs < min_vecs)) 556 return; 557 dev_warn(rvu->dev, 558 "PF%d is configured with too few vectors, %d, min is %d\n", 559 pf, nvecs, min_vecs); 560 } 561 562 static int rvu_setup_msix_resources(struct rvu *rvu) 563 { 564 struct rvu_hwinfo *hw = rvu->hw; 565 int pf, vf, numvfs, hwvf, err; 566 int nvecs, offset, max_msix; 567 struct rvu_pfvf *pfvf; 568 u64 cfg, phy_addr; 569 dma_addr_t iova; 570 571 for (pf = 0; pf < hw->total_pfs; pf++) { 572 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 573 /* If PF is not enabled, nothing to do */ 574 if (!((cfg >> 20) & 0x01)) 575 continue; 576 577 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 578 579 pfvf = &rvu->pf[pf]; 580 /* Get num of MSIX vectors attached to this PF */ 581 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 582 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 583 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 584 585 /* Alloc msix bitmap for this PF */ 586 err = rvu_alloc_bitmap(&pfvf->msix); 587 if (err) 588 return err; 589 590 /* Allocate memory for MSIX vector to RVU block LF mapping */ 591 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 592 sizeof(u16), GFP_KERNEL); 593 if (!pfvf->msix_lfmap) 594 return -ENOMEM; 595 596 /* For PF0 (AF) firmware will set msix vector offsets for 597 * AF, block AF and PF0_INT vectors, so jump to VFs. 598 */ 599 if (!pf) 600 goto setup_vfmsix; 601 602 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 603 * These are allocated on driver init and never freed, 604 * so no need to set 'msix_lfmap' for these. 605 */ 606 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 607 nvecs = (cfg >> 12) & 0xFF; 608 cfg &= ~0x7FFULL; 609 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 610 rvu_write64(rvu, BLKADDR_RVUM, 611 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 612 setup_vfmsix: 613 /* Alloc msix bitmap for VFs */ 614 for (vf = 0; vf < numvfs; vf++) { 615 pfvf = &rvu->hwvf[hwvf + vf]; 616 /* Get num of MSIX vectors attached to this VF */ 617 cfg = rvu_read64(rvu, BLKADDR_RVUM, 618 RVU_PRIV_PFX_MSIX_CFG(pf)); 619 pfvf->msix.max = (cfg & 0xFFF) + 1; 620 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 621 622 /* Alloc msix bitmap for this VF */ 623 err = rvu_alloc_bitmap(&pfvf->msix); 624 if (err) 625 return err; 626 627 pfvf->msix_lfmap = 628 devm_kcalloc(rvu->dev, pfvf->msix.max, 629 sizeof(u16), GFP_KERNEL); 630 if (!pfvf->msix_lfmap) 631 return -ENOMEM; 632 633 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 634 * These are allocated on driver init and never freed, 635 * so no need to set 'msix_lfmap' for these. 636 */ 637 cfg = rvu_read64(rvu, BLKADDR_RVUM, 638 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 639 nvecs = (cfg >> 12) & 0xFF; 640 cfg &= ~0x7FFULL; 641 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 642 rvu_write64(rvu, BLKADDR_RVUM, 643 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 644 cfg | offset); 645 } 646 } 647 648 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 649 * create a IOMMU mapping for the physcial address configured by 650 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 651 */ 652 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 653 max_msix = cfg & 0xFFFFF; 654 if (rvu->fwdata && rvu->fwdata->msixtr_base) 655 phy_addr = rvu->fwdata->msixtr_base; 656 else 657 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 658 659 iova = dma_map_resource(rvu->dev, phy_addr, 660 max_msix * PCI_MSIX_ENTRY_SIZE, 661 DMA_BIDIRECTIONAL, 0); 662 663 if (dma_mapping_error(rvu->dev, iova)) 664 return -ENOMEM; 665 666 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 667 rvu->msix_base_iova = iova; 668 rvu->msixtr_base_phy = phy_addr; 669 670 return 0; 671 } 672 673 static void rvu_reset_msix(struct rvu *rvu) 674 { 675 /* Restore msixtr base register */ 676 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 677 rvu->msixtr_base_phy); 678 } 679 680 static void rvu_free_hw_resources(struct rvu *rvu) 681 { 682 struct rvu_hwinfo *hw = rvu->hw; 683 struct rvu_block *block; 684 struct rvu_pfvf *pfvf; 685 int id, max_msix; 686 u64 cfg; 687 688 rvu_npa_freemem(rvu); 689 rvu_npc_freemem(rvu); 690 rvu_nix_freemem(rvu); 691 692 /* Free block LF bitmaps */ 693 for (id = 0; id < BLK_COUNT; id++) { 694 block = &hw->block[id]; 695 kfree(block->lf.bmap); 696 } 697 698 /* Free MSIX bitmaps */ 699 for (id = 0; id < hw->total_pfs; id++) { 700 pfvf = &rvu->pf[id]; 701 kfree(pfvf->msix.bmap); 702 } 703 704 for (id = 0; id < hw->total_vfs; id++) { 705 pfvf = &rvu->hwvf[id]; 706 kfree(pfvf->msix.bmap); 707 } 708 709 /* Unmap MSIX vector base IOVA mapping */ 710 if (!rvu->msix_base_iova) 711 return; 712 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 713 max_msix = cfg & 0xFFFFF; 714 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 715 max_msix * PCI_MSIX_ENTRY_SIZE, 716 DMA_BIDIRECTIONAL, 0); 717 718 rvu_reset_msix(rvu); 719 mutex_destroy(&rvu->rsrc_lock); 720 } 721 722 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 723 { 724 struct rvu_hwinfo *hw = rvu->hw; 725 int pf, vf, numvfs, hwvf; 726 struct rvu_pfvf *pfvf; 727 u64 *mac; 728 729 for (pf = 0; pf < hw->total_pfs; pf++) { 730 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 731 if (!pf) 732 goto lbkvf; 733 734 if (!is_pf_cgxmapped(rvu, pf)) 735 continue; 736 /* Assign MAC address to PF */ 737 pfvf = &rvu->pf[pf]; 738 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 739 mac = &rvu->fwdata->pf_macs[pf]; 740 if (*mac) 741 u64_to_ether_addr(*mac, pfvf->mac_addr); 742 else 743 eth_random_addr(pfvf->mac_addr); 744 } else { 745 eth_random_addr(pfvf->mac_addr); 746 } 747 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 748 749 lbkvf: 750 /* Assign MAC address to VFs*/ 751 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 752 for (vf = 0; vf < numvfs; vf++, hwvf++) { 753 pfvf = &rvu->hwvf[hwvf]; 754 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 755 mac = &rvu->fwdata->vf_macs[hwvf]; 756 if (*mac) 757 u64_to_ether_addr(*mac, pfvf->mac_addr); 758 else 759 eth_random_addr(pfvf->mac_addr); 760 } else { 761 eth_random_addr(pfvf->mac_addr); 762 } 763 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 764 } 765 } 766 } 767 768 static int rvu_fwdata_init(struct rvu *rvu) 769 { 770 u64 fwdbase; 771 int err; 772 773 /* Get firmware data base address */ 774 err = cgx_get_fwdata_base(&fwdbase); 775 if (err) 776 goto fail; 777 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 778 if (!rvu->fwdata) 779 goto fail; 780 if (!is_rvu_fwdata_valid(rvu)) { 781 dev_err(rvu->dev, 782 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 783 iounmap(rvu->fwdata); 784 rvu->fwdata = NULL; 785 return -EINVAL; 786 } 787 return 0; 788 fail: 789 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 790 return -EIO; 791 } 792 793 static void rvu_fwdata_exit(struct rvu *rvu) 794 { 795 if (rvu->fwdata) 796 iounmap(rvu->fwdata); 797 } 798 799 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 800 { 801 struct rvu_hwinfo *hw = rvu->hw; 802 struct rvu_block *block; 803 int blkid; 804 u64 cfg; 805 806 /* Init NIX LF's bitmap */ 807 block = &hw->block[blkaddr]; 808 if (!block->implemented) 809 return 0; 810 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 811 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 812 block->lf.max = cfg & 0xFFF; 813 block->addr = blkaddr; 814 block->type = BLKTYPE_NIX; 815 block->lfshift = 8; 816 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 817 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 818 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 819 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 820 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 821 block->lfreset_reg = NIX_AF_LF_RST; 822 sprintf(block->name, "NIX%d", blkid); 823 rvu->nix_blkaddr[blkid] = blkaddr; 824 return rvu_alloc_bitmap(&block->lf); 825 } 826 827 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 828 { 829 struct rvu_hwinfo *hw = rvu->hw; 830 struct rvu_block *block; 831 int blkid; 832 u64 cfg; 833 834 /* Init CPT LF's bitmap */ 835 block = &hw->block[blkaddr]; 836 if (!block->implemented) 837 return 0; 838 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 839 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 840 block->lf.max = cfg & 0xFF; 841 block->addr = blkaddr; 842 block->type = BLKTYPE_CPT; 843 block->multislot = true; 844 block->lfshift = 3; 845 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 846 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 847 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 848 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 849 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 850 block->lfreset_reg = CPT_AF_LF_RST; 851 sprintf(block->name, "CPT%d", blkid); 852 return rvu_alloc_bitmap(&block->lf); 853 } 854 855 static int rvu_setup_hw_resources(struct rvu *rvu) 856 { 857 struct rvu_hwinfo *hw = rvu->hw; 858 struct rvu_block *block; 859 int blkid, err; 860 u64 cfg; 861 862 /* Get HW supported max RVU PF & VF count */ 863 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 864 hw->total_pfs = (cfg >> 32) & 0xFF; 865 hw->total_vfs = (cfg >> 20) & 0xFFF; 866 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 867 868 /* Init NPA LF's bitmap */ 869 block = &hw->block[BLKADDR_NPA]; 870 if (!block->implemented) 871 goto nix; 872 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 873 block->lf.max = (cfg >> 16) & 0xFFF; 874 block->addr = BLKADDR_NPA; 875 block->type = BLKTYPE_NPA; 876 block->lfshift = 8; 877 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 878 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 879 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 880 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 881 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 882 block->lfreset_reg = NPA_AF_LF_RST; 883 sprintf(block->name, "NPA"); 884 err = rvu_alloc_bitmap(&block->lf); 885 if (err) 886 return err; 887 888 nix: 889 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 890 if (err) 891 return err; 892 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 893 if (err) 894 return err; 895 896 /* Init SSO group's bitmap */ 897 block = &hw->block[BLKADDR_SSO]; 898 if (!block->implemented) 899 goto ssow; 900 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 901 block->lf.max = cfg & 0xFFFF; 902 block->addr = BLKADDR_SSO; 903 block->type = BLKTYPE_SSO; 904 block->multislot = true; 905 block->lfshift = 3; 906 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 907 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 908 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 909 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 910 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 911 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 912 sprintf(block->name, "SSO GROUP"); 913 err = rvu_alloc_bitmap(&block->lf); 914 if (err) 915 return err; 916 917 ssow: 918 /* Init SSO workslot's bitmap */ 919 block = &hw->block[BLKADDR_SSOW]; 920 if (!block->implemented) 921 goto tim; 922 block->lf.max = (cfg >> 56) & 0xFF; 923 block->addr = BLKADDR_SSOW; 924 block->type = BLKTYPE_SSOW; 925 block->multislot = true; 926 block->lfshift = 3; 927 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 928 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 929 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 930 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 931 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 932 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 933 sprintf(block->name, "SSOWS"); 934 err = rvu_alloc_bitmap(&block->lf); 935 if (err) 936 return err; 937 938 tim: 939 /* Init TIM LF's bitmap */ 940 block = &hw->block[BLKADDR_TIM]; 941 if (!block->implemented) 942 goto cpt; 943 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 944 block->lf.max = cfg & 0xFFFF; 945 block->addr = BLKADDR_TIM; 946 block->type = BLKTYPE_TIM; 947 block->multislot = true; 948 block->lfshift = 3; 949 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 950 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 951 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 952 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 953 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 954 block->lfreset_reg = TIM_AF_LF_RST; 955 sprintf(block->name, "TIM"); 956 err = rvu_alloc_bitmap(&block->lf); 957 if (err) 958 return err; 959 960 cpt: 961 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 962 if (err) 963 return err; 964 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 965 if (err) 966 return err; 967 968 /* Allocate memory for PFVF data */ 969 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 970 sizeof(struct rvu_pfvf), GFP_KERNEL); 971 if (!rvu->pf) 972 return -ENOMEM; 973 974 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 975 sizeof(struct rvu_pfvf), GFP_KERNEL); 976 if (!rvu->hwvf) 977 return -ENOMEM; 978 979 mutex_init(&rvu->rsrc_lock); 980 981 rvu_fwdata_init(rvu); 982 983 err = rvu_setup_msix_resources(rvu); 984 if (err) 985 return err; 986 987 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 988 block = &hw->block[blkid]; 989 if (!block->lf.bmap) 990 continue; 991 992 /* Allocate memory for block LF/slot to pcifunc mapping info */ 993 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 994 sizeof(u16), GFP_KERNEL); 995 if (!block->fn_map) { 996 err = -ENOMEM; 997 goto msix_err; 998 } 999 1000 /* Scan all blocks to check if low level firmware has 1001 * already provisioned any of the resources to a PF/VF. 1002 */ 1003 rvu_scan_block(rvu, block); 1004 } 1005 1006 err = rvu_npc_init(rvu); 1007 if (err) 1008 goto npc_err; 1009 1010 err = rvu_cgx_init(rvu); 1011 if (err) 1012 goto cgx_err; 1013 1014 /* Assign MACs for CGX mapped functions */ 1015 rvu_setup_pfvf_macaddress(rvu); 1016 1017 err = rvu_npa_init(rvu); 1018 if (err) 1019 goto npa_err; 1020 1021 err = rvu_nix_init(rvu); 1022 if (err) 1023 goto nix_err; 1024 1025 return 0; 1026 1027 nix_err: 1028 rvu_nix_freemem(rvu); 1029 npa_err: 1030 rvu_npa_freemem(rvu); 1031 cgx_err: 1032 rvu_cgx_exit(rvu); 1033 npc_err: 1034 rvu_npc_freemem(rvu); 1035 rvu_fwdata_exit(rvu); 1036 msix_err: 1037 rvu_reset_msix(rvu); 1038 return err; 1039 } 1040 1041 /* NPA and NIX admin queue APIs */ 1042 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1043 { 1044 if (!aq) 1045 return; 1046 1047 qmem_free(rvu->dev, aq->inst); 1048 qmem_free(rvu->dev, aq->res); 1049 devm_kfree(rvu->dev, aq); 1050 } 1051 1052 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1053 int qsize, int inst_size, int res_size) 1054 { 1055 struct admin_queue *aq; 1056 int err; 1057 1058 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1059 if (!*ad_queue) 1060 return -ENOMEM; 1061 aq = *ad_queue; 1062 1063 /* Alloc memory for instructions i.e AQ */ 1064 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1065 if (err) { 1066 devm_kfree(rvu->dev, aq); 1067 return err; 1068 } 1069 1070 /* Alloc memory for results */ 1071 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1072 if (err) { 1073 rvu_aq_free(rvu, aq); 1074 return err; 1075 } 1076 1077 spin_lock_init(&aq->lock); 1078 return 0; 1079 } 1080 1081 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1082 struct ready_msg_rsp *rsp) 1083 { 1084 if (rvu->fwdata) { 1085 rsp->rclk_freq = rvu->fwdata->rclk; 1086 rsp->sclk_freq = rvu->fwdata->sclk; 1087 } 1088 return 0; 1089 } 1090 1091 /* Get current count of a RVU block's LF/slots 1092 * provisioned to a given RVU func. 1093 */ 1094 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1095 { 1096 switch (blkaddr) { 1097 case BLKADDR_NPA: 1098 return pfvf->npalf ? 1 : 0; 1099 case BLKADDR_NIX0: 1100 case BLKADDR_NIX1: 1101 return pfvf->nixlf ? 1 : 0; 1102 case BLKADDR_SSO: 1103 return pfvf->sso; 1104 case BLKADDR_SSOW: 1105 return pfvf->ssow; 1106 case BLKADDR_TIM: 1107 return pfvf->timlfs; 1108 case BLKADDR_CPT0: 1109 return pfvf->cptlfs; 1110 case BLKADDR_CPT1: 1111 return pfvf->cpt1_lfs; 1112 } 1113 return 0; 1114 } 1115 1116 /* Return true if LFs of block type are attached to pcifunc */ 1117 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1118 { 1119 switch (blktype) { 1120 case BLKTYPE_NPA: 1121 return pfvf->npalf ? 1 : 0; 1122 case BLKTYPE_NIX: 1123 return pfvf->nixlf ? 1 : 0; 1124 case BLKTYPE_SSO: 1125 return !!pfvf->sso; 1126 case BLKTYPE_SSOW: 1127 return !!pfvf->ssow; 1128 case BLKTYPE_TIM: 1129 return !!pfvf->timlfs; 1130 case BLKTYPE_CPT: 1131 return pfvf->cptlfs || pfvf->cpt1_lfs; 1132 } 1133 1134 return false; 1135 } 1136 1137 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1138 { 1139 struct rvu_pfvf *pfvf; 1140 1141 if (!is_pf_func_valid(rvu, pcifunc)) 1142 return false; 1143 1144 pfvf = rvu_get_pfvf(rvu, pcifunc); 1145 1146 /* Check if this PFFUNC has a LF of type blktype attached */ 1147 if (!is_blktype_attached(pfvf, blktype)) 1148 return false; 1149 1150 return true; 1151 } 1152 1153 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1154 int pcifunc, int slot) 1155 { 1156 u64 val; 1157 1158 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1159 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1160 /* Wait for the lookup to finish */ 1161 /* TODO: put some timeout here */ 1162 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1163 ; 1164 1165 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1166 1167 /* Check LF valid bit */ 1168 if (!(val & (1ULL << 12))) 1169 return -1; 1170 1171 return (val & 0xFFF); 1172 } 1173 1174 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1175 { 1176 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1177 struct rvu_hwinfo *hw = rvu->hw; 1178 struct rvu_block *block; 1179 int slot, lf, num_lfs; 1180 int blkaddr; 1181 1182 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1183 if (blkaddr < 0) 1184 return; 1185 1186 if (blktype == BLKTYPE_NIX) 1187 rvu_nix_reset_mac(pfvf, pcifunc); 1188 1189 block = &hw->block[blkaddr]; 1190 1191 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1192 if (!num_lfs) 1193 return; 1194 1195 for (slot = 0; slot < num_lfs; slot++) { 1196 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1197 if (lf < 0) /* This should never happen */ 1198 continue; 1199 1200 /* Disable the LF */ 1201 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1202 (lf << block->lfshift), 0x00ULL); 1203 1204 /* Update SW maintained mapping info as well */ 1205 rvu_update_rsrc_map(rvu, pfvf, block, 1206 pcifunc, lf, false); 1207 1208 /* Free the resource */ 1209 rvu_free_rsrc(&block->lf, lf); 1210 1211 /* Clear MSIX vector offset for this LF */ 1212 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1213 } 1214 } 1215 1216 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1217 u16 pcifunc) 1218 { 1219 struct rvu_hwinfo *hw = rvu->hw; 1220 bool detach_all = true; 1221 struct rvu_block *block; 1222 int blkid; 1223 1224 mutex_lock(&rvu->rsrc_lock); 1225 1226 /* Check for partial resource detach */ 1227 if (detach && detach->partial) 1228 detach_all = false; 1229 1230 /* Check for RVU block's LFs attached to this func, 1231 * if so, detach them. 1232 */ 1233 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1234 block = &hw->block[blkid]; 1235 if (!block->lf.bmap) 1236 continue; 1237 if (!detach_all && detach) { 1238 if (blkid == BLKADDR_NPA && !detach->npalf) 1239 continue; 1240 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1241 continue; 1242 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1243 continue; 1244 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1245 continue; 1246 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1247 continue; 1248 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1249 continue; 1250 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1251 continue; 1252 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1253 continue; 1254 } 1255 rvu_detach_block(rvu, pcifunc, block->type); 1256 } 1257 1258 mutex_unlock(&rvu->rsrc_lock); 1259 return 0; 1260 } 1261 1262 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1263 struct rsrc_detach *detach, 1264 struct msg_rsp *rsp) 1265 { 1266 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1267 } 1268 1269 static int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1270 { 1271 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1272 int blkaddr = BLKADDR_NIX0, vf; 1273 struct rvu_pfvf *pf; 1274 1275 /* All CGX mapped PFs are set with assigned NIX block during init */ 1276 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1277 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1278 blkaddr = pf->nix_blkaddr; 1279 } else if (is_afvf(pcifunc)) { 1280 vf = pcifunc - 1; 1281 /* Assign NIX based on VF number. All even numbered VFs get 1282 * NIX0 and odd numbered gets NIX1 1283 */ 1284 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1285 /* NIX1 is not present on all silicons */ 1286 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1287 blkaddr = BLKADDR_NIX0; 1288 } 1289 1290 switch (blkaddr) { 1291 case BLKADDR_NIX1: 1292 pfvf->nix_blkaddr = BLKADDR_NIX1; 1293 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1294 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1295 break; 1296 case BLKADDR_NIX0: 1297 default: 1298 pfvf->nix_blkaddr = BLKADDR_NIX0; 1299 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1300 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1301 break; 1302 } 1303 1304 return pfvf->nix_blkaddr; 1305 } 1306 1307 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1308 u16 pcifunc, struct rsrc_attach *attach) 1309 { 1310 int blkaddr; 1311 1312 switch (blktype) { 1313 case BLKTYPE_NIX: 1314 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1315 break; 1316 case BLKTYPE_CPT: 1317 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1318 return rvu_get_blkaddr(rvu, blktype, 0); 1319 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1320 BLKADDR_CPT0; 1321 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1322 return -ENODEV; 1323 break; 1324 default: 1325 return rvu_get_blkaddr(rvu, blktype, 0); 1326 }; 1327 1328 if (is_block_implemented(rvu->hw, blkaddr)) 1329 return blkaddr; 1330 1331 return -ENODEV; 1332 } 1333 1334 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1335 int num_lfs, struct rsrc_attach *attach) 1336 { 1337 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1338 struct rvu_hwinfo *hw = rvu->hw; 1339 struct rvu_block *block; 1340 int slot, lf; 1341 int blkaddr; 1342 u64 cfg; 1343 1344 if (!num_lfs) 1345 return; 1346 1347 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1348 if (blkaddr < 0) 1349 return; 1350 1351 block = &hw->block[blkaddr]; 1352 if (!block->lf.bmap) 1353 return; 1354 1355 for (slot = 0; slot < num_lfs; slot++) { 1356 /* Allocate the resource */ 1357 lf = rvu_alloc_rsrc(&block->lf); 1358 if (lf < 0) 1359 return; 1360 1361 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1362 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1363 (lf << block->lfshift), cfg); 1364 rvu_update_rsrc_map(rvu, pfvf, block, 1365 pcifunc, lf, true); 1366 1367 /* Set start MSIX vector for this LF within this PF/VF */ 1368 rvu_set_msix_offset(rvu, pfvf, block, lf); 1369 } 1370 } 1371 1372 static int rvu_check_rsrc_availability(struct rvu *rvu, 1373 struct rsrc_attach *req, u16 pcifunc) 1374 { 1375 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1376 int free_lfs, mappedlfs, blkaddr; 1377 struct rvu_hwinfo *hw = rvu->hw; 1378 struct rvu_block *block; 1379 1380 /* Only one NPA LF can be attached */ 1381 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1382 block = &hw->block[BLKADDR_NPA]; 1383 free_lfs = rvu_rsrc_free_count(&block->lf); 1384 if (!free_lfs) 1385 goto fail; 1386 } else if (req->npalf) { 1387 dev_err(&rvu->pdev->dev, 1388 "Func 0x%x: Invalid req, already has NPA\n", 1389 pcifunc); 1390 return -EINVAL; 1391 } 1392 1393 /* Only one NIX LF can be attached */ 1394 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1395 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1396 pcifunc, req); 1397 if (blkaddr < 0) 1398 return blkaddr; 1399 block = &hw->block[blkaddr]; 1400 free_lfs = rvu_rsrc_free_count(&block->lf); 1401 if (!free_lfs) 1402 goto fail; 1403 } else if (req->nixlf) { 1404 dev_err(&rvu->pdev->dev, 1405 "Func 0x%x: Invalid req, already has NIX\n", 1406 pcifunc); 1407 return -EINVAL; 1408 } 1409 1410 if (req->sso) { 1411 block = &hw->block[BLKADDR_SSO]; 1412 /* Is request within limits ? */ 1413 if (req->sso > block->lf.max) { 1414 dev_err(&rvu->pdev->dev, 1415 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1416 pcifunc, req->sso, block->lf.max); 1417 return -EINVAL; 1418 } 1419 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1420 free_lfs = rvu_rsrc_free_count(&block->lf); 1421 /* Check if additional resources are available */ 1422 if (req->sso > mappedlfs && 1423 ((req->sso - mappedlfs) > free_lfs)) 1424 goto fail; 1425 } 1426 1427 if (req->ssow) { 1428 block = &hw->block[BLKADDR_SSOW]; 1429 if (req->ssow > block->lf.max) { 1430 dev_err(&rvu->pdev->dev, 1431 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1432 pcifunc, req->sso, block->lf.max); 1433 return -EINVAL; 1434 } 1435 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1436 free_lfs = rvu_rsrc_free_count(&block->lf); 1437 if (req->ssow > mappedlfs && 1438 ((req->ssow - mappedlfs) > free_lfs)) 1439 goto fail; 1440 } 1441 1442 if (req->timlfs) { 1443 block = &hw->block[BLKADDR_TIM]; 1444 if (req->timlfs > block->lf.max) { 1445 dev_err(&rvu->pdev->dev, 1446 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1447 pcifunc, req->timlfs, block->lf.max); 1448 return -EINVAL; 1449 } 1450 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1451 free_lfs = rvu_rsrc_free_count(&block->lf); 1452 if (req->timlfs > mappedlfs && 1453 ((req->timlfs - mappedlfs) > free_lfs)) 1454 goto fail; 1455 } 1456 1457 if (req->cptlfs) { 1458 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1459 pcifunc, req); 1460 if (blkaddr < 0) 1461 return blkaddr; 1462 block = &hw->block[blkaddr]; 1463 if (req->cptlfs > block->lf.max) { 1464 dev_err(&rvu->pdev->dev, 1465 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1466 pcifunc, req->cptlfs, block->lf.max); 1467 return -EINVAL; 1468 } 1469 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1470 free_lfs = rvu_rsrc_free_count(&block->lf); 1471 if (req->cptlfs > mappedlfs && 1472 ((req->cptlfs - mappedlfs) > free_lfs)) 1473 goto fail; 1474 } 1475 1476 return 0; 1477 1478 fail: 1479 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1480 return -ENOSPC; 1481 } 1482 1483 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1484 struct rsrc_attach *attach) 1485 { 1486 int blkaddr, num_lfs; 1487 1488 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1489 attach->hdr.pcifunc, attach); 1490 if (blkaddr < 0) 1491 return false; 1492 1493 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1494 blkaddr); 1495 /* Requester already has LFs from given block ? */ 1496 return !!num_lfs; 1497 } 1498 1499 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1500 struct rsrc_attach *attach, 1501 struct msg_rsp *rsp) 1502 { 1503 u16 pcifunc = attach->hdr.pcifunc; 1504 int err; 1505 1506 /* If first request, detach all existing attached resources */ 1507 if (!attach->modify) 1508 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1509 1510 mutex_lock(&rvu->rsrc_lock); 1511 1512 /* Check if the request can be accommodated */ 1513 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1514 if (err) 1515 goto exit; 1516 1517 /* Now attach the requested resources */ 1518 if (attach->npalf) 1519 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1520 1521 if (attach->nixlf) 1522 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1523 1524 if (attach->sso) { 1525 /* RVU func doesn't know which exact LF or slot is attached 1526 * to it, it always sees as slot 0,1,2. So for a 'modify' 1527 * request, simply detach all existing attached LFs/slots 1528 * and attach a fresh. 1529 */ 1530 if (attach->modify) 1531 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1532 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1533 attach->sso, attach); 1534 } 1535 1536 if (attach->ssow) { 1537 if (attach->modify) 1538 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1539 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1540 attach->ssow, attach); 1541 } 1542 1543 if (attach->timlfs) { 1544 if (attach->modify) 1545 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1546 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1547 attach->timlfs, attach); 1548 } 1549 1550 if (attach->cptlfs) { 1551 if (attach->modify && 1552 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1553 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1554 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1555 attach->cptlfs, attach); 1556 } 1557 1558 exit: 1559 mutex_unlock(&rvu->rsrc_lock); 1560 return err; 1561 } 1562 1563 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1564 int blkaddr, int lf) 1565 { 1566 u16 vec; 1567 1568 if (lf < 0) 1569 return MSIX_VECTOR_INVALID; 1570 1571 for (vec = 0; vec < pfvf->msix.max; vec++) { 1572 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1573 return vec; 1574 } 1575 return MSIX_VECTOR_INVALID; 1576 } 1577 1578 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1579 struct rvu_block *block, int lf) 1580 { 1581 u16 nvecs, vec, offset; 1582 u64 cfg; 1583 1584 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1585 (lf << block->lfshift)); 1586 nvecs = (cfg >> 12) & 0xFF; 1587 1588 /* Check and alloc MSIX vectors, must be contiguous */ 1589 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1590 return; 1591 1592 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1593 1594 /* Config MSIX offset in LF */ 1595 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1596 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1597 1598 /* Update the bitmap as well */ 1599 for (vec = 0; vec < nvecs; vec++) 1600 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1601 } 1602 1603 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1604 struct rvu_block *block, int lf) 1605 { 1606 u16 nvecs, vec, offset; 1607 u64 cfg; 1608 1609 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1610 (lf << block->lfshift)); 1611 nvecs = (cfg >> 12) & 0xFF; 1612 1613 /* Clear MSIX offset in LF */ 1614 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1615 (lf << block->lfshift), cfg & ~0x7FFULL); 1616 1617 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1618 1619 /* Update the mapping */ 1620 for (vec = 0; vec < nvecs; vec++) 1621 pfvf->msix_lfmap[offset + vec] = 0; 1622 1623 /* Free the same in MSIX bitmap */ 1624 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1625 } 1626 1627 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1628 struct msix_offset_rsp *rsp) 1629 { 1630 struct rvu_hwinfo *hw = rvu->hw; 1631 u16 pcifunc = req->hdr.pcifunc; 1632 struct rvu_pfvf *pfvf; 1633 int lf, slot, blkaddr; 1634 1635 pfvf = rvu_get_pfvf(rvu, pcifunc); 1636 if (!pfvf->msix.bmap) 1637 return 0; 1638 1639 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1640 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1641 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1642 1643 /* Get BLKADDR from which LFs are attached to pcifunc */ 1644 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1645 if (blkaddr < 0) { 1646 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1647 } else { 1648 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1649 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1650 } 1651 1652 rsp->sso = pfvf->sso; 1653 for (slot = 0; slot < rsp->sso; slot++) { 1654 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1655 rsp->sso_msixoff[slot] = 1656 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1657 } 1658 1659 rsp->ssow = pfvf->ssow; 1660 for (slot = 0; slot < rsp->ssow; slot++) { 1661 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1662 rsp->ssow_msixoff[slot] = 1663 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1664 } 1665 1666 rsp->timlfs = pfvf->timlfs; 1667 for (slot = 0; slot < rsp->timlfs; slot++) { 1668 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1669 rsp->timlf_msixoff[slot] = 1670 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1671 } 1672 1673 rsp->cptlfs = pfvf->cptlfs; 1674 for (slot = 0; slot < rsp->cptlfs; slot++) { 1675 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1676 rsp->cptlf_msixoff[slot] = 1677 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1678 } 1679 1680 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1681 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1682 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1683 rsp->cpt1_lf_msixoff[slot] = 1684 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1685 } 1686 1687 return 0; 1688 } 1689 1690 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1691 struct msg_rsp *rsp) 1692 { 1693 u16 pcifunc = req->hdr.pcifunc; 1694 u16 vf, numvfs; 1695 u64 cfg; 1696 1697 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1698 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1699 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1700 numvfs = (cfg >> 12) & 0xFF; 1701 1702 if (vf && vf <= numvfs) 1703 __rvu_flr_handler(rvu, pcifunc); 1704 else 1705 return RVU_INVALID_VF_ID; 1706 1707 return 0; 1708 } 1709 1710 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1711 struct get_hw_cap_rsp *rsp) 1712 { 1713 struct rvu_hwinfo *hw = rvu->hw; 1714 1715 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1716 rsp->nix_shaping = hw->cap.nix_shaping; 1717 1718 return 0; 1719 } 1720 1721 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1722 struct mbox_msghdr *req) 1723 { 1724 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1725 1726 /* Check if valid, if not reply with a invalid msg */ 1727 if (req->sig != OTX2_MBOX_REQ_SIG) 1728 goto bad_message; 1729 1730 switch (req->id) { 1731 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1732 case _id: { \ 1733 struct _rsp_type *rsp; \ 1734 int err; \ 1735 \ 1736 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1737 mbox, devid, \ 1738 sizeof(struct _rsp_type)); \ 1739 /* some handlers should complete even if reply */ \ 1740 /* could not be allocated */ \ 1741 if (!rsp && \ 1742 _id != MBOX_MSG_DETACH_RESOURCES && \ 1743 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1744 _id != MBOX_MSG_VF_FLR) \ 1745 return -ENOMEM; \ 1746 if (rsp) { \ 1747 rsp->hdr.id = _id; \ 1748 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1749 rsp->hdr.pcifunc = req->pcifunc; \ 1750 rsp->hdr.rc = 0; \ 1751 } \ 1752 \ 1753 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1754 (struct _req_type *)req, \ 1755 rsp); \ 1756 if (rsp && err) \ 1757 rsp->hdr.rc = err; \ 1758 \ 1759 trace_otx2_msg_process(mbox->pdev, _id, err); \ 1760 return rsp ? err : -ENOMEM; \ 1761 } 1762 MBOX_MESSAGES 1763 #undef M 1764 1765 bad_message: 1766 default: 1767 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1768 return -ENODEV; 1769 } 1770 } 1771 1772 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1773 { 1774 struct rvu *rvu = mwork->rvu; 1775 int offset, err, id, devid; 1776 struct otx2_mbox_dev *mdev; 1777 struct mbox_hdr *req_hdr; 1778 struct mbox_msghdr *msg; 1779 struct mbox_wq_info *mw; 1780 struct otx2_mbox *mbox; 1781 1782 switch (type) { 1783 case TYPE_AFPF: 1784 mw = &rvu->afpf_wq_info; 1785 break; 1786 case TYPE_AFVF: 1787 mw = &rvu->afvf_wq_info; 1788 break; 1789 default: 1790 return; 1791 } 1792 1793 devid = mwork - mw->mbox_wrk; 1794 mbox = &mw->mbox; 1795 mdev = &mbox->dev[devid]; 1796 1797 /* Process received mbox messages */ 1798 req_hdr = mdev->mbase + mbox->rx_start; 1799 if (mw->mbox_wrk[devid].num_msgs == 0) 1800 return; 1801 1802 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1803 1804 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 1805 msg = mdev->mbase + offset; 1806 1807 /* Set which PF/VF sent this message based on mbox IRQ */ 1808 switch (type) { 1809 case TYPE_AFPF: 1810 msg->pcifunc &= 1811 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1812 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1813 break; 1814 case TYPE_AFVF: 1815 msg->pcifunc &= 1816 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1817 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1818 break; 1819 } 1820 1821 err = rvu_process_mbox_msg(mbox, devid, msg); 1822 if (!err) { 1823 offset = mbox->rx_start + msg->next_msgoff; 1824 continue; 1825 } 1826 1827 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1828 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1829 err, otx2_mbox_id2name(msg->id), 1830 msg->id, rvu_get_pf(msg->pcifunc), 1831 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1832 else 1833 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1834 err, otx2_mbox_id2name(msg->id), 1835 msg->id, devid); 1836 } 1837 mw->mbox_wrk[devid].num_msgs = 0; 1838 1839 /* Send mbox responses to VF/PF */ 1840 otx2_mbox_msg_send(mbox, devid); 1841 } 1842 1843 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1844 { 1845 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1846 1847 __rvu_mbox_handler(mwork, TYPE_AFPF); 1848 } 1849 1850 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1851 { 1852 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1853 1854 __rvu_mbox_handler(mwork, TYPE_AFVF); 1855 } 1856 1857 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1858 { 1859 struct rvu *rvu = mwork->rvu; 1860 struct otx2_mbox_dev *mdev; 1861 struct mbox_hdr *rsp_hdr; 1862 struct mbox_msghdr *msg; 1863 struct mbox_wq_info *mw; 1864 struct otx2_mbox *mbox; 1865 int offset, id, devid; 1866 1867 switch (type) { 1868 case TYPE_AFPF: 1869 mw = &rvu->afpf_wq_info; 1870 break; 1871 case TYPE_AFVF: 1872 mw = &rvu->afvf_wq_info; 1873 break; 1874 default: 1875 return; 1876 } 1877 1878 devid = mwork - mw->mbox_wrk_up; 1879 mbox = &mw->mbox_up; 1880 mdev = &mbox->dev[devid]; 1881 1882 rsp_hdr = mdev->mbase + mbox->rx_start; 1883 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 1884 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 1885 return; 1886 } 1887 1888 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1889 1890 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 1891 msg = mdev->mbase + offset; 1892 1893 if (msg->id >= MBOX_MSG_MAX) { 1894 dev_err(rvu->dev, 1895 "Mbox msg with unknown ID 0x%x\n", msg->id); 1896 goto end; 1897 } 1898 1899 if (msg->sig != OTX2_MBOX_RSP_SIG) { 1900 dev_err(rvu->dev, 1901 "Mbox msg with wrong signature %x, ID 0x%x\n", 1902 msg->sig, msg->id); 1903 goto end; 1904 } 1905 1906 switch (msg->id) { 1907 case MBOX_MSG_CGX_LINK_EVENT: 1908 break; 1909 default: 1910 if (msg->rc) 1911 dev_err(rvu->dev, 1912 "Mbox msg response has err %d, ID 0x%x\n", 1913 msg->rc, msg->id); 1914 break; 1915 } 1916 end: 1917 offset = mbox->rx_start + msg->next_msgoff; 1918 mdev->msgs_acked++; 1919 } 1920 mw->mbox_wrk_up[devid].up_num_msgs = 0; 1921 1922 otx2_mbox_reset(mbox, devid); 1923 } 1924 1925 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 1926 { 1927 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1928 1929 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 1930 } 1931 1932 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 1933 { 1934 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1935 1936 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 1937 } 1938 1939 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 1940 int type, int num, 1941 void (mbox_handler)(struct work_struct *), 1942 void (mbox_up_handler)(struct work_struct *)) 1943 { 1944 void __iomem *hwbase = NULL, *reg_base; 1945 int err, i, dir, dir_up; 1946 struct rvu_work *mwork; 1947 const char *name; 1948 u64 bar4_addr; 1949 1950 switch (type) { 1951 case TYPE_AFPF: 1952 name = "rvu_afpf_mailbox"; 1953 bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR); 1954 dir = MBOX_DIR_AFPF; 1955 dir_up = MBOX_DIR_AFPF_UP; 1956 reg_base = rvu->afreg_base; 1957 break; 1958 case TYPE_AFVF: 1959 name = "rvu_afvf_mailbox"; 1960 bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 1961 dir = MBOX_DIR_PFVF; 1962 dir_up = MBOX_DIR_PFVF_UP; 1963 reg_base = rvu->pfreg_base; 1964 break; 1965 default: 1966 return -EINVAL; 1967 } 1968 1969 mw->mbox_wq = alloc_workqueue(name, 1970 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 1971 num); 1972 if (!mw->mbox_wq) 1973 return -ENOMEM; 1974 1975 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 1976 sizeof(struct rvu_work), GFP_KERNEL); 1977 if (!mw->mbox_wrk) { 1978 err = -ENOMEM; 1979 goto exit; 1980 } 1981 1982 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 1983 sizeof(struct rvu_work), GFP_KERNEL); 1984 if (!mw->mbox_wrk_up) { 1985 err = -ENOMEM; 1986 goto exit; 1987 } 1988 1989 /* Mailbox is a reserved memory (in RAM) region shared between 1990 * RVU devices, shouldn't be mapped as device memory to allow 1991 * unaligned accesses. 1992 */ 1993 hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * num); 1994 if (!hwbase) { 1995 dev_err(rvu->dev, "Unable to map mailbox region\n"); 1996 err = -ENOMEM; 1997 goto exit; 1998 } 1999 2000 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); 2001 if (err) 2002 goto exit; 2003 2004 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, 2005 reg_base, dir_up, num); 2006 if (err) 2007 goto exit; 2008 2009 for (i = 0; i < num; i++) { 2010 mwork = &mw->mbox_wrk[i]; 2011 mwork->rvu = rvu; 2012 INIT_WORK(&mwork->work, mbox_handler); 2013 2014 mwork = &mw->mbox_wrk_up[i]; 2015 mwork->rvu = rvu; 2016 INIT_WORK(&mwork->work, mbox_up_handler); 2017 } 2018 2019 return 0; 2020 exit: 2021 if (hwbase) 2022 iounmap((void __iomem *)hwbase); 2023 destroy_workqueue(mw->mbox_wq); 2024 return err; 2025 } 2026 2027 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2028 { 2029 if (mw->mbox_wq) { 2030 flush_workqueue(mw->mbox_wq); 2031 destroy_workqueue(mw->mbox_wq); 2032 mw->mbox_wq = NULL; 2033 } 2034 2035 if (mw->mbox.hwbase) 2036 iounmap((void __iomem *)mw->mbox.hwbase); 2037 2038 otx2_mbox_destroy(&mw->mbox); 2039 otx2_mbox_destroy(&mw->mbox_up); 2040 } 2041 2042 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2043 int mdevs, u64 intr) 2044 { 2045 struct otx2_mbox_dev *mdev; 2046 struct otx2_mbox *mbox; 2047 struct mbox_hdr *hdr; 2048 int i; 2049 2050 for (i = first; i < mdevs; i++) { 2051 /* start from 0 */ 2052 if (!(intr & BIT_ULL(i - first))) 2053 continue; 2054 2055 mbox = &mw->mbox; 2056 mdev = &mbox->dev[i]; 2057 hdr = mdev->mbase + mbox->rx_start; 2058 2059 /*The hdr->num_msgs is set to zero immediately in the interrupt 2060 * handler to ensure that it holds a correct value next time 2061 * when the interrupt handler is called. 2062 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2063 * pf>mbox.up_num_msgs holds the data for use in 2064 * pfaf_mbox_up_handler. 2065 */ 2066 2067 if (hdr->num_msgs) { 2068 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2069 hdr->num_msgs = 0; 2070 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2071 } 2072 mbox = &mw->mbox_up; 2073 mdev = &mbox->dev[i]; 2074 hdr = mdev->mbase + mbox->rx_start; 2075 if (hdr->num_msgs) { 2076 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2077 hdr->num_msgs = 0; 2078 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2079 } 2080 } 2081 } 2082 2083 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2084 { 2085 struct rvu *rvu = (struct rvu *)rvu_irq; 2086 int vfs = rvu->vfs; 2087 u64 intr; 2088 2089 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2090 /* Clear interrupts */ 2091 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2092 if (intr) 2093 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2094 2095 /* Sync with mbox memory region */ 2096 rmb(); 2097 2098 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2099 2100 /* Handle VF interrupts */ 2101 if (vfs > 64) { 2102 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2103 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2104 2105 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2106 vfs -= 64; 2107 } 2108 2109 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2110 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2111 if (intr) 2112 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2113 2114 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2115 2116 return IRQ_HANDLED; 2117 } 2118 2119 static void rvu_enable_mbox_intr(struct rvu *rvu) 2120 { 2121 struct rvu_hwinfo *hw = rvu->hw; 2122 2123 /* Clear spurious irqs, if any */ 2124 rvu_write64(rvu, BLKADDR_RVUM, 2125 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2126 2127 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2128 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2129 INTR_MASK(hw->total_pfs) & ~1ULL); 2130 } 2131 2132 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2133 { 2134 struct rvu_block *block; 2135 int slot, lf, num_lfs; 2136 int err; 2137 2138 block = &rvu->hw->block[blkaddr]; 2139 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2140 block->addr); 2141 if (!num_lfs) 2142 return; 2143 for (slot = 0; slot < num_lfs; slot++) { 2144 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2145 if (lf < 0) 2146 continue; 2147 2148 /* Cleanup LF and reset it */ 2149 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2150 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2151 else if (block->addr == BLKADDR_NPA) 2152 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2153 2154 err = rvu_lf_reset(rvu, block, lf); 2155 if (err) { 2156 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2157 block->addr, lf); 2158 } 2159 } 2160 } 2161 2162 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2163 { 2164 mutex_lock(&rvu->flr_lock); 2165 /* Reset order should reflect inter-block dependencies: 2166 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2167 * 2. Flush and reset SSO/SSOW 2168 * 3. Cleanup pools (NPA) 2169 */ 2170 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2171 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2172 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2173 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2174 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2175 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2176 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2177 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2178 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2179 mutex_unlock(&rvu->flr_lock); 2180 } 2181 2182 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2183 { 2184 int reg = 0; 2185 2186 /* pcifunc = 0(PF0) | (vf + 1) */ 2187 __rvu_flr_handler(rvu, vf + 1); 2188 2189 if (vf >= 64) { 2190 reg = 1; 2191 vf = vf - 64; 2192 } 2193 2194 /* Signal FLR finish and enable IRQ */ 2195 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2196 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2197 } 2198 2199 static void rvu_flr_handler(struct work_struct *work) 2200 { 2201 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2202 struct rvu *rvu = flrwork->rvu; 2203 u16 pcifunc, numvfs, vf; 2204 u64 cfg; 2205 int pf; 2206 2207 pf = flrwork - rvu->flr_wrk; 2208 if (pf >= rvu->hw->total_pfs) { 2209 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2210 return; 2211 } 2212 2213 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2214 numvfs = (cfg >> 12) & 0xFF; 2215 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2216 2217 for (vf = 0; vf < numvfs; vf++) 2218 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2219 2220 __rvu_flr_handler(rvu, pcifunc); 2221 2222 /* Signal FLR finish */ 2223 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2224 2225 /* Enable interrupt */ 2226 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2227 } 2228 2229 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2230 { 2231 int dev, vf, reg = 0; 2232 u64 intr; 2233 2234 if (start_vf >= 64) 2235 reg = 1; 2236 2237 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2238 if (!intr) 2239 return; 2240 2241 for (vf = 0; vf < numvfs; vf++) { 2242 if (!(intr & BIT_ULL(vf))) 2243 continue; 2244 dev = vf + start_vf + rvu->hw->total_pfs; 2245 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2246 /* Clear and disable the interrupt */ 2247 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2248 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2249 } 2250 } 2251 2252 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2253 { 2254 struct rvu *rvu = (struct rvu *)rvu_irq; 2255 u64 intr; 2256 u8 pf; 2257 2258 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2259 if (!intr) 2260 goto afvf_flr; 2261 2262 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2263 if (intr & (1ULL << pf)) { 2264 /* PF is already dead do only AF related operations */ 2265 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2266 /* clear interrupt */ 2267 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2268 BIT_ULL(pf)); 2269 /* Disable the interrupt */ 2270 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2271 BIT_ULL(pf)); 2272 } 2273 } 2274 2275 afvf_flr: 2276 rvu_afvf_queue_flr_work(rvu, 0, 64); 2277 if (rvu->vfs > 64) 2278 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2279 2280 return IRQ_HANDLED; 2281 } 2282 2283 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2284 { 2285 int vf; 2286 2287 /* Nothing to be done here other than clearing the 2288 * TRPEND bit. 2289 */ 2290 for (vf = 0; vf < 64; vf++) { 2291 if (intr & (1ULL << vf)) { 2292 /* clear the trpend due to ME(master enable) */ 2293 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2294 /* clear interrupt */ 2295 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2296 } 2297 } 2298 } 2299 2300 /* Handles ME interrupts from VFs of AF */ 2301 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2302 { 2303 struct rvu *rvu = (struct rvu *)rvu_irq; 2304 int vfset; 2305 u64 intr; 2306 2307 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2308 2309 for (vfset = 0; vfset <= 1; vfset++) { 2310 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2311 if (intr) 2312 rvu_me_handle_vfset(rvu, vfset, intr); 2313 } 2314 2315 return IRQ_HANDLED; 2316 } 2317 2318 /* Handles ME interrupts from PFs */ 2319 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2320 { 2321 struct rvu *rvu = (struct rvu *)rvu_irq; 2322 u64 intr; 2323 u8 pf; 2324 2325 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2326 2327 /* Nothing to be done here other than clearing the 2328 * TRPEND bit. 2329 */ 2330 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2331 if (intr & (1ULL << pf)) { 2332 /* clear the trpend due to ME(master enable) */ 2333 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2334 BIT_ULL(pf)); 2335 /* clear interrupt */ 2336 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2337 BIT_ULL(pf)); 2338 } 2339 } 2340 2341 return IRQ_HANDLED; 2342 } 2343 2344 static void rvu_unregister_interrupts(struct rvu *rvu) 2345 { 2346 int irq; 2347 2348 /* Disable the Mbox interrupt */ 2349 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2350 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2351 2352 /* Disable the PF FLR interrupt */ 2353 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2354 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2355 2356 /* Disable the PF ME interrupt */ 2357 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2358 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2359 2360 for (irq = 0; irq < rvu->num_vec; irq++) { 2361 if (rvu->irq_allocated[irq]) 2362 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2363 } 2364 2365 pci_free_irq_vectors(rvu->pdev); 2366 rvu->num_vec = 0; 2367 } 2368 2369 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2370 { 2371 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2372 int offset; 2373 2374 pfvf = &rvu->pf[0]; 2375 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2376 2377 /* Make sure there are enough MSIX vectors configured so that 2378 * VF interrupts can be handled. Offset equal to zero means 2379 * that PF vectors are not configured and overlapping AF vectors. 2380 */ 2381 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2382 offset; 2383 } 2384 2385 static int rvu_register_interrupts(struct rvu *rvu) 2386 { 2387 int ret, offset, pf_vec_start; 2388 2389 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2390 2391 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2392 NAME_SIZE, GFP_KERNEL); 2393 if (!rvu->irq_name) 2394 return -ENOMEM; 2395 2396 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2397 sizeof(bool), GFP_KERNEL); 2398 if (!rvu->irq_allocated) 2399 return -ENOMEM; 2400 2401 /* Enable MSI-X */ 2402 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2403 rvu->num_vec, PCI_IRQ_MSIX); 2404 if (ret < 0) { 2405 dev_err(rvu->dev, 2406 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2407 rvu->num_vec, ret); 2408 return ret; 2409 } 2410 2411 /* Register mailbox interrupt handler */ 2412 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2413 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2414 rvu_mbox_intr_handler, 0, 2415 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2416 if (ret) { 2417 dev_err(rvu->dev, 2418 "RVUAF: IRQ registration failed for mbox irq\n"); 2419 goto fail; 2420 } 2421 2422 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2423 2424 /* Enable mailbox interrupts from all PFs */ 2425 rvu_enable_mbox_intr(rvu); 2426 2427 /* Register FLR interrupt handler */ 2428 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2429 "RVUAF FLR"); 2430 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2431 rvu_flr_intr_handler, 0, 2432 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2433 rvu); 2434 if (ret) { 2435 dev_err(rvu->dev, 2436 "RVUAF: IRQ registration failed for FLR\n"); 2437 goto fail; 2438 } 2439 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2440 2441 /* Enable FLR interrupt for all PFs*/ 2442 rvu_write64(rvu, BLKADDR_RVUM, 2443 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2444 2445 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2446 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2447 2448 /* Register ME interrupt handler */ 2449 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2450 "RVUAF ME"); 2451 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2452 rvu_me_pf_intr_handler, 0, 2453 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2454 rvu); 2455 if (ret) { 2456 dev_err(rvu->dev, 2457 "RVUAF: IRQ registration failed for ME\n"); 2458 } 2459 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2460 2461 /* Clear TRPEND bit for all PF */ 2462 rvu_write64(rvu, BLKADDR_RVUM, 2463 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2464 /* Enable ME interrupt for all PFs*/ 2465 rvu_write64(rvu, BLKADDR_RVUM, 2466 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2467 2468 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2469 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2470 2471 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2472 return 0; 2473 2474 /* Get PF MSIX vectors offset. */ 2475 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2476 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2477 2478 /* Register MBOX0 interrupt. */ 2479 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2480 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2481 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2482 rvu_mbox_intr_handler, 0, 2483 &rvu->irq_name[offset * NAME_SIZE], 2484 rvu); 2485 if (ret) 2486 dev_err(rvu->dev, 2487 "RVUAF: IRQ registration failed for Mbox0\n"); 2488 2489 rvu->irq_allocated[offset] = true; 2490 2491 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2492 * simply increment current offset by 1. 2493 */ 2494 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2495 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2496 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2497 rvu_mbox_intr_handler, 0, 2498 &rvu->irq_name[offset * NAME_SIZE], 2499 rvu); 2500 if (ret) 2501 dev_err(rvu->dev, 2502 "RVUAF: IRQ registration failed for Mbox1\n"); 2503 2504 rvu->irq_allocated[offset] = true; 2505 2506 /* Register FLR interrupt handler for AF's VFs */ 2507 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2508 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2509 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2510 rvu_flr_intr_handler, 0, 2511 &rvu->irq_name[offset * NAME_SIZE], rvu); 2512 if (ret) { 2513 dev_err(rvu->dev, 2514 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2515 goto fail; 2516 } 2517 rvu->irq_allocated[offset] = true; 2518 2519 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2520 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2521 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2522 rvu_flr_intr_handler, 0, 2523 &rvu->irq_name[offset * NAME_SIZE], rvu); 2524 if (ret) { 2525 dev_err(rvu->dev, 2526 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2527 goto fail; 2528 } 2529 rvu->irq_allocated[offset] = true; 2530 2531 /* Register ME interrupt handler for AF's VFs */ 2532 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2533 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2534 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2535 rvu_me_vf_intr_handler, 0, 2536 &rvu->irq_name[offset * NAME_SIZE], rvu); 2537 if (ret) { 2538 dev_err(rvu->dev, 2539 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2540 goto fail; 2541 } 2542 rvu->irq_allocated[offset] = true; 2543 2544 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2545 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2546 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2547 rvu_me_vf_intr_handler, 0, 2548 &rvu->irq_name[offset * NAME_SIZE], rvu); 2549 if (ret) { 2550 dev_err(rvu->dev, 2551 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2552 goto fail; 2553 } 2554 rvu->irq_allocated[offset] = true; 2555 return 0; 2556 2557 fail: 2558 rvu_unregister_interrupts(rvu); 2559 return ret; 2560 } 2561 2562 static void rvu_flr_wq_destroy(struct rvu *rvu) 2563 { 2564 if (rvu->flr_wq) { 2565 flush_workqueue(rvu->flr_wq); 2566 destroy_workqueue(rvu->flr_wq); 2567 rvu->flr_wq = NULL; 2568 } 2569 } 2570 2571 static int rvu_flr_init(struct rvu *rvu) 2572 { 2573 int dev, num_devs; 2574 u64 cfg; 2575 int pf; 2576 2577 /* Enable FLR for all PFs*/ 2578 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2579 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2580 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2581 cfg | BIT_ULL(22)); 2582 } 2583 2584 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2585 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2586 1); 2587 if (!rvu->flr_wq) 2588 return -ENOMEM; 2589 2590 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2591 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2592 sizeof(struct rvu_work), GFP_KERNEL); 2593 if (!rvu->flr_wrk) { 2594 destroy_workqueue(rvu->flr_wq); 2595 return -ENOMEM; 2596 } 2597 2598 for (dev = 0; dev < num_devs; dev++) { 2599 rvu->flr_wrk[dev].rvu = rvu; 2600 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2601 } 2602 2603 mutex_init(&rvu->flr_lock); 2604 2605 return 0; 2606 } 2607 2608 static void rvu_disable_afvf_intr(struct rvu *rvu) 2609 { 2610 int vfs = rvu->vfs; 2611 2612 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2613 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2614 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2615 if (vfs <= 64) 2616 return; 2617 2618 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2619 INTR_MASK(vfs - 64)); 2620 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2621 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2622 } 2623 2624 static void rvu_enable_afvf_intr(struct rvu *rvu) 2625 { 2626 int vfs = rvu->vfs; 2627 2628 /* Clear any pending interrupts and enable AF VF interrupts for 2629 * the first 64 VFs. 2630 */ 2631 /* Mbox */ 2632 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2633 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2634 2635 /* FLR */ 2636 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2637 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2638 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2639 2640 /* Same for remaining VFs, if any. */ 2641 if (vfs <= 64) 2642 return; 2643 2644 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2645 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2646 INTR_MASK(vfs - 64)); 2647 2648 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2649 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2650 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2651 } 2652 2653 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 2654 2655 int rvu_get_num_lbk_chans(void) 2656 { 2657 struct pci_dev *pdev; 2658 void __iomem *base; 2659 int ret = -EIO; 2660 2661 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2662 NULL); 2663 if (!pdev) 2664 goto err; 2665 2666 base = pci_ioremap_bar(pdev, 0); 2667 if (!base) 2668 goto err_put; 2669 2670 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2671 ret = (readq(base + 0x10) >> 32) & 0xffff; 2672 iounmap(base); 2673 err_put: 2674 pci_dev_put(pdev); 2675 err: 2676 return ret; 2677 } 2678 2679 static int rvu_enable_sriov(struct rvu *rvu) 2680 { 2681 struct pci_dev *pdev = rvu->pdev; 2682 int err, chans, vfs; 2683 2684 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2685 dev_warn(&pdev->dev, 2686 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2687 return 0; 2688 } 2689 2690 chans = rvu_get_num_lbk_chans(); 2691 if (chans < 0) 2692 return chans; 2693 2694 vfs = pci_sriov_get_totalvfs(pdev); 2695 2696 /* Limit VFs in case we have more VFs than LBK channels available. */ 2697 if (vfs > chans) 2698 vfs = chans; 2699 2700 if (!vfs) 2701 return 0; 2702 2703 /* Save VFs number for reference in VF interrupts handlers. 2704 * Since interrupts might start arriving during SRIOV enablement 2705 * ordinary API cannot be used to get number of enabled VFs. 2706 */ 2707 rvu->vfs = vfs; 2708 2709 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2710 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2711 if (err) 2712 return err; 2713 2714 rvu_enable_afvf_intr(rvu); 2715 /* Make sure IRQs are enabled before SRIOV. */ 2716 mb(); 2717 2718 err = pci_enable_sriov(pdev, vfs); 2719 if (err) { 2720 rvu_disable_afvf_intr(rvu); 2721 rvu_mbox_destroy(&rvu->afvf_wq_info); 2722 return err; 2723 } 2724 2725 return 0; 2726 } 2727 2728 static void rvu_disable_sriov(struct rvu *rvu) 2729 { 2730 rvu_disable_afvf_intr(rvu); 2731 rvu_mbox_destroy(&rvu->afvf_wq_info); 2732 pci_disable_sriov(rvu->pdev); 2733 } 2734 2735 static void rvu_update_module_params(struct rvu *rvu) 2736 { 2737 const char *default_pfl_name = "default"; 2738 2739 strscpy(rvu->mkex_pfl_name, 2740 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 2741 } 2742 2743 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2744 { 2745 struct device *dev = &pdev->dev; 2746 struct rvu *rvu; 2747 int err; 2748 2749 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2750 if (!rvu) 2751 return -ENOMEM; 2752 2753 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2754 if (!rvu->hw) { 2755 devm_kfree(dev, rvu); 2756 return -ENOMEM; 2757 } 2758 2759 pci_set_drvdata(pdev, rvu); 2760 rvu->pdev = pdev; 2761 rvu->dev = &pdev->dev; 2762 2763 err = pci_enable_device(pdev); 2764 if (err) { 2765 dev_err(dev, "Failed to enable PCI device\n"); 2766 goto err_freemem; 2767 } 2768 2769 err = pci_request_regions(pdev, DRV_NAME); 2770 if (err) { 2771 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2772 goto err_disable_device; 2773 } 2774 2775 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2776 if (err) { 2777 dev_err(dev, "DMA mask config failed, abort\n"); 2778 goto err_release_regions; 2779 } 2780 2781 pci_set_master(pdev); 2782 2783 rvu->ptp = ptp_get(); 2784 if (IS_ERR(rvu->ptp)) { 2785 err = PTR_ERR(rvu->ptp); 2786 if (err == -EPROBE_DEFER) 2787 goto err_release_regions; 2788 rvu->ptp = NULL; 2789 } 2790 2791 /* Map Admin function CSRs */ 2792 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 2793 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 2794 if (!rvu->afreg_base || !rvu->pfreg_base) { 2795 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 2796 err = -ENOMEM; 2797 goto err_put_ptp; 2798 } 2799 2800 /* Store module params in rvu structure */ 2801 rvu_update_module_params(rvu); 2802 2803 /* Check which blocks the HW supports */ 2804 rvu_check_block_implemented(rvu); 2805 2806 rvu_reset_all_blocks(rvu); 2807 2808 rvu_setup_hw_capabilities(rvu); 2809 2810 err = rvu_setup_hw_resources(rvu); 2811 if (err) 2812 goto err_put_ptp; 2813 2814 /* Init mailbox btw AF and PFs */ 2815 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 2816 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 2817 rvu_afpf_mbox_up_handler); 2818 if (err) 2819 goto err_hwsetup; 2820 2821 err = rvu_flr_init(rvu); 2822 if (err) 2823 goto err_mbox; 2824 2825 err = rvu_register_interrupts(rvu); 2826 if (err) 2827 goto err_flr; 2828 2829 err = rvu_register_dl(rvu); 2830 if (err) 2831 goto err_irq; 2832 2833 rvu_setup_rvum_blk_revid(rvu); 2834 2835 /* Enable AF's VFs (if any) */ 2836 err = rvu_enable_sriov(rvu); 2837 if (err) 2838 goto err_dl; 2839 2840 /* Initialize debugfs */ 2841 rvu_dbg_init(rvu); 2842 2843 return 0; 2844 err_dl: 2845 rvu_unregister_dl(rvu); 2846 err_irq: 2847 rvu_unregister_interrupts(rvu); 2848 err_flr: 2849 rvu_flr_wq_destroy(rvu); 2850 err_mbox: 2851 rvu_mbox_destroy(&rvu->afpf_wq_info); 2852 err_hwsetup: 2853 rvu_cgx_exit(rvu); 2854 rvu_fwdata_exit(rvu); 2855 rvu_reset_all_blocks(rvu); 2856 rvu_free_hw_resources(rvu); 2857 rvu_clear_rvum_blk_revid(rvu); 2858 err_put_ptp: 2859 ptp_put(rvu->ptp); 2860 err_release_regions: 2861 pci_release_regions(pdev); 2862 err_disable_device: 2863 pci_disable_device(pdev); 2864 err_freemem: 2865 pci_set_drvdata(pdev, NULL); 2866 devm_kfree(&pdev->dev, rvu->hw); 2867 devm_kfree(dev, rvu); 2868 return err; 2869 } 2870 2871 static void rvu_remove(struct pci_dev *pdev) 2872 { 2873 struct rvu *rvu = pci_get_drvdata(pdev); 2874 2875 rvu_dbg_exit(rvu); 2876 rvu_unregister_interrupts(rvu); 2877 rvu_unregister_dl(rvu); 2878 rvu_flr_wq_destroy(rvu); 2879 rvu_cgx_exit(rvu); 2880 rvu_fwdata_exit(rvu); 2881 rvu_mbox_destroy(&rvu->afpf_wq_info); 2882 rvu_disable_sriov(rvu); 2883 rvu_reset_all_blocks(rvu); 2884 rvu_free_hw_resources(rvu); 2885 rvu_clear_rvum_blk_revid(rvu); 2886 ptp_put(rvu->ptp); 2887 pci_release_regions(pdev); 2888 pci_disable_device(pdev); 2889 pci_set_drvdata(pdev, NULL); 2890 2891 devm_kfree(&pdev->dev, rvu->hw); 2892 devm_kfree(&pdev->dev, rvu); 2893 } 2894 2895 static struct pci_driver rvu_driver = { 2896 .name = DRV_NAME, 2897 .id_table = rvu_id_table, 2898 .probe = rvu_probe, 2899 .remove = rvu_remove, 2900 }; 2901 2902 static int __init rvu_init_module(void) 2903 { 2904 int err; 2905 2906 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2907 2908 err = pci_register_driver(&cgx_driver); 2909 if (err < 0) 2910 return err; 2911 2912 err = pci_register_driver(&ptp_driver); 2913 if (err < 0) 2914 goto ptp_err; 2915 2916 err = pci_register_driver(&rvu_driver); 2917 if (err < 0) 2918 goto rvu_err; 2919 2920 return 0; 2921 rvu_err: 2922 pci_unregister_driver(&ptp_driver); 2923 ptp_err: 2924 pci_unregister_driver(&cgx_driver); 2925 2926 return err; 2927 } 2928 2929 static void __exit rvu_cleanup_module(void) 2930 { 2931 pci_unregister_driver(&rvu_driver); 2932 pci_unregister_driver(&ptp_driver); 2933 pci_unregister_driver(&cgx_driver); 2934 } 2935 2936 module_init(rvu_init_module); 2937 module_exit(rvu_cleanup_module); 2938