1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 20 #include "rvu_trace.h" 21 22 #define DRV_NAME "rvu_af" 23 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 24 25 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 26 27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 28 struct rvu_block *block, int lf); 29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 32 33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 34 int type, int num, 35 void (mbox_handler)(struct work_struct *), 36 void (mbox_up_handler)(struct work_struct *)); 37 enum { 38 TYPE_AFVF, 39 TYPE_AFPF, 40 }; 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->rvu = rvu; 72 73 if (is_rvu_pre_96xx_C0(rvu)) { 74 hw->cap.nix_fixed_txschq_mapping = true; 75 hw->cap.nix_txsch_per_cgx_lmac = 4; 76 hw->cap.nix_txsch_per_lbk_lmac = 132; 77 hw->cap.nix_txsch_per_sdp_lmac = 76; 78 hw->cap.nix_shaping = false; 79 hw->cap.nix_tx_link_bp = false; 80 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 81 hw->cap.nix_rx_multicast = false; 82 } 83 if (!is_rvu_pre_96xx_C0(rvu)) 84 hw->cap.nix_shaper_toggle_wait = true; 85 86 if (!is_rvu_otx2(rvu)) 87 hw->cap.per_pf_mbox_regs = true; 88 } 89 90 /* Poll a RVU block's register 'offset', for a 'zero' 91 * or 'nonzero' at bits specified by 'mask' 92 */ 93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 94 { 95 unsigned long timeout = jiffies + usecs_to_jiffies(10000); 96 void __iomem *reg; 97 u64 reg_val; 98 99 reg = rvu->afreg_base + ((block << 28) | offset); 100 again: 101 reg_val = readq(reg); 102 if (zero && !(reg_val & mask)) 103 return 0; 104 if (!zero && (reg_val & mask)) 105 return 0; 106 if (time_before(jiffies, timeout)) { 107 usleep_range(1, 5); 108 goto again; 109 } 110 return -EBUSY; 111 } 112 113 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 114 { 115 int id; 116 117 if (!rsrc->bmap) 118 return -EINVAL; 119 120 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 121 if (id >= rsrc->max) 122 return -ENOSPC; 123 124 __set_bit(id, rsrc->bmap); 125 126 return id; 127 } 128 129 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 130 { 131 int start; 132 133 if (!rsrc->bmap) 134 return -EINVAL; 135 136 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 137 if (start >= rsrc->max) 138 return -ENOSPC; 139 140 bitmap_set(rsrc->bmap, start, nrsrc); 141 return start; 142 } 143 144 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 145 { 146 if (!rsrc->bmap) 147 return; 148 if (start >= rsrc->max) 149 return; 150 151 bitmap_clear(rsrc->bmap, start, nrsrc); 152 } 153 154 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 155 { 156 int start; 157 158 if (!rsrc->bmap) 159 return false; 160 161 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 162 if (start >= rsrc->max) 163 return false; 164 165 return true; 166 } 167 168 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 169 { 170 if (!rsrc->bmap) 171 return; 172 173 __clear_bit(id, rsrc->bmap); 174 } 175 176 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 177 { 178 int used; 179 180 if (!rsrc->bmap) 181 return 0; 182 183 used = bitmap_weight(rsrc->bmap, rsrc->max); 184 return (rsrc->max - used); 185 } 186 187 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 188 { 189 if (!rsrc->bmap) 190 return false; 191 192 return !test_bit(id, rsrc->bmap); 193 } 194 195 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 196 { 197 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 198 sizeof(long), GFP_KERNEL); 199 if (!rsrc->bmap) 200 return -ENOMEM; 201 return 0; 202 } 203 204 /* Get block LF's HW index from a PF_FUNC's block slot number */ 205 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 206 { 207 u16 match = 0; 208 int lf; 209 210 mutex_lock(&rvu->rsrc_lock); 211 for (lf = 0; lf < block->lf.max; lf++) { 212 if (block->fn_map[lf] == pcifunc) { 213 if (slot == match) { 214 mutex_unlock(&rvu->rsrc_lock); 215 return lf; 216 } 217 match++; 218 } 219 } 220 mutex_unlock(&rvu->rsrc_lock); 221 return -ENODEV; 222 } 223 224 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 225 * Some silicon variants of OcteonTX2 supports 226 * multiple blocks of same type. 227 * 228 * @pcifunc has to be zero when no LF is yet attached. 229 * 230 * For a pcifunc if LFs are attached from multiple blocks of same type, then 231 * return blkaddr of first encountered block. 232 */ 233 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 234 { 235 int devnum, blkaddr = -ENODEV; 236 u64 cfg, reg; 237 bool is_pf; 238 239 switch (blktype) { 240 case BLKTYPE_NPC: 241 blkaddr = BLKADDR_NPC; 242 goto exit; 243 case BLKTYPE_NPA: 244 blkaddr = BLKADDR_NPA; 245 goto exit; 246 case BLKTYPE_NIX: 247 /* For now assume NIX0 */ 248 if (!pcifunc) { 249 blkaddr = BLKADDR_NIX0; 250 goto exit; 251 } 252 break; 253 case BLKTYPE_SSO: 254 blkaddr = BLKADDR_SSO; 255 goto exit; 256 case BLKTYPE_SSOW: 257 blkaddr = BLKADDR_SSOW; 258 goto exit; 259 case BLKTYPE_TIM: 260 blkaddr = BLKADDR_TIM; 261 goto exit; 262 case BLKTYPE_CPT: 263 /* For now assume CPT0 */ 264 if (!pcifunc) { 265 blkaddr = BLKADDR_CPT0; 266 goto exit; 267 } 268 break; 269 } 270 271 /* Check if this is a RVU PF or VF */ 272 if (pcifunc & RVU_PFVF_FUNC_MASK) { 273 is_pf = false; 274 devnum = rvu_get_hwvf(rvu, pcifunc); 275 } else { 276 is_pf = true; 277 devnum = rvu_get_pf(pcifunc); 278 } 279 280 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 281 * 'BLKADDR_NIX1'. 282 */ 283 if (blktype == BLKTYPE_NIX) { 284 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 285 RVU_PRIV_HWVFX_NIXX_CFG(0); 286 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 287 if (cfg) { 288 blkaddr = BLKADDR_NIX0; 289 goto exit; 290 } 291 292 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 293 RVU_PRIV_HWVFX_NIXX_CFG(1); 294 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 295 if (cfg) 296 blkaddr = BLKADDR_NIX1; 297 } 298 299 if (blktype == BLKTYPE_CPT) { 300 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 301 RVU_PRIV_HWVFX_CPTX_CFG(0); 302 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 303 if (cfg) { 304 blkaddr = BLKADDR_CPT0; 305 goto exit; 306 } 307 308 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 309 RVU_PRIV_HWVFX_CPTX_CFG(1); 310 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 311 if (cfg) 312 blkaddr = BLKADDR_CPT1; 313 } 314 315 exit: 316 if (is_block_implemented(rvu->hw, blkaddr)) 317 return blkaddr; 318 return -ENODEV; 319 } 320 321 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 322 struct rvu_block *block, u16 pcifunc, 323 u16 lf, bool attach) 324 { 325 int devnum, num_lfs = 0; 326 bool is_pf; 327 u64 reg; 328 329 if (lf >= block->lf.max) { 330 dev_err(&rvu->pdev->dev, 331 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 332 __func__, lf, block->name, block->lf.max); 333 return; 334 } 335 336 /* Check if this is for a RVU PF or VF */ 337 if (pcifunc & RVU_PFVF_FUNC_MASK) { 338 is_pf = false; 339 devnum = rvu_get_hwvf(rvu, pcifunc); 340 } else { 341 is_pf = true; 342 devnum = rvu_get_pf(pcifunc); 343 } 344 345 block->fn_map[lf] = attach ? pcifunc : 0; 346 347 switch (block->addr) { 348 case BLKADDR_NPA: 349 pfvf->npalf = attach ? true : false; 350 num_lfs = pfvf->npalf; 351 break; 352 case BLKADDR_NIX0: 353 case BLKADDR_NIX1: 354 pfvf->nixlf = attach ? true : false; 355 num_lfs = pfvf->nixlf; 356 break; 357 case BLKADDR_SSO: 358 attach ? pfvf->sso++ : pfvf->sso--; 359 num_lfs = pfvf->sso; 360 break; 361 case BLKADDR_SSOW: 362 attach ? pfvf->ssow++ : pfvf->ssow--; 363 num_lfs = pfvf->ssow; 364 break; 365 case BLKADDR_TIM: 366 attach ? pfvf->timlfs++ : pfvf->timlfs--; 367 num_lfs = pfvf->timlfs; 368 break; 369 case BLKADDR_CPT0: 370 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 371 num_lfs = pfvf->cptlfs; 372 break; 373 case BLKADDR_CPT1: 374 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 375 num_lfs = pfvf->cpt1_lfs; 376 break; 377 } 378 379 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 380 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 381 } 382 383 inline int rvu_get_pf(u16 pcifunc) 384 { 385 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 386 } 387 388 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 389 { 390 u64 cfg; 391 392 /* Get numVFs attached to this PF and first HWVF */ 393 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 394 if (numvfs) 395 *numvfs = (cfg >> 12) & 0xFF; 396 if (hwvf) 397 *hwvf = cfg & 0xFFF; 398 } 399 400 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 401 { 402 int pf, func; 403 u64 cfg; 404 405 pf = rvu_get_pf(pcifunc); 406 func = pcifunc & RVU_PFVF_FUNC_MASK; 407 408 /* Get first HWVF attached to this PF */ 409 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 410 411 return ((cfg & 0xFFF) + func - 1); 412 } 413 414 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 415 { 416 /* Check if it is a PF or VF */ 417 if (pcifunc & RVU_PFVF_FUNC_MASK) 418 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 419 else 420 return &rvu->pf[rvu_get_pf(pcifunc)]; 421 } 422 423 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 424 { 425 int pf, vf, nvfs; 426 u64 cfg; 427 428 pf = rvu_get_pf(pcifunc); 429 if (pf >= rvu->hw->total_pfs) 430 return false; 431 432 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 433 return true; 434 435 /* Check if VF is within number of VFs attached to this PF */ 436 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 437 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 438 nvfs = (cfg >> 12) & 0xFF; 439 if (vf >= nvfs) 440 return false; 441 442 return true; 443 } 444 445 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 446 { 447 struct rvu_block *block; 448 449 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 450 return false; 451 452 block = &hw->block[blkaddr]; 453 return block->implemented; 454 } 455 456 static void rvu_check_block_implemented(struct rvu *rvu) 457 { 458 struct rvu_hwinfo *hw = rvu->hw; 459 struct rvu_block *block; 460 int blkid; 461 u64 cfg; 462 463 /* For each block check if 'implemented' bit is set */ 464 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 465 block = &hw->block[blkid]; 466 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 467 if (cfg & BIT_ULL(11)) 468 block->implemented = true; 469 } 470 } 471 472 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 473 { 474 rvu_write64(rvu, BLKADDR_RVUM, 475 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 476 RVU_BLK_RVUM_REVID); 477 } 478 479 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 480 { 481 rvu_write64(rvu, BLKADDR_RVUM, 482 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 483 } 484 485 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 486 { 487 int err; 488 489 if (!block->implemented) 490 return 0; 491 492 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 493 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 494 true); 495 return err; 496 } 497 498 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 499 { 500 struct rvu_block *block = &rvu->hw->block[blkaddr]; 501 int err; 502 503 if (!block->implemented) 504 return; 505 506 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 507 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 508 if (err) 509 dev_err(rvu->dev, "HW block:%d reset failed\n", blkaddr); 510 } 511 512 static void rvu_reset_all_blocks(struct rvu *rvu) 513 { 514 /* Do a HW reset of all RVU blocks */ 515 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 516 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 517 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 518 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 519 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 520 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 521 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 522 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 523 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 524 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 525 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 526 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 527 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 528 } 529 530 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 531 { 532 struct rvu_pfvf *pfvf; 533 u64 cfg; 534 int lf; 535 536 for (lf = 0; lf < block->lf.max; lf++) { 537 cfg = rvu_read64(rvu, block->addr, 538 block->lfcfg_reg | (lf << block->lfshift)); 539 if (!(cfg & BIT_ULL(63))) 540 continue; 541 542 /* Set this resource as being used */ 543 __set_bit(lf, block->lf.bmap); 544 545 /* Get, to whom this LF is attached */ 546 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 547 rvu_update_rsrc_map(rvu, pfvf, block, 548 (cfg >> 8) & 0xFFFF, lf, true); 549 550 /* Set start MSIX vector for this LF within this PF/VF */ 551 rvu_set_msix_offset(rvu, pfvf, block, lf); 552 } 553 } 554 555 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 556 { 557 int min_vecs; 558 559 if (!vf) 560 goto check_pf; 561 562 if (!nvecs) { 563 dev_warn(rvu->dev, 564 "PF%d:VF%d is configured with zero msix vectors, %d\n", 565 pf, vf - 1, nvecs); 566 } 567 return; 568 569 check_pf: 570 if (pf == 0) 571 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 572 else 573 min_vecs = RVU_PF_INT_VEC_CNT; 574 575 if (!(nvecs < min_vecs)) 576 return; 577 dev_warn(rvu->dev, 578 "PF%d is configured with too few vectors, %d, min is %d\n", 579 pf, nvecs, min_vecs); 580 } 581 582 static int rvu_setup_msix_resources(struct rvu *rvu) 583 { 584 struct rvu_hwinfo *hw = rvu->hw; 585 int pf, vf, numvfs, hwvf, err; 586 int nvecs, offset, max_msix; 587 struct rvu_pfvf *pfvf; 588 u64 cfg, phy_addr; 589 dma_addr_t iova; 590 591 for (pf = 0; pf < hw->total_pfs; pf++) { 592 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 593 /* If PF is not enabled, nothing to do */ 594 if (!((cfg >> 20) & 0x01)) 595 continue; 596 597 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 598 599 pfvf = &rvu->pf[pf]; 600 /* Get num of MSIX vectors attached to this PF */ 601 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 602 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 603 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 604 605 /* Alloc msix bitmap for this PF */ 606 err = rvu_alloc_bitmap(&pfvf->msix); 607 if (err) 608 return err; 609 610 /* Allocate memory for MSIX vector to RVU block LF mapping */ 611 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 612 sizeof(u16), GFP_KERNEL); 613 if (!pfvf->msix_lfmap) 614 return -ENOMEM; 615 616 /* For PF0 (AF) firmware will set msix vector offsets for 617 * AF, block AF and PF0_INT vectors, so jump to VFs. 618 */ 619 if (!pf) 620 goto setup_vfmsix; 621 622 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 623 * These are allocated on driver init and never freed, 624 * so no need to set 'msix_lfmap' for these. 625 */ 626 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 627 nvecs = (cfg >> 12) & 0xFF; 628 cfg &= ~0x7FFULL; 629 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 630 rvu_write64(rvu, BLKADDR_RVUM, 631 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 632 setup_vfmsix: 633 /* Alloc msix bitmap for VFs */ 634 for (vf = 0; vf < numvfs; vf++) { 635 pfvf = &rvu->hwvf[hwvf + vf]; 636 /* Get num of MSIX vectors attached to this VF */ 637 cfg = rvu_read64(rvu, BLKADDR_RVUM, 638 RVU_PRIV_PFX_MSIX_CFG(pf)); 639 pfvf->msix.max = (cfg & 0xFFF) + 1; 640 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 641 642 /* Alloc msix bitmap for this VF */ 643 err = rvu_alloc_bitmap(&pfvf->msix); 644 if (err) 645 return err; 646 647 pfvf->msix_lfmap = 648 devm_kcalloc(rvu->dev, pfvf->msix.max, 649 sizeof(u16), GFP_KERNEL); 650 if (!pfvf->msix_lfmap) 651 return -ENOMEM; 652 653 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 654 * These are allocated on driver init and never freed, 655 * so no need to set 'msix_lfmap' for these. 656 */ 657 cfg = rvu_read64(rvu, BLKADDR_RVUM, 658 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 659 nvecs = (cfg >> 12) & 0xFF; 660 cfg &= ~0x7FFULL; 661 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 662 rvu_write64(rvu, BLKADDR_RVUM, 663 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 664 cfg | offset); 665 } 666 } 667 668 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 669 * create an IOMMU mapping for the physical address configured by 670 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 671 */ 672 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 673 max_msix = cfg & 0xFFFFF; 674 if (rvu->fwdata && rvu->fwdata->msixtr_base) 675 phy_addr = rvu->fwdata->msixtr_base; 676 else 677 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 678 679 iova = dma_map_resource(rvu->dev, phy_addr, 680 max_msix * PCI_MSIX_ENTRY_SIZE, 681 DMA_BIDIRECTIONAL, 0); 682 683 if (dma_mapping_error(rvu->dev, iova)) 684 return -ENOMEM; 685 686 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 687 rvu->msix_base_iova = iova; 688 rvu->msixtr_base_phy = phy_addr; 689 690 return 0; 691 } 692 693 static void rvu_reset_msix(struct rvu *rvu) 694 { 695 /* Restore msixtr base register */ 696 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 697 rvu->msixtr_base_phy); 698 } 699 700 static void rvu_free_hw_resources(struct rvu *rvu) 701 { 702 struct rvu_hwinfo *hw = rvu->hw; 703 struct rvu_block *block; 704 struct rvu_pfvf *pfvf; 705 int id, max_msix; 706 u64 cfg; 707 708 rvu_npa_freemem(rvu); 709 rvu_npc_freemem(rvu); 710 rvu_nix_freemem(rvu); 711 712 /* Free block LF bitmaps */ 713 for (id = 0; id < BLK_COUNT; id++) { 714 block = &hw->block[id]; 715 kfree(block->lf.bmap); 716 } 717 718 /* Free MSIX bitmaps */ 719 for (id = 0; id < hw->total_pfs; id++) { 720 pfvf = &rvu->pf[id]; 721 kfree(pfvf->msix.bmap); 722 } 723 724 for (id = 0; id < hw->total_vfs; id++) { 725 pfvf = &rvu->hwvf[id]; 726 kfree(pfvf->msix.bmap); 727 } 728 729 /* Unmap MSIX vector base IOVA mapping */ 730 if (!rvu->msix_base_iova) 731 return; 732 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 733 max_msix = cfg & 0xFFFFF; 734 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 735 max_msix * PCI_MSIX_ENTRY_SIZE, 736 DMA_BIDIRECTIONAL, 0); 737 738 rvu_reset_msix(rvu); 739 mutex_destroy(&rvu->rsrc_lock); 740 } 741 742 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 743 { 744 struct rvu_hwinfo *hw = rvu->hw; 745 int pf, vf, numvfs, hwvf; 746 struct rvu_pfvf *pfvf; 747 u64 *mac; 748 749 for (pf = 0; pf < hw->total_pfs; pf++) { 750 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 751 if (!pf) 752 goto lbkvf; 753 754 if (!is_pf_cgxmapped(rvu, pf)) 755 continue; 756 /* Assign MAC address to PF */ 757 pfvf = &rvu->pf[pf]; 758 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 759 mac = &rvu->fwdata->pf_macs[pf]; 760 if (*mac) 761 u64_to_ether_addr(*mac, pfvf->mac_addr); 762 else 763 eth_random_addr(pfvf->mac_addr); 764 } else { 765 eth_random_addr(pfvf->mac_addr); 766 } 767 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 768 769 lbkvf: 770 /* Assign MAC address to VFs*/ 771 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 772 for (vf = 0; vf < numvfs; vf++, hwvf++) { 773 pfvf = &rvu->hwvf[hwvf]; 774 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 775 mac = &rvu->fwdata->vf_macs[hwvf]; 776 if (*mac) 777 u64_to_ether_addr(*mac, pfvf->mac_addr); 778 else 779 eth_random_addr(pfvf->mac_addr); 780 } else { 781 eth_random_addr(pfvf->mac_addr); 782 } 783 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 784 } 785 } 786 } 787 788 static int rvu_fwdata_init(struct rvu *rvu) 789 { 790 u64 fwdbase; 791 int err; 792 793 /* Get firmware data base address */ 794 err = cgx_get_fwdata_base(&fwdbase); 795 if (err) 796 goto fail; 797 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 798 if (!rvu->fwdata) 799 goto fail; 800 if (!is_rvu_fwdata_valid(rvu)) { 801 dev_err(rvu->dev, 802 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 803 iounmap(rvu->fwdata); 804 rvu->fwdata = NULL; 805 return -EINVAL; 806 } 807 return 0; 808 fail: 809 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 810 return -EIO; 811 } 812 813 static void rvu_fwdata_exit(struct rvu *rvu) 814 { 815 if (rvu->fwdata) 816 iounmap(rvu->fwdata); 817 } 818 819 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 820 { 821 struct rvu_hwinfo *hw = rvu->hw; 822 struct rvu_block *block; 823 int blkid; 824 u64 cfg; 825 826 /* Init NIX LF's bitmap */ 827 block = &hw->block[blkaddr]; 828 if (!block->implemented) 829 return 0; 830 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 831 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 832 block->lf.max = cfg & 0xFFF; 833 block->addr = blkaddr; 834 block->type = BLKTYPE_NIX; 835 block->lfshift = 8; 836 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 837 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 838 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 839 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 840 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 841 block->lfreset_reg = NIX_AF_LF_RST; 842 sprintf(block->name, "NIX%d", blkid); 843 rvu->nix_blkaddr[blkid] = blkaddr; 844 return rvu_alloc_bitmap(&block->lf); 845 } 846 847 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 848 { 849 struct rvu_hwinfo *hw = rvu->hw; 850 struct rvu_block *block; 851 int blkid; 852 u64 cfg; 853 854 /* Init CPT LF's bitmap */ 855 block = &hw->block[blkaddr]; 856 if (!block->implemented) 857 return 0; 858 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 859 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 860 block->lf.max = cfg & 0xFF; 861 block->addr = blkaddr; 862 block->type = BLKTYPE_CPT; 863 block->multislot = true; 864 block->lfshift = 3; 865 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 866 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 867 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 868 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 869 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 870 block->lfreset_reg = CPT_AF_LF_RST; 871 sprintf(block->name, "CPT%d", blkid); 872 return rvu_alloc_bitmap(&block->lf); 873 } 874 875 static void rvu_get_lbk_bufsize(struct rvu *rvu) 876 { 877 struct pci_dev *pdev = NULL; 878 void __iomem *base; 879 u64 lbk_const; 880 881 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 882 PCI_DEVID_OCTEONTX2_LBK, pdev); 883 if (!pdev) 884 return; 885 886 base = pci_ioremap_bar(pdev, 0); 887 if (!base) 888 goto err_put; 889 890 lbk_const = readq(base + LBK_CONST); 891 892 /* cache fifo size */ 893 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 894 895 iounmap(base); 896 err_put: 897 pci_dev_put(pdev); 898 } 899 900 static int rvu_setup_hw_resources(struct rvu *rvu) 901 { 902 struct rvu_hwinfo *hw = rvu->hw; 903 struct rvu_block *block; 904 int blkid, err; 905 u64 cfg; 906 907 /* Get HW supported max RVU PF & VF count */ 908 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 909 hw->total_pfs = (cfg >> 32) & 0xFF; 910 hw->total_vfs = (cfg >> 20) & 0xFFF; 911 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 912 913 /* Init NPA LF's bitmap */ 914 block = &hw->block[BLKADDR_NPA]; 915 if (!block->implemented) 916 goto nix; 917 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 918 block->lf.max = (cfg >> 16) & 0xFFF; 919 block->addr = BLKADDR_NPA; 920 block->type = BLKTYPE_NPA; 921 block->lfshift = 8; 922 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 923 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 924 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 925 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 926 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 927 block->lfreset_reg = NPA_AF_LF_RST; 928 sprintf(block->name, "NPA"); 929 err = rvu_alloc_bitmap(&block->lf); 930 if (err) { 931 dev_err(rvu->dev, 932 "%s: Failed to allocate NPA LF bitmap\n", __func__); 933 return err; 934 } 935 936 nix: 937 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 938 if (err) { 939 dev_err(rvu->dev, 940 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 941 return err; 942 } 943 944 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 945 if (err) { 946 dev_err(rvu->dev, 947 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 948 return err; 949 } 950 951 /* Init SSO group's bitmap */ 952 block = &hw->block[BLKADDR_SSO]; 953 if (!block->implemented) 954 goto ssow; 955 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 956 block->lf.max = cfg & 0xFFFF; 957 block->addr = BLKADDR_SSO; 958 block->type = BLKTYPE_SSO; 959 block->multislot = true; 960 block->lfshift = 3; 961 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 962 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 963 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 964 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 965 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 966 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 967 sprintf(block->name, "SSO GROUP"); 968 err = rvu_alloc_bitmap(&block->lf); 969 if (err) { 970 dev_err(rvu->dev, 971 "%s: Failed to allocate SSO LF bitmap\n", __func__); 972 return err; 973 } 974 975 ssow: 976 /* Init SSO workslot's bitmap */ 977 block = &hw->block[BLKADDR_SSOW]; 978 if (!block->implemented) 979 goto tim; 980 block->lf.max = (cfg >> 56) & 0xFF; 981 block->addr = BLKADDR_SSOW; 982 block->type = BLKTYPE_SSOW; 983 block->multislot = true; 984 block->lfshift = 3; 985 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 986 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 987 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 988 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 989 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 990 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 991 sprintf(block->name, "SSOWS"); 992 err = rvu_alloc_bitmap(&block->lf); 993 if (err) { 994 dev_err(rvu->dev, 995 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 996 return err; 997 } 998 999 tim: 1000 /* Init TIM LF's bitmap */ 1001 block = &hw->block[BLKADDR_TIM]; 1002 if (!block->implemented) 1003 goto cpt; 1004 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1005 block->lf.max = cfg & 0xFFFF; 1006 block->addr = BLKADDR_TIM; 1007 block->type = BLKTYPE_TIM; 1008 block->multislot = true; 1009 block->lfshift = 3; 1010 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1011 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1012 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1013 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1014 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1015 block->lfreset_reg = TIM_AF_LF_RST; 1016 sprintf(block->name, "TIM"); 1017 err = rvu_alloc_bitmap(&block->lf); 1018 if (err) { 1019 dev_err(rvu->dev, 1020 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1021 return err; 1022 } 1023 1024 cpt: 1025 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1026 if (err) { 1027 dev_err(rvu->dev, 1028 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1029 return err; 1030 } 1031 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1032 if (err) { 1033 dev_err(rvu->dev, 1034 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1035 return err; 1036 } 1037 1038 /* Allocate memory for PFVF data */ 1039 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1040 sizeof(struct rvu_pfvf), GFP_KERNEL); 1041 if (!rvu->pf) { 1042 dev_err(rvu->dev, 1043 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1044 return -ENOMEM; 1045 } 1046 1047 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1048 sizeof(struct rvu_pfvf), GFP_KERNEL); 1049 if (!rvu->hwvf) { 1050 dev_err(rvu->dev, 1051 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1052 return -ENOMEM; 1053 } 1054 1055 mutex_init(&rvu->rsrc_lock); 1056 1057 rvu_fwdata_init(rvu); 1058 1059 err = rvu_setup_msix_resources(rvu); 1060 if (err) { 1061 dev_err(rvu->dev, 1062 "%s: Failed to setup MSIX resources\n", __func__); 1063 return err; 1064 } 1065 1066 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1067 block = &hw->block[blkid]; 1068 if (!block->lf.bmap) 1069 continue; 1070 1071 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1072 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1073 sizeof(u16), GFP_KERNEL); 1074 if (!block->fn_map) { 1075 err = -ENOMEM; 1076 goto msix_err; 1077 } 1078 1079 /* Scan all blocks to check if low level firmware has 1080 * already provisioned any of the resources to a PF/VF. 1081 */ 1082 rvu_scan_block(rvu, block); 1083 } 1084 1085 err = rvu_set_channels_base(rvu); 1086 if (err) 1087 goto msix_err; 1088 1089 err = rvu_npc_init(rvu); 1090 if (err) { 1091 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1092 goto npc_err; 1093 } 1094 1095 err = rvu_cgx_init(rvu); 1096 if (err) { 1097 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1098 goto cgx_err; 1099 } 1100 1101 /* Assign MACs for CGX mapped functions */ 1102 rvu_setup_pfvf_macaddress(rvu); 1103 1104 err = rvu_npa_init(rvu); 1105 if (err) { 1106 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1107 goto npa_err; 1108 } 1109 1110 rvu_get_lbk_bufsize(rvu); 1111 1112 err = rvu_nix_init(rvu); 1113 if (err) { 1114 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1115 goto nix_err; 1116 } 1117 1118 err = rvu_sdp_init(rvu); 1119 if (err) { 1120 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1121 goto nix_err; 1122 } 1123 1124 rvu_program_channels(rvu); 1125 1126 return 0; 1127 1128 nix_err: 1129 rvu_nix_freemem(rvu); 1130 npa_err: 1131 rvu_npa_freemem(rvu); 1132 cgx_err: 1133 rvu_cgx_exit(rvu); 1134 npc_err: 1135 rvu_npc_freemem(rvu); 1136 rvu_fwdata_exit(rvu); 1137 msix_err: 1138 rvu_reset_msix(rvu); 1139 return err; 1140 } 1141 1142 /* NPA and NIX admin queue APIs */ 1143 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1144 { 1145 if (!aq) 1146 return; 1147 1148 qmem_free(rvu->dev, aq->inst); 1149 qmem_free(rvu->dev, aq->res); 1150 devm_kfree(rvu->dev, aq); 1151 } 1152 1153 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1154 int qsize, int inst_size, int res_size) 1155 { 1156 struct admin_queue *aq; 1157 int err; 1158 1159 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1160 if (!*ad_queue) 1161 return -ENOMEM; 1162 aq = *ad_queue; 1163 1164 /* Alloc memory for instructions i.e AQ */ 1165 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1166 if (err) { 1167 devm_kfree(rvu->dev, aq); 1168 return err; 1169 } 1170 1171 /* Alloc memory for results */ 1172 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1173 if (err) { 1174 rvu_aq_free(rvu, aq); 1175 return err; 1176 } 1177 1178 spin_lock_init(&aq->lock); 1179 return 0; 1180 } 1181 1182 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1183 struct ready_msg_rsp *rsp) 1184 { 1185 if (rvu->fwdata) { 1186 rsp->rclk_freq = rvu->fwdata->rclk; 1187 rsp->sclk_freq = rvu->fwdata->sclk; 1188 } 1189 return 0; 1190 } 1191 1192 /* Get current count of a RVU block's LF/slots 1193 * provisioned to a given RVU func. 1194 */ 1195 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1196 { 1197 switch (blkaddr) { 1198 case BLKADDR_NPA: 1199 return pfvf->npalf ? 1 : 0; 1200 case BLKADDR_NIX0: 1201 case BLKADDR_NIX1: 1202 return pfvf->nixlf ? 1 : 0; 1203 case BLKADDR_SSO: 1204 return pfvf->sso; 1205 case BLKADDR_SSOW: 1206 return pfvf->ssow; 1207 case BLKADDR_TIM: 1208 return pfvf->timlfs; 1209 case BLKADDR_CPT0: 1210 return pfvf->cptlfs; 1211 case BLKADDR_CPT1: 1212 return pfvf->cpt1_lfs; 1213 } 1214 return 0; 1215 } 1216 1217 /* Return true if LFs of block type are attached to pcifunc */ 1218 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1219 { 1220 switch (blktype) { 1221 case BLKTYPE_NPA: 1222 return pfvf->npalf ? 1 : 0; 1223 case BLKTYPE_NIX: 1224 return pfvf->nixlf ? 1 : 0; 1225 case BLKTYPE_SSO: 1226 return !!pfvf->sso; 1227 case BLKTYPE_SSOW: 1228 return !!pfvf->ssow; 1229 case BLKTYPE_TIM: 1230 return !!pfvf->timlfs; 1231 case BLKTYPE_CPT: 1232 return pfvf->cptlfs || pfvf->cpt1_lfs; 1233 } 1234 1235 return false; 1236 } 1237 1238 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1239 { 1240 struct rvu_pfvf *pfvf; 1241 1242 if (!is_pf_func_valid(rvu, pcifunc)) 1243 return false; 1244 1245 pfvf = rvu_get_pfvf(rvu, pcifunc); 1246 1247 /* Check if this PFFUNC has a LF of type blktype attached */ 1248 if (!is_blktype_attached(pfvf, blktype)) 1249 return false; 1250 1251 return true; 1252 } 1253 1254 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1255 int pcifunc, int slot) 1256 { 1257 u64 val; 1258 1259 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1260 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1261 /* Wait for the lookup to finish */ 1262 /* TODO: put some timeout here */ 1263 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1264 ; 1265 1266 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1267 1268 /* Check LF valid bit */ 1269 if (!(val & (1ULL << 12))) 1270 return -1; 1271 1272 return (val & 0xFFF); 1273 } 1274 1275 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1276 { 1277 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1278 struct rvu_hwinfo *hw = rvu->hw; 1279 struct rvu_block *block; 1280 int slot, lf, num_lfs; 1281 int blkaddr; 1282 1283 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1284 if (blkaddr < 0) 1285 return; 1286 1287 if (blktype == BLKTYPE_NIX) 1288 rvu_nix_reset_mac(pfvf, pcifunc); 1289 1290 block = &hw->block[blkaddr]; 1291 1292 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1293 if (!num_lfs) 1294 return; 1295 1296 for (slot = 0; slot < num_lfs; slot++) { 1297 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1298 if (lf < 0) /* This should never happen */ 1299 continue; 1300 1301 /* Disable the LF */ 1302 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1303 (lf << block->lfshift), 0x00ULL); 1304 1305 /* Update SW maintained mapping info as well */ 1306 rvu_update_rsrc_map(rvu, pfvf, block, 1307 pcifunc, lf, false); 1308 1309 /* Free the resource */ 1310 rvu_free_rsrc(&block->lf, lf); 1311 1312 /* Clear MSIX vector offset for this LF */ 1313 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1314 } 1315 } 1316 1317 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1318 u16 pcifunc) 1319 { 1320 struct rvu_hwinfo *hw = rvu->hw; 1321 bool detach_all = true; 1322 struct rvu_block *block; 1323 int blkid; 1324 1325 mutex_lock(&rvu->rsrc_lock); 1326 1327 /* Check for partial resource detach */ 1328 if (detach && detach->partial) 1329 detach_all = false; 1330 1331 /* Check for RVU block's LFs attached to this func, 1332 * if so, detach them. 1333 */ 1334 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1335 block = &hw->block[blkid]; 1336 if (!block->lf.bmap) 1337 continue; 1338 if (!detach_all && detach) { 1339 if (blkid == BLKADDR_NPA && !detach->npalf) 1340 continue; 1341 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1342 continue; 1343 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1344 continue; 1345 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1346 continue; 1347 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1348 continue; 1349 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1350 continue; 1351 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1352 continue; 1353 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1354 continue; 1355 } 1356 rvu_detach_block(rvu, pcifunc, block->type); 1357 } 1358 1359 mutex_unlock(&rvu->rsrc_lock); 1360 return 0; 1361 } 1362 1363 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1364 struct rsrc_detach *detach, 1365 struct msg_rsp *rsp) 1366 { 1367 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1368 } 1369 1370 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1371 { 1372 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1373 int blkaddr = BLKADDR_NIX0, vf; 1374 struct rvu_pfvf *pf; 1375 1376 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1377 1378 /* All CGX mapped PFs are set with assigned NIX block during init */ 1379 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1380 blkaddr = pf->nix_blkaddr; 1381 } else if (is_afvf(pcifunc)) { 1382 vf = pcifunc - 1; 1383 /* Assign NIX based on VF number. All even numbered VFs get 1384 * NIX0 and odd numbered gets NIX1 1385 */ 1386 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1387 /* NIX1 is not present on all silicons */ 1388 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1389 blkaddr = BLKADDR_NIX0; 1390 } 1391 1392 /* if SDP1 then the blkaddr is NIX1 */ 1393 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1394 blkaddr = BLKADDR_NIX1; 1395 1396 switch (blkaddr) { 1397 case BLKADDR_NIX1: 1398 pfvf->nix_blkaddr = BLKADDR_NIX1; 1399 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1400 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1401 break; 1402 case BLKADDR_NIX0: 1403 default: 1404 pfvf->nix_blkaddr = BLKADDR_NIX0; 1405 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1406 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1407 break; 1408 } 1409 1410 return pfvf->nix_blkaddr; 1411 } 1412 1413 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1414 u16 pcifunc, struct rsrc_attach *attach) 1415 { 1416 int blkaddr; 1417 1418 switch (blktype) { 1419 case BLKTYPE_NIX: 1420 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1421 break; 1422 case BLKTYPE_CPT: 1423 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1424 return rvu_get_blkaddr(rvu, blktype, 0); 1425 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1426 BLKADDR_CPT0; 1427 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1428 return -ENODEV; 1429 break; 1430 default: 1431 return rvu_get_blkaddr(rvu, blktype, 0); 1432 } 1433 1434 if (is_block_implemented(rvu->hw, blkaddr)) 1435 return blkaddr; 1436 1437 return -ENODEV; 1438 } 1439 1440 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1441 int num_lfs, struct rsrc_attach *attach) 1442 { 1443 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1444 struct rvu_hwinfo *hw = rvu->hw; 1445 struct rvu_block *block; 1446 int slot, lf; 1447 int blkaddr; 1448 u64 cfg; 1449 1450 if (!num_lfs) 1451 return; 1452 1453 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1454 if (blkaddr < 0) 1455 return; 1456 1457 block = &hw->block[blkaddr]; 1458 if (!block->lf.bmap) 1459 return; 1460 1461 for (slot = 0; slot < num_lfs; slot++) { 1462 /* Allocate the resource */ 1463 lf = rvu_alloc_rsrc(&block->lf); 1464 if (lf < 0) 1465 return; 1466 1467 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1468 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1469 (lf << block->lfshift), cfg); 1470 rvu_update_rsrc_map(rvu, pfvf, block, 1471 pcifunc, lf, true); 1472 1473 /* Set start MSIX vector for this LF within this PF/VF */ 1474 rvu_set_msix_offset(rvu, pfvf, block, lf); 1475 } 1476 } 1477 1478 static int rvu_check_rsrc_availability(struct rvu *rvu, 1479 struct rsrc_attach *req, u16 pcifunc) 1480 { 1481 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1482 int free_lfs, mappedlfs, blkaddr; 1483 struct rvu_hwinfo *hw = rvu->hw; 1484 struct rvu_block *block; 1485 1486 /* Only one NPA LF can be attached */ 1487 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1488 block = &hw->block[BLKADDR_NPA]; 1489 free_lfs = rvu_rsrc_free_count(&block->lf); 1490 if (!free_lfs) 1491 goto fail; 1492 } else if (req->npalf) { 1493 dev_err(&rvu->pdev->dev, 1494 "Func 0x%x: Invalid req, already has NPA\n", 1495 pcifunc); 1496 return -EINVAL; 1497 } 1498 1499 /* Only one NIX LF can be attached */ 1500 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1501 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1502 pcifunc, req); 1503 if (blkaddr < 0) 1504 return blkaddr; 1505 block = &hw->block[blkaddr]; 1506 free_lfs = rvu_rsrc_free_count(&block->lf); 1507 if (!free_lfs) 1508 goto fail; 1509 } else if (req->nixlf) { 1510 dev_err(&rvu->pdev->dev, 1511 "Func 0x%x: Invalid req, already has NIX\n", 1512 pcifunc); 1513 return -EINVAL; 1514 } 1515 1516 if (req->sso) { 1517 block = &hw->block[BLKADDR_SSO]; 1518 /* Is request within limits ? */ 1519 if (req->sso > block->lf.max) { 1520 dev_err(&rvu->pdev->dev, 1521 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1522 pcifunc, req->sso, block->lf.max); 1523 return -EINVAL; 1524 } 1525 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1526 free_lfs = rvu_rsrc_free_count(&block->lf); 1527 /* Check if additional resources are available */ 1528 if (req->sso > mappedlfs && 1529 ((req->sso - mappedlfs) > free_lfs)) 1530 goto fail; 1531 } 1532 1533 if (req->ssow) { 1534 block = &hw->block[BLKADDR_SSOW]; 1535 if (req->ssow > block->lf.max) { 1536 dev_err(&rvu->pdev->dev, 1537 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1538 pcifunc, req->sso, block->lf.max); 1539 return -EINVAL; 1540 } 1541 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1542 free_lfs = rvu_rsrc_free_count(&block->lf); 1543 if (req->ssow > mappedlfs && 1544 ((req->ssow - mappedlfs) > free_lfs)) 1545 goto fail; 1546 } 1547 1548 if (req->timlfs) { 1549 block = &hw->block[BLKADDR_TIM]; 1550 if (req->timlfs > block->lf.max) { 1551 dev_err(&rvu->pdev->dev, 1552 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1553 pcifunc, req->timlfs, block->lf.max); 1554 return -EINVAL; 1555 } 1556 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1557 free_lfs = rvu_rsrc_free_count(&block->lf); 1558 if (req->timlfs > mappedlfs && 1559 ((req->timlfs - mappedlfs) > free_lfs)) 1560 goto fail; 1561 } 1562 1563 if (req->cptlfs) { 1564 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1565 pcifunc, req); 1566 if (blkaddr < 0) 1567 return blkaddr; 1568 block = &hw->block[blkaddr]; 1569 if (req->cptlfs > block->lf.max) { 1570 dev_err(&rvu->pdev->dev, 1571 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1572 pcifunc, req->cptlfs, block->lf.max); 1573 return -EINVAL; 1574 } 1575 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1576 free_lfs = rvu_rsrc_free_count(&block->lf); 1577 if (req->cptlfs > mappedlfs && 1578 ((req->cptlfs - mappedlfs) > free_lfs)) 1579 goto fail; 1580 } 1581 1582 return 0; 1583 1584 fail: 1585 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1586 return -ENOSPC; 1587 } 1588 1589 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1590 struct rsrc_attach *attach) 1591 { 1592 int blkaddr, num_lfs; 1593 1594 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1595 attach->hdr.pcifunc, attach); 1596 if (blkaddr < 0) 1597 return false; 1598 1599 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1600 blkaddr); 1601 /* Requester already has LFs from given block ? */ 1602 return !!num_lfs; 1603 } 1604 1605 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1606 struct rsrc_attach *attach, 1607 struct msg_rsp *rsp) 1608 { 1609 u16 pcifunc = attach->hdr.pcifunc; 1610 int err; 1611 1612 /* If first request, detach all existing attached resources */ 1613 if (!attach->modify) 1614 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1615 1616 mutex_lock(&rvu->rsrc_lock); 1617 1618 /* Check if the request can be accommodated */ 1619 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1620 if (err) 1621 goto exit; 1622 1623 /* Now attach the requested resources */ 1624 if (attach->npalf) 1625 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1626 1627 if (attach->nixlf) 1628 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1629 1630 if (attach->sso) { 1631 /* RVU func doesn't know which exact LF or slot is attached 1632 * to it, it always sees as slot 0,1,2. So for a 'modify' 1633 * request, simply detach all existing attached LFs/slots 1634 * and attach a fresh. 1635 */ 1636 if (attach->modify) 1637 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1638 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1639 attach->sso, attach); 1640 } 1641 1642 if (attach->ssow) { 1643 if (attach->modify) 1644 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1645 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1646 attach->ssow, attach); 1647 } 1648 1649 if (attach->timlfs) { 1650 if (attach->modify) 1651 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1652 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1653 attach->timlfs, attach); 1654 } 1655 1656 if (attach->cptlfs) { 1657 if (attach->modify && 1658 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1659 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1660 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1661 attach->cptlfs, attach); 1662 } 1663 1664 exit: 1665 mutex_unlock(&rvu->rsrc_lock); 1666 return err; 1667 } 1668 1669 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1670 int blkaddr, int lf) 1671 { 1672 u16 vec; 1673 1674 if (lf < 0) 1675 return MSIX_VECTOR_INVALID; 1676 1677 for (vec = 0; vec < pfvf->msix.max; vec++) { 1678 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1679 return vec; 1680 } 1681 return MSIX_VECTOR_INVALID; 1682 } 1683 1684 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1685 struct rvu_block *block, int lf) 1686 { 1687 u16 nvecs, vec, offset; 1688 u64 cfg; 1689 1690 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1691 (lf << block->lfshift)); 1692 nvecs = (cfg >> 12) & 0xFF; 1693 1694 /* Check and alloc MSIX vectors, must be contiguous */ 1695 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1696 return; 1697 1698 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1699 1700 /* Config MSIX offset in LF */ 1701 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1702 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1703 1704 /* Update the bitmap as well */ 1705 for (vec = 0; vec < nvecs; vec++) 1706 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1707 } 1708 1709 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1710 struct rvu_block *block, int lf) 1711 { 1712 u16 nvecs, vec, offset; 1713 u64 cfg; 1714 1715 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1716 (lf << block->lfshift)); 1717 nvecs = (cfg >> 12) & 0xFF; 1718 1719 /* Clear MSIX offset in LF */ 1720 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1721 (lf << block->lfshift), cfg & ~0x7FFULL); 1722 1723 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1724 1725 /* Update the mapping */ 1726 for (vec = 0; vec < nvecs; vec++) 1727 pfvf->msix_lfmap[offset + vec] = 0; 1728 1729 /* Free the same in MSIX bitmap */ 1730 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1731 } 1732 1733 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1734 struct msix_offset_rsp *rsp) 1735 { 1736 struct rvu_hwinfo *hw = rvu->hw; 1737 u16 pcifunc = req->hdr.pcifunc; 1738 struct rvu_pfvf *pfvf; 1739 int lf, slot, blkaddr; 1740 1741 pfvf = rvu_get_pfvf(rvu, pcifunc); 1742 if (!pfvf->msix.bmap) 1743 return 0; 1744 1745 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1746 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1747 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1748 1749 /* Get BLKADDR from which LFs are attached to pcifunc */ 1750 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1751 if (blkaddr < 0) { 1752 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1753 } else { 1754 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1755 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1756 } 1757 1758 rsp->sso = pfvf->sso; 1759 for (slot = 0; slot < rsp->sso; slot++) { 1760 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1761 rsp->sso_msixoff[slot] = 1762 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1763 } 1764 1765 rsp->ssow = pfvf->ssow; 1766 for (slot = 0; slot < rsp->ssow; slot++) { 1767 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1768 rsp->ssow_msixoff[slot] = 1769 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1770 } 1771 1772 rsp->timlfs = pfvf->timlfs; 1773 for (slot = 0; slot < rsp->timlfs; slot++) { 1774 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1775 rsp->timlf_msixoff[slot] = 1776 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1777 } 1778 1779 rsp->cptlfs = pfvf->cptlfs; 1780 for (slot = 0; slot < rsp->cptlfs; slot++) { 1781 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1782 rsp->cptlf_msixoff[slot] = 1783 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1784 } 1785 1786 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1787 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1788 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1789 rsp->cpt1_lf_msixoff[slot] = 1790 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1791 } 1792 1793 return 0; 1794 } 1795 1796 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1797 struct free_rsrcs_rsp *rsp) 1798 { 1799 struct rvu_hwinfo *hw = rvu->hw; 1800 struct rvu_block *block; 1801 struct nix_txsch *txsch; 1802 struct nix_hw *nix_hw; 1803 1804 mutex_lock(&rvu->rsrc_lock); 1805 1806 block = &hw->block[BLKADDR_NPA]; 1807 rsp->npa = rvu_rsrc_free_count(&block->lf); 1808 1809 block = &hw->block[BLKADDR_NIX0]; 1810 rsp->nix = rvu_rsrc_free_count(&block->lf); 1811 1812 block = &hw->block[BLKADDR_NIX1]; 1813 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1814 1815 block = &hw->block[BLKADDR_SSO]; 1816 rsp->sso = rvu_rsrc_free_count(&block->lf); 1817 1818 block = &hw->block[BLKADDR_SSOW]; 1819 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1820 1821 block = &hw->block[BLKADDR_TIM]; 1822 rsp->tim = rvu_rsrc_free_count(&block->lf); 1823 1824 block = &hw->block[BLKADDR_CPT0]; 1825 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1826 1827 block = &hw->block[BLKADDR_CPT1]; 1828 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1829 1830 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1831 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1832 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1833 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1834 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1835 /* NIX1 */ 1836 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1837 goto out; 1838 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1839 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1840 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1841 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1842 } else { 1843 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1844 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1845 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1846 rvu_rsrc_free_count(&txsch->schq); 1847 1848 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1849 rsp->schq[NIX_TXSCH_LVL_TL4] = 1850 rvu_rsrc_free_count(&txsch->schq); 1851 1852 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1853 rsp->schq[NIX_TXSCH_LVL_TL3] = 1854 rvu_rsrc_free_count(&txsch->schq); 1855 1856 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1857 rsp->schq[NIX_TXSCH_LVL_TL2] = 1858 rvu_rsrc_free_count(&txsch->schq); 1859 1860 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1861 goto out; 1862 1863 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1864 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1865 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1866 rvu_rsrc_free_count(&txsch->schq); 1867 1868 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1869 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1870 rvu_rsrc_free_count(&txsch->schq); 1871 1872 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1873 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1874 rvu_rsrc_free_count(&txsch->schq); 1875 1876 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1877 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1878 rvu_rsrc_free_count(&txsch->schq); 1879 } 1880 1881 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1882 out: 1883 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1884 mutex_unlock(&rvu->rsrc_lock); 1885 1886 return 0; 1887 } 1888 1889 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1890 struct msg_rsp *rsp) 1891 { 1892 u16 pcifunc = req->hdr.pcifunc; 1893 u16 vf, numvfs; 1894 u64 cfg; 1895 1896 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1897 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1898 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1899 numvfs = (cfg >> 12) & 0xFF; 1900 1901 if (vf && vf <= numvfs) 1902 __rvu_flr_handler(rvu, pcifunc); 1903 else 1904 return RVU_INVALID_VF_ID; 1905 1906 return 0; 1907 } 1908 1909 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1910 struct get_hw_cap_rsp *rsp) 1911 { 1912 struct rvu_hwinfo *hw = rvu->hw; 1913 1914 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1915 rsp->nix_shaping = hw->cap.nix_shaping; 1916 1917 return 0; 1918 } 1919 1920 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 1921 struct msg_rsp *rsp) 1922 { 1923 struct rvu_hwinfo *hw = rvu->hw; 1924 u16 pcifunc = req->hdr.pcifunc; 1925 struct rvu_pfvf *pfvf; 1926 int blkaddr, nixlf; 1927 u16 target; 1928 1929 /* Only PF can add VF permissions */ 1930 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc)) 1931 return -EOPNOTSUPP; 1932 1933 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 1934 pfvf = rvu_get_pfvf(rvu, target); 1935 1936 if (req->flags & RESET_VF_PERM) { 1937 pfvf->flags &= RVU_CLEAR_VF_PERM; 1938 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 1939 (req->flags & VF_TRUSTED)) { 1940 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 1941 /* disable multicast and promisc entries */ 1942 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 1943 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 1944 if (blkaddr < 0) 1945 return 0; 1946 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 1947 target, 0); 1948 if (nixlf < 0) 1949 return 0; 1950 npc_enadis_default_mce_entry(rvu, target, nixlf, 1951 NIXLF_ALLMULTI_ENTRY, 1952 false); 1953 npc_enadis_default_mce_entry(rvu, target, nixlf, 1954 NIXLF_PROMISC_ENTRY, 1955 false); 1956 } 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1963 struct mbox_msghdr *req) 1964 { 1965 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1966 1967 /* Check if valid, if not reply with a invalid msg */ 1968 if (req->sig != OTX2_MBOX_REQ_SIG) 1969 goto bad_message; 1970 1971 switch (req->id) { 1972 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1973 case _id: { \ 1974 struct _rsp_type *rsp; \ 1975 int err; \ 1976 \ 1977 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1978 mbox, devid, \ 1979 sizeof(struct _rsp_type)); \ 1980 /* some handlers should complete even if reply */ \ 1981 /* could not be allocated */ \ 1982 if (!rsp && \ 1983 _id != MBOX_MSG_DETACH_RESOURCES && \ 1984 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1985 _id != MBOX_MSG_VF_FLR) \ 1986 return -ENOMEM; \ 1987 if (rsp) { \ 1988 rsp->hdr.id = _id; \ 1989 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1990 rsp->hdr.pcifunc = req->pcifunc; \ 1991 rsp->hdr.rc = 0; \ 1992 } \ 1993 \ 1994 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1995 (struct _req_type *)req, \ 1996 rsp); \ 1997 if (rsp && err) \ 1998 rsp->hdr.rc = err; \ 1999 \ 2000 trace_otx2_msg_process(mbox->pdev, _id, err); \ 2001 return rsp ? err : -ENOMEM; \ 2002 } 2003 MBOX_MESSAGES 2004 #undef M 2005 2006 bad_message: 2007 default: 2008 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2009 return -ENODEV; 2010 } 2011 } 2012 2013 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 2014 { 2015 struct rvu *rvu = mwork->rvu; 2016 int offset, err, id, devid; 2017 struct otx2_mbox_dev *mdev; 2018 struct mbox_hdr *req_hdr; 2019 struct mbox_msghdr *msg; 2020 struct mbox_wq_info *mw; 2021 struct otx2_mbox *mbox; 2022 2023 switch (type) { 2024 case TYPE_AFPF: 2025 mw = &rvu->afpf_wq_info; 2026 break; 2027 case TYPE_AFVF: 2028 mw = &rvu->afvf_wq_info; 2029 break; 2030 default: 2031 return; 2032 } 2033 2034 devid = mwork - mw->mbox_wrk; 2035 mbox = &mw->mbox; 2036 mdev = &mbox->dev[devid]; 2037 2038 /* Process received mbox messages */ 2039 req_hdr = mdev->mbase + mbox->rx_start; 2040 if (mw->mbox_wrk[devid].num_msgs == 0) 2041 return; 2042 2043 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2044 2045 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2046 msg = mdev->mbase + offset; 2047 2048 /* Set which PF/VF sent this message based on mbox IRQ */ 2049 switch (type) { 2050 case TYPE_AFPF: 2051 msg->pcifunc &= 2052 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2053 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2054 break; 2055 case TYPE_AFVF: 2056 msg->pcifunc &= 2057 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2058 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2059 break; 2060 } 2061 2062 err = rvu_process_mbox_msg(mbox, devid, msg); 2063 if (!err) { 2064 offset = mbox->rx_start + msg->next_msgoff; 2065 continue; 2066 } 2067 2068 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2069 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2070 err, otx2_mbox_id2name(msg->id), 2071 msg->id, rvu_get_pf(msg->pcifunc), 2072 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2073 else 2074 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2075 err, otx2_mbox_id2name(msg->id), 2076 msg->id, devid); 2077 } 2078 mw->mbox_wrk[devid].num_msgs = 0; 2079 2080 /* Send mbox responses to VF/PF */ 2081 otx2_mbox_msg_send(mbox, devid); 2082 } 2083 2084 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2085 { 2086 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2087 2088 __rvu_mbox_handler(mwork, TYPE_AFPF); 2089 } 2090 2091 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2092 { 2093 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2094 2095 __rvu_mbox_handler(mwork, TYPE_AFVF); 2096 } 2097 2098 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2099 { 2100 struct rvu *rvu = mwork->rvu; 2101 struct otx2_mbox_dev *mdev; 2102 struct mbox_hdr *rsp_hdr; 2103 struct mbox_msghdr *msg; 2104 struct mbox_wq_info *mw; 2105 struct otx2_mbox *mbox; 2106 int offset, id, devid; 2107 2108 switch (type) { 2109 case TYPE_AFPF: 2110 mw = &rvu->afpf_wq_info; 2111 break; 2112 case TYPE_AFVF: 2113 mw = &rvu->afvf_wq_info; 2114 break; 2115 default: 2116 return; 2117 } 2118 2119 devid = mwork - mw->mbox_wrk_up; 2120 mbox = &mw->mbox_up; 2121 mdev = &mbox->dev[devid]; 2122 2123 rsp_hdr = mdev->mbase + mbox->rx_start; 2124 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2125 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2126 return; 2127 } 2128 2129 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2130 2131 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2132 msg = mdev->mbase + offset; 2133 2134 if (msg->id >= MBOX_MSG_MAX) { 2135 dev_err(rvu->dev, 2136 "Mbox msg with unknown ID 0x%x\n", msg->id); 2137 goto end; 2138 } 2139 2140 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2141 dev_err(rvu->dev, 2142 "Mbox msg with wrong signature %x, ID 0x%x\n", 2143 msg->sig, msg->id); 2144 goto end; 2145 } 2146 2147 switch (msg->id) { 2148 case MBOX_MSG_CGX_LINK_EVENT: 2149 break; 2150 default: 2151 if (msg->rc) 2152 dev_err(rvu->dev, 2153 "Mbox msg response has err %d, ID 0x%x\n", 2154 msg->rc, msg->id); 2155 break; 2156 } 2157 end: 2158 offset = mbox->rx_start + msg->next_msgoff; 2159 mdev->msgs_acked++; 2160 } 2161 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2162 2163 otx2_mbox_reset(mbox, devid); 2164 } 2165 2166 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2167 { 2168 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2169 2170 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2171 } 2172 2173 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2174 { 2175 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2176 2177 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2178 } 2179 2180 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2181 int num, int type) 2182 { 2183 struct rvu_hwinfo *hw = rvu->hw; 2184 int region; 2185 u64 bar4; 2186 2187 /* For cn10k platform VF mailbox regions of a PF follows after the 2188 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2189 * RVU_PF_VF_BAR4_ADDR register. 2190 */ 2191 if (type == TYPE_AFVF) { 2192 for (region = 0; region < num; region++) { 2193 if (hw->cap.per_pf_mbox_regs) { 2194 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2195 RVU_AF_PFX_BAR4_ADDR(0)) + 2196 MBOX_SIZE; 2197 bar4 += region * MBOX_SIZE; 2198 } else { 2199 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2200 bar4 += region * MBOX_SIZE; 2201 } 2202 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2203 if (!mbox_addr[region]) 2204 goto error; 2205 } 2206 return 0; 2207 } 2208 2209 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2210 * PF registers. Whereas for Octeontx2 it is read from 2211 * RVU_AF_PF_BAR4_ADDR register. 2212 */ 2213 for (region = 0; region < num; region++) { 2214 if (hw->cap.per_pf_mbox_regs) { 2215 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2216 RVU_AF_PFX_BAR4_ADDR(region)); 2217 } else { 2218 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2219 RVU_AF_PF_BAR4_ADDR); 2220 bar4 += region * MBOX_SIZE; 2221 } 2222 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2223 if (!mbox_addr[region]) 2224 goto error; 2225 } 2226 return 0; 2227 2228 error: 2229 while (region--) 2230 iounmap((void __iomem *)mbox_addr[region]); 2231 return -ENOMEM; 2232 } 2233 2234 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2235 int type, int num, 2236 void (mbox_handler)(struct work_struct *), 2237 void (mbox_up_handler)(struct work_struct *)) 2238 { 2239 int err = -EINVAL, i, dir, dir_up; 2240 void __iomem *reg_base; 2241 struct rvu_work *mwork; 2242 void **mbox_regions; 2243 const char *name; 2244 2245 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2246 if (!mbox_regions) 2247 return -ENOMEM; 2248 2249 switch (type) { 2250 case TYPE_AFPF: 2251 name = "rvu_afpf_mailbox"; 2252 dir = MBOX_DIR_AFPF; 2253 dir_up = MBOX_DIR_AFPF_UP; 2254 reg_base = rvu->afreg_base; 2255 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF); 2256 if (err) 2257 goto free_regions; 2258 break; 2259 case TYPE_AFVF: 2260 name = "rvu_afvf_mailbox"; 2261 dir = MBOX_DIR_PFVF; 2262 dir_up = MBOX_DIR_PFVF_UP; 2263 reg_base = rvu->pfreg_base; 2264 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF); 2265 if (err) 2266 goto free_regions; 2267 break; 2268 default: 2269 return err; 2270 } 2271 2272 mw->mbox_wq = alloc_workqueue(name, 2273 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2274 num); 2275 if (!mw->mbox_wq) { 2276 err = -ENOMEM; 2277 goto unmap_regions; 2278 } 2279 2280 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2281 sizeof(struct rvu_work), GFP_KERNEL); 2282 if (!mw->mbox_wrk) { 2283 err = -ENOMEM; 2284 goto exit; 2285 } 2286 2287 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2288 sizeof(struct rvu_work), GFP_KERNEL); 2289 if (!mw->mbox_wrk_up) { 2290 err = -ENOMEM; 2291 goto exit; 2292 } 2293 2294 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2295 reg_base, dir, num); 2296 if (err) 2297 goto exit; 2298 2299 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2300 reg_base, dir_up, num); 2301 if (err) 2302 goto exit; 2303 2304 for (i = 0; i < num; i++) { 2305 mwork = &mw->mbox_wrk[i]; 2306 mwork->rvu = rvu; 2307 INIT_WORK(&mwork->work, mbox_handler); 2308 2309 mwork = &mw->mbox_wrk_up[i]; 2310 mwork->rvu = rvu; 2311 INIT_WORK(&mwork->work, mbox_up_handler); 2312 } 2313 kfree(mbox_regions); 2314 return 0; 2315 2316 exit: 2317 destroy_workqueue(mw->mbox_wq); 2318 unmap_regions: 2319 while (num--) 2320 iounmap((void __iomem *)mbox_regions[num]); 2321 free_regions: 2322 kfree(mbox_regions); 2323 return err; 2324 } 2325 2326 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2327 { 2328 struct otx2_mbox *mbox = &mw->mbox; 2329 struct otx2_mbox_dev *mdev; 2330 int devid; 2331 2332 if (mw->mbox_wq) { 2333 flush_workqueue(mw->mbox_wq); 2334 destroy_workqueue(mw->mbox_wq); 2335 mw->mbox_wq = NULL; 2336 } 2337 2338 for (devid = 0; devid < mbox->ndevs; devid++) { 2339 mdev = &mbox->dev[devid]; 2340 if (mdev->hwbase) 2341 iounmap((void __iomem *)mdev->hwbase); 2342 } 2343 2344 otx2_mbox_destroy(&mw->mbox); 2345 otx2_mbox_destroy(&mw->mbox_up); 2346 } 2347 2348 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2349 int mdevs, u64 intr) 2350 { 2351 struct otx2_mbox_dev *mdev; 2352 struct otx2_mbox *mbox; 2353 struct mbox_hdr *hdr; 2354 int i; 2355 2356 for (i = first; i < mdevs; i++) { 2357 /* start from 0 */ 2358 if (!(intr & BIT_ULL(i - first))) 2359 continue; 2360 2361 mbox = &mw->mbox; 2362 mdev = &mbox->dev[i]; 2363 hdr = mdev->mbase + mbox->rx_start; 2364 2365 /*The hdr->num_msgs is set to zero immediately in the interrupt 2366 * handler to ensure that it holds a correct value next time 2367 * when the interrupt handler is called. 2368 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2369 * pf>mbox.up_num_msgs holds the data for use in 2370 * pfaf_mbox_up_handler. 2371 */ 2372 2373 if (hdr->num_msgs) { 2374 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2375 hdr->num_msgs = 0; 2376 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2377 } 2378 mbox = &mw->mbox_up; 2379 mdev = &mbox->dev[i]; 2380 hdr = mdev->mbase + mbox->rx_start; 2381 if (hdr->num_msgs) { 2382 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2383 hdr->num_msgs = 0; 2384 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2385 } 2386 } 2387 } 2388 2389 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2390 { 2391 struct rvu *rvu = (struct rvu *)rvu_irq; 2392 int vfs = rvu->vfs; 2393 u64 intr; 2394 2395 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2396 /* Clear interrupts */ 2397 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2398 if (intr) 2399 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2400 2401 /* Sync with mbox memory region */ 2402 rmb(); 2403 2404 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2405 2406 /* Handle VF interrupts */ 2407 if (vfs > 64) { 2408 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2409 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2410 2411 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2412 vfs -= 64; 2413 } 2414 2415 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2416 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2417 if (intr) 2418 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2419 2420 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2421 2422 return IRQ_HANDLED; 2423 } 2424 2425 static void rvu_enable_mbox_intr(struct rvu *rvu) 2426 { 2427 struct rvu_hwinfo *hw = rvu->hw; 2428 2429 /* Clear spurious irqs, if any */ 2430 rvu_write64(rvu, BLKADDR_RVUM, 2431 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2432 2433 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2434 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2435 INTR_MASK(hw->total_pfs) & ~1ULL); 2436 } 2437 2438 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2439 { 2440 struct rvu_block *block; 2441 int slot, lf, num_lfs; 2442 int err; 2443 2444 block = &rvu->hw->block[blkaddr]; 2445 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2446 block->addr); 2447 if (!num_lfs) 2448 return; 2449 for (slot = 0; slot < num_lfs; slot++) { 2450 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2451 if (lf < 0) 2452 continue; 2453 2454 /* Cleanup LF and reset it */ 2455 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2456 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2457 else if (block->addr == BLKADDR_NPA) 2458 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2459 else if ((block->addr == BLKADDR_CPT0) || 2460 (block->addr == BLKADDR_CPT1)) 2461 rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot); 2462 2463 err = rvu_lf_reset(rvu, block, lf); 2464 if (err) { 2465 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2466 block->addr, lf); 2467 } 2468 } 2469 } 2470 2471 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2472 { 2473 mutex_lock(&rvu->flr_lock); 2474 /* Reset order should reflect inter-block dependencies: 2475 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2476 * 2. Flush and reset SSO/SSOW 2477 * 3. Cleanup pools (NPA) 2478 */ 2479 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2480 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2481 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2482 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2483 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2484 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2485 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2486 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2487 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2488 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2489 mutex_unlock(&rvu->flr_lock); 2490 } 2491 2492 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2493 { 2494 int reg = 0; 2495 2496 /* pcifunc = 0(PF0) | (vf + 1) */ 2497 __rvu_flr_handler(rvu, vf + 1); 2498 2499 if (vf >= 64) { 2500 reg = 1; 2501 vf = vf - 64; 2502 } 2503 2504 /* Signal FLR finish and enable IRQ */ 2505 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2506 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2507 } 2508 2509 static void rvu_flr_handler(struct work_struct *work) 2510 { 2511 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2512 struct rvu *rvu = flrwork->rvu; 2513 u16 pcifunc, numvfs, vf; 2514 u64 cfg; 2515 int pf; 2516 2517 pf = flrwork - rvu->flr_wrk; 2518 if (pf >= rvu->hw->total_pfs) { 2519 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2520 return; 2521 } 2522 2523 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2524 numvfs = (cfg >> 12) & 0xFF; 2525 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2526 2527 for (vf = 0; vf < numvfs; vf++) 2528 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2529 2530 __rvu_flr_handler(rvu, pcifunc); 2531 2532 /* Signal FLR finish */ 2533 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2534 2535 /* Enable interrupt */ 2536 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2537 } 2538 2539 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2540 { 2541 int dev, vf, reg = 0; 2542 u64 intr; 2543 2544 if (start_vf >= 64) 2545 reg = 1; 2546 2547 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2548 if (!intr) 2549 return; 2550 2551 for (vf = 0; vf < numvfs; vf++) { 2552 if (!(intr & BIT_ULL(vf))) 2553 continue; 2554 /* Clear and disable the interrupt */ 2555 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2556 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2557 2558 dev = vf + start_vf + rvu->hw->total_pfs; 2559 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2560 } 2561 } 2562 2563 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2564 { 2565 struct rvu *rvu = (struct rvu *)rvu_irq; 2566 u64 intr; 2567 u8 pf; 2568 2569 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2570 if (!intr) 2571 goto afvf_flr; 2572 2573 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2574 if (intr & (1ULL << pf)) { 2575 /* clear interrupt */ 2576 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2577 BIT_ULL(pf)); 2578 /* Disable the interrupt */ 2579 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2580 BIT_ULL(pf)); 2581 /* PF is already dead do only AF related operations */ 2582 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2583 } 2584 } 2585 2586 afvf_flr: 2587 rvu_afvf_queue_flr_work(rvu, 0, 64); 2588 if (rvu->vfs > 64) 2589 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2590 2591 return IRQ_HANDLED; 2592 } 2593 2594 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2595 { 2596 int vf; 2597 2598 /* Nothing to be done here other than clearing the 2599 * TRPEND bit. 2600 */ 2601 for (vf = 0; vf < 64; vf++) { 2602 if (intr & (1ULL << vf)) { 2603 /* clear the trpend due to ME(master enable) */ 2604 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2605 /* clear interrupt */ 2606 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2607 } 2608 } 2609 } 2610 2611 /* Handles ME interrupts from VFs of AF */ 2612 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2613 { 2614 struct rvu *rvu = (struct rvu *)rvu_irq; 2615 int vfset; 2616 u64 intr; 2617 2618 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2619 2620 for (vfset = 0; vfset <= 1; vfset++) { 2621 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2622 if (intr) 2623 rvu_me_handle_vfset(rvu, vfset, intr); 2624 } 2625 2626 return IRQ_HANDLED; 2627 } 2628 2629 /* Handles ME interrupts from PFs */ 2630 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2631 { 2632 struct rvu *rvu = (struct rvu *)rvu_irq; 2633 u64 intr; 2634 u8 pf; 2635 2636 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2637 2638 /* Nothing to be done here other than clearing the 2639 * TRPEND bit. 2640 */ 2641 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2642 if (intr & (1ULL << pf)) { 2643 /* clear the trpend due to ME(master enable) */ 2644 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2645 BIT_ULL(pf)); 2646 /* clear interrupt */ 2647 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2648 BIT_ULL(pf)); 2649 } 2650 } 2651 2652 return IRQ_HANDLED; 2653 } 2654 2655 static void rvu_unregister_interrupts(struct rvu *rvu) 2656 { 2657 int irq; 2658 2659 /* Disable the Mbox interrupt */ 2660 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2661 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2662 2663 /* Disable the PF FLR interrupt */ 2664 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2665 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2666 2667 /* Disable the PF ME interrupt */ 2668 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2669 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2670 2671 for (irq = 0; irq < rvu->num_vec; irq++) { 2672 if (rvu->irq_allocated[irq]) { 2673 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2674 rvu->irq_allocated[irq] = false; 2675 } 2676 } 2677 2678 pci_free_irq_vectors(rvu->pdev); 2679 rvu->num_vec = 0; 2680 } 2681 2682 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2683 { 2684 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2685 int offset; 2686 2687 pfvf = &rvu->pf[0]; 2688 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2689 2690 /* Make sure there are enough MSIX vectors configured so that 2691 * VF interrupts can be handled. Offset equal to zero means 2692 * that PF vectors are not configured and overlapping AF vectors. 2693 */ 2694 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2695 offset; 2696 } 2697 2698 static int rvu_register_interrupts(struct rvu *rvu) 2699 { 2700 int ret, offset, pf_vec_start; 2701 2702 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2703 2704 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2705 NAME_SIZE, GFP_KERNEL); 2706 if (!rvu->irq_name) 2707 return -ENOMEM; 2708 2709 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2710 sizeof(bool), GFP_KERNEL); 2711 if (!rvu->irq_allocated) 2712 return -ENOMEM; 2713 2714 /* Enable MSI-X */ 2715 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2716 rvu->num_vec, PCI_IRQ_MSIX); 2717 if (ret < 0) { 2718 dev_err(rvu->dev, 2719 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2720 rvu->num_vec, ret); 2721 return ret; 2722 } 2723 2724 /* Register mailbox interrupt handler */ 2725 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2726 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2727 rvu_mbox_intr_handler, 0, 2728 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2729 if (ret) { 2730 dev_err(rvu->dev, 2731 "RVUAF: IRQ registration failed for mbox irq\n"); 2732 goto fail; 2733 } 2734 2735 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2736 2737 /* Enable mailbox interrupts from all PFs */ 2738 rvu_enable_mbox_intr(rvu); 2739 2740 /* Register FLR interrupt handler */ 2741 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2742 "RVUAF FLR"); 2743 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2744 rvu_flr_intr_handler, 0, 2745 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2746 rvu); 2747 if (ret) { 2748 dev_err(rvu->dev, 2749 "RVUAF: IRQ registration failed for FLR\n"); 2750 goto fail; 2751 } 2752 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2753 2754 /* Enable FLR interrupt for all PFs*/ 2755 rvu_write64(rvu, BLKADDR_RVUM, 2756 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2757 2758 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2759 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2760 2761 /* Register ME interrupt handler */ 2762 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2763 "RVUAF ME"); 2764 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2765 rvu_me_pf_intr_handler, 0, 2766 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2767 rvu); 2768 if (ret) { 2769 dev_err(rvu->dev, 2770 "RVUAF: IRQ registration failed for ME\n"); 2771 } 2772 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2773 2774 /* Clear TRPEND bit for all PF */ 2775 rvu_write64(rvu, BLKADDR_RVUM, 2776 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2777 /* Enable ME interrupt for all PFs*/ 2778 rvu_write64(rvu, BLKADDR_RVUM, 2779 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2780 2781 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2782 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2783 2784 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2785 return 0; 2786 2787 /* Get PF MSIX vectors offset. */ 2788 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2789 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2790 2791 /* Register MBOX0 interrupt. */ 2792 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2793 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2794 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2795 rvu_mbox_intr_handler, 0, 2796 &rvu->irq_name[offset * NAME_SIZE], 2797 rvu); 2798 if (ret) 2799 dev_err(rvu->dev, 2800 "RVUAF: IRQ registration failed for Mbox0\n"); 2801 2802 rvu->irq_allocated[offset] = true; 2803 2804 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2805 * simply increment current offset by 1. 2806 */ 2807 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2808 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2809 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2810 rvu_mbox_intr_handler, 0, 2811 &rvu->irq_name[offset * NAME_SIZE], 2812 rvu); 2813 if (ret) 2814 dev_err(rvu->dev, 2815 "RVUAF: IRQ registration failed for Mbox1\n"); 2816 2817 rvu->irq_allocated[offset] = true; 2818 2819 /* Register FLR interrupt handler for AF's VFs */ 2820 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2821 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2822 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2823 rvu_flr_intr_handler, 0, 2824 &rvu->irq_name[offset * NAME_SIZE], rvu); 2825 if (ret) { 2826 dev_err(rvu->dev, 2827 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2828 goto fail; 2829 } 2830 rvu->irq_allocated[offset] = true; 2831 2832 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2833 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2834 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2835 rvu_flr_intr_handler, 0, 2836 &rvu->irq_name[offset * NAME_SIZE], rvu); 2837 if (ret) { 2838 dev_err(rvu->dev, 2839 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2840 goto fail; 2841 } 2842 rvu->irq_allocated[offset] = true; 2843 2844 /* Register ME interrupt handler for AF's VFs */ 2845 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2846 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2847 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2848 rvu_me_vf_intr_handler, 0, 2849 &rvu->irq_name[offset * NAME_SIZE], rvu); 2850 if (ret) { 2851 dev_err(rvu->dev, 2852 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2853 goto fail; 2854 } 2855 rvu->irq_allocated[offset] = true; 2856 2857 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2858 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2859 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2860 rvu_me_vf_intr_handler, 0, 2861 &rvu->irq_name[offset * NAME_SIZE], rvu); 2862 if (ret) { 2863 dev_err(rvu->dev, 2864 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2865 goto fail; 2866 } 2867 rvu->irq_allocated[offset] = true; 2868 return 0; 2869 2870 fail: 2871 rvu_unregister_interrupts(rvu); 2872 return ret; 2873 } 2874 2875 static void rvu_flr_wq_destroy(struct rvu *rvu) 2876 { 2877 if (rvu->flr_wq) { 2878 flush_workqueue(rvu->flr_wq); 2879 destroy_workqueue(rvu->flr_wq); 2880 rvu->flr_wq = NULL; 2881 } 2882 } 2883 2884 static int rvu_flr_init(struct rvu *rvu) 2885 { 2886 int dev, num_devs; 2887 u64 cfg; 2888 int pf; 2889 2890 /* Enable FLR for all PFs*/ 2891 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2892 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2893 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2894 cfg | BIT_ULL(22)); 2895 } 2896 2897 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2898 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2899 1); 2900 if (!rvu->flr_wq) 2901 return -ENOMEM; 2902 2903 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2904 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2905 sizeof(struct rvu_work), GFP_KERNEL); 2906 if (!rvu->flr_wrk) { 2907 destroy_workqueue(rvu->flr_wq); 2908 return -ENOMEM; 2909 } 2910 2911 for (dev = 0; dev < num_devs; dev++) { 2912 rvu->flr_wrk[dev].rvu = rvu; 2913 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2914 } 2915 2916 mutex_init(&rvu->flr_lock); 2917 2918 return 0; 2919 } 2920 2921 static void rvu_disable_afvf_intr(struct rvu *rvu) 2922 { 2923 int vfs = rvu->vfs; 2924 2925 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2926 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2927 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2928 if (vfs <= 64) 2929 return; 2930 2931 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2932 INTR_MASK(vfs - 64)); 2933 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2934 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2935 } 2936 2937 static void rvu_enable_afvf_intr(struct rvu *rvu) 2938 { 2939 int vfs = rvu->vfs; 2940 2941 /* Clear any pending interrupts and enable AF VF interrupts for 2942 * the first 64 VFs. 2943 */ 2944 /* Mbox */ 2945 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2946 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2947 2948 /* FLR */ 2949 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2950 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2951 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2952 2953 /* Same for remaining VFs, if any. */ 2954 if (vfs <= 64) 2955 return; 2956 2957 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2958 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2959 INTR_MASK(vfs - 64)); 2960 2961 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2962 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2963 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2964 } 2965 2966 int rvu_get_num_lbk_chans(void) 2967 { 2968 struct pci_dev *pdev; 2969 void __iomem *base; 2970 int ret = -EIO; 2971 2972 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2973 NULL); 2974 if (!pdev) 2975 goto err; 2976 2977 base = pci_ioremap_bar(pdev, 0); 2978 if (!base) 2979 goto err_put; 2980 2981 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2982 ret = (readq(base + 0x10) >> 32) & 0xffff; 2983 iounmap(base); 2984 err_put: 2985 pci_dev_put(pdev); 2986 err: 2987 return ret; 2988 } 2989 2990 static int rvu_enable_sriov(struct rvu *rvu) 2991 { 2992 struct pci_dev *pdev = rvu->pdev; 2993 int err, chans, vfs; 2994 2995 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2996 dev_warn(&pdev->dev, 2997 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2998 return 0; 2999 } 3000 3001 chans = rvu_get_num_lbk_chans(); 3002 if (chans < 0) 3003 return chans; 3004 3005 vfs = pci_sriov_get_totalvfs(pdev); 3006 3007 /* Limit VFs in case we have more VFs than LBK channels available. */ 3008 if (vfs > chans) 3009 vfs = chans; 3010 3011 if (!vfs) 3012 return 0; 3013 3014 /* LBK channel number 63 is used for switching packets between 3015 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3016 */ 3017 if (vfs > 62) 3018 vfs = 62; 3019 3020 /* Save VFs number for reference in VF interrupts handlers. 3021 * Since interrupts might start arriving during SRIOV enablement 3022 * ordinary API cannot be used to get number of enabled VFs. 3023 */ 3024 rvu->vfs = vfs; 3025 3026 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3027 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3028 if (err) 3029 return err; 3030 3031 rvu_enable_afvf_intr(rvu); 3032 /* Make sure IRQs are enabled before SRIOV. */ 3033 mb(); 3034 3035 err = pci_enable_sriov(pdev, vfs); 3036 if (err) { 3037 rvu_disable_afvf_intr(rvu); 3038 rvu_mbox_destroy(&rvu->afvf_wq_info); 3039 return err; 3040 } 3041 3042 return 0; 3043 } 3044 3045 static void rvu_disable_sriov(struct rvu *rvu) 3046 { 3047 rvu_disable_afvf_intr(rvu); 3048 rvu_mbox_destroy(&rvu->afvf_wq_info); 3049 pci_disable_sriov(rvu->pdev); 3050 } 3051 3052 static void rvu_update_module_params(struct rvu *rvu) 3053 { 3054 const char *default_pfl_name = "default"; 3055 3056 strscpy(rvu->mkex_pfl_name, 3057 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3058 strscpy(rvu->kpu_pfl_name, 3059 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3060 } 3061 3062 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3063 { 3064 struct device *dev = &pdev->dev; 3065 struct rvu *rvu; 3066 int err; 3067 3068 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3069 if (!rvu) 3070 return -ENOMEM; 3071 3072 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3073 if (!rvu->hw) { 3074 devm_kfree(dev, rvu); 3075 return -ENOMEM; 3076 } 3077 3078 pci_set_drvdata(pdev, rvu); 3079 rvu->pdev = pdev; 3080 rvu->dev = &pdev->dev; 3081 3082 err = pci_enable_device(pdev); 3083 if (err) { 3084 dev_err(dev, "Failed to enable PCI device\n"); 3085 goto err_freemem; 3086 } 3087 3088 err = pci_request_regions(pdev, DRV_NAME); 3089 if (err) { 3090 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3091 goto err_disable_device; 3092 } 3093 3094 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3095 if (err) { 3096 dev_err(dev, "DMA mask config failed, abort\n"); 3097 goto err_release_regions; 3098 } 3099 3100 pci_set_master(pdev); 3101 3102 rvu->ptp = ptp_get(); 3103 if (IS_ERR(rvu->ptp)) { 3104 err = PTR_ERR(rvu->ptp); 3105 if (err == -EPROBE_DEFER) 3106 goto err_release_regions; 3107 rvu->ptp = NULL; 3108 } 3109 3110 /* Map Admin function CSRs */ 3111 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3112 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3113 if (!rvu->afreg_base || !rvu->pfreg_base) { 3114 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3115 err = -ENOMEM; 3116 goto err_put_ptp; 3117 } 3118 3119 /* Store module params in rvu structure */ 3120 rvu_update_module_params(rvu); 3121 3122 /* Check which blocks the HW supports */ 3123 rvu_check_block_implemented(rvu); 3124 3125 rvu_reset_all_blocks(rvu); 3126 3127 rvu_setup_hw_capabilities(rvu); 3128 3129 err = rvu_setup_hw_resources(rvu); 3130 if (err) 3131 goto err_put_ptp; 3132 3133 /* Init mailbox btw AF and PFs */ 3134 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3135 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3136 rvu_afpf_mbox_up_handler); 3137 if (err) { 3138 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3139 goto err_hwsetup; 3140 } 3141 3142 err = rvu_flr_init(rvu); 3143 if (err) { 3144 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3145 goto err_mbox; 3146 } 3147 3148 err = rvu_register_interrupts(rvu); 3149 if (err) { 3150 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3151 goto err_flr; 3152 } 3153 3154 err = rvu_register_dl(rvu); 3155 if (err) { 3156 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3157 goto err_irq; 3158 } 3159 3160 rvu_setup_rvum_blk_revid(rvu); 3161 3162 /* Enable AF's VFs (if any) */ 3163 err = rvu_enable_sriov(rvu); 3164 if (err) { 3165 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3166 goto err_dl; 3167 } 3168 3169 /* Initialize debugfs */ 3170 rvu_dbg_init(rvu); 3171 3172 mutex_init(&rvu->rswitch.switch_lock); 3173 3174 return 0; 3175 err_dl: 3176 rvu_unregister_dl(rvu); 3177 err_irq: 3178 rvu_unregister_interrupts(rvu); 3179 err_flr: 3180 rvu_flr_wq_destroy(rvu); 3181 err_mbox: 3182 rvu_mbox_destroy(&rvu->afpf_wq_info); 3183 err_hwsetup: 3184 rvu_cgx_exit(rvu); 3185 rvu_fwdata_exit(rvu); 3186 rvu_reset_all_blocks(rvu); 3187 rvu_free_hw_resources(rvu); 3188 rvu_clear_rvum_blk_revid(rvu); 3189 err_put_ptp: 3190 ptp_put(rvu->ptp); 3191 err_release_regions: 3192 pci_release_regions(pdev); 3193 err_disable_device: 3194 pci_disable_device(pdev); 3195 err_freemem: 3196 pci_set_drvdata(pdev, NULL); 3197 devm_kfree(&pdev->dev, rvu->hw); 3198 devm_kfree(dev, rvu); 3199 return err; 3200 } 3201 3202 static void rvu_remove(struct pci_dev *pdev) 3203 { 3204 struct rvu *rvu = pci_get_drvdata(pdev); 3205 3206 rvu_dbg_exit(rvu); 3207 rvu_unregister_dl(rvu); 3208 rvu_unregister_interrupts(rvu); 3209 rvu_flr_wq_destroy(rvu); 3210 rvu_cgx_exit(rvu); 3211 rvu_fwdata_exit(rvu); 3212 rvu_mbox_destroy(&rvu->afpf_wq_info); 3213 rvu_disable_sriov(rvu); 3214 rvu_reset_all_blocks(rvu); 3215 rvu_free_hw_resources(rvu); 3216 rvu_clear_rvum_blk_revid(rvu); 3217 ptp_put(rvu->ptp); 3218 pci_release_regions(pdev); 3219 pci_disable_device(pdev); 3220 pci_set_drvdata(pdev, NULL); 3221 3222 devm_kfree(&pdev->dev, rvu->hw); 3223 devm_kfree(&pdev->dev, rvu); 3224 } 3225 3226 static struct pci_driver rvu_driver = { 3227 .name = DRV_NAME, 3228 .id_table = rvu_id_table, 3229 .probe = rvu_probe, 3230 .remove = rvu_remove, 3231 }; 3232 3233 static int __init rvu_init_module(void) 3234 { 3235 int err; 3236 3237 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3238 3239 err = pci_register_driver(&cgx_driver); 3240 if (err < 0) 3241 return err; 3242 3243 err = pci_register_driver(&ptp_driver); 3244 if (err < 0) 3245 goto ptp_err; 3246 3247 err = pci_register_driver(&rvu_driver); 3248 if (err < 0) 3249 goto rvu_err; 3250 3251 return 0; 3252 rvu_err: 3253 pci_unregister_driver(&ptp_driver); 3254 ptp_err: 3255 pci_unregister_driver(&cgx_driver); 3256 3257 return err; 3258 } 3259 3260 static void __exit rvu_cleanup_module(void) 3261 { 3262 pci_unregister_driver(&rvu_driver); 3263 pci_unregister_driver(&ptp_driver); 3264 pci_unregister_driver(&cgx_driver); 3265 } 3266 3267 module_init(rvu_init_module); 3268 module_exit(rvu_cleanup_module); 3269