1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 #include "ptp.h" 22 23 #include "rvu_trace.h" 24 25 #define DRV_NAME "rvu_af" 26 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 27 28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 29 30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 33 struct rvu_block *block, int lf); 34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 35 36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 37 int type, int num, 38 void (mbox_handler)(struct work_struct *), 39 void (mbox_up_handler)(struct work_struct *)); 40 enum { 41 TYPE_AFVF, 42 TYPE_AFPF, 43 }; 44 45 /* Supported devices */ 46 static const struct pci_device_id rvu_id_table[] = { 47 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 48 { 0, } /* end of table */ 49 }; 50 51 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 52 MODULE_DESCRIPTION(DRV_STRING); 53 MODULE_LICENSE("GPL v2"); 54 MODULE_DEVICE_TABLE(pci, rvu_id_table); 55 56 static char *mkex_profile; /* MKEX profile name */ 57 module_param(mkex_profile, charp, 0000); 58 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 59 60 static char *kpu_profile; /* KPU profile name */ 61 module_param(kpu_profile, charp, 0000); 62 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 63 64 static void rvu_setup_hw_capabilities(struct rvu *rvu) 65 { 66 struct rvu_hwinfo *hw = rvu->hw; 67 68 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 69 hw->cap.nix_fixed_txschq_mapping = false; 70 hw->cap.nix_shaping = true; 71 hw->cap.nix_tx_link_bp = true; 72 hw->cap.nix_rx_multicast = true; 73 hw->rvu = rvu; 74 75 if (is_rvu_96xx_B0(rvu)) { 76 hw->cap.nix_fixed_txschq_mapping = true; 77 hw->cap.nix_txsch_per_cgx_lmac = 4; 78 hw->cap.nix_txsch_per_lbk_lmac = 132; 79 hw->cap.nix_txsch_per_sdp_lmac = 76; 80 hw->cap.nix_shaping = false; 81 hw->cap.nix_tx_link_bp = false; 82 if (is_rvu_96xx_A0(rvu)) 83 hw->cap.nix_rx_multicast = false; 84 } 85 86 if (!is_rvu_otx2(rvu)) 87 hw->cap.per_pf_mbox_regs = true; 88 } 89 90 /* Poll a RVU block's register 'offset', for a 'zero' 91 * or 'nonzero' at bits specified by 'mask' 92 */ 93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 94 { 95 unsigned long timeout = jiffies + usecs_to_jiffies(10000); 96 void __iomem *reg; 97 u64 reg_val; 98 99 reg = rvu->afreg_base + ((block << 28) | offset); 100 again: 101 reg_val = readq(reg); 102 if (zero && !(reg_val & mask)) 103 return 0; 104 if (!zero && (reg_val & mask)) 105 return 0; 106 if (time_before(jiffies, timeout)) { 107 usleep_range(1, 5); 108 goto again; 109 } 110 return -EBUSY; 111 } 112 113 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 114 { 115 int id; 116 117 if (!rsrc->bmap) 118 return -EINVAL; 119 120 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 121 if (id >= rsrc->max) 122 return -ENOSPC; 123 124 __set_bit(id, rsrc->bmap); 125 126 return id; 127 } 128 129 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 130 { 131 int start; 132 133 if (!rsrc->bmap) 134 return -EINVAL; 135 136 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 137 if (start >= rsrc->max) 138 return -ENOSPC; 139 140 bitmap_set(rsrc->bmap, start, nrsrc); 141 return start; 142 } 143 144 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 145 { 146 if (!rsrc->bmap) 147 return; 148 if (start >= rsrc->max) 149 return; 150 151 bitmap_clear(rsrc->bmap, start, nrsrc); 152 } 153 154 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 155 { 156 int start; 157 158 if (!rsrc->bmap) 159 return false; 160 161 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 162 if (start >= rsrc->max) 163 return false; 164 165 return true; 166 } 167 168 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 169 { 170 if (!rsrc->bmap) 171 return; 172 173 __clear_bit(id, rsrc->bmap); 174 } 175 176 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 177 { 178 int used; 179 180 if (!rsrc->bmap) 181 return 0; 182 183 used = bitmap_weight(rsrc->bmap, rsrc->max); 184 return (rsrc->max - used); 185 } 186 187 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 188 { 189 if (!rsrc->bmap) 190 return false; 191 192 return !test_bit(id, rsrc->bmap); 193 } 194 195 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 196 { 197 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 198 sizeof(long), GFP_KERNEL); 199 if (!rsrc->bmap) 200 return -ENOMEM; 201 return 0; 202 } 203 204 /* Get block LF's HW index from a PF_FUNC's block slot number */ 205 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 206 { 207 u16 match = 0; 208 int lf; 209 210 mutex_lock(&rvu->rsrc_lock); 211 for (lf = 0; lf < block->lf.max; lf++) { 212 if (block->fn_map[lf] == pcifunc) { 213 if (slot == match) { 214 mutex_unlock(&rvu->rsrc_lock); 215 return lf; 216 } 217 match++; 218 } 219 } 220 mutex_unlock(&rvu->rsrc_lock); 221 return -ENODEV; 222 } 223 224 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 225 * Some silicon variants of OcteonTX2 supports 226 * multiple blocks of same type. 227 * 228 * @pcifunc has to be zero when no LF is yet attached. 229 * 230 * For a pcifunc if LFs are attached from multiple blocks of same type, then 231 * return blkaddr of first encountered block. 232 */ 233 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 234 { 235 int devnum, blkaddr = -ENODEV; 236 u64 cfg, reg; 237 bool is_pf; 238 239 switch (blktype) { 240 case BLKTYPE_NPC: 241 blkaddr = BLKADDR_NPC; 242 goto exit; 243 case BLKTYPE_NPA: 244 blkaddr = BLKADDR_NPA; 245 goto exit; 246 case BLKTYPE_NIX: 247 /* For now assume NIX0 */ 248 if (!pcifunc) { 249 blkaddr = BLKADDR_NIX0; 250 goto exit; 251 } 252 break; 253 case BLKTYPE_SSO: 254 blkaddr = BLKADDR_SSO; 255 goto exit; 256 case BLKTYPE_SSOW: 257 blkaddr = BLKADDR_SSOW; 258 goto exit; 259 case BLKTYPE_TIM: 260 blkaddr = BLKADDR_TIM; 261 goto exit; 262 case BLKTYPE_CPT: 263 /* For now assume CPT0 */ 264 if (!pcifunc) { 265 blkaddr = BLKADDR_CPT0; 266 goto exit; 267 } 268 break; 269 } 270 271 /* Check if this is a RVU PF or VF */ 272 if (pcifunc & RVU_PFVF_FUNC_MASK) { 273 is_pf = false; 274 devnum = rvu_get_hwvf(rvu, pcifunc); 275 } else { 276 is_pf = true; 277 devnum = rvu_get_pf(pcifunc); 278 } 279 280 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 281 * 'BLKADDR_NIX1'. 282 */ 283 if (blktype == BLKTYPE_NIX) { 284 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 285 RVU_PRIV_HWVFX_NIXX_CFG(0); 286 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 287 if (cfg) { 288 blkaddr = BLKADDR_NIX0; 289 goto exit; 290 } 291 292 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 293 RVU_PRIV_HWVFX_NIXX_CFG(1); 294 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 295 if (cfg) 296 blkaddr = BLKADDR_NIX1; 297 } 298 299 if (blktype == BLKTYPE_CPT) { 300 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 301 RVU_PRIV_HWVFX_CPTX_CFG(0); 302 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 303 if (cfg) { 304 blkaddr = BLKADDR_CPT0; 305 goto exit; 306 } 307 308 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 309 RVU_PRIV_HWVFX_CPTX_CFG(1); 310 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 311 if (cfg) 312 blkaddr = BLKADDR_CPT1; 313 } 314 315 exit: 316 if (is_block_implemented(rvu->hw, blkaddr)) 317 return blkaddr; 318 return -ENODEV; 319 } 320 321 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 322 struct rvu_block *block, u16 pcifunc, 323 u16 lf, bool attach) 324 { 325 int devnum, num_lfs = 0; 326 bool is_pf; 327 u64 reg; 328 329 if (lf >= block->lf.max) { 330 dev_err(&rvu->pdev->dev, 331 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 332 __func__, lf, block->name, block->lf.max); 333 return; 334 } 335 336 /* Check if this is for a RVU PF or VF */ 337 if (pcifunc & RVU_PFVF_FUNC_MASK) { 338 is_pf = false; 339 devnum = rvu_get_hwvf(rvu, pcifunc); 340 } else { 341 is_pf = true; 342 devnum = rvu_get_pf(pcifunc); 343 } 344 345 block->fn_map[lf] = attach ? pcifunc : 0; 346 347 switch (block->addr) { 348 case BLKADDR_NPA: 349 pfvf->npalf = attach ? true : false; 350 num_lfs = pfvf->npalf; 351 break; 352 case BLKADDR_NIX0: 353 case BLKADDR_NIX1: 354 pfvf->nixlf = attach ? true : false; 355 num_lfs = pfvf->nixlf; 356 break; 357 case BLKADDR_SSO: 358 attach ? pfvf->sso++ : pfvf->sso--; 359 num_lfs = pfvf->sso; 360 break; 361 case BLKADDR_SSOW: 362 attach ? pfvf->ssow++ : pfvf->ssow--; 363 num_lfs = pfvf->ssow; 364 break; 365 case BLKADDR_TIM: 366 attach ? pfvf->timlfs++ : pfvf->timlfs--; 367 num_lfs = pfvf->timlfs; 368 break; 369 case BLKADDR_CPT0: 370 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 371 num_lfs = pfvf->cptlfs; 372 break; 373 case BLKADDR_CPT1: 374 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 375 num_lfs = pfvf->cpt1_lfs; 376 break; 377 } 378 379 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 380 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 381 } 382 383 inline int rvu_get_pf(u16 pcifunc) 384 { 385 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 386 } 387 388 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 389 { 390 u64 cfg; 391 392 /* Get numVFs attached to this PF and first HWVF */ 393 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 394 if (numvfs) 395 *numvfs = (cfg >> 12) & 0xFF; 396 if (hwvf) 397 *hwvf = cfg & 0xFFF; 398 } 399 400 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 401 { 402 int pf, func; 403 u64 cfg; 404 405 pf = rvu_get_pf(pcifunc); 406 func = pcifunc & RVU_PFVF_FUNC_MASK; 407 408 /* Get first HWVF attached to this PF */ 409 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 410 411 return ((cfg & 0xFFF) + func - 1); 412 } 413 414 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 415 { 416 /* Check if it is a PF or VF */ 417 if (pcifunc & RVU_PFVF_FUNC_MASK) 418 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 419 else 420 return &rvu->pf[rvu_get_pf(pcifunc)]; 421 } 422 423 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 424 { 425 int pf, vf, nvfs; 426 u64 cfg; 427 428 pf = rvu_get_pf(pcifunc); 429 if (pf >= rvu->hw->total_pfs) 430 return false; 431 432 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 433 return true; 434 435 /* Check if VF is within number of VFs attached to this PF */ 436 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 437 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 438 nvfs = (cfg >> 12) & 0xFF; 439 if (vf >= nvfs) 440 return false; 441 442 return true; 443 } 444 445 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 446 { 447 struct rvu_block *block; 448 449 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 450 return false; 451 452 block = &hw->block[blkaddr]; 453 return block->implemented; 454 } 455 456 static void rvu_check_block_implemented(struct rvu *rvu) 457 { 458 struct rvu_hwinfo *hw = rvu->hw; 459 struct rvu_block *block; 460 int blkid; 461 u64 cfg; 462 463 /* For each block check if 'implemented' bit is set */ 464 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 465 block = &hw->block[blkid]; 466 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 467 if (cfg & BIT_ULL(11)) 468 block->implemented = true; 469 } 470 } 471 472 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 473 { 474 rvu_write64(rvu, BLKADDR_RVUM, 475 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 476 RVU_BLK_RVUM_REVID); 477 } 478 479 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 480 { 481 rvu_write64(rvu, BLKADDR_RVUM, 482 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 483 } 484 485 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 486 { 487 int err; 488 489 if (!block->implemented) 490 return 0; 491 492 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 493 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 494 true); 495 return err; 496 } 497 498 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 499 { 500 struct rvu_block *block = &rvu->hw->block[blkaddr]; 501 502 if (!block->implemented) 503 return; 504 505 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 506 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 507 } 508 509 static void rvu_reset_all_blocks(struct rvu *rvu) 510 { 511 /* Do a HW reset of all RVU blocks */ 512 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 513 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 514 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 515 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 516 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 517 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 518 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 519 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 520 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 521 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 522 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 523 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 524 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 525 } 526 527 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 528 { 529 struct rvu_pfvf *pfvf; 530 u64 cfg; 531 int lf; 532 533 for (lf = 0; lf < block->lf.max; lf++) { 534 cfg = rvu_read64(rvu, block->addr, 535 block->lfcfg_reg | (lf << block->lfshift)); 536 if (!(cfg & BIT_ULL(63))) 537 continue; 538 539 /* Set this resource as being used */ 540 __set_bit(lf, block->lf.bmap); 541 542 /* Get, to whom this LF is attached */ 543 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 544 rvu_update_rsrc_map(rvu, pfvf, block, 545 (cfg >> 8) & 0xFFFF, lf, true); 546 547 /* Set start MSIX vector for this LF within this PF/VF */ 548 rvu_set_msix_offset(rvu, pfvf, block, lf); 549 } 550 } 551 552 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 553 { 554 int min_vecs; 555 556 if (!vf) 557 goto check_pf; 558 559 if (!nvecs) { 560 dev_warn(rvu->dev, 561 "PF%d:VF%d is configured with zero msix vectors, %d\n", 562 pf, vf - 1, nvecs); 563 } 564 return; 565 566 check_pf: 567 if (pf == 0) 568 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 569 else 570 min_vecs = RVU_PF_INT_VEC_CNT; 571 572 if (!(nvecs < min_vecs)) 573 return; 574 dev_warn(rvu->dev, 575 "PF%d is configured with too few vectors, %d, min is %d\n", 576 pf, nvecs, min_vecs); 577 } 578 579 static int rvu_setup_msix_resources(struct rvu *rvu) 580 { 581 struct rvu_hwinfo *hw = rvu->hw; 582 int pf, vf, numvfs, hwvf, err; 583 int nvecs, offset, max_msix; 584 struct rvu_pfvf *pfvf; 585 u64 cfg, phy_addr; 586 dma_addr_t iova; 587 588 for (pf = 0; pf < hw->total_pfs; pf++) { 589 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 590 /* If PF is not enabled, nothing to do */ 591 if (!((cfg >> 20) & 0x01)) 592 continue; 593 594 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 595 596 pfvf = &rvu->pf[pf]; 597 /* Get num of MSIX vectors attached to this PF */ 598 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 599 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 600 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 601 602 /* Alloc msix bitmap for this PF */ 603 err = rvu_alloc_bitmap(&pfvf->msix); 604 if (err) 605 return err; 606 607 /* Allocate memory for MSIX vector to RVU block LF mapping */ 608 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 609 sizeof(u16), GFP_KERNEL); 610 if (!pfvf->msix_lfmap) 611 return -ENOMEM; 612 613 /* For PF0 (AF) firmware will set msix vector offsets for 614 * AF, block AF and PF0_INT vectors, so jump to VFs. 615 */ 616 if (!pf) 617 goto setup_vfmsix; 618 619 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 620 * These are allocated on driver init and never freed, 621 * so no need to set 'msix_lfmap' for these. 622 */ 623 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 624 nvecs = (cfg >> 12) & 0xFF; 625 cfg &= ~0x7FFULL; 626 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 627 rvu_write64(rvu, BLKADDR_RVUM, 628 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 629 setup_vfmsix: 630 /* Alloc msix bitmap for VFs */ 631 for (vf = 0; vf < numvfs; vf++) { 632 pfvf = &rvu->hwvf[hwvf + vf]; 633 /* Get num of MSIX vectors attached to this VF */ 634 cfg = rvu_read64(rvu, BLKADDR_RVUM, 635 RVU_PRIV_PFX_MSIX_CFG(pf)); 636 pfvf->msix.max = (cfg & 0xFFF) + 1; 637 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 638 639 /* Alloc msix bitmap for this VF */ 640 err = rvu_alloc_bitmap(&pfvf->msix); 641 if (err) 642 return err; 643 644 pfvf->msix_lfmap = 645 devm_kcalloc(rvu->dev, pfvf->msix.max, 646 sizeof(u16), GFP_KERNEL); 647 if (!pfvf->msix_lfmap) 648 return -ENOMEM; 649 650 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 651 * These are allocated on driver init and never freed, 652 * so no need to set 'msix_lfmap' for these. 653 */ 654 cfg = rvu_read64(rvu, BLKADDR_RVUM, 655 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 656 nvecs = (cfg >> 12) & 0xFF; 657 cfg &= ~0x7FFULL; 658 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 659 rvu_write64(rvu, BLKADDR_RVUM, 660 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 661 cfg | offset); 662 } 663 } 664 665 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 666 * create an IOMMU mapping for the physical address configured by 667 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 668 */ 669 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 670 max_msix = cfg & 0xFFFFF; 671 if (rvu->fwdata && rvu->fwdata->msixtr_base) 672 phy_addr = rvu->fwdata->msixtr_base; 673 else 674 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 675 676 iova = dma_map_resource(rvu->dev, phy_addr, 677 max_msix * PCI_MSIX_ENTRY_SIZE, 678 DMA_BIDIRECTIONAL, 0); 679 680 if (dma_mapping_error(rvu->dev, iova)) 681 return -ENOMEM; 682 683 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 684 rvu->msix_base_iova = iova; 685 rvu->msixtr_base_phy = phy_addr; 686 687 return 0; 688 } 689 690 static void rvu_reset_msix(struct rvu *rvu) 691 { 692 /* Restore msixtr base register */ 693 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 694 rvu->msixtr_base_phy); 695 } 696 697 static void rvu_free_hw_resources(struct rvu *rvu) 698 { 699 struct rvu_hwinfo *hw = rvu->hw; 700 struct rvu_block *block; 701 struct rvu_pfvf *pfvf; 702 int id, max_msix; 703 u64 cfg; 704 705 rvu_npa_freemem(rvu); 706 rvu_npc_freemem(rvu); 707 rvu_nix_freemem(rvu); 708 709 /* Free block LF bitmaps */ 710 for (id = 0; id < BLK_COUNT; id++) { 711 block = &hw->block[id]; 712 kfree(block->lf.bmap); 713 } 714 715 /* Free MSIX bitmaps */ 716 for (id = 0; id < hw->total_pfs; id++) { 717 pfvf = &rvu->pf[id]; 718 kfree(pfvf->msix.bmap); 719 } 720 721 for (id = 0; id < hw->total_vfs; id++) { 722 pfvf = &rvu->hwvf[id]; 723 kfree(pfvf->msix.bmap); 724 } 725 726 /* Unmap MSIX vector base IOVA mapping */ 727 if (!rvu->msix_base_iova) 728 return; 729 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 730 max_msix = cfg & 0xFFFFF; 731 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 732 max_msix * PCI_MSIX_ENTRY_SIZE, 733 DMA_BIDIRECTIONAL, 0); 734 735 rvu_reset_msix(rvu); 736 mutex_destroy(&rvu->rsrc_lock); 737 } 738 739 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 740 { 741 struct rvu_hwinfo *hw = rvu->hw; 742 int pf, vf, numvfs, hwvf; 743 struct rvu_pfvf *pfvf; 744 u64 *mac; 745 746 for (pf = 0; pf < hw->total_pfs; pf++) { 747 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 748 if (!pf) 749 goto lbkvf; 750 751 if (!is_pf_cgxmapped(rvu, pf)) 752 continue; 753 /* Assign MAC address to PF */ 754 pfvf = &rvu->pf[pf]; 755 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 756 mac = &rvu->fwdata->pf_macs[pf]; 757 if (*mac) 758 u64_to_ether_addr(*mac, pfvf->mac_addr); 759 else 760 eth_random_addr(pfvf->mac_addr); 761 } else { 762 eth_random_addr(pfvf->mac_addr); 763 } 764 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 765 766 lbkvf: 767 /* Assign MAC address to VFs*/ 768 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 769 for (vf = 0; vf < numvfs; vf++, hwvf++) { 770 pfvf = &rvu->hwvf[hwvf]; 771 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 772 mac = &rvu->fwdata->vf_macs[hwvf]; 773 if (*mac) 774 u64_to_ether_addr(*mac, pfvf->mac_addr); 775 else 776 eth_random_addr(pfvf->mac_addr); 777 } else { 778 eth_random_addr(pfvf->mac_addr); 779 } 780 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 781 } 782 } 783 } 784 785 static int rvu_fwdata_init(struct rvu *rvu) 786 { 787 u64 fwdbase; 788 int err; 789 790 /* Get firmware data base address */ 791 err = cgx_get_fwdata_base(&fwdbase); 792 if (err) 793 goto fail; 794 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 795 if (!rvu->fwdata) 796 goto fail; 797 if (!is_rvu_fwdata_valid(rvu)) { 798 dev_err(rvu->dev, 799 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 800 iounmap(rvu->fwdata); 801 rvu->fwdata = NULL; 802 return -EINVAL; 803 } 804 return 0; 805 fail: 806 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 807 return -EIO; 808 } 809 810 static void rvu_fwdata_exit(struct rvu *rvu) 811 { 812 if (rvu->fwdata) 813 iounmap(rvu->fwdata); 814 } 815 816 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 817 { 818 struct rvu_hwinfo *hw = rvu->hw; 819 struct rvu_block *block; 820 int blkid; 821 u64 cfg; 822 823 /* Init NIX LF's bitmap */ 824 block = &hw->block[blkaddr]; 825 if (!block->implemented) 826 return 0; 827 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 828 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 829 block->lf.max = cfg & 0xFFF; 830 block->addr = blkaddr; 831 block->type = BLKTYPE_NIX; 832 block->lfshift = 8; 833 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 834 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 835 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 836 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 837 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 838 block->lfreset_reg = NIX_AF_LF_RST; 839 sprintf(block->name, "NIX%d", blkid); 840 rvu->nix_blkaddr[blkid] = blkaddr; 841 return rvu_alloc_bitmap(&block->lf); 842 } 843 844 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 845 { 846 struct rvu_hwinfo *hw = rvu->hw; 847 struct rvu_block *block; 848 int blkid; 849 u64 cfg; 850 851 /* Init CPT LF's bitmap */ 852 block = &hw->block[blkaddr]; 853 if (!block->implemented) 854 return 0; 855 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 856 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 857 block->lf.max = cfg & 0xFF; 858 block->addr = blkaddr; 859 block->type = BLKTYPE_CPT; 860 block->multislot = true; 861 block->lfshift = 3; 862 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 863 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 864 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 865 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 866 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 867 block->lfreset_reg = CPT_AF_LF_RST; 868 sprintf(block->name, "CPT%d", blkid); 869 return rvu_alloc_bitmap(&block->lf); 870 } 871 872 static void rvu_get_lbk_bufsize(struct rvu *rvu) 873 { 874 struct pci_dev *pdev = NULL; 875 void __iomem *base; 876 u64 lbk_const; 877 878 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 879 PCI_DEVID_OCTEONTX2_LBK, pdev); 880 if (!pdev) 881 return; 882 883 base = pci_ioremap_bar(pdev, 0); 884 if (!base) 885 goto err_put; 886 887 lbk_const = readq(base + LBK_CONST); 888 889 /* cache fifo size */ 890 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 891 892 iounmap(base); 893 err_put: 894 pci_dev_put(pdev); 895 } 896 897 static int rvu_setup_hw_resources(struct rvu *rvu) 898 { 899 struct rvu_hwinfo *hw = rvu->hw; 900 struct rvu_block *block; 901 int blkid, err; 902 u64 cfg; 903 904 /* Get HW supported max RVU PF & VF count */ 905 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 906 hw->total_pfs = (cfg >> 32) & 0xFF; 907 hw->total_vfs = (cfg >> 20) & 0xFFF; 908 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 909 910 /* Init NPA LF's bitmap */ 911 block = &hw->block[BLKADDR_NPA]; 912 if (!block->implemented) 913 goto nix; 914 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 915 block->lf.max = (cfg >> 16) & 0xFFF; 916 block->addr = BLKADDR_NPA; 917 block->type = BLKTYPE_NPA; 918 block->lfshift = 8; 919 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 920 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 921 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 922 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 923 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 924 block->lfreset_reg = NPA_AF_LF_RST; 925 sprintf(block->name, "NPA"); 926 err = rvu_alloc_bitmap(&block->lf); 927 if (err) { 928 dev_err(rvu->dev, 929 "%s: Failed to allocate NPA LF bitmap\n", __func__); 930 return err; 931 } 932 933 nix: 934 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 935 if (err) { 936 dev_err(rvu->dev, 937 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 938 return err; 939 } 940 941 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 942 if (err) { 943 dev_err(rvu->dev, 944 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 945 return err; 946 } 947 948 /* Init SSO group's bitmap */ 949 block = &hw->block[BLKADDR_SSO]; 950 if (!block->implemented) 951 goto ssow; 952 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 953 block->lf.max = cfg & 0xFFFF; 954 block->addr = BLKADDR_SSO; 955 block->type = BLKTYPE_SSO; 956 block->multislot = true; 957 block->lfshift = 3; 958 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 959 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 960 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 961 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 962 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 963 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 964 sprintf(block->name, "SSO GROUP"); 965 err = rvu_alloc_bitmap(&block->lf); 966 if (err) { 967 dev_err(rvu->dev, 968 "%s: Failed to allocate SSO LF bitmap\n", __func__); 969 return err; 970 } 971 972 ssow: 973 /* Init SSO workslot's bitmap */ 974 block = &hw->block[BLKADDR_SSOW]; 975 if (!block->implemented) 976 goto tim; 977 block->lf.max = (cfg >> 56) & 0xFF; 978 block->addr = BLKADDR_SSOW; 979 block->type = BLKTYPE_SSOW; 980 block->multislot = true; 981 block->lfshift = 3; 982 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 983 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 984 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 985 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 986 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 987 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 988 sprintf(block->name, "SSOWS"); 989 err = rvu_alloc_bitmap(&block->lf); 990 if (err) { 991 dev_err(rvu->dev, 992 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 993 return err; 994 } 995 996 tim: 997 /* Init TIM LF's bitmap */ 998 block = &hw->block[BLKADDR_TIM]; 999 if (!block->implemented) 1000 goto cpt; 1001 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1002 block->lf.max = cfg & 0xFFFF; 1003 block->addr = BLKADDR_TIM; 1004 block->type = BLKTYPE_TIM; 1005 block->multislot = true; 1006 block->lfshift = 3; 1007 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1008 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1009 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1010 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1011 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1012 block->lfreset_reg = TIM_AF_LF_RST; 1013 sprintf(block->name, "TIM"); 1014 err = rvu_alloc_bitmap(&block->lf); 1015 if (err) { 1016 dev_err(rvu->dev, 1017 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1018 return err; 1019 } 1020 1021 cpt: 1022 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1023 if (err) { 1024 dev_err(rvu->dev, 1025 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1026 return err; 1027 } 1028 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1029 if (err) { 1030 dev_err(rvu->dev, 1031 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1032 return err; 1033 } 1034 1035 /* Allocate memory for PFVF data */ 1036 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1037 sizeof(struct rvu_pfvf), GFP_KERNEL); 1038 if (!rvu->pf) { 1039 dev_err(rvu->dev, 1040 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1041 return -ENOMEM; 1042 } 1043 1044 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1045 sizeof(struct rvu_pfvf), GFP_KERNEL); 1046 if (!rvu->hwvf) { 1047 dev_err(rvu->dev, 1048 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1049 return -ENOMEM; 1050 } 1051 1052 mutex_init(&rvu->rsrc_lock); 1053 1054 rvu_fwdata_init(rvu); 1055 1056 err = rvu_setup_msix_resources(rvu); 1057 if (err) { 1058 dev_err(rvu->dev, 1059 "%s: Failed to setup MSIX resources\n", __func__); 1060 return err; 1061 } 1062 1063 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1064 block = &hw->block[blkid]; 1065 if (!block->lf.bmap) 1066 continue; 1067 1068 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1069 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1070 sizeof(u16), GFP_KERNEL); 1071 if (!block->fn_map) { 1072 err = -ENOMEM; 1073 goto msix_err; 1074 } 1075 1076 /* Scan all blocks to check if low level firmware has 1077 * already provisioned any of the resources to a PF/VF. 1078 */ 1079 rvu_scan_block(rvu, block); 1080 } 1081 1082 err = rvu_set_channels_base(rvu); 1083 if (err) 1084 goto msix_err; 1085 1086 err = rvu_npc_init(rvu); 1087 if (err) { 1088 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1089 goto npc_err; 1090 } 1091 1092 err = rvu_cgx_init(rvu); 1093 if (err) { 1094 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1095 goto cgx_err; 1096 } 1097 1098 /* Assign MACs for CGX mapped functions */ 1099 rvu_setup_pfvf_macaddress(rvu); 1100 1101 err = rvu_npa_init(rvu); 1102 if (err) { 1103 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1104 goto npa_err; 1105 } 1106 1107 rvu_get_lbk_bufsize(rvu); 1108 1109 err = rvu_nix_init(rvu); 1110 if (err) { 1111 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1112 goto nix_err; 1113 } 1114 1115 rvu_program_channels(rvu); 1116 1117 return 0; 1118 1119 nix_err: 1120 rvu_nix_freemem(rvu); 1121 npa_err: 1122 rvu_npa_freemem(rvu); 1123 cgx_err: 1124 rvu_cgx_exit(rvu); 1125 npc_err: 1126 rvu_npc_freemem(rvu); 1127 rvu_fwdata_exit(rvu); 1128 msix_err: 1129 rvu_reset_msix(rvu); 1130 return err; 1131 } 1132 1133 /* NPA and NIX admin queue APIs */ 1134 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1135 { 1136 if (!aq) 1137 return; 1138 1139 qmem_free(rvu->dev, aq->inst); 1140 qmem_free(rvu->dev, aq->res); 1141 devm_kfree(rvu->dev, aq); 1142 } 1143 1144 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1145 int qsize, int inst_size, int res_size) 1146 { 1147 struct admin_queue *aq; 1148 int err; 1149 1150 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1151 if (!*ad_queue) 1152 return -ENOMEM; 1153 aq = *ad_queue; 1154 1155 /* Alloc memory for instructions i.e AQ */ 1156 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1157 if (err) { 1158 devm_kfree(rvu->dev, aq); 1159 return err; 1160 } 1161 1162 /* Alloc memory for results */ 1163 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1164 if (err) { 1165 rvu_aq_free(rvu, aq); 1166 return err; 1167 } 1168 1169 spin_lock_init(&aq->lock); 1170 return 0; 1171 } 1172 1173 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1174 struct ready_msg_rsp *rsp) 1175 { 1176 if (rvu->fwdata) { 1177 rsp->rclk_freq = rvu->fwdata->rclk; 1178 rsp->sclk_freq = rvu->fwdata->sclk; 1179 } 1180 return 0; 1181 } 1182 1183 /* Get current count of a RVU block's LF/slots 1184 * provisioned to a given RVU func. 1185 */ 1186 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1187 { 1188 switch (blkaddr) { 1189 case BLKADDR_NPA: 1190 return pfvf->npalf ? 1 : 0; 1191 case BLKADDR_NIX0: 1192 case BLKADDR_NIX1: 1193 return pfvf->nixlf ? 1 : 0; 1194 case BLKADDR_SSO: 1195 return pfvf->sso; 1196 case BLKADDR_SSOW: 1197 return pfvf->ssow; 1198 case BLKADDR_TIM: 1199 return pfvf->timlfs; 1200 case BLKADDR_CPT0: 1201 return pfvf->cptlfs; 1202 case BLKADDR_CPT1: 1203 return pfvf->cpt1_lfs; 1204 } 1205 return 0; 1206 } 1207 1208 /* Return true if LFs of block type are attached to pcifunc */ 1209 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1210 { 1211 switch (blktype) { 1212 case BLKTYPE_NPA: 1213 return pfvf->npalf ? 1 : 0; 1214 case BLKTYPE_NIX: 1215 return pfvf->nixlf ? 1 : 0; 1216 case BLKTYPE_SSO: 1217 return !!pfvf->sso; 1218 case BLKTYPE_SSOW: 1219 return !!pfvf->ssow; 1220 case BLKTYPE_TIM: 1221 return !!pfvf->timlfs; 1222 case BLKTYPE_CPT: 1223 return pfvf->cptlfs || pfvf->cpt1_lfs; 1224 } 1225 1226 return false; 1227 } 1228 1229 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1230 { 1231 struct rvu_pfvf *pfvf; 1232 1233 if (!is_pf_func_valid(rvu, pcifunc)) 1234 return false; 1235 1236 pfvf = rvu_get_pfvf(rvu, pcifunc); 1237 1238 /* Check if this PFFUNC has a LF of type blktype attached */ 1239 if (!is_blktype_attached(pfvf, blktype)) 1240 return false; 1241 1242 return true; 1243 } 1244 1245 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1246 int pcifunc, int slot) 1247 { 1248 u64 val; 1249 1250 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1251 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1252 /* Wait for the lookup to finish */ 1253 /* TODO: put some timeout here */ 1254 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1255 ; 1256 1257 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1258 1259 /* Check LF valid bit */ 1260 if (!(val & (1ULL << 12))) 1261 return -1; 1262 1263 return (val & 0xFFF); 1264 } 1265 1266 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1267 { 1268 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1269 struct rvu_hwinfo *hw = rvu->hw; 1270 struct rvu_block *block; 1271 int slot, lf, num_lfs; 1272 int blkaddr; 1273 1274 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1275 if (blkaddr < 0) 1276 return; 1277 1278 if (blktype == BLKTYPE_NIX) 1279 rvu_nix_reset_mac(pfvf, pcifunc); 1280 1281 block = &hw->block[blkaddr]; 1282 1283 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1284 if (!num_lfs) 1285 return; 1286 1287 for (slot = 0; slot < num_lfs; slot++) { 1288 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1289 if (lf < 0) /* This should never happen */ 1290 continue; 1291 1292 /* Disable the LF */ 1293 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1294 (lf << block->lfshift), 0x00ULL); 1295 1296 /* Update SW maintained mapping info as well */ 1297 rvu_update_rsrc_map(rvu, pfvf, block, 1298 pcifunc, lf, false); 1299 1300 /* Free the resource */ 1301 rvu_free_rsrc(&block->lf, lf); 1302 1303 /* Clear MSIX vector offset for this LF */ 1304 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1305 } 1306 } 1307 1308 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1309 u16 pcifunc) 1310 { 1311 struct rvu_hwinfo *hw = rvu->hw; 1312 bool detach_all = true; 1313 struct rvu_block *block; 1314 int blkid; 1315 1316 mutex_lock(&rvu->rsrc_lock); 1317 1318 /* Check for partial resource detach */ 1319 if (detach && detach->partial) 1320 detach_all = false; 1321 1322 /* Check for RVU block's LFs attached to this func, 1323 * if so, detach them. 1324 */ 1325 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1326 block = &hw->block[blkid]; 1327 if (!block->lf.bmap) 1328 continue; 1329 if (!detach_all && detach) { 1330 if (blkid == BLKADDR_NPA && !detach->npalf) 1331 continue; 1332 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1333 continue; 1334 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1335 continue; 1336 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1337 continue; 1338 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1339 continue; 1340 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1341 continue; 1342 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1343 continue; 1344 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1345 continue; 1346 } 1347 rvu_detach_block(rvu, pcifunc, block->type); 1348 } 1349 1350 mutex_unlock(&rvu->rsrc_lock); 1351 return 0; 1352 } 1353 1354 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1355 struct rsrc_detach *detach, 1356 struct msg_rsp *rsp) 1357 { 1358 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1359 } 1360 1361 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1362 { 1363 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1364 int blkaddr = BLKADDR_NIX0, vf; 1365 struct rvu_pfvf *pf; 1366 1367 /* All CGX mapped PFs are set with assigned NIX block during init */ 1368 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1369 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1370 blkaddr = pf->nix_blkaddr; 1371 } else if (is_afvf(pcifunc)) { 1372 vf = pcifunc - 1; 1373 /* Assign NIX based on VF number. All even numbered VFs get 1374 * NIX0 and odd numbered gets NIX1 1375 */ 1376 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1377 /* NIX1 is not present on all silicons */ 1378 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1379 blkaddr = BLKADDR_NIX0; 1380 } 1381 1382 switch (blkaddr) { 1383 case BLKADDR_NIX1: 1384 pfvf->nix_blkaddr = BLKADDR_NIX1; 1385 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1386 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1387 break; 1388 case BLKADDR_NIX0: 1389 default: 1390 pfvf->nix_blkaddr = BLKADDR_NIX0; 1391 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1392 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1393 break; 1394 } 1395 1396 return pfvf->nix_blkaddr; 1397 } 1398 1399 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1400 u16 pcifunc, struct rsrc_attach *attach) 1401 { 1402 int blkaddr; 1403 1404 switch (blktype) { 1405 case BLKTYPE_NIX: 1406 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1407 break; 1408 case BLKTYPE_CPT: 1409 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1410 return rvu_get_blkaddr(rvu, blktype, 0); 1411 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1412 BLKADDR_CPT0; 1413 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1414 return -ENODEV; 1415 break; 1416 default: 1417 return rvu_get_blkaddr(rvu, blktype, 0); 1418 } 1419 1420 if (is_block_implemented(rvu->hw, blkaddr)) 1421 return blkaddr; 1422 1423 return -ENODEV; 1424 } 1425 1426 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1427 int num_lfs, struct rsrc_attach *attach) 1428 { 1429 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1430 struct rvu_hwinfo *hw = rvu->hw; 1431 struct rvu_block *block; 1432 int slot, lf; 1433 int blkaddr; 1434 u64 cfg; 1435 1436 if (!num_lfs) 1437 return; 1438 1439 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1440 if (blkaddr < 0) 1441 return; 1442 1443 block = &hw->block[blkaddr]; 1444 if (!block->lf.bmap) 1445 return; 1446 1447 for (slot = 0; slot < num_lfs; slot++) { 1448 /* Allocate the resource */ 1449 lf = rvu_alloc_rsrc(&block->lf); 1450 if (lf < 0) 1451 return; 1452 1453 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1454 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1455 (lf << block->lfshift), cfg); 1456 rvu_update_rsrc_map(rvu, pfvf, block, 1457 pcifunc, lf, true); 1458 1459 /* Set start MSIX vector for this LF within this PF/VF */ 1460 rvu_set_msix_offset(rvu, pfvf, block, lf); 1461 } 1462 } 1463 1464 static int rvu_check_rsrc_availability(struct rvu *rvu, 1465 struct rsrc_attach *req, u16 pcifunc) 1466 { 1467 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1468 int free_lfs, mappedlfs, blkaddr; 1469 struct rvu_hwinfo *hw = rvu->hw; 1470 struct rvu_block *block; 1471 1472 /* Only one NPA LF can be attached */ 1473 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1474 block = &hw->block[BLKADDR_NPA]; 1475 free_lfs = rvu_rsrc_free_count(&block->lf); 1476 if (!free_lfs) 1477 goto fail; 1478 } else if (req->npalf) { 1479 dev_err(&rvu->pdev->dev, 1480 "Func 0x%x: Invalid req, already has NPA\n", 1481 pcifunc); 1482 return -EINVAL; 1483 } 1484 1485 /* Only one NIX LF can be attached */ 1486 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1487 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1488 pcifunc, req); 1489 if (blkaddr < 0) 1490 return blkaddr; 1491 block = &hw->block[blkaddr]; 1492 free_lfs = rvu_rsrc_free_count(&block->lf); 1493 if (!free_lfs) 1494 goto fail; 1495 } else if (req->nixlf) { 1496 dev_err(&rvu->pdev->dev, 1497 "Func 0x%x: Invalid req, already has NIX\n", 1498 pcifunc); 1499 return -EINVAL; 1500 } 1501 1502 if (req->sso) { 1503 block = &hw->block[BLKADDR_SSO]; 1504 /* Is request within limits ? */ 1505 if (req->sso > block->lf.max) { 1506 dev_err(&rvu->pdev->dev, 1507 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1508 pcifunc, req->sso, block->lf.max); 1509 return -EINVAL; 1510 } 1511 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1512 free_lfs = rvu_rsrc_free_count(&block->lf); 1513 /* Check if additional resources are available */ 1514 if (req->sso > mappedlfs && 1515 ((req->sso - mappedlfs) > free_lfs)) 1516 goto fail; 1517 } 1518 1519 if (req->ssow) { 1520 block = &hw->block[BLKADDR_SSOW]; 1521 if (req->ssow > block->lf.max) { 1522 dev_err(&rvu->pdev->dev, 1523 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1524 pcifunc, req->sso, block->lf.max); 1525 return -EINVAL; 1526 } 1527 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1528 free_lfs = rvu_rsrc_free_count(&block->lf); 1529 if (req->ssow > mappedlfs && 1530 ((req->ssow - mappedlfs) > free_lfs)) 1531 goto fail; 1532 } 1533 1534 if (req->timlfs) { 1535 block = &hw->block[BLKADDR_TIM]; 1536 if (req->timlfs > block->lf.max) { 1537 dev_err(&rvu->pdev->dev, 1538 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1539 pcifunc, req->timlfs, block->lf.max); 1540 return -EINVAL; 1541 } 1542 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1543 free_lfs = rvu_rsrc_free_count(&block->lf); 1544 if (req->timlfs > mappedlfs && 1545 ((req->timlfs - mappedlfs) > free_lfs)) 1546 goto fail; 1547 } 1548 1549 if (req->cptlfs) { 1550 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1551 pcifunc, req); 1552 if (blkaddr < 0) 1553 return blkaddr; 1554 block = &hw->block[blkaddr]; 1555 if (req->cptlfs > block->lf.max) { 1556 dev_err(&rvu->pdev->dev, 1557 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1558 pcifunc, req->cptlfs, block->lf.max); 1559 return -EINVAL; 1560 } 1561 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1562 free_lfs = rvu_rsrc_free_count(&block->lf); 1563 if (req->cptlfs > mappedlfs && 1564 ((req->cptlfs - mappedlfs) > free_lfs)) 1565 goto fail; 1566 } 1567 1568 return 0; 1569 1570 fail: 1571 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1572 return -ENOSPC; 1573 } 1574 1575 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1576 struct rsrc_attach *attach) 1577 { 1578 int blkaddr, num_lfs; 1579 1580 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1581 attach->hdr.pcifunc, attach); 1582 if (blkaddr < 0) 1583 return false; 1584 1585 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1586 blkaddr); 1587 /* Requester already has LFs from given block ? */ 1588 return !!num_lfs; 1589 } 1590 1591 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1592 struct rsrc_attach *attach, 1593 struct msg_rsp *rsp) 1594 { 1595 u16 pcifunc = attach->hdr.pcifunc; 1596 int err; 1597 1598 /* If first request, detach all existing attached resources */ 1599 if (!attach->modify) 1600 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1601 1602 mutex_lock(&rvu->rsrc_lock); 1603 1604 /* Check if the request can be accommodated */ 1605 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1606 if (err) 1607 goto exit; 1608 1609 /* Now attach the requested resources */ 1610 if (attach->npalf) 1611 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1612 1613 if (attach->nixlf) 1614 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1615 1616 if (attach->sso) { 1617 /* RVU func doesn't know which exact LF or slot is attached 1618 * to it, it always sees as slot 0,1,2. So for a 'modify' 1619 * request, simply detach all existing attached LFs/slots 1620 * and attach a fresh. 1621 */ 1622 if (attach->modify) 1623 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1624 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1625 attach->sso, attach); 1626 } 1627 1628 if (attach->ssow) { 1629 if (attach->modify) 1630 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1631 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1632 attach->ssow, attach); 1633 } 1634 1635 if (attach->timlfs) { 1636 if (attach->modify) 1637 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1638 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1639 attach->timlfs, attach); 1640 } 1641 1642 if (attach->cptlfs) { 1643 if (attach->modify && 1644 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1645 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1646 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1647 attach->cptlfs, attach); 1648 } 1649 1650 exit: 1651 mutex_unlock(&rvu->rsrc_lock); 1652 return err; 1653 } 1654 1655 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1656 int blkaddr, int lf) 1657 { 1658 u16 vec; 1659 1660 if (lf < 0) 1661 return MSIX_VECTOR_INVALID; 1662 1663 for (vec = 0; vec < pfvf->msix.max; vec++) { 1664 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1665 return vec; 1666 } 1667 return MSIX_VECTOR_INVALID; 1668 } 1669 1670 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1671 struct rvu_block *block, int lf) 1672 { 1673 u16 nvecs, vec, offset; 1674 u64 cfg; 1675 1676 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1677 (lf << block->lfshift)); 1678 nvecs = (cfg >> 12) & 0xFF; 1679 1680 /* Check and alloc MSIX vectors, must be contiguous */ 1681 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1682 return; 1683 1684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1685 1686 /* Config MSIX offset in LF */ 1687 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1688 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1689 1690 /* Update the bitmap as well */ 1691 for (vec = 0; vec < nvecs; vec++) 1692 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1693 } 1694 1695 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1696 struct rvu_block *block, int lf) 1697 { 1698 u16 nvecs, vec, offset; 1699 u64 cfg; 1700 1701 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1702 (lf << block->lfshift)); 1703 nvecs = (cfg >> 12) & 0xFF; 1704 1705 /* Clear MSIX offset in LF */ 1706 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1707 (lf << block->lfshift), cfg & ~0x7FFULL); 1708 1709 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1710 1711 /* Update the mapping */ 1712 for (vec = 0; vec < nvecs; vec++) 1713 pfvf->msix_lfmap[offset + vec] = 0; 1714 1715 /* Free the same in MSIX bitmap */ 1716 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1717 } 1718 1719 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1720 struct msix_offset_rsp *rsp) 1721 { 1722 struct rvu_hwinfo *hw = rvu->hw; 1723 u16 pcifunc = req->hdr.pcifunc; 1724 struct rvu_pfvf *pfvf; 1725 int lf, slot, blkaddr; 1726 1727 pfvf = rvu_get_pfvf(rvu, pcifunc); 1728 if (!pfvf->msix.bmap) 1729 return 0; 1730 1731 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1732 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1733 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1734 1735 /* Get BLKADDR from which LFs are attached to pcifunc */ 1736 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1737 if (blkaddr < 0) { 1738 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1739 } else { 1740 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1741 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1742 } 1743 1744 rsp->sso = pfvf->sso; 1745 for (slot = 0; slot < rsp->sso; slot++) { 1746 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1747 rsp->sso_msixoff[slot] = 1748 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1749 } 1750 1751 rsp->ssow = pfvf->ssow; 1752 for (slot = 0; slot < rsp->ssow; slot++) { 1753 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1754 rsp->ssow_msixoff[slot] = 1755 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1756 } 1757 1758 rsp->timlfs = pfvf->timlfs; 1759 for (slot = 0; slot < rsp->timlfs; slot++) { 1760 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1761 rsp->timlf_msixoff[slot] = 1762 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1763 } 1764 1765 rsp->cptlfs = pfvf->cptlfs; 1766 for (slot = 0; slot < rsp->cptlfs; slot++) { 1767 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1768 rsp->cptlf_msixoff[slot] = 1769 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1770 } 1771 1772 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1773 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1774 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1775 rsp->cpt1_lf_msixoff[slot] = 1776 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1777 } 1778 1779 return 0; 1780 } 1781 1782 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1783 struct msg_rsp *rsp) 1784 { 1785 u16 pcifunc = req->hdr.pcifunc; 1786 u16 vf, numvfs; 1787 u64 cfg; 1788 1789 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1790 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1791 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1792 numvfs = (cfg >> 12) & 0xFF; 1793 1794 if (vf && vf <= numvfs) 1795 __rvu_flr_handler(rvu, pcifunc); 1796 else 1797 return RVU_INVALID_VF_ID; 1798 1799 return 0; 1800 } 1801 1802 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1803 struct get_hw_cap_rsp *rsp) 1804 { 1805 struct rvu_hwinfo *hw = rvu->hw; 1806 1807 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1808 rsp->nix_shaping = hw->cap.nix_shaping; 1809 1810 return 0; 1811 } 1812 1813 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 1814 struct msg_rsp *rsp) 1815 { 1816 struct rvu_hwinfo *hw = rvu->hw; 1817 u16 pcifunc = req->hdr.pcifunc; 1818 struct rvu_pfvf *pfvf; 1819 int blkaddr, nixlf; 1820 u16 target; 1821 1822 /* Only PF can add VF permissions */ 1823 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc)) 1824 return -EOPNOTSUPP; 1825 1826 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 1827 pfvf = rvu_get_pfvf(rvu, target); 1828 1829 if (req->flags & RESET_VF_PERM) { 1830 pfvf->flags &= RVU_CLEAR_VF_PERM; 1831 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 1832 (req->flags & VF_TRUSTED)) { 1833 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 1834 /* disable multicast and promisc entries */ 1835 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 1836 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 1837 if (blkaddr < 0) 1838 return 0; 1839 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 1840 target, 0); 1841 if (nixlf < 0) 1842 return 0; 1843 npc_enadis_default_mce_entry(rvu, target, nixlf, 1844 NIXLF_ALLMULTI_ENTRY, 1845 false); 1846 npc_enadis_default_mce_entry(rvu, target, nixlf, 1847 NIXLF_PROMISC_ENTRY, 1848 false); 1849 } 1850 } 1851 1852 return 0; 1853 } 1854 1855 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1856 struct mbox_msghdr *req) 1857 { 1858 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1859 1860 /* Check if valid, if not reply with a invalid msg */ 1861 if (req->sig != OTX2_MBOX_REQ_SIG) 1862 goto bad_message; 1863 1864 switch (req->id) { 1865 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1866 case _id: { \ 1867 struct _rsp_type *rsp; \ 1868 int err; \ 1869 \ 1870 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1871 mbox, devid, \ 1872 sizeof(struct _rsp_type)); \ 1873 /* some handlers should complete even if reply */ \ 1874 /* could not be allocated */ \ 1875 if (!rsp && \ 1876 _id != MBOX_MSG_DETACH_RESOURCES && \ 1877 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1878 _id != MBOX_MSG_VF_FLR) \ 1879 return -ENOMEM; \ 1880 if (rsp) { \ 1881 rsp->hdr.id = _id; \ 1882 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1883 rsp->hdr.pcifunc = req->pcifunc; \ 1884 rsp->hdr.rc = 0; \ 1885 } \ 1886 \ 1887 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1888 (struct _req_type *)req, \ 1889 rsp); \ 1890 if (rsp && err) \ 1891 rsp->hdr.rc = err; \ 1892 \ 1893 trace_otx2_msg_process(mbox->pdev, _id, err); \ 1894 return rsp ? err : -ENOMEM; \ 1895 } 1896 MBOX_MESSAGES 1897 #undef M 1898 1899 bad_message: 1900 default: 1901 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1902 return -ENODEV; 1903 } 1904 } 1905 1906 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1907 { 1908 struct rvu *rvu = mwork->rvu; 1909 int offset, err, id, devid; 1910 struct otx2_mbox_dev *mdev; 1911 struct mbox_hdr *req_hdr; 1912 struct mbox_msghdr *msg; 1913 struct mbox_wq_info *mw; 1914 struct otx2_mbox *mbox; 1915 1916 switch (type) { 1917 case TYPE_AFPF: 1918 mw = &rvu->afpf_wq_info; 1919 break; 1920 case TYPE_AFVF: 1921 mw = &rvu->afvf_wq_info; 1922 break; 1923 default: 1924 return; 1925 } 1926 1927 devid = mwork - mw->mbox_wrk; 1928 mbox = &mw->mbox; 1929 mdev = &mbox->dev[devid]; 1930 1931 /* Process received mbox messages */ 1932 req_hdr = mdev->mbase + mbox->rx_start; 1933 if (mw->mbox_wrk[devid].num_msgs == 0) 1934 return; 1935 1936 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1937 1938 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 1939 msg = mdev->mbase + offset; 1940 1941 /* Set which PF/VF sent this message based on mbox IRQ */ 1942 switch (type) { 1943 case TYPE_AFPF: 1944 msg->pcifunc &= 1945 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1946 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1947 break; 1948 case TYPE_AFVF: 1949 msg->pcifunc &= 1950 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1951 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1952 break; 1953 } 1954 1955 err = rvu_process_mbox_msg(mbox, devid, msg); 1956 if (!err) { 1957 offset = mbox->rx_start + msg->next_msgoff; 1958 continue; 1959 } 1960 1961 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1962 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1963 err, otx2_mbox_id2name(msg->id), 1964 msg->id, rvu_get_pf(msg->pcifunc), 1965 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1966 else 1967 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1968 err, otx2_mbox_id2name(msg->id), 1969 msg->id, devid); 1970 } 1971 mw->mbox_wrk[devid].num_msgs = 0; 1972 1973 /* Send mbox responses to VF/PF */ 1974 otx2_mbox_msg_send(mbox, devid); 1975 } 1976 1977 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1978 { 1979 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1980 1981 __rvu_mbox_handler(mwork, TYPE_AFPF); 1982 } 1983 1984 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1985 { 1986 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1987 1988 __rvu_mbox_handler(mwork, TYPE_AFVF); 1989 } 1990 1991 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1992 { 1993 struct rvu *rvu = mwork->rvu; 1994 struct otx2_mbox_dev *mdev; 1995 struct mbox_hdr *rsp_hdr; 1996 struct mbox_msghdr *msg; 1997 struct mbox_wq_info *mw; 1998 struct otx2_mbox *mbox; 1999 int offset, id, devid; 2000 2001 switch (type) { 2002 case TYPE_AFPF: 2003 mw = &rvu->afpf_wq_info; 2004 break; 2005 case TYPE_AFVF: 2006 mw = &rvu->afvf_wq_info; 2007 break; 2008 default: 2009 return; 2010 } 2011 2012 devid = mwork - mw->mbox_wrk_up; 2013 mbox = &mw->mbox_up; 2014 mdev = &mbox->dev[devid]; 2015 2016 rsp_hdr = mdev->mbase + mbox->rx_start; 2017 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2018 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2019 return; 2020 } 2021 2022 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2023 2024 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2025 msg = mdev->mbase + offset; 2026 2027 if (msg->id >= MBOX_MSG_MAX) { 2028 dev_err(rvu->dev, 2029 "Mbox msg with unknown ID 0x%x\n", msg->id); 2030 goto end; 2031 } 2032 2033 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2034 dev_err(rvu->dev, 2035 "Mbox msg with wrong signature %x, ID 0x%x\n", 2036 msg->sig, msg->id); 2037 goto end; 2038 } 2039 2040 switch (msg->id) { 2041 case MBOX_MSG_CGX_LINK_EVENT: 2042 break; 2043 default: 2044 if (msg->rc) 2045 dev_err(rvu->dev, 2046 "Mbox msg response has err %d, ID 0x%x\n", 2047 msg->rc, msg->id); 2048 break; 2049 } 2050 end: 2051 offset = mbox->rx_start + msg->next_msgoff; 2052 mdev->msgs_acked++; 2053 } 2054 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2055 2056 otx2_mbox_reset(mbox, devid); 2057 } 2058 2059 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2060 { 2061 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2062 2063 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2064 } 2065 2066 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2067 { 2068 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2069 2070 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2071 } 2072 2073 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2074 int num, int type) 2075 { 2076 struct rvu_hwinfo *hw = rvu->hw; 2077 int region; 2078 u64 bar4; 2079 2080 /* For cn10k platform VF mailbox regions of a PF follows after the 2081 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2082 * RVU_PF_VF_BAR4_ADDR register. 2083 */ 2084 if (type == TYPE_AFVF) { 2085 for (region = 0; region < num; region++) { 2086 if (hw->cap.per_pf_mbox_regs) { 2087 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2088 RVU_AF_PFX_BAR4_ADDR(0)) + 2089 MBOX_SIZE; 2090 bar4 += region * MBOX_SIZE; 2091 } else { 2092 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2093 bar4 += region * MBOX_SIZE; 2094 } 2095 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2096 if (!mbox_addr[region]) 2097 goto error; 2098 } 2099 return 0; 2100 } 2101 2102 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2103 * PF registers. Whereas for Octeontx2 it is read from 2104 * RVU_AF_PF_BAR4_ADDR register. 2105 */ 2106 for (region = 0; region < num; region++) { 2107 if (hw->cap.per_pf_mbox_regs) { 2108 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2109 RVU_AF_PFX_BAR4_ADDR(region)); 2110 } else { 2111 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2112 RVU_AF_PF_BAR4_ADDR); 2113 bar4 += region * MBOX_SIZE; 2114 } 2115 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2116 if (!mbox_addr[region]) 2117 goto error; 2118 } 2119 return 0; 2120 2121 error: 2122 while (region--) 2123 iounmap((void __iomem *)mbox_addr[region]); 2124 return -ENOMEM; 2125 } 2126 2127 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2128 int type, int num, 2129 void (mbox_handler)(struct work_struct *), 2130 void (mbox_up_handler)(struct work_struct *)) 2131 { 2132 int err = -EINVAL, i, dir, dir_up; 2133 void __iomem *reg_base; 2134 struct rvu_work *mwork; 2135 void **mbox_regions; 2136 const char *name; 2137 2138 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2139 if (!mbox_regions) 2140 return -ENOMEM; 2141 2142 switch (type) { 2143 case TYPE_AFPF: 2144 name = "rvu_afpf_mailbox"; 2145 dir = MBOX_DIR_AFPF; 2146 dir_up = MBOX_DIR_AFPF_UP; 2147 reg_base = rvu->afreg_base; 2148 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF); 2149 if (err) 2150 goto free_regions; 2151 break; 2152 case TYPE_AFVF: 2153 name = "rvu_afvf_mailbox"; 2154 dir = MBOX_DIR_PFVF; 2155 dir_up = MBOX_DIR_PFVF_UP; 2156 reg_base = rvu->pfreg_base; 2157 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF); 2158 if (err) 2159 goto free_regions; 2160 break; 2161 default: 2162 return err; 2163 } 2164 2165 mw->mbox_wq = alloc_workqueue(name, 2166 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2167 num); 2168 if (!mw->mbox_wq) { 2169 err = -ENOMEM; 2170 goto unmap_regions; 2171 } 2172 2173 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2174 sizeof(struct rvu_work), GFP_KERNEL); 2175 if (!mw->mbox_wrk) { 2176 err = -ENOMEM; 2177 goto exit; 2178 } 2179 2180 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2181 sizeof(struct rvu_work), GFP_KERNEL); 2182 if (!mw->mbox_wrk_up) { 2183 err = -ENOMEM; 2184 goto exit; 2185 } 2186 2187 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2188 reg_base, dir, num); 2189 if (err) 2190 goto exit; 2191 2192 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2193 reg_base, dir_up, num); 2194 if (err) 2195 goto exit; 2196 2197 for (i = 0; i < num; i++) { 2198 mwork = &mw->mbox_wrk[i]; 2199 mwork->rvu = rvu; 2200 INIT_WORK(&mwork->work, mbox_handler); 2201 2202 mwork = &mw->mbox_wrk_up[i]; 2203 mwork->rvu = rvu; 2204 INIT_WORK(&mwork->work, mbox_up_handler); 2205 } 2206 kfree(mbox_regions); 2207 return 0; 2208 2209 exit: 2210 destroy_workqueue(mw->mbox_wq); 2211 unmap_regions: 2212 while (num--) 2213 iounmap((void __iomem *)mbox_regions[num]); 2214 free_regions: 2215 kfree(mbox_regions); 2216 return err; 2217 } 2218 2219 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2220 { 2221 struct otx2_mbox *mbox = &mw->mbox; 2222 struct otx2_mbox_dev *mdev; 2223 int devid; 2224 2225 if (mw->mbox_wq) { 2226 flush_workqueue(mw->mbox_wq); 2227 destroy_workqueue(mw->mbox_wq); 2228 mw->mbox_wq = NULL; 2229 } 2230 2231 for (devid = 0; devid < mbox->ndevs; devid++) { 2232 mdev = &mbox->dev[devid]; 2233 if (mdev->hwbase) 2234 iounmap((void __iomem *)mdev->hwbase); 2235 } 2236 2237 otx2_mbox_destroy(&mw->mbox); 2238 otx2_mbox_destroy(&mw->mbox_up); 2239 } 2240 2241 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2242 int mdevs, u64 intr) 2243 { 2244 struct otx2_mbox_dev *mdev; 2245 struct otx2_mbox *mbox; 2246 struct mbox_hdr *hdr; 2247 int i; 2248 2249 for (i = first; i < mdevs; i++) { 2250 /* start from 0 */ 2251 if (!(intr & BIT_ULL(i - first))) 2252 continue; 2253 2254 mbox = &mw->mbox; 2255 mdev = &mbox->dev[i]; 2256 hdr = mdev->mbase + mbox->rx_start; 2257 2258 /*The hdr->num_msgs is set to zero immediately in the interrupt 2259 * handler to ensure that it holds a correct value next time 2260 * when the interrupt handler is called. 2261 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2262 * pf>mbox.up_num_msgs holds the data for use in 2263 * pfaf_mbox_up_handler. 2264 */ 2265 2266 if (hdr->num_msgs) { 2267 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2268 hdr->num_msgs = 0; 2269 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2270 } 2271 mbox = &mw->mbox_up; 2272 mdev = &mbox->dev[i]; 2273 hdr = mdev->mbase + mbox->rx_start; 2274 if (hdr->num_msgs) { 2275 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2276 hdr->num_msgs = 0; 2277 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2278 } 2279 } 2280 } 2281 2282 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2283 { 2284 struct rvu *rvu = (struct rvu *)rvu_irq; 2285 int vfs = rvu->vfs; 2286 u64 intr; 2287 2288 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2289 /* Clear interrupts */ 2290 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2291 if (intr) 2292 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2293 2294 /* Sync with mbox memory region */ 2295 rmb(); 2296 2297 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2298 2299 /* Handle VF interrupts */ 2300 if (vfs > 64) { 2301 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2302 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2303 2304 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2305 vfs -= 64; 2306 } 2307 2308 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2309 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2310 if (intr) 2311 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2312 2313 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2314 2315 return IRQ_HANDLED; 2316 } 2317 2318 static void rvu_enable_mbox_intr(struct rvu *rvu) 2319 { 2320 struct rvu_hwinfo *hw = rvu->hw; 2321 2322 /* Clear spurious irqs, if any */ 2323 rvu_write64(rvu, BLKADDR_RVUM, 2324 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2325 2326 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2327 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2328 INTR_MASK(hw->total_pfs) & ~1ULL); 2329 } 2330 2331 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2332 { 2333 struct rvu_block *block; 2334 int slot, lf, num_lfs; 2335 int err; 2336 2337 block = &rvu->hw->block[blkaddr]; 2338 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2339 block->addr); 2340 if (!num_lfs) 2341 return; 2342 for (slot = 0; slot < num_lfs; slot++) { 2343 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2344 if (lf < 0) 2345 continue; 2346 2347 /* Cleanup LF and reset it */ 2348 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2349 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2350 else if (block->addr == BLKADDR_NPA) 2351 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2352 else if ((block->addr == BLKADDR_CPT0) || 2353 (block->addr == BLKADDR_CPT1)) 2354 rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot); 2355 2356 err = rvu_lf_reset(rvu, block, lf); 2357 if (err) { 2358 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2359 block->addr, lf); 2360 } 2361 } 2362 } 2363 2364 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2365 { 2366 mutex_lock(&rvu->flr_lock); 2367 /* Reset order should reflect inter-block dependencies: 2368 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2369 * 2. Flush and reset SSO/SSOW 2370 * 3. Cleanup pools (NPA) 2371 */ 2372 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2373 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2374 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2375 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2376 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2377 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2378 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2379 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2380 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2381 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2382 mutex_unlock(&rvu->flr_lock); 2383 } 2384 2385 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2386 { 2387 int reg = 0; 2388 2389 /* pcifunc = 0(PF0) | (vf + 1) */ 2390 __rvu_flr_handler(rvu, vf + 1); 2391 2392 if (vf >= 64) { 2393 reg = 1; 2394 vf = vf - 64; 2395 } 2396 2397 /* Signal FLR finish and enable IRQ */ 2398 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2399 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2400 } 2401 2402 static void rvu_flr_handler(struct work_struct *work) 2403 { 2404 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2405 struct rvu *rvu = flrwork->rvu; 2406 u16 pcifunc, numvfs, vf; 2407 u64 cfg; 2408 int pf; 2409 2410 pf = flrwork - rvu->flr_wrk; 2411 if (pf >= rvu->hw->total_pfs) { 2412 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2413 return; 2414 } 2415 2416 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2417 numvfs = (cfg >> 12) & 0xFF; 2418 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2419 2420 for (vf = 0; vf < numvfs; vf++) 2421 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2422 2423 __rvu_flr_handler(rvu, pcifunc); 2424 2425 /* Signal FLR finish */ 2426 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2427 2428 /* Enable interrupt */ 2429 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2430 } 2431 2432 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2433 { 2434 int dev, vf, reg = 0; 2435 u64 intr; 2436 2437 if (start_vf >= 64) 2438 reg = 1; 2439 2440 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2441 if (!intr) 2442 return; 2443 2444 for (vf = 0; vf < numvfs; vf++) { 2445 if (!(intr & BIT_ULL(vf))) 2446 continue; 2447 dev = vf + start_vf + rvu->hw->total_pfs; 2448 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2449 /* Clear and disable the interrupt */ 2450 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2451 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2452 } 2453 } 2454 2455 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2456 { 2457 struct rvu *rvu = (struct rvu *)rvu_irq; 2458 u64 intr; 2459 u8 pf; 2460 2461 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2462 if (!intr) 2463 goto afvf_flr; 2464 2465 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2466 if (intr & (1ULL << pf)) { 2467 /* PF is already dead do only AF related operations */ 2468 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2469 /* clear interrupt */ 2470 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2471 BIT_ULL(pf)); 2472 /* Disable the interrupt */ 2473 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2474 BIT_ULL(pf)); 2475 } 2476 } 2477 2478 afvf_flr: 2479 rvu_afvf_queue_flr_work(rvu, 0, 64); 2480 if (rvu->vfs > 64) 2481 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2482 2483 return IRQ_HANDLED; 2484 } 2485 2486 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2487 { 2488 int vf; 2489 2490 /* Nothing to be done here other than clearing the 2491 * TRPEND bit. 2492 */ 2493 for (vf = 0; vf < 64; vf++) { 2494 if (intr & (1ULL << vf)) { 2495 /* clear the trpend due to ME(master enable) */ 2496 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2497 /* clear interrupt */ 2498 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2499 } 2500 } 2501 } 2502 2503 /* Handles ME interrupts from VFs of AF */ 2504 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2505 { 2506 struct rvu *rvu = (struct rvu *)rvu_irq; 2507 int vfset; 2508 u64 intr; 2509 2510 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2511 2512 for (vfset = 0; vfset <= 1; vfset++) { 2513 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2514 if (intr) 2515 rvu_me_handle_vfset(rvu, vfset, intr); 2516 } 2517 2518 return IRQ_HANDLED; 2519 } 2520 2521 /* Handles ME interrupts from PFs */ 2522 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2523 { 2524 struct rvu *rvu = (struct rvu *)rvu_irq; 2525 u64 intr; 2526 u8 pf; 2527 2528 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2529 2530 /* Nothing to be done here other than clearing the 2531 * TRPEND bit. 2532 */ 2533 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2534 if (intr & (1ULL << pf)) { 2535 /* clear the trpend due to ME(master enable) */ 2536 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2537 BIT_ULL(pf)); 2538 /* clear interrupt */ 2539 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2540 BIT_ULL(pf)); 2541 } 2542 } 2543 2544 return IRQ_HANDLED; 2545 } 2546 2547 static void rvu_unregister_interrupts(struct rvu *rvu) 2548 { 2549 int irq; 2550 2551 /* Disable the Mbox interrupt */ 2552 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2553 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2554 2555 /* Disable the PF FLR interrupt */ 2556 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2557 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2558 2559 /* Disable the PF ME interrupt */ 2560 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2561 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2562 2563 for (irq = 0; irq < rvu->num_vec; irq++) { 2564 if (rvu->irq_allocated[irq]) { 2565 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2566 rvu->irq_allocated[irq] = false; 2567 } 2568 } 2569 2570 pci_free_irq_vectors(rvu->pdev); 2571 rvu->num_vec = 0; 2572 } 2573 2574 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2575 { 2576 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2577 int offset; 2578 2579 pfvf = &rvu->pf[0]; 2580 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2581 2582 /* Make sure there are enough MSIX vectors configured so that 2583 * VF interrupts can be handled. Offset equal to zero means 2584 * that PF vectors are not configured and overlapping AF vectors. 2585 */ 2586 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2587 offset; 2588 } 2589 2590 static int rvu_register_interrupts(struct rvu *rvu) 2591 { 2592 int ret, offset, pf_vec_start; 2593 2594 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2595 2596 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2597 NAME_SIZE, GFP_KERNEL); 2598 if (!rvu->irq_name) 2599 return -ENOMEM; 2600 2601 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2602 sizeof(bool), GFP_KERNEL); 2603 if (!rvu->irq_allocated) 2604 return -ENOMEM; 2605 2606 /* Enable MSI-X */ 2607 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2608 rvu->num_vec, PCI_IRQ_MSIX); 2609 if (ret < 0) { 2610 dev_err(rvu->dev, 2611 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2612 rvu->num_vec, ret); 2613 return ret; 2614 } 2615 2616 /* Register mailbox interrupt handler */ 2617 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2618 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2619 rvu_mbox_intr_handler, 0, 2620 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2621 if (ret) { 2622 dev_err(rvu->dev, 2623 "RVUAF: IRQ registration failed for mbox irq\n"); 2624 goto fail; 2625 } 2626 2627 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2628 2629 /* Enable mailbox interrupts from all PFs */ 2630 rvu_enable_mbox_intr(rvu); 2631 2632 /* Register FLR interrupt handler */ 2633 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2634 "RVUAF FLR"); 2635 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2636 rvu_flr_intr_handler, 0, 2637 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2638 rvu); 2639 if (ret) { 2640 dev_err(rvu->dev, 2641 "RVUAF: IRQ registration failed for FLR\n"); 2642 goto fail; 2643 } 2644 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2645 2646 /* Enable FLR interrupt for all PFs*/ 2647 rvu_write64(rvu, BLKADDR_RVUM, 2648 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2649 2650 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2651 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2652 2653 /* Register ME interrupt handler */ 2654 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2655 "RVUAF ME"); 2656 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2657 rvu_me_pf_intr_handler, 0, 2658 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2659 rvu); 2660 if (ret) { 2661 dev_err(rvu->dev, 2662 "RVUAF: IRQ registration failed for ME\n"); 2663 } 2664 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2665 2666 /* Clear TRPEND bit for all PF */ 2667 rvu_write64(rvu, BLKADDR_RVUM, 2668 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2669 /* Enable ME interrupt for all PFs*/ 2670 rvu_write64(rvu, BLKADDR_RVUM, 2671 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2672 2673 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2674 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2675 2676 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2677 return 0; 2678 2679 /* Get PF MSIX vectors offset. */ 2680 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2681 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2682 2683 /* Register MBOX0 interrupt. */ 2684 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2685 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2686 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2687 rvu_mbox_intr_handler, 0, 2688 &rvu->irq_name[offset * NAME_SIZE], 2689 rvu); 2690 if (ret) 2691 dev_err(rvu->dev, 2692 "RVUAF: IRQ registration failed for Mbox0\n"); 2693 2694 rvu->irq_allocated[offset] = true; 2695 2696 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2697 * simply increment current offset by 1. 2698 */ 2699 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2700 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2701 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2702 rvu_mbox_intr_handler, 0, 2703 &rvu->irq_name[offset * NAME_SIZE], 2704 rvu); 2705 if (ret) 2706 dev_err(rvu->dev, 2707 "RVUAF: IRQ registration failed for Mbox1\n"); 2708 2709 rvu->irq_allocated[offset] = true; 2710 2711 /* Register FLR interrupt handler for AF's VFs */ 2712 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2713 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2714 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2715 rvu_flr_intr_handler, 0, 2716 &rvu->irq_name[offset * NAME_SIZE], rvu); 2717 if (ret) { 2718 dev_err(rvu->dev, 2719 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2720 goto fail; 2721 } 2722 rvu->irq_allocated[offset] = true; 2723 2724 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2725 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2726 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2727 rvu_flr_intr_handler, 0, 2728 &rvu->irq_name[offset * NAME_SIZE], rvu); 2729 if (ret) { 2730 dev_err(rvu->dev, 2731 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2732 goto fail; 2733 } 2734 rvu->irq_allocated[offset] = true; 2735 2736 /* Register ME interrupt handler for AF's VFs */ 2737 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2738 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2739 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2740 rvu_me_vf_intr_handler, 0, 2741 &rvu->irq_name[offset * NAME_SIZE], rvu); 2742 if (ret) { 2743 dev_err(rvu->dev, 2744 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2745 goto fail; 2746 } 2747 rvu->irq_allocated[offset] = true; 2748 2749 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2750 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2751 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2752 rvu_me_vf_intr_handler, 0, 2753 &rvu->irq_name[offset * NAME_SIZE], rvu); 2754 if (ret) { 2755 dev_err(rvu->dev, 2756 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2757 goto fail; 2758 } 2759 rvu->irq_allocated[offset] = true; 2760 return 0; 2761 2762 fail: 2763 rvu_unregister_interrupts(rvu); 2764 return ret; 2765 } 2766 2767 static void rvu_flr_wq_destroy(struct rvu *rvu) 2768 { 2769 if (rvu->flr_wq) { 2770 flush_workqueue(rvu->flr_wq); 2771 destroy_workqueue(rvu->flr_wq); 2772 rvu->flr_wq = NULL; 2773 } 2774 } 2775 2776 static int rvu_flr_init(struct rvu *rvu) 2777 { 2778 int dev, num_devs; 2779 u64 cfg; 2780 int pf; 2781 2782 /* Enable FLR for all PFs*/ 2783 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2784 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2785 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2786 cfg | BIT_ULL(22)); 2787 } 2788 2789 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2790 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2791 1); 2792 if (!rvu->flr_wq) 2793 return -ENOMEM; 2794 2795 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2796 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2797 sizeof(struct rvu_work), GFP_KERNEL); 2798 if (!rvu->flr_wrk) { 2799 destroy_workqueue(rvu->flr_wq); 2800 return -ENOMEM; 2801 } 2802 2803 for (dev = 0; dev < num_devs; dev++) { 2804 rvu->flr_wrk[dev].rvu = rvu; 2805 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2806 } 2807 2808 mutex_init(&rvu->flr_lock); 2809 2810 return 0; 2811 } 2812 2813 static void rvu_disable_afvf_intr(struct rvu *rvu) 2814 { 2815 int vfs = rvu->vfs; 2816 2817 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2818 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2819 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2820 if (vfs <= 64) 2821 return; 2822 2823 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2824 INTR_MASK(vfs - 64)); 2825 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2826 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2827 } 2828 2829 static void rvu_enable_afvf_intr(struct rvu *rvu) 2830 { 2831 int vfs = rvu->vfs; 2832 2833 /* Clear any pending interrupts and enable AF VF interrupts for 2834 * the first 64 VFs. 2835 */ 2836 /* Mbox */ 2837 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2838 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2839 2840 /* FLR */ 2841 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2842 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2843 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2844 2845 /* Same for remaining VFs, if any. */ 2846 if (vfs <= 64) 2847 return; 2848 2849 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2850 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2851 INTR_MASK(vfs - 64)); 2852 2853 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2854 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2855 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2856 } 2857 2858 int rvu_get_num_lbk_chans(void) 2859 { 2860 struct pci_dev *pdev; 2861 void __iomem *base; 2862 int ret = -EIO; 2863 2864 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2865 NULL); 2866 if (!pdev) 2867 goto err; 2868 2869 base = pci_ioremap_bar(pdev, 0); 2870 if (!base) 2871 goto err_put; 2872 2873 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2874 ret = (readq(base + 0x10) >> 32) & 0xffff; 2875 iounmap(base); 2876 err_put: 2877 pci_dev_put(pdev); 2878 err: 2879 return ret; 2880 } 2881 2882 static int rvu_enable_sriov(struct rvu *rvu) 2883 { 2884 struct pci_dev *pdev = rvu->pdev; 2885 int err, chans, vfs; 2886 2887 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2888 dev_warn(&pdev->dev, 2889 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2890 return 0; 2891 } 2892 2893 chans = rvu_get_num_lbk_chans(); 2894 if (chans < 0) 2895 return chans; 2896 2897 vfs = pci_sriov_get_totalvfs(pdev); 2898 2899 /* Limit VFs in case we have more VFs than LBK channels available. */ 2900 if (vfs > chans) 2901 vfs = chans; 2902 2903 if (!vfs) 2904 return 0; 2905 2906 /* LBK channel number 63 is used for switching packets between 2907 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 2908 */ 2909 if (vfs > 62) 2910 vfs = 62; 2911 2912 /* Save VFs number for reference in VF interrupts handlers. 2913 * Since interrupts might start arriving during SRIOV enablement 2914 * ordinary API cannot be used to get number of enabled VFs. 2915 */ 2916 rvu->vfs = vfs; 2917 2918 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2919 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2920 if (err) 2921 return err; 2922 2923 rvu_enable_afvf_intr(rvu); 2924 /* Make sure IRQs are enabled before SRIOV. */ 2925 mb(); 2926 2927 err = pci_enable_sriov(pdev, vfs); 2928 if (err) { 2929 rvu_disable_afvf_intr(rvu); 2930 rvu_mbox_destroy(&rvu->afvf_wq_info); 2931 return err; 2932 } 2933 2934 return 0; 2935 } 2936 2937 static void rvu_disable_sriov(struct rvu *rvu) 2938 { 2939 rvu_disable_afvf_intr(rvu); 2940 rvu_mbox_destroy(&rvu->afvf_wq_info); 2941 pci_disable_sriov(rvu->pdev); 2942 } 2943 2944 static void rvu_update_module_params(struct rvu *rvu) 2945 { 2946 const char *default_pfl_name = "default"; 2947 2948 strscpy(rvu->mkex_pfl_name, 2949 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 2950 strscpy(rvu->kpu_pfl_name, 2951 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 2952 } 2953 2954 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2955 { 2956 struct device *dev = &pdev->dev; 2957 struct rvu *rvu; 2958 int err; 2959 2960 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2961 if (!rvu) 2962 return -ENOMEM; 2963 2964 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2965 if (!rvu->hw) { 2966 devm_kfree(dev, rvu); 2967 return -ENOMEM; 2968 } 2969 2970 pci_set_drvdata(pdev, rvu); 2971 rvu->pdev = pdev; 2972 rvu->dev = &pdev->dev; 2973 2974 err = pci_enable_device(pdev); 2975 if (err) { 2976 dev_err(dev, "Failed to enable PCI device\n"); 2977 goto err_freemem; 2978 } 2979 2980 err = pci_request_regions(pdev, DRV_NAME); 2981 if (err) { 2982 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2983 goto err_disable_device; 2984 } 2985 2986 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2987 if (err) { 2988 dev_err(dev, "DMA mask config failed, abort\n"); 2989 goto err_release_regions; 2990 } 2991 2992 pci_set_master(pdev); 2993 2994 rvu->ptp = ptp_get(); 2995 if (IS_ERR(rvu->ptp)) { 2996 err = PTR_ERR(rvu->ptp); 2997 if (err == -EPROBE_DEFER) 2998 goto err_release_regions; 2999 rvu->ptp = NULL; 3000 } 3001 3002 /* Map Admin function CSRs */ 3003 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3004 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3005 if (!rvu->afreg_base || !rvu->pfreg_base) { 3006 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3007 err = -ENOMEM; 3008 goto err_put_ptp; 3009 } 3010 3011 /* Store module params in rvu structure */ 3012 rvu_update_module_params(rvu); 3013 3014 /* Check which blocks the HW supports */ 3015 rvu_check_block_implemented(rvu); 3016 3017 rvu_reset_all_blocks(rvu); 3018 3019 rvu_setup_hw_capabilities(rvu); 3020 3021 err = rvu_setup_hw_resources(rvu); 3022 if (err) 3023 goto err_put_ptp; 3024 3025 /* Init mailbox btw AF and PFs */ 3026 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3027 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3028 rvu_afpf_mbox_up_handler); 3029 if (err) { 3030 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3031 goto err_hwsetup; 3032 } 3033 3034 err = rvu_flr_init(rvu); 3035 if (err) { 3036 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3037 goto err_mbox; 3038 } 3039 3040 err = rvu_register_interrupts(rvu); 3041 if (err) { 3042 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3043 goto err_flr; 3044 } 3045 3046 err = rvu_register_dl(rvu); 3047 if (err) { 3048 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3049 goto err_irq; 3050 } 3051 3052 rvu_setup_rvum_blk_revid(rvu); 3053 3054 /* Enable AF's VFs (if any) */ 3055 err = rvu_enable_sriov(rvu); 3056 if (err) { 3057 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3058 goto err_dl; 3059 } 3060 3061 /* Initialize debugfs */ 3062 rvu_dbg_init(rvu); 3063 3064 mutex_init(&rvu->rswitch.switch_lock); 3065 3066 return 0; 3067 err_dl: 3068 rvu_unregister_dl(rvu); 3069 err_irq: 3070 rvu_unregister_interrupts(rvu); 3071 err_flr: 3072 rvu_flr_wq_destroy(rvu); 3073 err_mbox: 3074 rvu_mbox_destroy(&rvu->afpf_wq_info); 3075 err_hwsetup: 3076 rvu_cgx_exit(rvu); 3077 rvu_fwdata_exit(rvu); 3078 rvu_reset_all_blocks(rvu); 3079 rvu_free_hw_resources(rvu); 3080 rvu_clear_rvum_blk_revid(rvu); 3081 err_put_ptp: 3082 ptp_put(rvu->ptp); 3083 err_release_regions: 3084 pci_release_regions(pdev); 3085 err_disable_device: 3086 pci_disable_device(pdev); 3087 err_freemem: 3088 pci_set_drvdata(pdev, NULL); 3089 devm_kfree(&pdev->dev, rvu->hw); 3090 devm_kfree(dev, rvu); 3091 return err; 3092 } 3093 3094 static void rvu_remove(struct pci_dev *pdev) 3095 { 3096 struct rvu *rvu = pci_get_drvdata(pdev); 3097 3098 rvu_dbg_exit(rvu); 3099 rvu_unregister_dl(rvu); 3100 rvu_unregister_interrupts(rvu); 3101 rvu_flr_wq_destroy(rvu); 3102 rvu_cgx_exit(rvu); 3103 rvu_fwdata_exit(rvu); 3104 rvu_mbox_destroy(&rvu->afpf_wq_info); 3105 rvu_disable_sriov(rvu); 3106 rvu_reset_all_blocks(rvu); 3107 rvu_free_hw_resources(rvu); 3108 rvu_clear_rvum_blk_revid(rvu); 3109 ptp_put(rvu->ptp); 3110 pci_release_regions(pdev); 3111 pci_disable_device(pdev); 3112 pci_set_drvdata(pdev, NULL); 3113 3114 devm_kfree(&pdev->dev, rvu->hw); 3115 devm_kfree(&pdev->dev, rvu); 3116 } 3117 3118 static struct pci_driver rvu_driver = { 3119 .name = DRV_NAME, 3120 .id_table = rvu_id_table, 3121 .probe = rvu_probe, 3122 .remove = rvu_remove, 3123 }; 3124 3125 static int __init rvu_init_module(void) 3126 { 3127 int err; 3128 3129 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3130 3131 err = pci_register_driver(&cgx_driver); 3132 if (err < 0) 3133 return err; 3134 3135 err = pci_register_driver(&ptp_driver); 3136 if (err < 0) 3137 goto ptp_err; 3138 3139 err = pci_register_driver(&rvu_driver); 3140 if (err < 0) 3141 goto rvu_err; 3142 3143 return 0; 3144 rvu_err: 3145 pci_unregister_driver(&ptp_driver); 3146 ptp_err: 3147 pci_unregister_driver(&cgx_driver); 3148 3149 return err; 3150 } 3151 3152 static void __exit rvu_cleanup_module(void) 3153 { 3154 pci_unregister_driver(&rvu_driver); 3155 pci_unregister_driver(&ptp_driver); 3156 pci_unregister_driver(&cgx_driver); 3157 } 3158 3159 module_init(rvu_init_module); 3160 module_exit(rvu_cleanup_module); 3161