1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 #include "mcs.h" 20 21 #include "rvu_trace.h" 22 #include "rvu_npc_hash.h" 23 24 #define DRV_NAME "rvu_af" 25 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 26 27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 28 struct rvu_block *block, int lf); 29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 32 33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 34 int type, int num, 35 void (mbox_handler)(struct work_struct *), 36 void (mbox_up_handler)(struct work_struct *)); 37 enum { 38 TYPE_AFVF, 39 TYPE_AFPF, 40 }; 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->cap.npc_hash_extract = false; 72 hw->cap.npc_exact_match_enabled = false; 73 hw->rvu = rvu; 74 75 if (is_rvu_pre_96xx_C0(rvu)) { 76 hw->cap.nix_fixed_txschq_mapping = true; 77 hw->cap.nix_txsch_per_cgx_lmac = 4; 78 hw->cap.nix_txsch_per_lbk_lmac = 132; 79 hw->cap.nix_txsch_per_sdp_lmac = 76; 80 hw->cap.nix_shaping = false; 81 hw->cap.nix_tx_link_bp = false; 82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 83 hw->cap.nix_rx_multicast = false; 84 } 85 if (!is_rvu_pre_96xx_C0(rvu)) 86 hw->cap.nix_shaper_toggle_wait = true; 87 88 if (!is_rvu_otx2(rvu)) 89 hw->cap.per_pf_mbox_regs = true; 90 91 if (is_rvu_npc_hash_extract_en(rvu)) 92 hw->cap.npc_hash_extract = true; 93 } 94 95 /* Poll a RVU block's register 'offset', for a 'zero' 96 * or 'nonzero' at bits specified by 'mask' 97 */ 98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 99 { 100 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 101 bool twice = false; 102 void __iomem *reg; 103 u64 reg_val; 104 105 reg = rvu->afreg_base + ((block << 28) | offset); 106 again: 107 reg_val = readq(reg); 108 if (zero && !(reg_val & mask)) 109 return 0; 110 if (!zero && (reg_val & mask)) 111 return 0; 112 if (time_before(jiffies, timeout)) { 113 usleep_range(1, 5); 114 goto again; 115 } 116 /* In scenarios where CPU is scheduled out before checking 117 * 'time_before' (above) and gets scheduled in such that 118 * jiffies are beyond timeout value, then check again if HW is 119 * done with the operation in the meantime. 120 */ 121 if (!twice) { 122 twice = true; 123 goto again; 124 } 125 return -EBUSY; 126 } 127 128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 129 { 130 int id; 131 132 if (!rsrc->bmap) 133 return -EINVAL; 134 135 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 136 if (id >= rsrc->max) 137 return -ENOSPC; 138 139 __set_bit(id, rsrc->bmap); 140 141 return id; 142 } 143 144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 145 { 146 int start; 147 148 if (!rsrc->bmap) 149 return -EINVAL; 150 151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 152 if (start >= rsrc->max) 153 return -ENOSPC; 154 155 bitmap_set(rsrc->bmap, start, nrsrc); 156 return start; 157 } 158 159 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 160 { 161 if (!rsrc->bmap) 162 return; 163 if (start >= rsrc->max) 164 return; 165 166 bitmap_clear(rsrc->bmap, start, nrsrc); 167 } 168 169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 170 { 171 int start; 172 173 if (!rsrc->bmap) 174 return false; 175 176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 177 if (start >= rsrc->max) 178 return false; 179 180 return true; 181 } 182 183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 184 { 185 if (!rsrc->bmap) 186 return; 187 188 __clear_bit(id, rsrc->bmap); 189 } 190 191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 192 { 193 int used; 194 195 if (!rsrc->bmap) 196 return 0; 197 198 used = bitmap_weight(rsrc->bmap, rsrc->max); 199 return (rsrc->max - used); 200 } 201 202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 203 { 204 if (!rsrc->bmap) 205 return false; 206 207 return !test_bit(id, rsrc->bmap); 208 } 209 210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 211 { 212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 213 sizeof(long), GFP_KERNEL); 214 if (!rsrc->bmap) 215 return -ENOMEM; 216 return 0; 217 } 218 219 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 220 { 221 kfree(rsrc->bmap); 222 } 223 224 /* Get block LF's HW index from a PF_FUNC's block slot number */ 225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 226 { 227 u16 match = 0; 228 int lf; 229 230 mutex_lock(&rvu->rsrc_lock); 231 for (lf = 0; lf < block->lf.max; lf++) { 232 if (block->fn_map[lf] == pcifunc) { 233 if (slot == match) { 234 mutex_unlock(&rvu->rsrc_lock); 235 return lf; 236 } 237 match++; 238 } 239 } 240 mutex_unlock(&rvu->rsrc_lock); 241 return -ENODEV; 242 } 243 244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 245 * Some silicon variants of OcteonTX2 supports 246 * multiple blocks of same type. 247 * 248 * @pcifunc has to be zero when no LF is yet attached. 249 * 250 * For a pcifunc if LFs are attached from multiple blocks of same type, then 251 * return blkaddr of first encountered block. 252 */ 253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 254 { 255 int devnum, blkaddr = -ENODEV; 256 u64 cfg, reg; 257 bool is_pf; 258 259 switch (blktype) { 260 case BLKTYPE_NPC: 261 blkaddr = BLKADDR_NPC; 262 goto exit; 263 case BLKTYPE_NPA: 264 blkaddr = BLKADDR_NPA; 265 goto exit; 266 case BLKTYPE_NIX: 267 /* For now assume NIX0 */ 268 if (!pcifunc) { 269 blkaddr = BLKADDR_NIX0; 270 goto exit; 271 } 272 break; 273 case BLKTYPE_SSO: 274 blkaddr = BLKADDR_SSO; 275 goto exit; 276 case BLKTYPE_SSOW: 277 blkaddr = BLKADDR_SSOW; 278 goto exit; 279 case BLKTYPE_TIM: 280 blkaddr = BLKADDR_TIM; 281 goto exit; 282 case BLKTYPE_CPT: 283 /* For now assume CPT0 */ 284 if (!pcifunc) { 285 blkaddr = BLKADDR_CPT0; 286 goto exit; 287 } 288 break; 289 } 290 291 /* Check if this is a RVU PF or VF */ 292 if (pcifunc & RVU_PFVF_FUNC_MASK) { 293 is_pf = false; 294 devnum = rvu_get_hwvf(rvu, pcifunc); 295 } else { 296 is_pf = true; 297 devnum = rvu_get_pf(pcifunc); 298 } 299 300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 301 * 'BLKADDR_NIX1'. 302 */ 303 if (blktype == BLKTYPE_NIX) { 304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 305 RVU_PRIV_HWVFX_NIXX_CFG(0); 306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 307 if (cfg) { 308 blkaddr = BLKADDR_NIX0; 309 goto exit; 310 } 311 312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 313 RVU_PRIV_HWVFX_NIXX_CFG(1); 314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 315 if (cfg) 316 blkaddr = BLKADDR_NIX1; 317 } 318 319 if (blktype == BLKTYPE_CPT) { 320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 321 RVU_PRIV_HWVFX_CPTX_CFG(0); 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 323 if (cfg) { 324 blkaddr = BLKADDR_CPT0; 325 goto exit; 326 } 327 328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 329 RVU_PRIV_HWVFX_CPTX_CFG(1); 330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 331 if (cfg) 332 blkaddr = BLKADDR_CPT1; 333 } 334 335 exit: 336 if (is_block_implemented(rvu->hw, blkaddr)) 337 return blkaddr; 338 return -ENODEV; 339 } 340 341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 342 struct rvu_block *block, u16 pcifunc, 343 u16 lf, bool attach) 344 { 345 int devnum, num_lfs = 0; 346 bool is_pf; 347 u64 reg; 348 349 if (lf >= block->lf.max) { 350 dev_err(&rvu->pdev->dev, 351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 352 __func__, lf, block->name, block->lf.max); 353 return; 354 } 355 356 /* Check if this is for a RVU PF or VF */ 357 if (pcifunc & RVU_PFVF_FUNC_MASK) { 358 is_pf = false; 359 devnum = rvu_get_hwvf(rvu, pcifunc); 360 } else { 361 is_pf = true; 362 devnum = rvu_get_pf(pcifunc); 363 } 364 365 block->fn_map[lf] = attach ? pcifunc : 0; 366 367 switch (block->addr) { 368 case BLKADDR_NPA: 369 pfvf->npalf = attach ? true : false; 370 num_lfs = pfvf->npalf; 371 break; 372 case BLKADDR_NIX0: 373 case BLKADDR_NIX1: 374 pfvf->nixlf = attach ? true : false; 375 num_lfs = pfvf->nixlf; 376 break; 377 case BLKADDR_SSO: 378 attach ? pfvf->sso++ : pfvf->sso--; 379 num_lfs = pfvf->sso; 380 break; 381 case BLKADDR_SSOW: 382 attach ? pfvf->ssow++ : pfvf->ssow--; 383 num_lfs = pfvf->ssow; 384 break; 385 case BLKADDR_TIM: 386 attach ? pfvf->timlfs++ : pfvf->timlfs--; 387 num_lfs = pfvf->timlfs; 388 break; 389 case BLKADDR_CPT0: 390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 391 num_lfs = pfvf->cptlfs; 392 break; 393 case BLKADDR_CPT1: 394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 395 num_lfs = pfvf->cpt1_lfs; 396 break; 397 } 398 399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 401 } 402 403 inline int rvu_get_pf(u16 pcifunc) 404 { 405 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 406 } 407 408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 409 { 410 u64 cfg; 411 412 /* Get numVFs attached to this PF and first HWVF */ 413 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 414 if (numvfs) 415 *numvfs = (cfg >> 12) & 0xFF; 416 if (hwvf) 417 *hwvf = cfg & 0xFFF; 418 } 419 420 int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 421 { 422 int pf, func; 423 u64 cfg; 424 425 pf = rvu_get_pf(pcifunc); 426 func = pcifunc & RVU_PFVF_FUNC_MASK; 427 428 /* Get first HWVF attached to this PF */ 429 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 430 431 return ((cfg & 0xFFF) + func - 1); 432 } 433 434 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 435 { 436 /* Check if it is a PF or VF */ 437 if (pcifunc & RVU_PFVF_FUNC_MASK) 438 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 439 else 440 return &rvu->pf[rvu_get_pf(pcifunc)]; 441 } 442 443 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 444 { 445 int pf, vf, nvfs; 446 u64 cfg; 447 448 pf = rvu_get_pf(pcifunc); 449 if (pf >= rvu->hw->total_pfs) 450 return false; 451 452 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 453 return true; 454 455 /* Check if VF is within number of VFs attached to this PF */ 456 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 457 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 458 nvfs = (cfg >> 12) & 0xFF; 459 if (vf >= nvfs) 460 return false; 461 462 return true; 463 } 464 465 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 466 { 467 struct rvu_block *block; 468 469 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 470 return false; 471 472 block = &hw->block[blkaddr]; 473 return block->implemented; 474 } 475 476 static void rvu_check_block_implemented(struct rvu *rvu) 477 { 478 struct rvu_hwinfo *hw = rvu->hw; 479 struct rvu_block *block; 480 int blkid; 481 u64 cfg; 482 483 /* For each block check if 'implemented' bit is set */ 484 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 485 block = &hw->block[blkid]; 486 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 487 if (cfg & BIT_ULL(11)) 488 block->implemented = true; 489 } 490 } 491 492 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 493 { 494 rvu_write64(rvu, BLKADDR_RVUM, 495 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 496 RVU_BLK_RVUM_REVID); 497 } 498 499 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 500 { 501 rvu_write64(rvu, BLKADDR_RVUM, 502 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 503 } 504 505 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 506 { 507 int err; 508 509 if (!block->implemented) 510 return 0; 511 512 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 513 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 514 true); 515 return err; 516 } 517 518 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 519 { 520 struct rvu_block *block = &rvu->hw->block[blkaddr]; 521 int err; 522 523 if (!block->implemented) 524 return; 525 526 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 527 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 528 if (err) { 529 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); 530 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) 531 ; 532 } 533 } 534 535 static void rvu_reset_all_blocks(struct rvu *rvu) 536 { 537 /* Do a HW reset of all RVU blocks */ 538 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 539 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 543 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 544 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 545 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 546 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 547 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 548 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 549 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 550 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 551 } 552 553 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 554 { 555 struct rvu_pfvf *pfvf; 556 u64 cfg; 557 int lf; 558 559 for (lf = 0; lf < block->lf.max; lf++) { 560 cfg = rvu_read64(rvu, block->addr, 561 block->lfcfg_reg | (lf << block->lfshift)); 562 if (!(cfg & BIT_ULL(63))) 563 continue; 564 565 /* Set this resource as being used */ 566 __set_bit(lf, block->lf.bmap); 567 568 /* Get, to whom this LF is attached */ 569 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 570 rvu_update_rsrc_map(rvu, pfvf, block, 571 (cfg >> 8) & 0xFFFF, lf, true); 572 573 /* Set start MSIX vector for this LF within this PF/VF */ 574 rvu_set_msix_offset(rvu, pfvf, block, lf); 575 } 576 } 577 578 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 579 { 580 int min_vecs; 581 582 if (!vf) 583 goto check_pf; 584 585 if (!nvecs) { 586 dev_warn(rvu->dev, 587 "PF%d:VF%d is configured with zero msix vectors, %d\n", 588 pf, vf - 1, nvecs); 589 } 590 return; 591 592 check_pf: 593 if (pf == 0) 594 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 595 else 596 min_vecs = RVU_PF_INT_VEC_CNT; 597 598 if (!(nvecs < min_vecs)) 599 return; 600 dev_warn(rvu->dev, 601 "PF%d is configured with too few vectors, %d, min is %d\n", 602 pf, nvecs, min_vecs); 603 } 604 605 static int rvu_setup_msix_resources(struct rvu *rvu) 606 { 607 struct rvu_hwinfo *hw = rvu->hw; 608 int pf, vf, numvfs, hwvf, err; 609 int nvecs, offset, max_msix; 610 struct rvu_pfvf *pfvf; 611 u64 cfg, phy_addr; 612 dma_addr_t iova; 613 614 for (pf = 0; pf < hw->total_pfs; pf++) { 615 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 616 /* If PF is not enabled, nothing to do */ 617 if (!((cfg >> 20) & 0x01)) 618 continue; 619 620 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 621 622 pfvf = &rvu->pf[pf]; 623 /* Get num of MSIX vectors attached to this PF */ 624 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 625 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 626 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 627 628 /* Alloc msix bitmap for this PF */ 629 err = rvu_alloc_bitmap(&pfvf->msix); 630 if (err) 631 return err; 632 633 /* Allocate memory for MSIX vector to RVU block LF mapping */ 634 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 635 sizeof(u16), GFP_KERNEL); 636 if (!pfvf->msix_lfmap) 637 return -ENOMEM; 638 639 /* For PF0 (AF) firmware will set msix vector offsets for 640 * AF, block AF and PF0_INT vectors, so jump to VFs. 641 */ 642 if (!pf) 643 goto setup_vfmsix; 644 645 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 646 * These are allocated on driver init and never freed, 647 * so no need to set 'msix_lfmap' for these. 648 */ 649 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 650 nvecs = (cfg >> 12) & 0xFF; 651 cfg &= ~0x7FFULL; 652 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 653 rvu_write64(rvu, BLKADDR_RVUM, 654 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 655 setup_vfmsix: 656 /* Alloc msix bitmap for VFs */ 657 for (vf = 0; vf < numvfs; vf++) { 658 pfvf = &rvu->hwvf[hwvf + vf]; 659 /* Get num of MSIX vectors attached to this VF */ 660 cfg = rvu_read64(rvu, BLKADDR_RVUM, 661 RVU_PRIV_PFX_MSIX_CFG(pf)); 662 pfvf->msix.max = (cfg & 0xFFF) + 1; 663 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 664 665 /* Alloc msix bitmap for this VF */ 666 err = rvu_alloc_bitmap(&pfvf->msix); 667 if (err) 668 return err; 669 670 pfvf->msix_lfmap = 671 devm_kcalloc(rvu->dev, pfvf->msix.max, 672 sizeof(u16), GFP_KERNEL); 673 if (!pfvf->msix_lfmap) 674 return -ENOMEM; 675 676 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 677 * These are allocated on driver init and never freed, 678 * so no need to set 'msix_lfmap' for these. 679 */ 680 cfg = rvu_read64(rvu, BLKADDR_RVUM, 681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 682 nvecs = (cfg >> 12) & 0xFF; 683 cfg &= ~0x7FFULL; 684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 685 rvu_write64(rvu, BLKADDR_RVUM, 686 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 687 cfg | offset); 688 } 689 } 690 691 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 692 * create an IOMMU mapping for the physical address configured by 693 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 694 */ 695 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 696 max_msix = cfg & 0xFFFFF; 697 if (rvu->fwdata && rvu->fwdata->msixtr_base) 698 phy_addr = rvu->fwdata->msixtr_base; 699 else 700 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 701 702 iova = dma_map_resource(rvu->dev, phy_addr, 703 max_msix * PCI_MSIX_ENTRY_SIZE, 704 DMA_BIDIRECTIONAL, 0); 705 706 if (dma_mapping_error(rvu->dev, iova)) 707 return -ENOMEM; 708 709 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 710 rvu->msix_base_iova = iova; 711 rvu->msixtr_base_phy = phy_addr; 712 713 return 0; 714 } 715 716 static void rvu_reset_msix(struct rvu *rvu) 717 { 718 /* Restore msixtr base register */ 719 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 720 rvu->msixtr_base_phy); 721 } 722 723 static void rvu_free_hw_resources(struct rvu *rvu) 724 { 725 struct rvu_hwinfo *hw = rvu->hw; 726 struct rvu_block *block; 727 struct rvu_pfvf *pfvf; 728 int id, max_msix; 729 u64 cfg; 730 731 rvu_npa_freemem(rvu); 732 rvu_npc_freemem(rvu); 733 rvu_nix_freemem(rvu); 734 735 /* Free block LF bitmaps */ 736 for (id = 0; id < BLK_COUNT; id++) { 737 block = &hw->block[id]; 738 kfree(block->lf.bmap); 739 } 740 741 /* Free MSIX bitmaps */ 742 for (id = 0; id < hw->total_pfs; id++) { 743 pfvf = &rvu->pf[id]; 744 kfree(pfvf->msix.bmap); 745 } 746 747 for (id = 0; id < hw->total_vfs; id++) { 748 pfvf = &rvu->hwvf[id]; 749 kfree(pfvf->msix.bmap); 750 } 751 752 /* Unmap MSIX vector base IOVA mapping */ 753 if (!rvu->msix_base_iova) 754 return; 755 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 756 max_msix = cfg & 0xFFFFF; 757 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 758 max_msix * PCI_MSIX_ENTRY_SIZE, 759 DMA_BIDIRECTIONAL, 0); 760 761 rvu_reset_msix(rvu); 762 mutex_destroy(&rvu->rsrc_lock); 763 } 764 765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 766 { 767 struct rvu_hwinfo *hw = rvu->hw; 768 int pf, vf, numvfs, hwvf; 769 struct rvu_pfvf *pfvf; 770 u64 *mac; 771 772 for (pf = 0; pf < hw->total_pfs; pf++) { 773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 774 if (!pf) 775 goto lbkvf; 776 777 if (!is_pf_cgxmapped(rvu, pf)) 778 continue; 779 /* Assign MAC address to PF */ 780 pfvf = &rvu->pf[pf]; 781 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 782 mac = &rvu->fwdata->pf_macs[pf]; 783 if (*mac) 784 u64_to_ether_addr(*mac, pfvf->mac_addr); 785 else 786 eth_random_addr(pfvf->mac_addr); 787 } else { 788 eth_random_addr(pfvf->mac_addr); 789 } 790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 791 792 lbkvf: 793 /* Assign MAC address to VFs*/ 794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 795 for (vf = 0; vf < numvfs; vf++, hwvf++) { 796 pfvf = &rvu->hwvf[hwvf]; 797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 798 mac = &rvu->fwdata->vf_macs[hwvf]; 799 if (*mac) 800 u64_to_ether_addr(*mac, pfvf->mac_addr); 801 else 802 eth_random_addr(pfvf->mac_addr); 803 } else { 804 eth_random_addr(pfvf->mac_addr); 805 } 806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 807 } 808 } 809 } 810 811 static int rvu_fwdata_init(struct rvu *rvu) 812 { 813 u64 fwdbase; 814 int err; 815 816 /* Get firmware data base address */ 817 err = cgx_get_fwdata_base(&fwdbase); 818 if (err) 819 goto fail; 820 821 BUILD_BUG_ON(offsetof(struct rvu_fwdata, cgx_fw_data) > FWDATA_CGX_LMAC_OFFSET); 822 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 823 if (!rvu->fwdata) 824 goto fail; 825 if (!is_rvu_fwdata_valid(rvu)) { 826 dev_err(rvu->dev, 827 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 828 iounmap(rvu->fwdata); 829 rvu->fwdata = NULL; 830 return -EINVAL; 831 } 832 return 0; 833 fail: 834 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 835 return -EIO; 836 } 837 838 static void rvu_fwdata_exit(struct rvu *rvu) 839 { 840 if (rvu->fwdata) 841 iounmap(rvu->fwdata); 842 } 843 844 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 845 { 846 struct rvu_hwinfo *hw = rvu->hw; 847 struct rvu_block *block; 848 int blkid; 849 u64 cfg; 850 851 /* Init NIX LF's bitmap */ 852 block = &hw->block[blkaddr]; 853 if (!block->implemented) 854 return 0; 855 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 856 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 857 block->lf.max = cfg & 0xFFF; 858 block->addr = blkaddr; 859 block->type = BLKTYPE_NIX; 860 block->lfshift = 8; 861 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 862 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 863 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 864 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 865 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 866 block->lfreset_reg = NIX_AF_LF_RST; 867 block->rvu = rvu; 868 sprintf(block->name, "NIX%d", blkid); 869 rvu->nix_blkaddr[blkid] = blkaddr; 870 return rvu_alloc_bitmap(&block->lf); 871 } 872 873 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 874 { 875 struct rvu_hwinfo *hw = rvu->hw; 876 struct rvu_block *block; 877 int blkid; 878 u64 cfg; 879 880 /* Init CPT LF's bitmap */ 881 block = &hw->block[blkaddr]; 882 if (!block->implemented) 883 return 0; 884 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 885 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 886 block->lf.max = cfg & 0xFF; 887 block->addr = blkaddr; 888 block->type = BLKTYPE_CPT; 889 block->multislot = true; 890 block->lfshift = 3; 891 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 892 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 893 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 894 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 895 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 896 block->lfreset_reg = CPT_AF_LF_RST; 897 block->rvu = rvu; 898 sprintf(block->name, "CPT%d", blkid); 899 return rvu_alloc_bitmap(&block->lf); 900 } 901 902 static void rvu_get_lbk_bufsize(struct rvu *rvu) 903 { 904 struct pci_dev *pdev = NULL; 905 void __iomem *base; 906 u64 lbk_const; 907 908 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 909 PCI_DEVID_OCTEONTX2_LBK, pdev); 910 if (!pdev) 911 return; 912 913 base = pci_ioremap_bar(pdev, 0); 914 if (!base) 915 goto err_put; 916 917 lbk_const = readq(base + LBK_CONST); 918 919 /* cache fifo size */ 920 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 921 922 iounmap(base); 923 err_put: 924 pci_dev_put(pdev); 925 } 926 927 static int rvu_setup_hw_resources(struct rvu *rvu) 928 { 929 struct rvu_hwinfo *hw = rvu->hw; 930 struct rvu_block *block; 931 int blkid, err; 932 u64 cfg; 933 934 /* Get HW supported max RVU PF & VF count */ 935 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 936 hw->total_pfs = (cfg >> 32) & 0xFF; 937 hw->total_vfs = (cfg >> 20) & 0xFFF; 938 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 939 940 if (!is_rvu_otx2(rvu)) 941 rvu_apr_block_cn10k_init(rvu); 942 943 /* Init NPA LF's bitmap */ 944 block = &hw->block[BLKADDR_NPA]; 945 if (!block->implemented) 946 goto nix; 947 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 948 block->lf.max = (cfg >> 16) & 0xFFF; 949 block->addr = BLKADDR_NPA; 950 block->type = BLKTYPE_NPA; 951 block->lfshift = 8; 952 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 953 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 954 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 955 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 956 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 957 block->lfreset_reg = NPA_AF_LF_RST; 958 block->rvu = rvu; 959 sprintf(block->name, "NPA"); 960 err = rvu_alloc_bitmap(&block->lf); 961 if (err) { 962 dev_err(rvu->dev, 963 "%s: Failed to allocate NPA LF bitmap\n", __func__); 964 return err; 965 } 966 967 nix: 968 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 969 if (err) { 970 dev_err(rvu->dev, 971 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 972 return err; 973 } 974 975 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 976 if (err) { 977 dev_err(rvu->dev, 978 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 979 return err; 980 } 981 982 /* Init SSO group's bitmap */ 983 block = &hw->block[BLKADDR_SSO]; 984 if (!block->implemented) 985 goto ssow; 986 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 987 block->lf.max = cfg & 0xFFFF; 988 block->addr = BLKADDR_SSO; 989 block->type = BLKTYPE_SSO; 990 block->multislot = true; 991 block->lfshift = 3; 992 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 993 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 994 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 995 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 996 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 997 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 998 block->rvu = rvu; 999 sprintf(block->name, "SSO GROUP"); 1000 err = rvu_alloc_bitmap(&block->lf); 1001 if (err) { 1002 dev_err(rvu->dev, 1003 "%s: Failed to allocate SSO LF bitmap\n", __func__); 1004 return err; 1005 } 1006 1007 ssow: 1008 /* Init SSO workslot's bitmap */ 1009 block = &hw->block[BLKADDR_SSOW]; 1010 if (!block->implemented) 1011 goto tim; 1012 block->lf.max = (cfg >> 56) & 0xFF; 1013 block->addr = BLKADDR_SSOW; 1014 block->type = BLKTYPE_SSOW; 1015 block->multislot = true; 1016 block->lfshift = 3; 1017 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1018 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1019 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1020 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1021 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1022 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1023 block->rvu = rvu; 1024 sprintf(block->name, "SSOWS"); 1025 err = rvu_alloc_bitmap(&block->lf); 1026 if (err) { 1027 dev_err(rvu->dev, 1028 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1029 return err; 1030 } 1031 1032 tim: 1033 /* Init TIM LF's bitmap */ 1034 block = &hw->block[BLKADDR_TIM]; 1035 if (!block->implemented) 1036 goto cpt; 1037 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1038 block->lf.max = cfg & 0xFFFF; 1039 block->addr = BLKADDR_TIM; 1040 block->type = BLKTYPE_TIM; 1041 block->multislot = true; 1042 block->lfshift = 3; 1043 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1044 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1045 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1046 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1047 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1048 block->lfreset_reg = TIM_AF_LF_RST; 1049 block->rvu = rvu; 1050 sprintf(block->name, "TIM"); 1051 err = rvu_alloc_bitmap(&block->lf); 1052 if (err) { 1053 dev_err(rvu->dev, 1054 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1055 return err; 1056 } 1057 1058 cpt: 1059 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1060 if (err) { 1061 dev_err(rvu->dev, 1062 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1063 return err; 1064 } 1065 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1066 if (err) { 1067 dev_err(rvu->dev, 1068 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1069 return err; 1070 } 1071 1072 /* Allocate memory for PFVF data */ 1073 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1074 sizeof(struct rvu_pfvf), GFP_KERNEL); 1075 if (!rvu->pf) { 1076 dev_err(rvu->dev, 1077 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1078 return -ENOMEM; 1079 } 1080 1081 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1082 sizeof(struct rvu_pfvf), GFP_KERNEL); 1083 if (!rvu->hwvf) { 1084 dev_err(rvu->dev, 1085 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1086 return -ENOMEM; 1087 } 1088 1089 mutex_init(&rvu->rsrc_lock); 1090 1091 rvu_fwdata_init(rvu); 1092 1093 err = rvu_setup_msix_resources(rvu); 1094 if (err) { 1095 dev_err(rvu->dev, 1096 "%s: Failed to setup MSIX resources\n", __func__); 1097 return err; 1098 } 1099 1100 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1101 block = &hw->block[blkid]; 1102 if (!block->lf.bmap) 1103 continue; 1104 1105 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1106 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1107 sizeof(u16), GFP_KERNEL); 1108 if (!block->fn_map) { 1109 err = -ENOMEM; 1110 goto msix_err; 1111 } 1112 1113 /* Scan all blocks to check if low level firmware has 1114 * already provisioned any of the resources to a PF/VF. 1115 */ 1116 rvu_scan_block(rvu, block); 1117 } 1118 1119 err = rvu_set_channels_base(rvu); 1120 if (err) 1121 goto msix_err; 1122 1123 err = rvu_npc_init(rvu); 1124 if (err) { 1125 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1126 goto npc_err; 1127 } 1128 1129 err = rvu_cgx_init(rvu); 1130 if (err) { 1131 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1132 goto cgx_err; 1133 } 1134 1135 err = rvu_npc_exact_init(rvu); 1136 if (err) { 1137 dev_err(rvu->dev, "failed to initialize exact match table\n"); 1138 return err; 1139 } 1140 1141 /* Assign MACs for CGX mapped functions */ 1142 rvu_setup_pfvf_macaddress(rvu); 1143 1144 err = rvu_npa_init(rvu); 1145 if (err) { 1146 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1147 goto npa_err; 1148 } 1149 1150 rvu_get_lbk_bufsize(rvu); 1151 1152 err = rvu_nix_init(rvu); 1153 if (err) { 1154 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1155 goto nix_err; 1156 } 1157 1158 err = rvu_sdp_init(rvu); 1159 if (err) { 1160 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1161 goto nix_err; 1162 } 1163 1164 rvu_program_channels(rvu); 1165 cgx_start_linkup(rvu); 1166 1167 err = rvu_mcs_init(rvu); 1168 if (err) { 1169 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); 1170 goto nix_err; 1171 } 1172 1173 err = rvu_cpt_init(rvu); 1174 if (err) { 1175 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__); 1176 goto mcs_err; 1177 } 1178 1179 return 0; 1180 1181 mcs_err: 1182 rvu_mcs_exit(rvu); 1183 nix_err: 1184 rvu_nix_freemem(rvu); 1185 npa_err: 1186 rvu_npa_freemem(rvu); 1187 cgx_err: 1188 rvu_cgx_exit(rvu); 1189 npc_err: 1190 rvu_npc_freemem(rvu); 1191 rvu_fwdata_exit(rvu); 1192 msix_err: 1193 rvu_reset_msix(rvu); 1194 return err; 1195 } 1196 1197 /* NPA and NIX admin queue APIs */ 1198 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1199 { 1200 if (!aq) 1201 return; 1202 1203 qmem_free(rvu->dev, aq->inst); 1204 qmem_free(rvu->dev, aq->res); 1205 devm_kfree(rvu->dev, aq); 1206 } 1207 1208 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1209 int qsize, int inst_size, int res_size) 1210 { 1211 struct admin_queue *aq; 1212 int err; 1213 1214 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1215 if (!*ad_queue) 1216 return -ENOMEM; 1217 aq = *ad_queue; 1218 1219 /* Alloc memory for instructions i.e AQ */ 1220 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1221 if (err) { 1222 devm_kfree(rvu->dev, aq); 1223 return err; 1224 } 1225 1226 /* Alloc memory for results */ 1227 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1228 if (err) { 1229 rvu_aq_free(rvu, aq); 1230 return err; 1231 } 1232 1233 spin_lock_init(&aq->lock); 1234 return 0; 1235 } 1236 1237 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1238 struct ready_msg_rsp *rsp) 1239 { 1240 if (rvu->fwdata) { 1241 rsp->rclk_freq = rvu->fwdata->rclk; 1242 rsp->sclk_freq = rvu->fwdata->sclk; 1243 } 1244 return 0; 1245 } 1246 1247 /* Get current count of a RVU block's LF/slots 1248 * provisioned to a given RVU func. 1249 */ 1250 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1251 { 1252 switch (blkaddr) { 1253 case BLKADDR_NPA: 1254 return pfvf->npalf ? 1 : 0; 1255 case BLKADDR_NIX0: 1256 case BLKADDR_NIX1: 1257 return pfvf->nixlf ? 1 : 0; 1258 case BLKADDR_SSO: 1259 return pfvf->sso; 1260 case BLKADDR_SSOW: 1261 return pfvf->ssow; 1262 case BLKADDR_TIM: 1263 return pfvf->timlfs; 1264 case BLKADDR_CPT0: 1265 return pfvf->cptlfs; 1266 case BLKADDR_CPT1: 1267 return pfvf->cpt1_lfs; 1268 } 1269 return 0; 1270 } 1271 1272 /* Return true if LFs of block type are attached to pcifunc */ 1273 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1274 { 1275 switch (blktype) { 1276 case BLKTYPE_NPA: 1277 return pfvf->npalf ? 1 : 0; 1278 case BLKTYPE_NIX: 1279 return pfvf->nixlf ? 1 : 0; 1280 case BLKTYPE_SSO: 1281 return !!pfvf->sso; 1282 case BLKTYPE_SSOW: 1283 return !!pfvf->ssow; 1284 case BLKTYPE_TIM: 1285 return !!pfvf->timlfs; 1286 case BLKTYPE_CPT: 1287 return pfvf->cptlfs || pfvf->cpt1_lfs; 1288 } 1289 1290 return false; 1291 } 1292 1293 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1294 { 1295 struct rvu_pfvf *pfvf; 1296 1297 if (!is_pf_func_valid(rvu, pcifunc)) 1298 return false; 1299 1300 pfvf = rvu_get_pfvf(rvu, pcifunc); 1301 1302 /* Check if this PFFUNC has a LF of type blktype attached */ 1303 if (!is_blktype_attached(pfvf, blktype)) 1304 return false; 1305 1306 return true; 1307 } 1308 1309 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1310 int pcifunc, int slot) 1311 { 1312 u64 val; 1313 1314 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1315 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1316 /* Wait for the lookup to finish */ 1317 /* TODO: put some timeout here */ 1318 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1319 ; 1320 1321 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1322 1323 /* Check LF valid bit */ 1324 if (!(val & (1ULL << 12))) 1325 return -1; 1326 1327 return (val & 0xFFF); 1328 } 1329 1330 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1331 u16 global_slot, u16 *slot_in_block) 1332 { 1333 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1334 int numlfs, total_lfs = 0, nr_blocks = 0; 1335 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1336 struct rvu_block *block; 1337 int blkaddr; 1338 u16 start_slot; 1339 1340 if (!is_blktype_attached(pfvf, blktype)) 1341 return -ENODEV; 1342 1343 /* Get all the block addresses from which LFs are attached to 1344 * the given pcifunc in num_blkaddr[]. 1345 */ 1346 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1347 block = &rvu->hw->block[blkaddr]; 1348 if (block->type != blktype) 1349 continue; 1350 if (!is_block_implemented(rvu->hw, blkaddr)) 1351 continue; 1352 1353 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1354 if (numlfs) { 1355 total_lfs += numlfs; 1356 num_blkaddr[nr_blocks] = blkaddr; 1357 nr_blocks++; 1358 } 1359 } 1360 1361 if (global_slot >= total_lfs) 1362 return -ENODEV; 1363 1364 /* Based on the given global slot number retrieve the 1365 * correct block address out of all attached block 1366 * addresses and slot number in that block. 1367 */ 1368 total_lfs = 0; 1369 blkaddr = -ENODEV; 1370 for (i = 0; i < nr_blocks; i++) { 1371 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1372 total_lfs += numlfs; 1373 if (global_slot < total_lfs) { 1374 blkaddr = num_blkaddr[i]; 1375 start_slot = total_lfs - numlfs; 1376 *slot_in_block = global_slot - start_slot; 1377 break; 1378 } 1379 } 1380 1381 return blkaddr; 1382 } 1383 1384 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1385 { 1386 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1387 struct rvu_hwinfo *hw = rvu->hw; 1388 struct rvu_block *block; 1389 int slot, lf, num_lfs; 1390 int blkaddr; 1391 1392 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1393 if (blkaddr < 0) 1394 return; 1395 1396 if (blktype == BLKTYPE_NIX) 1397 rvu_nix_reset_mac(pfvf, pcifunc); 1398 1399 block = &hw->block[blkaddr]; 1400 1401 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1402 if (!num_lfs) 1403 return; 1404 1405 for (slot = 0; slot < num_lfs; slot++) { 1406 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1407 if (lf < 0) /* This should never happen */ 1408 continue; 1409 1410 /* Disable the LF */ 1411 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1412 (lf << block->lfshift), 0x00ULL); 1413 1414 /* Update SW maintained mapping info as well */ 1415 rvu_update_rsrc_map(rvu, pfvf, block, 1416 pcifunc, lf, false); 1417 1418 /* Free the resource */ 1419 rvu_free_rsrc(&block->lf, lf); 1420 1421 /* Clear MSIX vector offset for this LF */ 1422 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1423 } 1424 } 1425 1426 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1427 u16 pcifunc) 1428 { 1429 struct rvu_hwinfo *hw = rvu->hw; 1430 bool detach_all = true; 1431 struct rvu_block *block; 1432 int blkid; 1433 1434 mutex_lock(&rvu->rsrc_lock); 1435 1436 /* Check for partial resource detach */ 1437 if (detach && detach->partial) 1438 detach_all = false; 1439 1440 /* Check for RVU block's LFs attached to this func, 1441 * if so, detach them. 1442 */ 1443 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1444 block = &hw->block[blkid]; 1445 if (!block->lf.bmap) 1446 continue; 1447 if (!detach_all && detach) { 1448 if (blkid == BLKADDR_NPA && !detach->npalf) 1449 continue; 1450 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1451 continue; 1452 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1453 continue; 1454 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1455 continue; 1456 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1457 continue; 1458 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1459 continue; 1460 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1461 continue; 1462 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1463 continue; 1464 } 1465 rvu_detach_block(rvu, pcifunc, block->type); 1466 } 1467 1468 mutex_unlock(&rvu->rsrc_lock); 1469 return 0; 1470 } 1471 1472 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1473 struct rsrc_detach *detach, 1474 struct msg_rsp *rsp) 1475 { 1476 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1477 } 1478 1479 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1480 { 1481 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1482 int blkaddr = BLKADDR_NIX0, vf; 1483 struct rvu_pfvf *pf; 1484 1485 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1486 1487 /* All CGX mapped PFs are set with assigned NIX block during init */ 1488 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1489 blkaddr = pf->nix_blkaddr; 1490 } else if (is_lbk_vf(rvu, pcifunc)) { 1491 vf = pcifunc - 1; 1492 /* Assign NIX based on VF number. All even numbered VFs get 1493 * NIX0 and odd numbered gets NIX1 1494 */ 1495 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1496 /* NIX1 is not present on all silicons */ 1497 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1498 blkaddr = BLKADDR_NIX0; 1499 } 1500 1501 /* if SDP1 then the blkaddr is NIX1 */ 1502 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1503 blkaddr = BLKADDR_NIX1; 1504 1505 switch (blkaddr) { 1506 case BLKADDR_NIX1: 1507 pfvf->nix_blkaddr = BLKADDR_NIX1; 1508 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1509 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1510 break; 1511 case BLKADDR_NIX0: 1512 default: 1513 pfvf->nix_blkaddr = BLKADDR_NIX0; 1514 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1515 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1516 break; 1517 } 1518 1519 return pfvf->nix_blkaddr; 1520 } 1521 1522 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1523 u16 pcifunc, struct rsrc_attach *attach) 1524 { 1525 int blkaddr; 1526 1527 switch (blktype) { 1528 case BLKTYPE_NIX: 1529 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1530 break; 1531 case BLKTYPE_CPT: 1532 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1533 return rvu_get_blkaddr(rvu, blktype, 0); 1534 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1535 BLKADDR_CPT0; 1536 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1537 return -ENODEV; 1538 break; 1539 default: 1540 return rvu_get_blkaddr(rvu, blktype, 0); 1541 } 1542 1543 if (is_block_implemented(rvu->hw, blkaddr)) 1544 return blkaddr; 1545 1546 return -ENODEV; 1547 } 1548 1549 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1550 int num_lfs, struct rsrc_attach *attach) 1551 { 1552 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1553 struct rvu_hwinfo *hw = rvu->hw; 1554 struct rvu_block *block; 1555 int slot, lf; 1556 int blkaddr; 1557 u64 cfg; 1558 1559 if (!num_lfs) 1560 return; 1561 1562 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1563 if (blkaddr < 0) 1564 return; 1565 1566 block = &hw->block[blkaddr]; 1567 if (!block->lf.bmap) 1568 return; 1569 1570 for (slot = 0; slot < num_lfs; slot++) { 1571 /* Allocate the resource */ 1572 lf = rvu_alloc_rsrc(&block->lf); 1573 if (lf < 0) 1574 return; 1575 1576 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1577 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1578 (lf << block->lfshift), cfg); 1579 rvu_update_rsrc_map(rvu, pfvf, block, 1580 pcifunc, lf, true); 1581 1582 /* Set start MSIX vector for this LF within this PF/VF */ 1583 rvu_set_msix_offset(rvu, pfvf, block, lf); 1584 } 1585 } 1586 1587 static int rvu_check_rsrc_availability(struct rvu *rvu, 1588 struct rsrc_attach *req, u16 pcifunc) 1589 { 1590 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1591 int free_lfs, mappedlfs, blkaddr; 1592 struct rvu_hwinfo *hw = rvu->hw; 1593 struct rvu_block *block; 1594 1595 /* Only one NPA LF can be attached */ 1596 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1597 block = &hw->block[BLKADDR_NPA]; 1598 free_lfs = rvu_rsrc_free_count(&block->lf); 1599 if (!free_lfs) 1600 goto fail; 1601 } else if (req->npalf) { 1602 dev_err(&rvu->pdev->dev, 1603 "Func 0x%x: Invalid req, already has NPA\n", 1604 pcifunc); 1605 return -EINVAL; 1606 } 1607 1608 /* Only one NIX LF can be attached */ 1609 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1610 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1611 pcifunc, req); 1612 if (blkaddr < 0) 1613 return blkaddr; 1614 block = &hw->block[blkaddr]; 1615 free_lfs = rvu_rsrc_free_count(&block->lf); 1616 if (!free_lfs) 1617 goto fail; 1618 } else if (req->nixlf) { 1619 dev_err(&rvu->pdev->dev, 1620 "Func 0x%x: Invalid req, already has NIX\n", 1621 pcifunc); 1622 return -EINVAL; 1623 } 1624 1625 if (req->sso) { 1626 block = &hw->block[BLKADDR_SSO]; 1627 /* Is request within limits ? */ 1628 if (req->sso > block->lf.max) { 1629 dev_err(&rvu->pdev->dev, 1630 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1631 pcifunc, req->sso, block->lf.max); 1632 return -EINVAL; 1633 } 1634 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1635 free_lfs = rvu_rsrc_free_count(&block->lf); 1636 /* Check if additional resources are available */ 1637 if (req->sso > mappedlfs && 1638 ((req->sso - mappedlfs) > free_lfs)) 1639 goto fail; 1640 } 1641 1642 if (req->ssow) { 1643 block = &hw->block[BLKADDR_SSOW]; 1644 if (req->ssow > block->lf.max) { 1645 dev_err(&rvu->pdev->dev, 1646 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1647 pcifunc, req->ssow, block->lf.max); 1648 return -EINVAL; 1649 } 1650 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1651 free_lfs = rvu_rsrc_free_count(&block->lf); 1652 if (req->ssow > mappedlfs && 1653 ((req->ssow - mappedlfs) > free_lfs)) 1654 goto fail; 1655 } 1656 1657 if (req->timlfs) { 1658 block = &hw->block[BLKADDR_TIM]; 1659 if (req->timlfs > block->lf.max) { 1660 dev_err(&rvu->pdev->dev, 1661 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1662 pcifunc, req->timlfs, block->lf.max); 1663 return -EINVAL; 1664 } 1665 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1666 free_lfs = rvu_rsrc_free_count(&block->lf); 1667 if (req->timlfs > mappedlfs && 1668 ((req->timlfs - mappedlfs) > free_lfs)) 1669 goto fail; 1670 } 1671 1672 if (req->cptlfs) { 1673 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1674 pcifunc, req); 1675 if (blkaddr < 0) 1676 return blkaddr; 1677 block = &hw->block[blkaddr]; 1678 if (req->cptlfs > block->lf.max) { 1679 dev_err(&rvu->pdev->dev, 1680 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1681 pcifunc, req->cptlfs, block->lf.max); 1682 return -EINVAL; 1683 } 1684 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1685 free_lfs = rvu_rsrc_free_count(&block->lf); 1686 if (req->cptlfs > mappedlfs && 1687 ((req->cptlfs - mappedlfs) > free_lfs)) 1688 goto fail; 1689 } 1690 1691 return 0; 1692 1693 fail: 1694 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1695 return -ENOSPC; 1696 } 1697 1698 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1699 struct rsrc_attach *attach) 1700 { 1701 int blkaddr, num_lfs; 1702 1703 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1704 attach->hdr.pcifunc, attach); 1705 if (blkaddr < 0) 1706 return false; 1707 1708 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1709 blkaddr); 1710 /* Requester already has LFs from given block ? */ 1711 return !!num_lfs; 1712 } 1713 1714 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1715 struct rsrc_attach *attach, 1716 struct msg_rsp *rsp) 1717 { 1718 u16 pcifunc = attach->hdr.pcifunc; 1719 int err; 1720 1721 /* If first request, detach all existing attached resources */ 1722 if (!attach->modify) 1723 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1724 1725 mutex_lock(&rvu->rsrc_lock); 1726 1727 /* Check if the request can be accommodated */ 1728 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1729 if (err) 1730 goto exit; 1731 1732 /* Now attach the requested resources */ 1733 if (attach->npalf) 1734 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1735 1736 if (attach->nixlf) 1737 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1738 1739 if (attach->sso) { 1740 /* RVU func doesn't know which exact LF or slot is attached 1741 * to it, it always sees as slot 0,1,2. So for a 'modify' 1742 * request, simply detach all existing attached LFs/slots 1743 * and attach a fresh. 1744 */ 1745 if (attach->modify) 1746 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1747 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1748 attach->sso, attach); 1749 } 1750 1751 if (attach->ssow) { 1752 if (attach->modify) 1753 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1754 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1755 attach->ssow, attach); 1756 } 1757 1758 if (attach->timlfs) { 1759 if (attach->modify) 1760 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1761 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1762 attach->timlfs, attach); 1763 } 1764 1765 if (attach->cptlfs) { 1766 if (attach->modify && 1767 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1768 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1769 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1770 attach->cptlfs, attach); 1771 } 1772 1773 exit: 1774 mutex_unlock(&rvu->rsrc_lock); 1775 return err; 1776 } 1777 1778 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1779 int blkaddr, int lf) 1780 { 1781 u16 vec; 1782 1783 if (lf < 0) 1784 return MSIX_VECTOR_INVALID; 1785 1786 for (vec = 0; vec < pfvf->msix.max; vec++) { 1787 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1788 return vec; 1789 } 1790 return MSIX_VECTOR_INVALID; 1791 } 1792 1793 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1794 struct rvu_block *block, int lf) 1795 { 1796 u16 nvecs, vec, offset; 1797 u64 cfg; 1798 1799 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1800 (lf << block->lfshift)); 1801 nvecs = (cfg >> 12) & 0xFF; 1802 1803 /* Check and alloc MSIX vectors, must be contiguous */ 1804 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1805 return; 1806 1807 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1808 1809 /* Config MSIX offset in LF */ 1810 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1811 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1812 1813 /* Update the bitmap as well */ 1814 for (vec = 0; vec < nvecs; vec++) 1815 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1816 } 1817 1818 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1819 struct rvu_block *block, int lf) 1820 { 1821 u16 nvecs, vec, offset; 1822 u64 cfg; 1823 1824 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1825 (lf << block->lfshift)); 1826 nvecs = (cfg >> 12) & 0xFF; 1827 1828 /* Clear MSIX offset in LF */ 1829 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1830 (lf << block->lfshift), cfg & ~0x7FFULL); 1831 1832 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1833 1834 /* Update the mapping */ 1835 for (vec = 0; vec < nvecs; vec++) 1836 pfvf->msix_lfmap[offset + vec] = 0; 1837 1838 /* Free the same in MSIX bitmap */ 1839 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1840 } 1841 1842 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1843 struct msix_offset_rsp *rsp) 1844 { 1845 struct rvu_hwinfo *hw = rvu->hw; 1846 u16 pcifunc = req->hdr.pcifunc; 1847 struct rvu_pfvf *pfvf; 1848 int lf, slot, blkaddr; 1849 1850 pfvf = rvu_get_pfvf(rvu, pcifunc); 1851 if (!pfvf->msix.bmap) 1852 return 0; 1853 1854 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1855 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1856 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1857 1858 /* Get BLKADDR from which LFs are attached to pcifunc */ 1859 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1860 if (blkaddr < 0) { 1861 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1862 } else { 1863 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1864 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1865 } 1866 1867 rsp->sso = pfvf->sso; 1868 for (slot = 0; slot < rsp->sso; slot++) { 1869 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1870 rsp->sso_msixoff[slot] = 1871 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1872 } 1873 1874 rsp->ssow = pfvf->ssow; 1875 for (slot = 0; slot < rsp->ssow; slot++) { 1876 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1877 rsp->ssow_msixoff[slot] = 1878 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1879 } 1880 1881 rsp->timlfs = pfvf->timlfs; 1882 for (slot = 0; slot < rsp->timlfs; slot++) { 1883 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1884 rsp->timlf_msixoff[slot] = 1885 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1886 } 1887 1888 rsp->cptlfs = pfvf->cptlfs; 1889 for (slot = 0; slot < rsp->cptlfs; slot++) { 1890 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1891 rsp->cptlf_msixoff[slot] = 1892 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1893 } 1894 1895 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1896 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1897 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1898 rsp->cpt1_lf_msixoff[slot] = 1899 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1900 } 1901 1902 return 0; 1903 } 1904 1905 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1906 struct free_rsrcs_rsp *rsp) 1907 { 1908 struct rvu_hwinfo *hw = rvu->hw; 1909 struct rvu_block *block; 1910 struct nix_txsch *txsch; 1911 struct nix_hw *nix_hw; 1912 1913 mutex_lock(&rvu->rsrc_lock); 1914 1915 block = &hw->block[BLKADDR_NPA]; 1916 rsp->npa = rvu_rsrc_free_count(&block->lf); 1917 1918 block = &hw->block[BLKADDR_NIX0]; 1919 rsp->nix = rvu_rsrc_free_count(&block->lf); 1920 1921 block = &hw->block[BLKADDR_NIX1]; 1922 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1923 1924 block = &hw->block[BLKADDR_SSO]; 1925 rsp->sso = rvu_rsrc_free_count(&block->lf); 1926 1927 block = &hw->block[BLKADDR_SSOW]; 1928 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1929 1930 block = &hw->block[BLKADDR_TIM]; 1931 rsp->tim = rvu_rsrc_free_count(&block->lf); 1932 1933 block = &hw->block[BLKADDR_CPT0]; 1934 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1935 1936 block = &hw->block[BLKADDR_CPT1]; 1937 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1938 1939 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1940 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1941 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1942 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1943 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1944 /* NIX1 */ 1945 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1946 goto out; 1947 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1948 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1949 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1950 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1951 } else { 1952 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1953 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1954 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1955 rvu_rsrc_free_count(&txsch->schq); 1956 1957 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1958 rsp->schq[NIX_TXSCH_LVL_TL4] = 1959 rvu_rsrc_free_count(&txsch->schq); 1960 1961 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1962 rsp->schq[NIX_TXSCH_LVL_TL3] = 1963 rvu_rsrc_free_count(&txsch->schq); 1964 1965 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1966 rsp->schq[NIX_TXSCH_LVL_TL2] = 1967 rvu_rsrc_free_count(&txsch->schq); 1968 1969 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1970 goto out; 1971 1972 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1973 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1974 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1975 rvu_rsrc_free_count(&txsch->schq); 1976 1977 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1978 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1979 rvu_rsrc_free_count(&txsch->schq); 1980 1981 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1982 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1983 rvu_rsrc_free_count(&txsch->schq); 1984 1985 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1986 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1987 rvu_rsrc_free_count(&txsch->schq); 1988 } 1989 1990 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1991 out: 1992 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1993 mutex_unlock(&rvu->rsrc_lock); 1994 1995 return 0; 1996 } 1997 1998 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1999 struct msg_rsp *rsp) 2000 { 2001 u16 pcifunc = req->hdr.pcifunc; 2002 u16 vf, numvfs; 2003 u64 cfg; 2004 2005 vf = pcifunc & RVU_PFVF_FUNC_MASK; 2006 cfg = rvu_read64(rvu, BLKADDR_RVUM, 2007 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 2008 numvfs = (cfg >> 12) & 0xFF; 2009 2010 if (vf && vf <= numvfs) 2011 __rvu_flr_handler(rvu, pcifunc); 2012 else 2013 return RVU_INVALID_VF_ID; 2014 2015 return 0; 2016 } 2017 2018 int rvu_ndc_sync(struct rvu *rvu, int lfblkaddr, int lfidx, u64 lfoffset) 2019 { 2020 /* Sync cached info for this LF in NDC to LLC/DRAM */ 2021 rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx); 2022 return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true); 2023 } 2024 2025 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2026 struct get_hw_cap_rsp *rsp) 2027 { 2028 struct rvu_hwinfo *hw = rvu->hw; 2029 2030 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 2031 rsp->nix_shaping = hw->cap.nix_shaping; 2032 rsp->npc_hash_extract = hw->cap.npc_hash_extract; 2033 2034 return 0; 2035 } 2036 2037 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 2038 struct msg_rsp *rsp) 2039 { 2040 struct rvu_hwinfo *hw = rvu->hw; 2041 u16 pcifunc = req->hdr.pcifunc; 2042 struct rvu_pfvf *pfvf; 2043 int blkaddr, nixlf; 2044 u16 target; 2045 2046 /* Only PF can add VF permissions */ 2047 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_lbk_vf(rvu, pcifunc)) 2048 return -EOPNOTSUPP; 2049 2050 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2051 pfvf = rvu_get_pfvf(rvu, target); 2052 2053 if (req->flags & RESET_VF_PERM) { 2054 pfvf->flags &= RVU_CLEAR_VF_PERM; 2055 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2056 (req->flags & VF_TRUSTED)) { 2057 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2058 /* disable multicast and promisc entries */ 2059 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2060 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2061 if (blkaddr < 0) 2062 return 0; 2063 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2064 target, 0); 2065 if (nixlf < 0) 2066 return 0; 2067 npc_enadis_default_mce_entry(rvu, target, nixlf, 2068 NIXLF_ALLMULTI_ENTRY, 2069 false); 2070 npc_enadis_default_mce_entry(rvu, target, nixlf, 2071 NIXLF_PROMISC_ENTRY, 2072 false); 2073 } 2074 } 2075 2076 return 0; 2077 } 2078 2079 int rvu_mbox_handler_ndc_sync_op(struct rvu *rvu, 2080 struct ndc_sync_op *req, 2081 struct msg_rsp *rsp) 2082 { 2083 struct rvu_hwinfo *hw = rvu->hw; 2084 u16 pcifunc = req->hdr.pcifunc; 2085 int err, lfidx, lfblkaddr; 2086 2087 if (req->npa_lf_sync) { 2088 /* Get NPA LF data */ 2089 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); 2090 if (lfblkaddr < 0) 2091 return NPA_AF_ERR_AF_LF_INVALID; 2092 2093 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2094 if (lfidx < 0) 2095 return NPA_AF_ERR_AF_LF_INVALID; 2096 2097 /* Sync NPA NDC */ 2098 err = rvu_ndc_sync(rvu, lfblkaddr, 2099 lfidx, NPA_AF_NDC_SYNC); 2100 if (err) 2101 dev_err(rvu->dev, 2102 "NDC-NPA sync failed for LF %u\n", lfidx); 2103 } 2104 2105 if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync) 2106 return 0; 2107 2108 /* Get NIX LF data */ 2109 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2110 if (lfblkaddr < 0) 2111 return NIX_AF_ERR_AF_LF_INVALID; 2112 2113 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2114 if (lfidx < 0) 2115 return NIX_AF_ERR_AF_LF_INVALID; 2116 2117 if (req->nix_lf_tx_sync) { 2118 /* Sync NIX TX NDC */ 2119 err = rvu_ndc_sync(rvu, lfblkaddr, 2120 lfidx, NIX_AF_NDC_TX_SYNC); 2121 if (err) 2122 dev_err(rvu->dev, 2123 "NDC-NIX-TX sync fail for LF %u\n", lfidx); 2124 } 2125 2126 if (req->nix_lf_rx_sync) { 2127 /* Sync NIX RX NDC */ 2128 err = rvu_ndc_sync(rvu, lfblkaddr, 2129 lfidx, NIX_AF_NDC_RX_SYNC); 2130 if (err) 2131 dev_err(rvu->dev, 2132 "NDC-NIX-RX sync failed for LF %u\n", lfidx); 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2139 struct mbox_msghdr *req) 2140 { 2141 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2142 2143 /* Check if valid, if not reply with a invalid msg */ 2144 if (req->sig != OTX2_MBOX_REQ_SIG) 2145 goto bad_message; 2146 2147 switch (req->id) { 2148 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2149 case _id: { \ 2150 struct _rsp_type *rsp; \ 2151 int err; \ 2152 \ 2153 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2154 mbox, devid, \ 2155 sizeof(struct _rsp_type)); \ 2156 /* some handlers should complete even if reply */ \ 2157 /* could not be allocated */ \ 2158 if (!rsp && \ 2159 _id != MBOX_MSG_DETACH_RESOURCES && \ 2160 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2161 _id != MBOX_MSG_VF_FLR) \ 2162 return -ENOMEM; \ 2163 if (rsp) { \ 2164 rsp->hdr.id = _id; \ 2165 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2166 rsp->hdr.pcifunc = req->pcifunc; \ 2167 rsp->hdr.rc = 0; \ 2168 } \ 2169 \ 2170 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2171 (struct _req_type *)req, \ 2172 rsp); \ 2173 if (rsp && err) \ 2174 rsp->hdr.rc = err; \ 2175 \ 2176 trace_otx2_msg_process(mbox->pdev, _id, err); \ 2177 return rsp ? err : -ENOMEM; \ 2178 } 2179 MBOX_MESSAGES 2180 #undef M 2181 2182 bad_message: 2183 default: 2184 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2185 return -ENODEV; 2186 } 2187 } 2188 2189 static void __rvu_mbox_handler(struct rvu_work *mwork, int type, bool poll) 2190 { 2191 struct rvu *rvu = mwork->rvu; 2192 int offset, err, id, devid; 2193 struct otx2_mbox_dev *mdev; 2194 struct mbox_hdr *req_hdr; 2195 struct mbox_msghdr *msg; 2196 struct mbox_wq_info *mw; 2197 struct otx2_mbox *mbox; 2198 2199 switch (type) { 2200 case TYPE_AFPF: 2201 mw = &rvu->afpf_wq_info; 2202 break; 2203 case TYPE_AFVF: 2204 mw = &rvu->afvf_wq_info; 2205 break; 2206 default: 2207 return; 2208 } 2209 2210 devid = mwork - mw->mbox_wrk; 2211 mbox = &mw->mbox; 2212 mdev = &mbox->dev[devid]; 2213 2214 /* Process received mbox messages */ 2215 req_hdr = mdev->mbase + mbox->rx_start; 2216 if (mw->mbox_wrk[devid].num_msgs == 0) 2217 return; 2218 2219 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2220 2221 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2222 msg = mdev->mbase + offset; 2223 2224 /* Set which PF/VF sent this message based on mbox IRQ */ 2225 switch (type) { 2226 case TYPE_AFPF: 2227 msg->pcifunc &= 2228 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2229 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2230 break; 2231 case TYPE_AFVF: 2232 msg->pcifunc &= 2233 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2234 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2235 break; 2236 } 2237 2238 err = rvu_process_mbox_msg(mbox, devid, msg); 2239 if (!err) { 2240 offset = mbox->rx_start + msg->next_msgoff; 2241 continue; 2242 } 2243 2244 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2245 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2246 err, otx2_mbox_id2name(msg->id), 2247 msg->id, rvu_get_pf(msg->pcifunc), 2248 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2249 else 2250 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2251 err, otx2_mbox_id2name(msg->id), 2252 msg->id, devid); 2253 } 2254 mw->mbox_wrk[devid].num_msgs = 0; 2255 2256 if (poll) 2257 otx2_mbox_wait_for_zero(mbox, devid); 2258 2259 /* Send mbox responses to VF/PF */ 2260 otx2_mbox_msg_send(mbox, devid); 2261 } 2262 2263 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2264 { 2265 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2266 struct rvu *rvu = mwork->rvu; 2267 2268 mutex_lock(&rvu->mbox_lock); 2269 __rvu_mbox_handler(mwork, TYPE_AFPF, true); 2270 mutex_unlock(&rvu->mbox_lock); 2271 } 2272 2273 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2274 { 2275 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2276 2277 __rvu_mbox_handler(mwork, TYPE_AFVF, false); 2278 } 2279 2280 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2281 { 2282 struct rvu *rvu = mwork->rvu; 2283 struct otx2_mbox_dev *mdev; 2284 struct mbox_hdr *rsp_hdr; 2285 struct mbox_msghdr *msg; 2286 struct mbox_wq_info *mw; 2287 struct otx2_mbox *mbox; 2288 int offset, id, devid; 2289 2290 switch (type) { 2291 case TYPE_AFPF: 2292 mw = &rvu->afpf_wq_info; 2293 break; 2294 case TYPE_AFVF: 2295 mw = &rvu->afvf_wq_info; 2296 break; 2297 default: 2298 return; 2299 } 2300 2301 devid = mwork - mw->mbox_wrk_up; 2302 mbox = &mw->mbox_up; 2303 mdev = &mbox->dev[devid]; 2304 2305 rsp_hdr = mdev->mbase + mbox->rx_start; 2306 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2307 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2308 return; 2309 } 2310 2311 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2312 2313 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2314 msg = mdev->mbase + offset; 2315 2316 if (msg->id >= MBOX_MSG_MAX) { 2317 dev_err(rvu->dev, 2318 "Mbox msg with unknown ID 0x%x\n", msg->id); 2319 goto end; 2320 } 2321 2322 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2323 dev_err(rvu->dev, 2324 "Mbox msg with wrong signature %x, ID 0x%x\n", 2325 msg->sig, msg->id); 2326 goto end; 2327 } 2328 2329 switch (msg->id) { 2330 case MBOX_MSG_CGX_LINK_EVENT: 2331 break; 2332 default: 2333 if (msg->rc) 2334 dev_err(rvu->dev, 2335 "Mbox msg response has err %d, ID 0x%x\n", 2336 msg->rc, msg->id); 2337 break; 2338 } 2339 end: 2340 offset = mbox->rx_start + msg->next_msgoff; 2341 mdev->msgs_acked++; 2342 } 2343 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2344 2345 otx2_mbox_reset(mbox, devid); 2346 } 2347 2348 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2349 { 2350 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2351 2352 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2353 } 2354 2355 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2356 { 2357 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2358 2359 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2360 } 2361 2362 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2363 int num, int type, unsigned long *pf_bmap) 2364 { 2365 struct rvu_hwinfo *hw = rvu->hw; 2366 int region; 2367 u64 bar4; 2368 2369 /* For cn10k platform VF mailbox regions of a PF follows after the 2370 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2371 * RVU_PF_VF_BAR4_ADDR register. 2372 */ 2373 if (type == TYPE_AFVF) { 2374 for (region = 0; region < num; region++) { 2375 if (!test_bit(region, pf_bmap)) 2376 continue; 2377 2378 if (hw->cap.per_pf_mbox_regs) { 2379 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2380 RVU_AF_PFX_BAR4_ADDR(0)) + 2381 MBOX_SIZE; 2382 bar4 += region * MBOX_SIZE; 2383 } else { 2384 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2385 bar4 += region * MBOX_SIZE; 2386 } 2387 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2388 if (!mbox_addr[region]) 2389 goto error; 2390 } 2391 return 0; 2392 } 2393 2394 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2395 * PF registers. Whereas for Octeontx2 it is read from 2396 * RVU_AF_PF_BAR4_ADDR register. 2397 */ 2398 for (region = 0; region < num; region++) { 2399 if (!test_bit(region, pf_bmap)) 2400 continue; 2401 2402 if (hw->cap.per_pf_mbox_regs) { 2403 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2404 RVU_AF_PFX_BAR4_ADDR(region)); 2405 } else { 2406 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2407 RVU_AF_PF_BAR4_ADDR); 2408 bar4 += region * MBOX_SIZE; 2409 } 2410 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2411 if (!mbox_addr[region]) 2412 goto error; 2413 } 2414 return 0; 2415 2416 error: 2417 while (region--) 2418 iounmap((void __iomem *)mbox_addr[region]); 2419 return -ENOMEM; 2420 } 2421 2422 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2423 int type, int num, 2424 void (mbox_handler)(struct work_struct *), 2425 void (mbox_up_handler)(struct work_struct *)) 2426 { 2427 int err = -EINVAL, i, dir, dir_up; 2428 void __iomem *reg_base; 2429 struct rvu_work *mwork; 2430 unsigned long *pf_bmap; 2431 void **mbox_regions; 2432 const char *name; 2433 u64 cfg; 2434 2435 pf_bmap = bitmap_zalloc(num, GFP_KERNEL); 2436 if (!pf_bmap) 2437 return -ENOMEM; 2438 2439 /* RVU VFs */ 2440 if (type == TYPE_AFVF) 2441 bitmap_set(pf_bmap, 0, num); 2442 2443 if (type == TYPE_AFPF) { 2444 /* Mark enabled PFs in bitmap */ 2445 for (i = 0; i < num; i++) { 2446 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i)); 2447 if (cfg & BIT_ULL(20)) 2448 set_bit(i, pf_bmap); 2449 } 2450 } 2451 2452 mutex_init(&rvu->mbox_lock); 2453 2454 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2455 if (!mbox_regions) { 2456 err = -ENOMEM; 2457 goto free_bitmap; 2458 } 2459 2460 switch (type) { 2461 case TYPE_AFPF: 2462 name = "rvu_afpf_mailbox"; 2463 dir = MBOX_DIR_AFPF; 2464 dir_up = MBOX_DIR_AFPF_UP; 2465 reg_base = rvu->afreg_base; 2466 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap); 2467 if (err) 2468 goto free_regions; 2469 break; 2470 case TYPE_AFVF: 2471 name = "rvu_afvf_mailbox"; 2472 dir = MBOX_DIR_PFVF; 2473 dir_up = MBOX_DIR_PFVF_UP; 2474 reg_base = rvu->pfreg_base; 2475 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap); 2476 if (err) 2477 goto free_regions; 2478 break; 2479 default: 2480 goto free_regions; 2481 } 2482 2483 mw->mbox_wq = alloc_workqueue("%s", 2484 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2485 num, name); 2486 if (!mw->mbox_wq) { 2487 err = -ENOMEM; 2488 goto unmap_regions; 2489 } 2490 2491 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2492 sizeof(struct rvu_work), GFP_KERNEL); 2493 if (!mw->mbox_wrk) { 2494 err = -ENOMEM; 2495 goto exit; 2496 } 2497 2498 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2499 sizeof(struct rvu_work), GFP_KERNEL); 2500 if (!mw->mbox_wrk_up) { 2501 err = -ENOMEM; 2502 goto exit; 2503 } 2504 2505 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2506 reg_base, dir, num, pf_bmap); 2507 if (err) 2508 goto exit; 2509 2510 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2511 reg_base, dir_up, num, pf_bmap); 2512 if (err) 2513 goto exit; 2514 2515 for (i = 0; i < num; i++) { 2516 if (!test_bit(i, pf_bmap)) 2517 continue; 2518 2519 mwork = &mw->mbox_wrk[i]; 2520 mwork->rvu = rvu; 2521 INIT_WORK(&mwork->work, mbox_handler); 2522 2523 mwork = &mw->mbox_wrk_up[i]; 2524 mwork->rvu = rvu; 2525 INIT_WORK(&mwork->work, mbox_up_handler); 2526 } 2527 goto free_regions; 2528 2529 exit: 2530 destroy_workqueue(mw->mbox_wq); 2531 unmap_regions: 2532 while (num--) 2533 iounmap((void __iomem *)mbox_regions[num]); 2534 free_regions: 2535 kfree(mbox_regions); 2536 free_bitmap: 2537 bitmap_free(pf_bmap); 2538 return err; 2539 } 2540 2541 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2542 { 2543 struct otx2_mbox *mbox = &mw->mbox; 2544 struct otx2_mbox_dev *mdev; 2545 int devid; 2546 2547 if (mw->mbox_wq) { 2548 destroy_workqueue(mw->mbox_wq); 2549 mw->mbox_wq = NULL; 2550 } 2551 2552 for (devid = 0; devid < mbox->ndevs; devid++) { 2553 mdev = &mbox->dev[devid]; 2554 if (mdev->hwbase) 2555 iounmap((void __iomem *)mdev->hwbase); 2556 } 2557 2558 otx2_mbox_destroy(&mw->mbox); 2559 otx2_mbox_destroy(&mw->mbox_up); 2560 } 2561 2562 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2563 int mdevs, u64 intr) 2564 { 2565 struct otx2_mbox_dev *mdev; 2566 struct otx2_mbox *mbox; 2567 struct mbox_hdr *hdr; 2568 int i; 2569 2570 for (i = first; i < mdevs; i++) { 2571 /* start from 0 */ 2572 if (!(intr & BIT_ULL(i - first))) 2573 continue; 2574 2575 mbox = &mw->mbox; 2576 mdev = &mbox->dev[i]; 2577 hdr = mdev->mbase + mbox->rx_start; 2578 2579 /*The hdr->num_msgs is set to zero immediately in the interrupt 2580 * handler to ensure that it holds a correct value next time 2581 * when the interrupt handler is called. 2582 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2583 * pf>mbox.up_num_msgs holds the data for use in 2584 * pfaf_mbox_up_handler. 2585 */ 2586 2587 if (hdr->num_msgs) { 2588 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2589 hdr->num_msgs = 0; 2590 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2591 } 2592 mbox = &mw->mbox_up; 2593 mdev = &mbox->dev[i]; 2594 hdr = mdev->mbase + mbox->rx_start; 2595 if (hdr->num_msgs) { 2596 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2597 hdr->num_msgs = 0; 2598 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2599 } 2600 } 2601 } 2602 2603 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) 2604 { 2605 struct rvu *rvu = (struct rvu *)rvu_irq; 2606 u64 intr; 2607 2608 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2609 /* Clear interrupts */ 2610 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2611 if (intr) 2612 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2613 2614 /* Sync with mbox memory region */ 2615 rmb(); 2616 2617 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2618 2619 return IRQ_HANDLED; 2620 } 2621 2622 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2623 { 2624 struct rvu *rvu = (struct rvu *)rvu_irq; 2625 int vfs = rvu->vfs; 2626 u64 intr; 2627 2628 /* Sync with mbox memory region */ 2629 rmb(); 2630 2631 /* Handle VF interrupts */ 2632 if (vfs > 64) { 2633 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2634 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2635 2636 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2637 vfs -= 64; 2638 } 2639 2640 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2641 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2642 if (intr) 2643 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2644 2645 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2646 2647 return IRQ_HANDLED; 2648 } 2649 2650 static void rvu_enable_mbox_intr(struct rvu *rvu) 2651 { 2652 struct rvu_hwinfo *hw = rvu->hw; 2653 2654 /* Clear spurious irqs, if any */ 2655 rvu_write64(rvu, BLKADDR_RVUM, 2656 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2657 2658 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2659 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2660 INTR_MASK(hw->total_pfs) & ~1ULL); 2661 } 2662 2663 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2664 { 2665 struct rvu_block *block; 2666 int slot, lf, num_lfs; 2667 int err; 2668 2669 block = &rvu->hw->block[blkaddr]; 2670 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2671 block->addr); 2672 if (!num_lfs) 2673 return; 2674 for (slot = 0; slot < num_lfs; slot++) { 2675 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2676 if (lf < 0) 2677 continue; 2678 2679 /* Cleanup LF and reset it */ 2680 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2681 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2682 else if (block->addr == BLKADDR_NPA) 2683 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2684 else if ((block->addr == BLKADDR_CPT0) || 2685 (block->addr == BLKADDR_CPT1)) 2686 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, 2687 slot); 2688 2689 err = rvu_lf_reset(rvu, block, lf); 2690 if (err) { 2691 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2692 block->addr, lf); 2693 } 2694 } 2695 } 2696 2697 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2698 { 2699 if (rvu_npc_exact_has_match_table(rvu)) 2700 rvu_npc_exact_reset(rvu, pcifunc); 2701 2702 mutex_lock(&rvu->flr_lock); 2703 /* Reset order should reflect inter-block dependencies: 2704 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2705 * 2. Flush and reset SSO/SSOW 2706 * 3. Cleanup pools (NPA) 2707 */ 2708 2709 /* Free allocated BPIDs */ 2710 rvu_nix_flr_free_bpids(rvu, pcifunc); 2711 2712 /* Free multicast/mirror node associated with the 'pcifunc' */ 2713 rvu_nix_mcast_flr_free_entries(rvu, pcifunc); 2714 2715 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2716 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2717 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2718 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2719 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2720 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2721 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2722 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2723 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2724 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2725 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM 2726 * entries, check and free the MCAM entries explicitly to avoid leak. 2727 * Since LF is detached use LF number as -1. 2728 */ 2729 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); 2730 rvu_mac_reset(rvu, pcifunc); 2731 2732 if (rvu->mcs_blk_cnt) 2733 rvu_mcs_flr_handler(rvu, pcifunc); 2734 2735 mutex_unlock(&rvu->flr_lock); 2736 } 2737 2738 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2739 { 2740 int reg = 0; 2741 2742 /* pcifunc = 0(PF0) | (vf + 1) */ 2743 __rvu_flr_handler(rvu, vf + 1); 2744 2745 if (vf >= 64) { 2746 reg = 1; 2747 vf = vf - 64; 2748 } 2749 2750 /* Signal FLR finish and enable IRQ */ 2751 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2752 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2753 } 2754 2755 static void rvu_flr_handler(struct work_struct *work) 2756 { 2757 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2758 struct rvu *rvu = flrwork->rvu; 2759 u16 pcifunc, numvfs, vf; 2760 u64 cfg; 2761 int pf; 2762 2763 pf = flrwork - rvu->flr_wrk; 2764 if (pf >= rvu->hw->total_pfs) { 2765 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2766 return; 2767 } 2768 2769 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2770 numvfs = (cfg >> 12) & 0xFF; 2771 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2772 2773 for (vf = 0; vf < numvfs; vf++) 2774 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2775 2776 __rvu_flr_handler(rvu, pcifunc); 2777 2778 /* Signal FLR finish */ 2779 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2780 2781 /* Enable interrupt */ 2782 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2783 } 2784 2785 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2786 { 2787 int dev, vf, reg = 0; 2788 u64 intr; 2789 2790 if (start_vf >= 64) 2791 reg = 1; 2792 2793 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2794 if (!intr) 2795 return; 2796 2797 for (vf = 0; vf < numvfs; vf++) { 2798 if (!(intr & BIT_ULL(vf))) 2799 continue; 2800 /* Clear and disable the interrupt */ 2801 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2802 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2803 2804 dev = vf + start_vf + rvu->hw->total_pfs; 2805 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2806 } 2807 } 2808 2809 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2810 { 2811 struct rvu *rvu = (struct rvu *)rvu_irq; 2812 u64 intr; 2813 u8 pf; 2814 2815 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2816 if (!intr) 2817 goto afvf_flr; 2818 2819 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2820 if (intr & (1ULL << pf)) { 2821 /* clear interrupt */ 2822 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2823 BIT_ULL(pf)); 2824 /* Disable the interrupt */ 2825 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2826 BIT_ULL(pf)); 2827 /* PF is already dead do only AF related operations */ 2828 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2829 } 2830 } 2831 2832 afvf_flr: 2833 rvu_afvf_queue_flr_work(rvu, 0, 64); 2834 if (rvu->vfs > 64) 2835 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2836 2837 return IRQ_HANDLED; 2838 } 2839 2840 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2841 { 2842 int vf; 2843 2844 /* Nothing to be done here other than clearing the 2845 * TRPEND bit. 2846 */ 2847 for (vf = 0; vf < 64; vf++) { 2848 if (intr & (1ULL << vf)) { 2849 /* clear the trpend due to ME(master enable) */ 2850 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2851 /* clear interrupt */ 2852 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2853 } 2854 } 2855 } 2856 2857 /* Handles ME interrupts from VFs of AF */ 2858 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2859 { 2860 struct rvu *rvu = (struct rvu *)rvu_irq; 2861 int vfset; 2862 u64 intr; 2863 2864 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2865 2866 for (vfset = 0; vfset <= 1; vfset++) { 2867 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2868 if (intr) 2869 rvu_me_handle_vfset(rvu, vfset, intr); 2870 } 2871 2872 return IRQ_HANDLED; 2873 } 2874 2875 /* Handles ME interrupts from PFs */ 2876 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2877 { 2878 struct rvu *rvu = (struct rvu *)rvu_irq; 2879 u64 intr; 2880 u8 pf; 2881 2882 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2883 2884 /* Nothing to be done here other than clearing the 2885 * TRPEND bit. 2886 */ 2887 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2888 if (intr & (1ULL << pf)) { 2889 /* clear the trpend due to ME(master enable) */ 2890 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2891 BIT_ULL(pf)); 2892 /* clear interrupt */ 2893 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2894 BIT_ULL(pf)); 2895 } 2896 } 2897 2898 return IRQ_HANDLED; 2899 } 2900 2901 static void rvu_unregister_interrupts(struct rvu *rvu) 2902 { 2903 int irq; 2904 2905 rvu_cpt_unregister_interrupts(rvu); 2906 2907 /* Disable the Mbox interrupt */ 2908 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2909 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2910 2911 /* Disable the PF FLR interrupt */ 2912 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2913 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2914 2915 /* Disable the PF ME interrupt */ 2916 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2917 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2918 2919 for (irq = 0; irq < rvu->num_vec; irq++) { 2920 if (rvu->irq_allocated[irq]) { 2921 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2922 rvu->irq_allocated[irq] = false; 2923 } 2924 } 2925 2926 pci_free_irq_vectors(rvu->pdev); 2927 rvu->num_vec = 0; 2928 } 2929 2930 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2931 { 2932 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2933 int offset; 2934 2935 pfvf = &rvu->pf[0]; 2936 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2937 2938 /* Make sure there are enough MSIX vectors configured so that 2939 * VF interrupts can be handled. Offset equal to zero means 2940 * that PF vectors are not configured and overlapping AF vectors. 2941 */ 2942 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2943 offset; 2944 } 2945 2946 static int rvu_register_interrupts(struct rvu *rvu) 2947 { 2948 int ret, offset, pf_vec_start; 2949 2950 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2951 2952 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2953 NAME_SIZE, GFP_KERNEL); 2954 if (!rvu->irq_name) 2955 return -ENOMEM; 2956 2957 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2958 sizeof(bool), GFP_KERNEL); 2959 if (!rvu->irq_allocated) 2960 return -ENOMEM; 2961 2962 /* Enable MSI-X */ 2963 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2964 rvu->num_vec, PCI_IRQ_MSIX); 2965 if (ret < 0) { 2966 dev_err(rvu->dev, 2967 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2968 rvu->num_vec, ret); 2969 return ret; 2970 } 2971 2972 /* Register mailbox interrupt handler */ 2973 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2974 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2975 rvu_mbox_pf_intr_handler, 0, 2976 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2977 if (ret) { 2978 dev_err(rvu->dev, 2979 "RVUAF: IRQ registration failed for mbox irq\n"); 2980 goto fail; 2981 } 2982 2983 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2984 2985 /* Enable mailbox interrupts from all PFs */ 2986 rvu_enable_mbox_intr(rvu); 2987 2988 /* Register FLR interrupt handler */ 2989 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2990 "RVUAF FLR"); 2991 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2992 rvu_flr_intr_handler, 0, 2993 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2994 rvu); 2995 if (ret) { 2996 dev_err(rvu->dev, 2997 "RVUAF: IRQ registration failed for FLR\n"); 2998 goto fail; 2999 } 3000 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 3001 3002 /* Enable FLR interrupt for all PFs*/ 3003 rvu_write64(rvu, BLKADDR_RVUM, 3004 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 3005 3006 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 3007 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3008 3009 /* Register ME interrupt handler */ 3010 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3011 "RVUAF ME"); 3012 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 3013 rvu_me_pf_intr_handler, 0, 3014 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3015 rvu); 3016 if (ret) { 3017 dev_err(rvu->dev, 3018 "RVUAF: IRQ registration failed for ME\n"); 3019 } 3020 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 3021 3022 /* Clear TRPEND bit for all PF */ 3023 rvu_write64(rvu, BLKADDR_RVUM, 3024 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 3025 /* Enable ME interrupt for all PFs*/ 3026 rvu_write64(rvu, BLKADDR_RVUM, 3027 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 3028 3029 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 3030 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3031 3032 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 3033 return 0; 3034 3035 /* Get PF MSIX vectors offset. */ 3036 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 3037 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 3038 3039 /* Register MBOX0 interrupt. */ 3040 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 3041 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 3042 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3043 rvu_mbox_intr_handler, 0, 3044 &rvu->irq_name[offset * NAME_SIZE], 3045 rvu); 3046 if (ret) 3047 dev_err(rvu->dev, 3048 "RVUAF: IRQ registration failed for Mbox0\n"); 3049 3050 rvu->irq_allocated[offset] = true; 3051 3052 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 3053 * simply increment current offset by 1. 3054 */ 3055 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 3056 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 3057 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3058 rvu_mbox_intr_handler, 0, 3059 &rvu->irq_name[offset * NAME_SIZE], 3060 rvu); 3061 if (ret) 3062 dev_err(rvu->dev, 3063 "RVUAF: IRQ registration failed for Mbox1\n"); 3064 3065 rvu->irq_allocated[offset] = true; 3066 3067 /* Register FLR interrupt handler for AF's VFs */ 3068 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 3069 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 3070 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3071 rvu_flr_intr_handler, 0, 3072 &rvu->irq_name[offset * NAME_SIZE], rvu); 3073 if (ret) { 3074 dev_err(rvu->dev, 3075 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 3076 goto fail; 3077 } 3078 rvu->irq_allocated[offset] = true; 3079 3080 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 3081 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 3082 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3083 rvu_flr_intr_handler, 0, 3084 &rvu->irq_name[offset * NAME_SIZE], rvu); 3085 if (ret) { 3086 dev_err(rvu->dev, 3087 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 3088 goto fail; 3089 } 3090 rvu->irq_allocated[offset] = true; 3091 3092 /* Register ME interrupt handler for AF's VFs */ 3093 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 3094 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 3095 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3096 rvu_me_vf_intr_handler, 0, 3097 &rvu->irq_name[offset * NAME_SIZE], rvu); 3098 if (ret) { 3099 dev_err(rvu->dev, 3100 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 3101 goto fail; 3102 } 3103 rvu->irq_allocated[offset] = true; 3104 3105 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 3106 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 3107 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3108 rvu_me_vf_intr_handler, 0, 3109 &rvu->irq_name[offset * NAME_SIZE], rvu); 3110 if (ret) { 3111 dev_err(rvu->dev, 3112 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 3113 goto fail; 3114 } 3115 rvu->irq_allocated[offset] = true; 3116 3117 ret = rvu_cpt_register_interrupts(rvu); 3118 if (ret) 3119 goto fail; 3120 3121 return 0; 3122 3123 fail: 3124 rvu_unregister_interrupts(rvu); 3125 return ret; 3126 } 3127 3128 static void rvu_flr_wq_destroy(struct rvu *rvu) 3129 { 3130 if (rvu->flr_wq) { 3131 destroy_workqueue(rvu->flr_wq); 3132 rvu->flr_wq = NULL; 3133 } 3134 } 3135 3136 static int rvu_flr_init(struct rvu *rvu) 3137 { 3138 int dev, num_devs; 3139 u64 cfg; 3140 int pf; 3141 3142 /* Enable FLR for all PFs*/ 3143 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 3144 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 3145 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 3146 cfg | BIT_ULL(22)); 3147 } 3148 3149 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr", 3150 WQ_HIGHPRI | WQ_MEM_RECLAIM); 3151 if (!rvu->flr_wq) 3152 return -ENOMEM; 3153 3154 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 3155 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 3156 sizeof(struct rvu_work), GFP_KERNEL); 3157 if (!rvu->flr_wrk) { 3158 destroy_workqueue(rvu->flr_wq); 3159 return -ENOMEM; 3160 } 3161 3162 for (dev = 0; dev < num_devs; dev++) { 3163 rvu->flr_wrk[dev].rvu = rvu; 3164 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 3165 } 3166 3167 mutex_init(&rvu->flr_lock); 3168 3169 return 0; 3170 } 3171 3172 static void rvu_disable_afvf_intr(struct rvu *rvu) 3173 { 3174 int vfs = rvu->vfs; 3175 3176 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3177 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3178 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3179 if (vfs <= 64) 3180 return; 3181 3182 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3183 INTR_MASK(vfs - 64)); 3184 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3185 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3186 } 3187 3188 static void rvu_enable_afvf_intr(struct rvu *rvu) 3189 { 3190 int vfs = rvu->vfs; 3191 3192 /* Clear any pending interrupts and enable AF VF interrupts for 3193 * the first 64 VFs. 3194 */ 3195 /* Mbox */ 3196 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3197 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3198 3199 /* FLR */ 3200 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3201 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3202 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3203 3204 /* Same for remaining VFs, if any. */ 3205 if (vfs <= 64) 3206 return; 3207 3208 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3209 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3210 INTR_MASK(vfs - 64)); 3211 3212 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3213 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3214 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3215 } 3216 3217 int rvu_get_num_lbk_chans(void) 3218 { 3219 struct pci_dev *pdev; 3220 void __iomem *base; 3221 int ret = -EIO; 3222 3223 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3224 NULL); 3225 if (!pdev) 3226 goto err; 3227 3228 base = pci_ioremap_bar(pdev, 0); 3229 if (!base) 3230 goto err_put; 3231 3232 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3233 ret = (readq(base + 0x10) >> 32) & 0xffff; 3234 iounmap(base); 3235 err_put: 3236 pci_dev_put(pdev); 3237 err: 3238 return ret; 3239 } 3240 3241 static int rvu_enable_sriov(struct rvu *rvu) 3242 { 3243 struct pci_dev *pdev = rvu->pdev; 3244 int err, chans, vfs; 3245 int pos = 0; 3246 3247 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3248 dev_warn(&pdev->dev, 3249 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3250 return 0; 3251 } 3252 3253 /* Get RVU VFs device id */ 3254 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 3255 if (!pos) 3256 return 0; 3257 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid); 3258 3259 chans = rvu_get_num_lbk_chans(); 3260 if (chans < 0) 3261 return chans; 3262 3263 vfs = pci_sriov_get_totalvfs(pdev); 3264 3265 /* Limit VFs in case we have more VFs than LBK channels available. */ 3266 if (vfs > chans) 3267 vfs = chans; 3268 3269 if (!vfs) 3270 return 0; 3271 3272 /* LBK channel number 63 is used for switching packets between 3273 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3274 */ 3275 if (vfs > 62) 3276 vfs = 62; 3277 3278 /* Save VFs number for reference in VF interrupts handlers. 3279 * Since interrupts might start arriving during SRIOV enablement 3280 * ordinary API cannot be used to get number of enabled VFs. 3281 */ 3282 rvu->vfs = vfs; 3283 3284 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3285 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3286 if (err) 3287 return err; 3288 3289 rvu_enable_afvf_intr(rvu); 3290 /* Make sure IRQs are enabled before SRIOV. */ 3291 mb(); 3292 3293 err = pci_enable_sriov(pdev, vfs); 3294 if (err) { 3295 rvu_disable_afvf_intr(rvu); 3296 rvu_mbox_destroy(&rvu->afvf_wq_info); 3297 return err; 3298 } 3299 3300 return 0; 3301 } 3302 3303 static void rvu_disable_sriov(struct rvu *rvu) 3304 { 3305 rvu_disable_afvf_intr(rvu); 3306 rvu_mbox_destroy(&rvu->afvf_wq_info); 3307 pci_disable_sriov(rvu->pdev); 3308 } 3309 3310 static void rvu_update_module_params(struct rvu *rvu) 3311 { 3312 const char *default_pfl_name = "default"; 3313 3314 strscpy(rvu->mkex_pfl_name, 3315 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3316 strscpy(rvu->kpu_pfl_name, 3317 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3318 } 3319 3320 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3321 { 3322 struct device *dev = &pdev->dev; 3323 struct rvu *rvu; 3324 int err; 3325 3326 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3327 if (!rvu) 3328 return -ENOMEM; 3329 3330 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3331 if (!rvu->hw) { 3332 devm_kfree(dev, rvu); 3333 return -ENOMEM; 3334 } 3335 3336 pci_set_drvdata(pdev, rvu); 3337 rvu->pdev = pdev; 3338 rvu->dev = &pdev->dev; 3339 3340 err = pci_enable_device(pdev); 3341 if (err) { 3342 dev_err(dev, "Failed to enable PCI device\n"); 3343 goto err_freemem; 3344 } 3345 3346 err = pci_request_regions(pdev, DRV_NAME); 3347 if (err) { 3348 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3349 goto err_disable_device; 3350 } 3351 3352 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3353 if (err) { 3354 dev_err(dev, "DMA mask config failed, abort\n"); 3355 goto err_release_regions; 3356 } 3357 3358 pci_set_master(pdev); 3359 3360 rvu->ptp = ptp_get(); 3361 if (IS_ERR(rvu->ptp)) { 3362 err = PTR_ERR(rvu->ptp); 3363 if (err) 3364 goto err_release_regions; 3365 rvu->ptp = NULL; 3366 } 3367 3368 /* Map Admin function CSRs */ 3369 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3370 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3371 if (!rvu->afreg_base || !rvu->pfreg_base) { 3372 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3373 err = -ENOMEM; 3374 goto err_put_ptp; 3375 } 3376 3377 /* Store module params in rvu structure */ 3378 rvu_update_module_params(rvu); 3379 3380 /* Check which blocks the HW supports */ 3381 rvu_check_block_implemented(rvu); 3382 3383 rvu_reset_all_blocks(rvu); 3384 3385 rvu_setup_hw_capabilities(rvu); 3386 3387 err = rvu_setup_hw_resources(rvu); 3388 if (err) 3389 goto err_put_ptp; 3390 3391 /* Init mailbox btw AF and PFs */ 3392 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3393 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3394 rvu_afpf_mbox_up_handler); 3395 if (err) { 3396 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3397 goto err_hwsetup; 3398 } 3399 3400 err = rvu_flr_init(rvu); 3401 if (err) { 3402 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3403 goto err_mbox; 3404 } 3405 3406 err = rvu_register_interrupts(rvu); 3407 if (err) { 3408 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3409 goto err_flr; 3410 } 3411 3412 err = rvu_register_dl(rvu); 3413 if (err) { 3414 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3415 goto err_irq; 3416 } 3417 3418 rvu_setup_rvum_blk_revid(rvu); 3419 3420 /* Enable AF's VFs (if any) */ 3421 err = rvu_enable_sriov(rvu); 3422 if (err) { 3423 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3424 goto err_dl; 3425 } 3426 3427 /* Initialize debugfs */ 3428 rvu_dbg_init(rvu); 3429 3430 mutex_init(&rvu->rswitch.switch_lock); 3431 3432 if (rvu->fwdata) 3433 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3434 rvu->fwdata->ptp_ext_tstamp); 3435 3436 return 0; 3437 err_dl: 3438 rvu_unregister_dl(rvu); 3439 err_irq: 3440 rvu_unregister_interrupts(rvu); 3441 err_flr: 3442 rvu_flr_wq_destroy(rvu); 3443 err_mbox: 3444 rvu_mbox_destroy(&rvu->afpf_wq_info); 3445 err_hwsetup: 3446 rvu_cgx_exit(rvu); 3447 rvu_fwdata_exit(rvu); 3448 rvu_mcs_exit(rvu); 3449 rvu_reset_all_blocks(rvu); 3450 rvu_free_hw_resources(rvu); 3451 rvu_clear_rvum_blk_revid(rvu); 3452 err_put_ptp: 3453 ptp_put(rvu->ptp); 3454 err_release_regions: 3455 pci_release_regions(pdev); 3456 err_disable_device: 3457 pci_disable_device(pdev); 3458 err_freemem: 3459 pci_set_drvdata(pdev, NULL); 3460 devm_kfree(&pdev->dev, rvu->hw); 3461 devm_kfree(dev, rvu); 3462 return err; 3463 } 3464 3465 static void rvu_remove(struct pci_dev *pdev) 3466 { 3467 struct rvu *rvu = pci_get_drvdata(pdev); 3468 3469 rvu_dbg_exit(rvu); 3470 rvu_unregister_dl(rvu); 3471 rvu_unregister_interrupts(rvu); 3472 rvu_flr_wq_destroy(rvu); 3473 rvu_cgx_exit(rvu); 3474 rvu_fwdata_exit(rvu); 3475 rvu_mcs_exit(rvu); 3476 rvu_mbox_destroy(&rvu->afpf_wq_info); 3477 rvu_disable_sriov(rvu); 3478 rvu_reset_all_blocks(rvu); 3479 rvu_free_hw_resources(rvu); 3480 rvu_clear_rvum_blk_revid(rvu); 3481 ptp_put(rvu->ptp); 3482 pci_release_regions(pdev); 3483 pci_disable_device(pdev); 3484 pci_set_drvdata(pdev, NULL); 3485 3486 devm_kfree(&pdev->dev, rvu->hw); 3487 devm_kfree(&pdev->dev, rvu); 3488 } 3489 3490 static struct pci_driver rvu_driver = { 3491 .name = DRV_NAME, 3492 .id_table = rvu_id_table, 3493 .probe = rvu_probe, 3494 .remove = rvu_remove, 3495 }; 3496 3497 static int __init rvu_init_module(void) 3498 { 3499 int err; 3500 3501 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3502 3503 err = pci_register_driver(&cgx_driver); 3504 if (err < 0) 3505 return err; 3506 3507 err = pci_register_driver(&ptp_driver); 3508 if (err < 0) 3509 goto ptp_err; 3510 3511 err = pci_register_driver(&mcs_driver); 3512 if (err < 0) 3513 goto mcs_err; 3514 3515 err = pci_register_driver(&rvu_driver); 3516 if (err < 0) 3517 goto rvu_err; 3518 3519 return 0; 3520 rvu_err: 3521 pci_unregister_driver(&mcs_driver); 3522 mcs_err: 3523 pci_unregister_driver(&ptp_driver); 3524 ptp_err: 3525 pci_unregister_driver(&cgx_driver); 3526 3527 return err; 3528 } 3529 3530 static void __exit rvu_cleanup_module(void) 3531 { 3532 pci_unregister_driver(&rvu_driver); 3533 pci_unregister_driver(&mcs_driver); 3534 pci_unregister_driver(&ptp_driver); 3535 pci_unregister_driver(&cgx_driver); 3536 } 3537 3538 module_init(rvu_init_module); 3539 module_exit(rvu_cleanup_module); 3540