1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 #include "mcs.h" 20 21 #include "rvu_trace.h" 22 #include "rvu_npc_hash.h" 23 #include "cn20k/reg.h" 24 #include "cn20k/api.h" 25 26 #define DRV_NAME "rvu_af" 27 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 28 29 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 32 struct rvu_block *block, int lf); 33 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 34 35 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 36 int type, int num, 37 void (mbox_handler)(struct work_struct *), 38 void (mbox_up_handler)(struct work_struct *)); 39 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq); 40 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq); 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->cap.npc_hash_extract = false; 72 hw->cap.npc_exact_match_enabled = false; 73 hw->rvu = rvu; 74 75 if (is_rvu_pre_96xx_C0(rvu)) { 76 hw->cap.nix_fixed_txschq_mapping = true; 77 hw->cap.nix_txsch_per_cgx_lmac = 4; 78 hw->cap.nix_txsch_per_lbk_lmac = 132; 79 hw->cap.nix_txsch_per_sdp_lmac = 76; 80 hw->cap.nix_shaping = false; 81 hw->cap.nix_tx_link_bp = false; 82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 83 hw->cap.nix_rx_multicast = false; 84 } 85 if (!is_rvu_pre_96xx_C0(rvu)) 86 hw->cap.nix_shaper_toggle_wait = true; 87 88 if (!is_rvu_otx2(rvu)) 89 hw->cap.per_pf_mbox_regs = true; 90 91 if (is_rvu_npc_hash_extract_en(rvu)) 92 hw->cap.npc_hash_extract = true; 93 } 94 95 /* Poll a RVU block's register 'offset', for a 'zero' 96 * or 'nonzero' at bits specified by 'mask' 97 */ 98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 99 { 100 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 101 bool twice = false; 102 void __iomem *reg; 103 u64 reg_val; 104 105 reg = rvu->afreg_base + ((block << 28) | offset); 106 again: 107 reg_val = readq(reg); 108 if (zero && !(reg_val & mask)) 109 return 0; 110 if (!zero && (reg_val & mask)) 111 return 0; 112 if (time_before(jiffies, timeout)) { 113 usleep_range(1, 5); 114 goto again; 115 } 116 /* In scenarios where CPU is scheduled out before checking 117 * 'time_before' (above) and gets scheduled in such that 118 * jiffies are beyond timeout value, then check again if HW is 119 * done with the operation in the meantime. 120 */ 121 if (!twice) { 122 twice = true; 123 goto again; 124 } 125 return -EBUSY; 126 } 127 128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 129 { 130 int id; 131 132 if (!rsrc->bmap) 133 return -EINVAL; 134 135 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 136 if (id >= rsrc->max) 137 return -ENOSPC; 138 139 __set_bit(id, rsrc->bmap); 140 141 return id; 142 } 143 144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 145 { 146 int start; 147 148 if (!rsrc->bmap) 149 return -EINVAL; 150 151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 152 if (start >= rsrc->max) 153 return -ENOSPC; 154 155 bitmap_set(rsrc->bmap, start, nrsrc); 156 return start; 157 } 158 159 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 160 { 161 if (!rsrc->bmap) 162 return; 163 if (start >= rsrc->max) 164 return; 165 166 bitmap_clear(rsrc->bmap, start, nrsrc); 167 } 168 169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 170 { 171 int start; 172 173 if (!rsrc->bmap) 174 return false; 175 176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 177 if (start >= rsrc->max) 178 return false; 179 180 return true; 181 } 182 183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 184 { 185 if (!rsrc->bmap) 186 return; 187 188 __clear_bit(id, rsrc->bmap); 189 } 190 191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 192 { 193 int used; 194 195 if (!rsrc->bmap) 196 return 0; 197 198 used = bitmap_weight(rsrc->bmap, rsrc->max); 199 return (rsrc->max - used); 200 } 201 202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 203 { 204 if (!rsrc->bmap) 205 return false; 206 207 return !test_bit(id, rsrc->bmap); 208 } 209 210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 211 { 212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 213 sizeof(long), GFP_KERNEL); 214 if (!rsrc->bmap) 215 return -ENOMEM; 216 return 0; 217 } 218 219 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 220 { 221 kfree(rsrc->bmap); 222 } 223 224 /* Get block LF's HW index from a PF_FUNC's block slot number */ 225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 226 { 227 u16 match = 0; 228 int lf; 229 230 mutex_lock(&rvu->rsrc_lock); 231 for (lf = 0; lf < block->lf.max; lf++) { 232 if (block->fn_map[lf] == pcifunc) { 233 if (slot == match) { 234 mutex_unlock(&rvu->rsrc_lock); 235 return lf; 236 } 237 match++; 238 } 239 } 240 mutex_unlock(&rvu->rsrc_lock); 241 return -ENODEV; 242 } 243 244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 245 * Some silicon variants of OcteonTX2 supports 246 * multiple blocks of same type. 247 * 248 * @pcifunc has to be zero when no LF is yet attached. 249 * 250 * For a pcifunc if LFs are attached from multiple blocks of same type, then 251 * return blkaddr of first encountered block. 252 */ 253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 254 { 255 int devnum, blkaddr = -ENODEV; 256 u64 cfg, reg; 257 bool is_pf; 258 259 switch (blktype) { 260 case BLKTYPE_NPC: 261 blkaddr = BLKADDR_NPC; 262 goto exit; 263 case BLKTYPE_NPA: 264 blkaddr = BLKADDR_NPA; 265 goto exit; 266 case BLKTYPE_NIX: 267 /* For now assume NIX0 */ 268 if (!pcifunc) { 269 blkaddr = BLKADDR_NIX0; 270 goto exit; 271 } 272 break; 273 case BLKTYPE_SSO: 274 blkaddr = BLKADDR_SSO; 275 goto exit; 276 case BLKTYPE_SSOW: 277 blkaddr = BLKADDR_SSOW; 278 goto exit; 279 case BLKTYPE_TIM: 280 blkaddr = BLKADDR_TIM; 281 goto exit; 282 case BLKTYPE_CPT: 283 /* For now assume CPT0 */ 284 if (!pcifunc) { 285 blkaddr = BLKADDR_CPT0; 286 goto exit; 287 } 288 break; 289 } 290 291 /* Check if this is a RVU PF or VF */ 292 if (pcifunc & RVU_PFVF_FUNC_MASK) { 293 is_pf = false; 294 devnum = rvu_get_hwvf(rvu, pcifunc); 295 } else { 296 is_pf = true; 297 devnum = rvu_get_pf(rvu->pdev, pcifunc); 298 } 299 300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 301 * 'BLKADDR_NIX1'. 302 */ 303 if (blktype == BLKTYPE_NIX) { 304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 305 RVU_PRIV_HWVFX_NIXX_CFG(0); 306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 307 if (cfg) { 308 blkaddr = BLKADDR_NIX0; 309 goto exit; 310 } 311 312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 313 RVU_PRIV_HWVFX_NIXX_CFG(1); 314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 315 if (cfg) 316 blkaddr = BLKADDR_NIX1; 317 } 318 319 if (blktype == BLKTYPE_CPT) { 320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 321 RVU_PRIV_HWVFX_CPTX_CFG(0); 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 323 if (cfg) { 324 blkaddr = BLKADDR_CPT0; 325 goto exit; 326 } 327 328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 329 RVU_PRIV_HWVFX_CPTX_CFG(1); 330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 331 if (cfg) 332 blkaddr = BLKADDR_CPT1; 333 } 334 335 exit: 336 if (is_block_implemented(rvu->hw, blkaddr)) 337 return blkaddr; 338 return -ENODEV; 339 } 340 341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 342 struct rvu_block *block, u16 pcifunc, 343 u16 lf, bool attach) 344 { 345 int devnum, num_lfs = 0; 346 bool is_pf; 347 u64 reg; 348 349 if (lf >= block->lf.max) { 350 dev_err(&rvu->pdev->dev, 351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 352 __func__, lf, block->name, block->lf.max); 353 return; 354 } 355 356 /* Check if this is for a RVU PF or VF */ 357 if (pcifunc & RVU_PFVF_FUNC_MASK) { 358 is_pf = false; 359 devnum = rvu_get_hwvf(rvu, pcifunc); 360 } else { 361 is_pf = true; 362 devnum = rvu_get_pf(rvu->pdev, pcifunc); 363 } 364 365 block->fn_map[lf] = attach ? pcifunc : 0; 366 367 switch (block->addr) { 368 case BLKADDR_NPA: 369 pfvf->npalf = attach ? true : false; 370 num_lfs = pfvf->npalf; 371 break; 372 case BLKADDR_NIX0: 373 case BLKADDR_NIX1: 374 pfvf->nixlf = attach ? true : false; 375 num_lfs = pfvf->nixlf; 376 break; 377 case BLKADDR_SSO: 378 attach ? pfvf->sso++ : pfvf->sso--; 379 num_lfs = pfvf->sso; 380 break; 381 case BLKADDR_SSOW: 382 attach ? pfvf->ssow++ : pfvf->ssow--; 383 num_lfs = pfvf->ssow; 384 break; 385 case BLKADDR_TIM: 386 attach ? pfvf->timlfs++ : pfvf->timlfs--; 387 num_lfs = pfvf->timlfs; 388 break; 389 case BLKADDR_CPT0: 390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 391 num_lfs = pfvf->cptlfs; 392 break; 393 case BLKADDR_CPT1: 394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 395 num_lfs = pfvf->cpt1_lfs; 396 break; 397 } 398 399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 401 } 402 403 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 404 { 405 u64 cfg; 406 407 /* Get numVFs attached to this PF and first HWVF */ 408 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 409 if (numvfs) 410 *numvfs = (cfg >> 12) & 0xFF; 411 if (hwvf) 412 *hwvf = cfg & 0xFFF; 413 } 414 415 int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 416 { 417 int pf, func; 418 u64 cfg; 419 420 pf = rvu_get_pf(rvu->pdev, pcifunc); 421 func = pcifunc & RVU_PFVF_FUNC_MASK; 422 423 /* Get first HWVF attached to this PF */ 424 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 425 426 return ((cfg & 0xFFF) + func - 1); 427 } 428 429 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 430 { 431 /* Check if it is a PF or VF */ 432 if (pcifunc & RVU_PFVF_FUNC_MASK) 433 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 434 else 435 return &rvu->pf[rvu_get_pf(rvu->pdev, pcifunc)]; 436 } 437 438 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 439 { 440 int pf, vf, nvfs; 441 u64 cfg; 442 443 pf = rvu_get_pf(rvu->pdev, pcifunc); 444 if (pf >= rvu->hw->total_pfs) 445 return false; 446 447 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 448 return true; 449 450 /* Check if VF is within number of VFs attached to this PF */ 451 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 452 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 453 nvfs = (cfg >> 12) & 0xFF; 454 if (vf >= nvfs) 455 return false; 456 457 return true; 458 } 459 460 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 461 { 462 struct rvu_block *block; 463 464 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 465 return false; 466 467 block = &hw->block[blkaddr]; 468 return block->implemented; 469 } 470 471 static void rvu_check_block_implemented(struct rvu *rvu) 472 { 473 struct rvu_hwinfo *hw = rvu->hw; 474 struct rvu_block *block; 475 int blkid; 476 u64 cfg; 477 478 /* For each block check if 'implemented' bit is set */ 479 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 480 block = &hw->block[blkid]; 481 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 482 if (cfg & BIT_ULL(11)) 483 block->implemented = true; 484 } 485 } 486 487 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 488 { 489 rvu_write64(rvu, BLKADDR_RVUM, 490 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 491 RVU_BLK_RVUM_REVID); 492 } 493 494 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 495 { 496 rvu_write64(rvu, BLKADDR_RVUM, 497 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 498 } 499 500 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 501 { 502 int err; 503 504 if (!block->implemented) 505 return 0; 506 507 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 508 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 509 true); 510 return err; 511 } 512 513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 514 { 515 struct rvu_block *block = &rvu->hw->block[blkaddr]; 516 int err; 517 518 if (!block->implemented) 519 return; 520 521 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 522 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 523 if (err) { 524 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); 525 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) 526 ; 527 } 528 } 529 530 static void rvu_reset_all_blocks(struct rvu *rvu) 531 { 532 /* Do a HW reset of all RVU blocks */ 533 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 534 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 535 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 536 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 537 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 538 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 539 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 543 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 544 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 545 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 546 } 547 548 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 549 { 550 struct rvu_pfvf *pfvf; 551 u64 cfg; 552 int lf; 553 554 for (lf = 0; lf < block->lf.max; lf++) { 555 cfg = rvu_read64(rvu, block->addr, 556 block->lfcfg_reg | (lf << block->lfshift)); 557 if (!(cfg & BIT_ULL(63))) 558 continue; 559 560 /* Set this resource as being used */ 561 __set_bit(lf, block->lf.bmap); 562 563 /* Get, to whom this LF is attached */ 564 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 565 rvu_update_rsrc_map(rvu, pfvf, block, 566 (cfg >> 8) & 0xFFFF, lf, true); 567 568 /* Set start MSIX vector for this LF within this PF/VF */ 569 rvu_set_msix_offset(rvu, pfvf, block, lf); 570 } 571 } 572 573 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 574 { 575 int min_vecs; 576 577 if (!vf) 578 goto check_pf; 579 580 if (!nvecs) { 581 dev_warn(rvu->dev, 582 "PF%d:VF%d is configured with zero msix vectors, %d\n", 583 pf, vf - 1, nvecs); 584 } 585 return; 586 587 check_pf: 588 if (pf == 0) 589 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 590 else 591 min_vecs = RVU_PF_INT_VEC_CNT; 592 593 if (!(nvecs < min_vecs)) 594 return; 595 dev_warn(rvu->dev, 596 "PF%d is configured with too few vectors, %d, min is %d\n", 597 pf, nvecs, min_vecs); 598 } 599 600 static int rvu_setup_msix_resources(struct rvu *rvu) 601 { 602 struct rvu_hwinfo *hw = rvu->hw; 603 int pf, vf, numvfs, hwvf, err; 604 int nvecs, offset, max_msix; 605 struct rvu_pfvf *pfvf; 606 u64 cfg, phy_addr; 607 dma_addr_t iova; 608 609 for (pf = 0; pf < hw->total_pfs; pf++) { 610 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 611 /* If PF is not enabled, nothing to do */ 612 if (!((cfg >> 20) & 0x01)) 613 continue; 614 615 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 616 617 pfvf = &rvu->pf[pf]; 618 /* Get num of MSIX vectors attached to this PF */ 619 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 620 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 621 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 622 623 /* Alloc msix bitmap for this PF */ 624 err = rvu_alloc_bitmap(&pfvf->msix); 625 if (err) 626 return err; 627 628 /* Allocate memory for MSIX vector to RVU block LF mapping */ 629 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 630 sizeof(u16), GFP_KERNEL); 631 if (!pfvf->msix_lfmap) 632 return -ENOMEM; 633 634 /* For PF0 (AF) firmware will set msix vector offsets for 635 * AF, block AF and PF0_INT vectors, so jump to VFs. 636 */ 637 if (!pf) 638 goto setup_vfmsix; 639 640 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 641 * These are allocated on driver init and never freed, 642 * so no need to set 'msix_lfmap' for these. 643 */ 644 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 645 nvecs = (cfg >> 12) & 0xFF; 646 cfg &= ~0x7FFULL; 647 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 648 rvu_write64(rvu, BLKADDR_RVUM, 649 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 650 setup_vfmsix: 651 /* Alloc msix bitmap for VFs */ 652 for (vf = 0; vf < numvfs; vf++) { 653 pfvf = &rvu->hwvf[hwvf + vf]; 654 /* Get num of MSIX vectors attached to this VF */ 655 cfg = rvu_read64(rvu, BLKADDR_RVUM, 656 RVU_PRIV_PFX_MSIX_CFG(pf)); 657 pfvf->msix.max = (cfg & 0xFFF) + 1; 658 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 659 660 /* Alloc msix bitmap for this VF */ 661 err = rvu_alloc_bitmap(&pfvf->msix); 662 if (err) 663 return err; 664 665 pfvf->msix_lfmap = 666 devm_kcalloc(rvu->dev, pfvf->msix.max, 667 sizeof(u16), GFP_KERNEL); 668 if (!pfvf->msix_lfmap) 669 return -ENOMEM; 670 671 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 672 * These are allocated on driver init and never freed, 673 * so no need to set 'msix_lfmap' for these. 674 */ 675 cfg = rvu_read64(rvu, BLKADDR_RVUM, 676 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 677 nvecs = (cfg >> 12) & 0xFF; 678 cfg &= ~0x7FFULL; 679 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 680 rvu_write64(rvu, BLKADDR_RVUM, 681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 682 cfg | offset); 683 } 684 } 685 686 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 687 * create an IOMMU mapping for the physical address configured by 688 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 689 */ 690 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 691 max_msix = cfg & 0xFFFFF; 692 if (rvu->fwdata && rvu->fwdata->msixtr_base) 693 phy_addr = rvu->fwdata->msixtr_base; 694 else 695 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 696 697 iova = dma_map_resource(rvu->dev, phy_addr, 698 max_msix * PCI_MSIX_ENTRY_SIZE, 699 DMA_BIDIRECTIONAL, 0); 700 701 if (dma_mapping_error(rvu->dev, iova)) 702 return -ENOMEM; 703 704 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 705 rvu->msix_base_iova = iova; 706 rvu->msixtr_base_phy = phy_addr; 707 708 return 0; 709 } 710 711 static void rvu_reset_msix(struct rvu *rvu) 712 { 713 /* Restore msixtr base register */ 714 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 715 rvu->msixtr_base_phy); 716 } 717 718 static void rvu_free_hw_resources(struct rvu *rvu) 719 { 720 struct rvu_hwinfo *hw = rvu->hw; 721 struct rvu_block *block; 722 struct rvu_pfvf *pfvf; 723 int id, max_msix; 724 u64 cfg; 725 726 rvu_npa_freemem(rvu); 727 rvu_npc_freemem(rvu); 728 rvu_nix_freemem(rvu); 729 730 /* Free block LF bitmaps */ 731 for (id = 0; id < BLK_COUNT; id++) { 732 block = &hw->block[id]; 733 kfree(block->lf.bmap); 734 } 735 736 /* Free MSIX bitmaps */ 737 for (id = 0; id < hw->total_pfs; id++) { 738 pfvf = &rvu->pf[id]; 739 kfree(pfvf->msix.bmap); 740 } 741 742 for (id = 0; id < hw->total_vfs; id++) { 743 pfvf = &rvu->hwvf[id]; 744 kfree(pfvf->msix.bmap); 745 } 746 747 /* Unmap MSIX vector base IOVA mapping */ 748 if (!rvu->msix_base_iova) 749 return; 750 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 751 max_msix = cfg & 0xFFFFF; 752 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 753 max_msix * PCI_MSIX_ENTRY_SIZE, 754 DMA_BIDIRECTIONAL, 0); 755 756 rvu_reset_msix(rvu); 757 mutex_destroy(&rvu->rsrc_lock); 758 759 /* Free the QINT/CINT memory */ 760 pfvf = &rvu->pf[RVU_AFPF]; 761 qmem_free(rvu->dev, pfvf->nix_qints_ctx); 762 qmem_free(rvu->dev, pfvf->cq_ints_ctx); 763 } 764 765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 766 { 767 struct rvu_hwinfo *hw = rvu->hw; 768 int pf, vf, numvfs, hwvf; 769 struct rvu_pfvf *pfvf; 770 u64 *mac; 771 772 for (pf = 0; pf < hw->total_pfs; pf++) { 773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 774 if (!pf) 775 goto lbkvf; 776 777 if (!is_pf_cgxmapped(rvu, pf)) 778 continue; 779 /* Assign MAC address to PF */ 780 pfvf = &rvu->pf[pf]; 781 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 782 mac = &rvu->fwdata->pf_macs[pf]; 783 if (*mac) 784 u64_to_ether_addr(*mac, pfvf->mac_addr); 785 else 786 eth_random_addr(pfvf->mac_addr); 787 } else { 788 eth_random_addr(pfvf->mac_addr); 789 } 790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 791 792 lbkvf: 793 /* Assign MAC address to VFs*/ 794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 795 for (vf = 0; vf < numvfs; vf++, hwvf++) { 796 pfvf = &rvu->hwvf[hwvf]; 797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 798 mac = &rvu->fwdata->vf_macs[hwvf]; 799 if (*mac) 800 u64_to_ether_addr(*mac, pfvf->mac_addr); 801 else 802 eth_random_addr(pfvf->mac_addr); 803 } else { 804 eth_random_addr(pfvf->mac_addr); 805 } 806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 807 } 808 } 809 } 810 811 static int rvu_fwdata_init(struct rvu *rvu) 812 { 813 u64 fwdbase; 814 int err; 815 816 /* Get firmware data base address */ 817 err = cgx_get_fwdata_base(&fwdbase); 818 if (err) 819 goto fail; 820 821 BUILD_BUG_ON(offsetof(struct rvu_fwdata, cgx_fw_data) > FWDATA_CGX_LMAC_OFFSET); 822 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 823 if (!rvu->fwdata) 824 goto fail; 825 if (!is_rvu_fwdata_valid(rvu)) { 826 dev_err(rvu->dev, 827 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 828 iounmap(rvu->fwdata); 829 rvu->fwdata = NULL; 830 return -EINVAL; 831 } 832 return 0; 833 fail: 834 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 835 return -EIO; 836 } 837 838 static void rvu_fwdata_exit(struct rvu *rvu) 839 { 840 if (rvu->fwdata) 841 iounmap(rvu->fwdata); 842 } 843 844 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 845 { 846 struct rvu_hwinfo *hw = rvu->hw; 847 struct rvu_block *block; 848 int blkid; 849 u64 cfg; 850 851 /* Init NIX LF's bitmap */ 852 block = &hw->block[blkaddr]; 853 if (!block->implemented) 854 return 0; 855 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 856 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 857 block->lf.max = cfg & 0xFFF; 858 block->addr = blkaddr; 859 block->type = BLKTYPE_NIX; 860 block->lfshift = 8; 861 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 862 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 863 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 864 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 865 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 866 block->lfreset_reg = NIX_AF_LF_RST; 867 block->rvu = rvu; 868 sprintf(block->name, "NIX%d", blkid); 869 rvu->nix_blkaddr[blkid] = blkaddr; 870 return rvu_alloc_bitmap(&block->lf); 871 } 872 873 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 874 { 875 struct rvu_hwinfo *hw = rvu->hw; 876 struct rvu_block *block; 877 int blkid; 878 u64 cfg; 879 880 /* Init CPT LF's bitmap */ 881 block = &hw->block[blkaddr]; 882 if (!block->implemented) 883 return 0; 884 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 885 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 886 block->lf.max = cfg & 0xFF; 887 block->addr = blkaddr; 888 block->type = BLKTYPE_CPT; 889 block->multislot = true; 890 block->lfshift = 3; 891 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 892 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 893 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 894 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 895 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 896 block->lfreset_reg = CPT_AF_LF_RST; 897 block->rvu = rvu; 898 sprintf(block->name, "CPT%d", blkid); 899 return rvu_alloc_bitmap(&block->lf); 900 } 901 902 static void rvu_get_lbk_bufsize(struct rvu *rvu) 903 { 904 struct pci_dev *pdev = NULL; 905 void __iomem *base; 906 u64 lbk_const; 907 908 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 909 PCI_DEVID_OCTEONTX2_LBK, pdev); 910 if (!pdev) 911 return; 912 913 base = pci_ioremap_bar(pdev, 0); 914 if (!base) 915 goto err_put; 916 917 lbk_const = readq(base + LBK_CONST); 918 919 /* cache fifo size */ 920 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 921 922 iounmap(base); 923 err_put: 924 pci_dev_put(pdev); 925 } 926 927 static int rvu_setup_hw_resources(struct rvu *rvu) 928 { 929 struct rvu_hwinfo *hw = rvu->hw; 930 struct rvu_block *block; 931 int blkid, err; 932 u64 cfg; 933 934 /* Get HW supported max RVU PF & VF count */ 935 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 936 hw->total_pfs = (cfg >> 32) & 0xFF; 937 hw->total_vfs = (cfg >> 20) & 0xFFF; 938 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 939 940 if (!is_rvu_otx2(rvu)) 941 rvu_apr_block_cn10k_init(rvu); 942 943 /* Init NPA LF's bitmap */ 944 block = &hw->block[BLKADDR_NPA]; 945 if (!block->implemented) 946 goto nix; 947 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 948 block->lf.max = (cfg >> 16) & 0xFFF; 949 block->addr = BLKADDR_NPA; 950 block->type = BLKTYPE_NPA; 951 block->lfshift = 8; 952 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 953 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 954 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 955 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 956 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 957 block->lfreset_reg = NPA_AF_LF_RST; 958 block->rvu = rvu; 959 sprintf(block->name, "NPA"); 960 err = rvu_alloc_bitmap(&block->lf); 961 if (err) { 962 dev_err(rvu->dev, 963 "%s: Failed to allocate NPA LF bitmap\n", __func__); 964 return err; 965 } 966 967 nix: 968 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 969 if (err) { 970 dev_err(rvu->dev, 971 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 972 return err; 973 } 974 975 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 976 if (err) { 977 dev_err(rvu->dev, 978 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 979 return err; 980 } 981 982 /* Init SSO group's bitmap */ 983 block = &hw->block[BLKADDR_SSO]; 984 if (!block->implemented) 985 goto ssow; 986 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 987 block->lf.max = cfg & 0xFFFF; 988 block->addr = BLKADDR_SSO; 989 block->type = BLKTYPE_SSO; 990 block->multislot = true; 991 block->lfshift = 3; 992 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 993 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 994 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 995 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 996 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 997 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 998 block->rvu = rvu; 999 sprintf(block->name, "SSO GROUP"); 1000 err = rvu_alloc_bitmap(&block->lf); 1001 if (err) { 1002 dev_err(rvu->dev, 1003 "%s: Failed to allocate SSO LF bitmap\n", __func__); 1004 return err; 1005 } 1006 1007 ssow: 1008 /* Init SSO workslot's bitmap */ 1009 block = &hw->block[BLKADDR_SSOW]; 1010 if (!block->implemented) 1011 goto tim; 1012 block->lf.max = (cfg >> 56) & 0xFF; 1013 block->addr = BLKADDR_SSOW; 1014 block->type = BLKTYPE_SSOW; 1015 block->multislot = true; 1016 block->lfshift = 3; 1017 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1018 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1019 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1020 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1021 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1022 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1023 block->rvu = rvu; 1024 sprintf(block->name, "SSOWS"); 1025 err = rvu_alloc_bitmap(&block->lf); 1026 if (err) { 1027 dev_err(rvu->dev, 1028 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1029 return err; 1030 } 1031 1032 tim: 1033 /* Init TIM LF's bitmap */ 1034 block = &hw->block[BLKADDR_TIM]; 1035 if (!block->implemented) 1036 goto cpt; 1037 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1038 block->lf.max = cfg & 0xFFFF; 1039 block->addr = BLKADDR_TIM; 1040 block->type = BLKTYPE_TIM; 1041 block->multislot = true; 1042 block->lfshift = 3; 1043 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1044 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1045 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1046 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1047 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1048 block->lfreset_reg = TIM_AF_LF_RST; 1049 block->rvu = rvu; 1050 sprintf(block->name, "TIM"); 1051 err = rvu_alloc_bitmap(&block->lf); 1052 if (err) { 1053 dev_err(rvu->dev, 1054 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1055 return err; 1056 } 1057 1058 cpt: 1059 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1060 if (err) { 1061 dev_err(rvu->dev, 1062 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1063 return err; 1064 } 1065 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1066 if (err) { 1067 dev_err(rvu->dev, 1068 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1069 return err; 1070 } 1071 1072 /* Allocate memory for PFVF data */ 1073 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1074 sizeof(struct rvu_pfvf), GFP_KERNEL); 1075 if (!rvu->pf) { 1076 dev_err(rvu->dev, 1077 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1078 return -ENOMEM; 1079 } 1080 1081 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1082 sizeof(struct rvu_pfvf), GFP_KERNEL); 1083 if (!rvu->hwvf) { 1084 dev_err(rvu->dev, 1085 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1086 return -ENOMEM; 1087 } 1088 1089 mutex_init(&rvu->rsrc_lock); 1090 1091 rvu_fwdata_init(rvu); 1092 1093 err = rvu_setup_msix_resources(rvu); 1094 if (err) { 1095 dev_err(rvu->dev, 1096 "%s: Failed to setup MSIX resources\n", __func__); 1097 return err; 1098 } 1099 1100 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1101 block = &hw->block[blkid]; 1102 if (!block->lf.bmap) 1103 continue; 1104 1105 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1106 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1107 sizeof(u16), GFP_KERNEL); 1108 if (!block->fn_map) { 1109 err = -ENOMEM; 1110 goto msix_err; 1111 } 1112 1113 /* Scan all blocks to check if low level firmware has 1114 * already provisioned any of the resources to a PF/VF. 1115 */ 1116 rvu_scan_block(rvu, block); 1117 } 1118 1119 err = rvu_set_channels_base(rvu); 1120 if (err) 1121 goto msix_err; 1122 1123 err = rvu_npc_init(rvu); 1124 if (err) { 1125 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1126 goto npc_err; 1127 } 1128 1129 err = rvu_cgx_init(rvu); 1130 if (err) { 1131 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1132 goto cgx_err; 1133 } 1134 1135 err = rvu_npc_exact_init(rvu); 1136 if (err) { 1137 dev_err(rvu->dev, "failed to initialize exact match table\n"); 1138 return err; 1139 } 1140 1141 /* Assign MACs for CGX mapped functions */ 1142 rvu_setup_pfvf_macaddress(rvu); 1143 1144 err = rvu_npa_init(rvu); 1145 if (err) { 1146 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1147 goto npa_err; 1148 } 1149 1150 rvu_get_lbk_bufsize(rvu); 1151 1152 err = rvu_nix_init(rvu); 1153 if (err) { 1154 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1155 goto nix_err; 1156 } 1157 1158 err = rvu_sdp_init(rvu); 1159 if (err) { 1160 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1161 goto nix_err; 1162 } 1163 1164 rvu_program_channels(rvu); 1165 cgx_start_linkup(rvu); 1166 1167 rvu_block_bcast_xon(rvu, BLKADDR_NIX0); 1168 rvu_block_bcast_xon(rvu, BLKADDR_NIX1); 1169 1170 err = rvu_mcs_init(rvu); 1171 if (err) { 1172 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); 1173 goto nix_err; 1174 } 1175 1176 err = rvu_cpt_init(rvu); 1177 if (err) { 1178 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__); 1179 goto mcs_err; 1180 } 1181 1182 return 0; 1183 1184 mcs_err: 1185 rvu_mcs_exit(rvu); 1186 nix_err: 1187 rvu_nix_freemem(rvu); 1188 npa_err: 1189 rvu_npa_freemem(rvu); 1190 cgx_err: 1191 rvu_cgx_exit(rvu); 1192 npc_err: 1193 rvu_npc_freemem(rvu); 1194 rvu_fwdata_exit(rvu); 1195 msix_err: 1196 rvu_reset_msix(rvu); 1197 return err; 1198 } 1199 1200 /* NPA and NIX admin queue APIs */ 1201 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1202 { 1203 if (!aq) 1204 return; 1205 1206 qmem_free(rvu->dev, aq->inst); 1207 qmem_free(rvu->dev, aq->res); 1208 devm_kfree(rvu->dev, aq); 1209 } 1210 1211 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1212 int qsize, int inst_size, int res_size) 1213 { 1214 struct admin_queue *aq; 1215 int err; 1216 1217 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1218 if (!*ad_queue) 1219 return -ENOMEM; 1220 aq = *ad_queue; 1221 1222 /* Alloc memory for instructions i.e AQ */ 1223 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1224 if (err) { 1225 devm_kfree(rvu->dev, aq); 1226 return err; 1227 } 1228 1229 /* Alloc memory for results */ 1230 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1231 if (err) { 1232 rvu_aq_free(rvu, aq); 1233 return err; 1234 } 1235 1236 spin_lock_init(&aq->lock); 1237 return 0; 1238 } 1239 1240 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1241 struct ready_msg_rsp *rsp) 1242 { 1243 if (rvu->fwdata) { 1244 rsp->rclk_freq = rvu->fwdata->rclk; 1245 rsp->sclk_freq = rvu->fwdata->sclk; 1246 } 1247 return 0; 1248 } 1249 1250 /* Get current count of a RVU block's LF/slots 1251 * provisioned to a given RVU func. 1252 */ 1253 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1254 { 1255 switch (blkaddr) { 1256 case BLKADDR_NPA: 1257 return pfvf->npalf ? 1 : 0; 1258 case BLKADDR_NIX0: 1259 case BLKADDR_NIX1: 1260 return pfvf->nixlf ? 1 : 0; 1261 case BLKADDR_SSO: 1262 return pfvf->sso; 1263 case BLKADDR_SSOW: 1264 return pfvf->ssow; 1265 case BLKADDR_TIM: 1266 return pfvf->timlfs; 1267 case BLKADDR_CPT0: 1268 return pfvf->cptlfs; 1269 case BLKADDR_CPT1: 1270 return pfvf->cpt1_lfs; 1271 } 1272 return 0; 1273 } 1274 1275 /* Return true if LFs of block type are attached to pcifunc */ 1276 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1277 { 1278 switch (blktype) { 1279 case BLKTYPE_NPA: 1280 return pfvf->npalf ? 1 : 0; 1281 case BLKTYPE_NIX: 1282 return pfvf->nixlf ? 1 : 0; 1283 case BLKTYPE_SSO: 1284 return !!pfvf->sso; 1285 case BLKTYPE_SSOW: 1286 return !!pfvf->ssow; 1287 case BLKTYPE_TIM: 1288 return !!pfvf->timlfs; 1289 case BLKTYPE_CPT: 1290 return pfvf->cptlfs || pfvf->cpt1_lfs; 1291 } 1292 1293 return false; 1294 } 1295 1296 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1297 { 1298 struct rvu_pfvf *pfvf; 1299 1300 if (!is_pf_func_valid(rvu, pcifunc)) 1301 return false; 1302 1303 pfvf = rvu_get_pfvf(rvu, pcifunc); 1304 1305 /* Check if this PFFUNC has a LF of type blktype attached */ 1306 if (!is_blktype_attached(pfvf, blktype)) 1307 return false; 1308 1309 return true; 1310 } 1311 1312 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1313 int pcifunc, int slot) 1314 { 1315 u64 val; 1316 1317 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1318 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1319 /* Wait for the lookup to finish */ 1320 /* TODO: put some timeout here */ 1321 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1322 ; 1323 1324 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1325 1326 /* Check LF valid bit */ 1327 if (!(val & (1ULL << 12))) 1328 return -1; 1329 1330 return (val & 0xFFF); 1331 } 1332 1333 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1334 u16 global_slot, u16 *slot_in_block) 1335 { 1336 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1337 int numlfs, total_lfs = 0, nr_blocks = 0; 1338 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1339 struct rvu_block *block; 1340 int blkaddr; 1341 u16 start_slot; 1342 1343 if (!is_blktype_attached(pfvf, blktype)) 1344 return -ENODEV; 1345 1346 /* Get all the block addresses from which LFs are attached to 1347 * the given pcifunc in num_blkaddr[]. 1348 */ 1349 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1350 block = &rvu->hw->block[blkaddr]; 1351 if (block->type != blktype) 1352 continue; 1353 if (!is_block_implemented(rvu->hw, blkaddr)) 1354 continue; 1355 1356 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1357 if (numlfs) { 1358 total_lfs += numlfs; 1359 num_blkaddr[nr_blocks] = blkaddr; 1360 nr_blocks++; 1361 } 1362 } 1363 1364 if (global_slot >= total_lfs) 1365 return -ENODEV; 1366 1367 /* Based on the given global slot number retrieve the 1368 * correct block address out of all attached block 1369 * addresses and slot number in that block. 1370 */ 1371 total_lfs = 0; 1372 blkaddr = -ENODEV; 1373 for (i = 0; i < nr_blocks; i++) { 1374 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1375 total_lfs += numlfs; 1376 if (global_slot < total_lfs) { 1377 blkaddr = num_blkaddr[i]; 1378 start_slot = total_lfs - numlfs; 1379 *slot_in_block = global_slot - start_slot; 1380 break; 1381 } 1382 } 1383 1384 return blkaddr; 1385 } 1386 1387 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1388 { 1389 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1390 struct rvu_hwinfo *hw = rvu->hw; 1391 struct rvu_block *block; 1392 int slot, lf, num_lfs; 1393 int blkaddr; 1394 1395 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1396 if (blkaddr < 0) 1397 return; 1398 1399 1400 block = &hw->block[blkaddr]; 1401 1402 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1403 if (!num_lfs) 1404 return; 1405 1406 for (slot = 0; slot < num_lfs; slot++) { 1407 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1408 if (lf < 0) /* This should never happen */ 1409 continue; 1410 1411 if (blktype == BLKTYPE_NIX) { 1412 rvu_nix_reset_mac(pfvf, pcifunc); 1413 rvu_npc_clear_ucast_entry(rvu, pcifunc, lf); 1414 } 1415 /* Disable the LF */ 1416 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1417 (lf << block->lfshift), 0x00ULL); 1418 1419 /* Update SW maintained mapping info as well */ 1420 rvu_update_rsrc_map(rvu, pfvf, block, 1421 pcifunc, lf, false); 1422 1423 /* Free the resource */ 1424 rvu_free_rsrc(&block->lf, lf); 1425 1426 /* Clear MSIX vector offset for this LF */ 1427 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1428 } 1429 } 1430 1431 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1432 u16 pcifunc) 1433 { 1434 struct rvu_hwinfo *hw = rvu->hw; 1435 bool detach_all = true; 1436 struct rvu_block *block; 1437 int blkid; 1438 1439 mutex_lock(&rvu->rsrc_lock); 1440 1441 /* Check for partial resource detach */ 1442 if (detach && detach->partial) 1443 detach_all = false; 1444 1445 /* Check for RVU block's LFs attached to this func, 1446 * if so, detach them. 1447 */ 1448 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1449 block = &hw->block[blkid]; 1450 if (!block->lf.bmap) 1451 continue; 1452 if (!detach_all && detach) { 1453 if (blkid == BLKADDR_NPA && !detach->npalf) 1454 continue; 1455 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1456 continue; 1457 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1458 continue; 1459 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1460 continue; 1461 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1462 continue; 1463 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1464 continue; 1465 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1466 continue; 1467 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1468 continue; 1469 } 1470 rvu_detach_block(rvu, pcifunc, block->type); 1471 } 1472 1473 mutex_unlock(&rvu->rsrc_lock); 1474 return 0; 1475 } 1476 1477 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1478 struct rsrc_detach *detach, 1479 struct msg_rsp *rsp) 1480 { 1481 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1482 } 1483 1484 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1485 { 1486 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1487 int blkaddr = BLKADDR_NIX0, vf; 1488 struct rvu_pfvf *pf; 1489 1490 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1491 1492 /* All CGX mapped PFs are set with assigned NIX block during init */ 1493 if (is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))) { 1494 blkaddr = pf->nix_blkaddr; 1495 } else if (is_lbk_vf(rvu, pcifunc)) { 1496 vf = pcifunc - 1; 1497 /* Assign NIX based on VF number. All even numbered VFs get 1498 * NIX0 and odd numbered gets NIX1 1499 */ 1500 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1501 /* NIX1 is not present on all silicons */ 1502 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1503 blkaddr = BLKADDR_NIX0; 1504 } 1505 1506 /* if SDP1 then the blkaddr is NIX1 */ 1507 if (is_sdp_pfvf(rvu, pcifunc) && pf->sdp_info->node_id == 1) 1508 blkaddr = BLKADDR_NIX1; 1509 1510 switch (blkaddr) { 1511 case BLKADDR_NIX1: 1512 pfvf->nix_blkaddr = BLKADDR_NIX1; 1513 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1514 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1515 break; 1516 case BLKADDR_NIX0: 1517 default: 1518 pfvf->nix_blkaddr = BLKADDR_NIX0; 1519 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1520 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1521 break; 1522 } 1523 1524 return pfvf->nix_blkaddr; 1525 } 1526 1527 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1528 u16 pcifunc, struct rsrc_attach *attach) 1529 { 1530 int blkaddr; 1531 1532 switch (blktype) { 1533 case BLKTYPE_NIX: 1534 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1535 break; 1536 case BLKTYPE_CPT: 1537 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1538 return rvu_get_blkaddr(rvu, blktype, 0); 1539 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1540 BLKADDR_CPT0; 1541 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1542 return -ENODEV; 1543 break; 1544 default: 1545 return rvu_get_blkaddr(rvu, blktype, 0); 1546 } 1547 1548 if (is_block_implemented(rvu->hw, blkaddr)) 1549 return blkaddr; 1550 1551 return -ENODEV; 1552 } 1553 1554 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1555 int num_lfs, struct rsrc_attach *attach) 1556 { 1557 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1558 struct rvu_hwinfo *hw = rvu->hw; 1559 struct rvu_block *block; 1560 int slot, lf; 1561 int blkaddr; 1562 u64 cfg; 1563 1564 if (!num_lfs) 1565 return; 1566 1567 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1568 if (blkaddr < 0) 1569 return; 1570 1571 block = &hw->block[blkaddr]; 1572 if (!block->lf.bmap) 1573 return; 1574 1575 for (slot = 0; slot < num_lfs; slot++) { 1576 /* Allocate the resource */ 1577 lf = rvu_alloc_rsrc(&block->lf); 1578 if (lf < 0) 1579 return; 1580 1581 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1582 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1583 (lf << block->lfshift), cfg); 1584 rvu_update_rsrc_map(rvu, pfvf, block, 1585 pcifunc, lf, true); 1586 1587 /* Set start MSIX vector for this LF within this PF/VF */ 1588 rvu_set_msix_offset(rvu, pfvf, block, lf); 1589 } 1590 } 1591 1592 static int rvu_check_rsrc_availability(struct rvu *rvu, 1593 struct rsrc_attach *req, u16 pcifunc) 1594 { 1595 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1596 int free_lfs, mappedlfs, blkaddr; 1597 struct rvu_hwinfo *hw = rvu->hw; 1598 struct rvu_block *block; 1599 1600 /* Only one NPA LF can be attached */ 1601 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1602 block = &hw->block[BLKADDR_NPA]; 1603 free_lfs = rvu_rsrc_free_count(&block->lf); 1604 if (!free_lfs) 1605 goto fail; 1606 } else if (req->npalf) { 1607 dev_err(&rvu->pdev->dev, 1608 "Func 0x%x: Invalid req, already has NPA\n", 1609 pcifunc); 1610 return -EINVAL; 1611 } 1612 1613 /* Only one NIX LF can be attached */ 1614 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1615 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1616 pcifunc, req); 1617 if (blkaddr < 0) 1618 return blkaddr; 1619 block = &hw->block[blkaddr]; 1620 free_lfs = rvu_rsrc_free_count(&block->lf); 1621 if (!free_lfs) 1622 goto fail; 1623 } else if (req->nixlf) { 1624 dev_err(&rvu->pdev->dev, 1625 "Func 0x%x: Invalid req, already has NIX\n", 1626 pcifunc); 1627 return -EINVAL; 1628 } 1629 1630 if (req->sso) { 1631 block = &hw->block[BLKADDR_SSO]; 1632 /* Is request within limits ? */ 1633 if (req->sso > block->lf.max) { 1634 dev_err(&rvu->pdev->dev, 1635 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1636 pcifunc, req->sso, block->lf.max); 1637 return -EINVAL; 1638 } 1639 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1640 free_lfs = rvu_rsrc_free_count(&block->lf); 1641 /* Check if additional resources are available */ 1642 if (req->sso > mappedlfs && 1643 ((req->sso - mappedlfs) > free_lfs)) 1644 goto fail; 1645 } 1646 1647 if (req->ssow) { 1648 block = &hw->block[BLKADDR_SSOW]; 1649 if (req->ssow > block->lf.max) { 1650 dev_err(&rvu->pdev->dev, 1651 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1652 pcifunc, req->ssow, block->lf.max); 1653 return -EINVAL; 1654 } 1655 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1656 free_lfs = rvu_rsrc_free_count(&block->lf); 1657 if (req->ssow > mappedlfs && 1658 ((req->ssow - mappedlfs) > free_lfs)) 1659 goto fail; 1660 } 1661 1662 if (req->timlfs) { 1663 block = &hw->block[BLKADDR_TIM]; 1664 if (req->timlfs > block->lf.max) { 1665 dev_err(&rvu->pdev->dev, 1666 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1667 pcifunc, req->timlfs, block->lf.max); 1668 return -EINVAL; 1669 } 1670 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1671 free_lfs = rvu_rsrc_free_count(&block->lf); 1672 if (req->timlfs > mappedlfs && 1673 ((req->timlfs - mappedlfs) > free_lfs)) 1674 goto fail; 1675 } 1676 1677 if (req->cptlfs) { 1678 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1679 pcifunc, req); 1680 if (blkaddr < 0) 1681 return blkaddr; 1682 block = &hw->block[blkaddr]; 1683 if (req->cptlfs > block->lf.max) { 1684 dev_err(&rvu->pdev->dev, 1685 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1686 pcifunc, req->cptlfs, block->lf.max); 1687 return -EINVAL; 1688 } 1689 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1690 free_lfs = rvu_rsrc_free_count(&block->lf); 1691 if (req->cptlfs > mappedlfs && 1692 ((req->cptlfs - mappedlfs) > free_lfs)) 1693 goto fail; 1694 } 1695 1696 return 0; 1697 1698 fail: 1699 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1700 return -ENOSPC; 1701 } 1702 1703 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1704 struct rsrc_attach *attach) 1705 { 1706 int blkaddr, num_lfs; 1707 1708 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1709 attach->hdr.pcifunc, attach); 1710 if (blkaddr < 0) 1711 return false; 1712 1713 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1714 blkaddr); 1715 /* Requester already has LFs from given block ? */ 1716 return !!num_lfs; 1717 } 1718 1719 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1720 struct rsrc_attach *attach, 1721 struct msg_rsp *rsp) 1722 { 1723 u16 pcifunc = attach->hdr.pcifunc; 1724 int err; 1725 1726 /* If first request, detach all existing attached resources */ 1727 if (!attach->modify) 1728 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1729 1730 mutex_lock(&rvu->rsrc_lock); 1731 1732 /* Check if the request can be accommodated */ 1733 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1734 if (err) 1735 goto exit; 1736 1737 /* Now attach the requested resources */ 1738 if (attach->npalf) 1739 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1740 1741 if (attach->nixlf) 1742 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1743 1744 if (attach->sso) { 1745 /* RVU func doesn't know which exact LF or slot is attached 1746 * to it, it always sees as slot 0,1,2. So for a 'modify' 1747 * request, simply detach all existing attached LFs/slots 1748 * and attach a fresh. 1749 */ 1750 if (attach->modify) 1751 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1752 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1753 attach->sso, attach); 1754 } 1755 1756 if (attach->ssow) { 1757 if (attach->modify) 1758 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1759 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1760 attach->ssow, attach); 1761 } 1762 1763 if (attach->timlfs) { 1764 if (attach->modify) 1765 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1766 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1767 attach->timlfs, attach); 1768 } 1769 1770 if (attach->cptlfs) { 1771 if (attach->modify && 1772 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1773 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1774 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1775 attach->cptlfs, attach); 1776 } 1777 1778 exit: 1779 mutex_unlock(&rvu->rsrc_lock); 1780 return err; 1781 } 1782 1783 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1784 int blkaddr, int lf) 1785 { 1786 u16 vec; 1787 1788 if (lf < 0) 1789 return MSIX_VECTOR_INVALID; 1790 1791 for (vec = 0; vec < pfvf->msix.max; vec++) { 1792 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1793 return vec; 1794 } 1795 return MSIX_VECTOR_INVALID; 1796 } 1797 1798 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1799 struct rvu_block *block, int lf) 1800 { 1801 u16 nvecs, vec, offset; 1802 u64 cfg; 1803 1804 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1805 (lf << block->lfshift)); 1806 nvecs = (cfg >> 12) & 0xFF; 1807 1808 /* Check and alloc MSIX vectors, must be contiguous */ 1809 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1810 return; 1811 1812 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1813 1814 /* Config MSIX offset in LF */ 1815 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1816 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1817 1818 /* Update the bitmap as well */ 1819 for (vec = 0; vec < nvecs; vec++) 1820 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1821 } 1822 1823 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1824 struct rvu_block *block, int lf) 1825 { 1826 u16 nvecs, vec, offset; 1827 u64 cfg; 1828 1829 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1830 (lf << block->lfshift)); 1831 nvecs = (cfg >> 12) & 0xFF; 1832 1833 /* Clear MSIX offset in LF */ 1834 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1835 (lf << block->lfshift), cfg & ~0x7FFULL); 1836 1837 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1838 1839 /* Update the mapping */ 1840 for (vec = 0; vec < nvecs; vec++) 1841 pfvf->msix_lfmap[offset + vec] = 0; 1842 1843 /* Free the same in MSIX bitmap */ 1844 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1845 } 1846 1847 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1848 struct msix_offset_rsp *rsp) 1849 { 1850 struct rvu_hwinfo *hw = rvu->hw; 1851 u16 pcifunc = req->hdr.pcifunc; 1852 struct rvu_pfvf *pfvf; 1853 int lf, slot, blkaddr; 1854 1855 pfvf = rvu_get_pfvf(rvu, pcifunc); 1856 if (!pfvf->msix.bmap) 1857 return 0; 1858 1859 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1860 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1861 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1862 1863 /* Get BLKADDR from which LFs are attached to pcifunc */ 1864 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1865 if (blkaddr < 0) { 1866 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1867 } else { 1868 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1869 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1870 } 1871 1872 rsp->sso = pfvf->sso; 1873 for (slot = 0; slot < rsp->sso; slot++) { 1874 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1875 rsp->sso_msixoff[slot] = 1876 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1877 } 1878 1879 rsp->ssow = pfvf->ssow; 1880 for (slot = 0; slot < rsp->ssow; slot++) { 1881 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1882 rsp->ssow_msixoff[slot] = 1883 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1884 } 1885 1886 rsp->timlfs = pfvf->timlfs; 1887 for (slot = 0; slot < rsp->timlfs; slot++) { 1888 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1889 rsp->timlf_msixoff[slot] = 1890 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1891 } 1892 1893 rsp->cptlfs = pfvf->cptlfs; 1894 for (slot = 0; slot < rsp->cptlfs; slot++) { 1895 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1896 rsp->cptlf_msixoff[slot] = 1897 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1898 } 1899 1900 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1901 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1902 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1903 rsp->cpt1_lf_msixoff[slot] = 1904 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1905 } 1906 1907 return 0; 1908 } 1909 1910 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1911 struct free_rsrcs_rsp *rsp) 1912 { 1913 struct rvu_hwinfo *hw = rvu->hw; 1914 struct rvu_block *block; 1915 struct nix_txsch *txsch; 1916 struct nix_hw *nix_hw; 1917 1918 mutex_lock(&rvu->rsrc_lock); 1919 1920 block = &hw->block[BLKADDR_NPA]; 1921 rsp->npa = rvu_rsrc_free_count(&block->lf); 1922 1923 block = &hw->block[BLKADDR_NIX0]; 1924 rsp->nix = rvu_rsrc_free_count(&block->lf); 1925 1926 block = &hw->block[BLKADDR_NIX1]; 1927 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1928 1929 block = &hw->block[BLKADDR_SSO]; 1930 rsp->sso = rvu_rsrc_free_count(&block->lf); 1931 1932 block = &hw->block[BLKADDR_SSOW]; 1933 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1934 1935 block = &hw->block[BLKADDR_TIM]; 1936 rsp->tim = rvu_rsrc_free_count(&block->lf); 1937 1938 block = &hw->block[BLKADDR_CPT0]; 1939 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1940 1941 block = &hw->block[BLKADDR_CPT1]; 1942 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1943 1944 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1945 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1946 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1947 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1948 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1949 /* NIX1 */ 1950 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1951 goto out; 1952 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1953 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1954 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1955 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1956 } else { 1957 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1958 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1959 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1960 rvu_rsrc_free_count(&txsch->schq); 1961 1962 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1963 rsp->schq[NIX_TXSCH_LVL_TL4] = 1964 rvu_rsrc_free_count(&txsch->schq); 1965 1966 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1967 rsp->schq[NIX_TXSCH_LVL_TL3] = 1968 rvu_rsrc_free_count(&txsch->schq); 1969 1970 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1971 rsp->schq[NIX_TXSCH_LVL_TL2] = 1972 rvu_rsrc_free_count(&txsch->schq); 1973 1974 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1975 goto out; 1976 1977 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1978 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1979 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1980 rvu_rsrc_free_count(&txsch->schq); 1981 1982 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1983 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1984 rvu_rsrc_free_count(&txsch->schq); 1985 1986 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1987 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1988 rvu_rsrc_free_count(&txsch->schq); 1989 1990 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1991 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1992 rvu_rsrc_free_count(&txsch->schq); 1993 } 1994 1995 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1996 out: 1997 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1998 mutex_unlock(&rvu->rsrc_lock); 1999 2000 return 0; 2001 } 2002 2003 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 2004 struct msg_rsp *rsp) 2005 { 2006 u16 pcifunc = req->hdr.pcifunc; 2007 u16 vf, numvfs; 2008 u64 cfg; 2009 2010 vf = pcifunc & RVU_PFVF_FUNC_MASK; 2011 cfg = rvu_read64(rvu, BLKADDR_RVUM, 2012 RVU_PRIV_PFX_CFG(rvu_get_pf(rvu->pdev, pcifunc))); 2013 numvfs = (cfg >> 12) & 0xFF; 2014 2015 if (vf && vf <= numvfs) 2016 __rvu_flr_handler(rvu, pcifunc); 2017 else 2018 return RVU_INVALID_VF_ID; 2019 2020 return 0; 2021 } 2022 2023 int rvu_ndc_sync(struct rvu *rvu, int lfblkaddr, int lfidx, u64 lfoffset) 2024 { 2025 /* Sync cached info for this LF in NDC to LLC/DRAM */ 2026 rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx); 2027 return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true); 2028 } 2029 2030 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2031 struct get_hw_cap_rsp *rsp) 2032 { 2033 struct rvu_hwinfo *hw = rvu->hw; 2034 2035 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 2036 rsp->nix_shaping = hw->cap.nix_shaping; 2037 rsp->npc_hash_extract = hw->cap.npc_hash_extract; 2038 2039 if (rvu->mcs_blk_cnt) 2040 rsp->hw_caps = HW_CAP_MACSEC; 2041 2042 return 0; 2043 } 2044 2045 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 2046 struct msg_rsp *rsp) 2047 { 2048 struct rvu_hwinfo *hw = rvu->hw; 2049 u16 pcifunc = req->hdr.pcifunc; 2050 struct rvu_pfvf *pfvf; 2051 int blkaddr, nixlf; 2052 u16 target; 2053 2054 /* Only PF can add VF permissions */ 2055 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_lbk_vf(rvu, pcifunc)) 2056 return -EOPNOTSUPP; 2057 2058 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2059 pfvf = rvu_get_pfvf(rvu, target); 2060 2061 if (req->flags & RESET_VF_PERM) { 2062 pfvf->flags &= RVU_CLEAR_VF_PERM; 2063 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2064 (req->flags & VF_TRUSTED)) { 2065 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2066 /* disable multicast and promisc entries */ 2067 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2068 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2069 if (blkaddr < 0) 2070 return 0; 2071 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2072 target, 0); 2073 if (nixlf < 0) 2074 return 0; 2075 npc_enadis_default_mce_entry(rvu, target, nixlf, 2076 NIXLF_ALLMULTI_ENTRY, 2077 false); 2078 npc_enadis_default_mce_entry(rvu, target, nixlf, 2079 NIXLF_PROMISC_ENTRY, 2080 false); 2081 } 2082 } 2083 2084 return 0; 2085 } 2086 2087 int rvu_mbox_handler_ndc_sync_op(struct rvu *rvu, 2088 struct ndc_sync_op *req, 2089 struct msg_rsp *rsp) 2090 { 2091 struct rvu_hwinfo *hw = rvu->hw; 2092 u16 pcifunc = req->hdr.pcifunc; 2093 int err, lfidx, lfblkaddr; 2094 2095 if (req->npa_lf_sync) { 2096 /* Get NPA LF data */ 2097 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); 2098 if (lfblkaddr < 0) 2099 return NPA_AF_ERR_AF_LF_INVALID; 2100 2101 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2102 if (lfidx < 0) 2103 return NPA_AF_ERR_AF_LF_INVALID; 2104 2105 /* Sync NPA NDC */ 2106 err = rvu_ndc_sync(rvu, lfblkaddr, 2107 lfidx, NPA_AF_NDC_SYNC); 2108 if (err) 2109 dev_err(rvu->dev, 2110 "NDC-NPA sync failed for LF %u\n", lfidx); 2111 } 2112 2113 if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync) 2114 return 0; 2115 2116 /* Get NIX LF data */ 2117 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2118 if (lfblkaddr < 0) 2119 return NIX_AF_ERR_AF_LF_INVALID; 2120 2121 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2122 if (lfidx < 0) 2123 return NIX_AF_ERR_AF_LF_INVALID; 2124 2125 if (req->nix_lf_tx_sync) { 2126 /* Sync NIX TX NDC */ 2127 err = rvu_ndc_sync(rvu, lfblkaddr, 2128 lfidx, NIX_AF_NDC_TX_SYNC); 2129 if (err) 2130 dev_err(rvu->dev, 2131 "NDC-NIX-TX sync fail for LF %u\n", lfidx); 2132 } 2133 2134 if (req->nix_lf_rx_sync) { 2135 /* Sync NIX RX NDC */ 2136 err = rvu_ndc_sync(rvu, lfblkaddr, 2137 lfidx, NIX_AF_NDC_RX_SYNC); 2138 if (err) 2139 dev_err(rvu->dev, 2140 "NDC-NIX-RX sync failed for LF %u\n", lfidx); 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2147 struct mbox_msghdr *req) 2148 { 2149 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2150 2151 /* Check if valid, if not reply with a invalid msg */ 2152 if (req->sig != OTX2_MBOX_REQ_SIG) 2153 goto bad_message; 2154 2155 switch (req->id) { 2156 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2157 case _id: { \ 2158 struct _rsp_type *rsp; \ 2159 int err; \ 2160 \ 2161 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2162 mbox, devid, \ 2163 sizeof(struct _rsp_type)); \ 2164 /* some handlers should complete even if reply */ \ 2165 /* could not be allocated */ \ 2166 if (!rsp && \ 2167 _id != MBOX_MSG_DETACH_RESOURCES && \ 2168 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2169 _id != MBOX_MSG_VF_FLR) \ 2170 return -ENOMEM; \ 2171 if (rsp) { \ 2172 rsp->hdr.id = _id; \ 2173 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2174 rsp->hdr.pcifunc = req->pcifunc; \ 2175 rsp->hdr.rc = 0; \ 2176 } \ 2177 \ 2178 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2179 (struct _req_type *)req, \ 2180 rsp); \ 2181 if (rsp && err) \ 2182 rsp->hdr.rc = err; \ 2183 \ 2184 trace_otx2_msg_process(mbox->pdev, _id, err, req->pcifunc); \ 2185 return rsp ? err : -ENOMEM; \ 2186 } 2187 MBOX_MESSAGES 2188 #undef M 2189 2190 bad_message: 2191 default: 2192 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2193 return -ENODEV; 2194 } 2195 } 2196 2197 static void __rvu_mbox_handler(struct rvu_work *mwork, int type, bool poll) 2198 { 2199 struct rvu *rvu = mwork->rvu; 2200 int offset, err, id, devid; 2201 struct otx2_mbox_dev *mdev; 2202 struct mbox_hdr *req_hdr; 2203 struct mbox_msghdr *msg; 2204 struct mbox_wq_info *mw; 2205 struct otx2_mbox *mbox; 2206 2207 switch (type) { 2208 case TYPE_AFPF: 2209 mw = &rvu->afpf_wq_info; 2210 break; 2211 case TYPE_AFVF: 2212 mw = &rvu->afvf_wq_info; 2213 break; 2214 default: 2215 return; 2216 } 2217 2218 devid = mwork - mw->mbox_wrk; 2219 mbox = &mw->mbox; 2220 mdev = &mbox->dev[devid]; 2221 2222 /* Process received mbox messages */ 2223 req_hdr = mdev->mbase + mbox->rx_start; 2224 if (mw->mbox_wrk[devid].num_msgs == 0) 2225 return; 2226 2227 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2228 2229 if (req_hdr->sig && !(is_rvu_otx2(rvu) || is_cn20k(rvu->pdev))) { 2230 req_hdr->opt_msg = mw->mbox_wrk[devid].num_msgs; 2231 rvu_write64(rvu, BLKADDR_NIX0, RVU_AF_BAR2_SEL, 2232 RVU_AF_BAR2_PFID); 2233 if (type == TYPE_AFPF) 2234 rvu_write64(rvu, BLKADDR_NIX0, 2235 AF_BAR2_ALIASX(0, NIX_CINTX_INT_W1S(devid)), 2236 0x1); 2237 else 2238 rvu_write64(rvu, BLKADDR_NIX0, 2239 AF_BAR2_ALIASX(0, NIX_QINTX_CNT(devid)), 2240 0x1); 2241 usleep_range(5000, 6000); 2242 goto done; 2243 } 2244 2245 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2246 msg = mdev->mbase + offset; 2247 2248 /* Set which PF/VF sent this message based on mbox IRQ */ 2249 switch (type) { 2250 case TYPE_AFPF: 2251 msg->pcifunc &= rvu_pcifunc_pf_mask(rvu->pdev); 2252 msg->pcifunc |= rvu_make_pcifunc(rvu->pdev, devid, 0); 2253 break; 2254 case TYPE_AFVF: 2255 msg->pcifunc &= 2256 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2257 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2258 break; 2259 } 2260 2261 err = rvu_process_mbox_msg(mbox, devid, msg); 2262 if (!err) { 2263 offset = mbox->rx_start + msg->next_msgoff; 2264 continue; 2265 } 2266 2267 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2268 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2269 err, otx2_mbox_id2name(msg->id), 2270 msg->id, rvu_get_pf(rvu->pdev, msg->pcifunc), 2271 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2272 else 2273 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2274 err, otx2_mbox_id2name(msg->id), 2275 msg->id, devid); 2276 } 2277 done: 2278 mw->mbox_wrk[devid].num_msgs = 0; 2279 2280 if (!is_cn20k(mbox->pdev) && poll) 2281 otx2_mbox_wait_for_zero(mbox, devid); 2282 2283 /* Send mbox responses to VF/PF */ 2284 otx2_mbox_msg_send(mbox, devid); 2285 } 2286 2287 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2288 { 2289 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2290 struct rvu *rvu = mwork->rvu; 2291 2292 mutex_lock(&rvu->mbox_lock); 2293 __rvu_mbox_handler(mwork, TYPE_AFPF, true); 2294 mutex_unlock(&rvu->mbox_lock); 2295 } 2296 2297 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2298 { 2299 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2300 2301 __rvu_mbox_handler(mwork, TYPE_AFVF, false); 2302 } 2303 2304 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2305 { 2306 struct rvu *rvu = mwork->rvu; 2307 struct otx2_mbox_dev *mdev; 2308 struct mbox_hdr *rsp_hdr; 2309 struct mbox_msghdr *msg; 2310 struct mbox_wq_info *mw; 2311 struct otx2_mbox *mbox; 2312 int offset, id, devid; 2313 2314 switch (type) { 2315 case TYPE_AFPF: 2316 mw = &rvu->afpf_wq_info; 2317 break; 2318 case TYPE_AFVF: 2319 mw = &rvu->afvf_wq_info; 2320 break; 2321 default: 2322 return; 2323 } 2324 2325 devid = mwork - mw->mbox_wrk_up; 2326 mbox = &mw->mbox_up; 2327 mdev = &mbox->dev[devid]; 2328 2329 rsp_hdr = mdev->mbase + mbox->rx_start; 2330 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2331 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2332 return; 2333 } 2334 2335 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2336 2337 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2338 msg = mdev->mbase + offset; 2339 2340 if (msg->id >= MBOX_MSG_MAX) { 2341 dev_err(rvu->dev, 2342 "Mbox msg with unknown ID 0x%x\n", msg->id); 2343 goto end; 2344 } 2345 2346 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2347 dev_err(rvu->dev, 2348 "Mbox msg with wrong signature %x, ID 0x%x\n", 2349 msg->sig, msg->id); 2350 goto end; 2351 } 2352 2353 switch (msg->id) { 2354 case MBOX_MSG_CGX_LINK_EVENT: 2355 break; 2356 default: 2357 if (msg->rc) 2358 dev_err(rvu->dev, 2359 "Mbox msg response has err %d, ID 0x%x\n", 2360 msg->rc, msg->id); 2361 break; 2362 } 2363 end: 2364 offset = mbox->rx_start + msg->next_msgoff; 2365 mdev->msgs_acked++; 2366 } 2367 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2368 2369 otx2_mbox_reset(mbox, devid); 2370 } 2371 2372 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2373 { 2374 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2375 2376 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2377 } 2378 2379 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2380 { 2381 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2382 2383 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2384 } 2385 2386 static int rvu_get_mbox_regions(struct rvu *rvu, void __iomem **mbox_addr, 2387 int num, int type, unsigned long *pf_bmap) 2388 { 2389 struct rvu_hwinfo *hw = rvu->hw; 2390 int region; 2391 u64 bar4; 2392 2393 /* For cn20k platform AF mailbox region is allocated by software 2394 * and the corresponding IOVA is programmed in hardware unlike earlier 2395 * silicons where software uses the hardware region after ioremap. 2396 */ 2397 if (is_cn20k(rvu->pdev)) 2398 return cn20k_rvu_get_mbox_regions(rvu, (void *)mbox_addr, 2399 num, type, pf_bmap); 2400 2401 /* For cn10k platform VF mailbox regions of a PF follows after the 2402 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2403 * RVU_PF_VF_BAR4_ADDR register. 2404 */ 2405 if (type == TYPE_AFVF) { 2406 for (region = 0; region < num; region++) { 2407 if (!test_bit(region, pf_bmap)) 2408 continue; 2409 2410 if (hw->cap.per_pf_mbox_regs) { 2411 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2412 RVU_AF_PFX_BAR4_ADDR(0)) + 2413 MBOX_SIZE; 2414 bar4 += region * MBOX_SIZE; 2415 } else { 2416 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2417 bar4 += region * MBOX_SIZE; 2418 } 2419 mbox_addr[region] = ioremap_wc(bar4, MBOX_SIZE); 2420 if (!mbox_addr[region]) 2421 goto error; 2422 } 2423 return 0; 2424 } 2425 2426 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2427 * PF registers. Whereas for Octeontx2 it is read from 2428 * RVU_AF_PF_BAR4_ADDR register. 2429 */ 2430 for (region = 0; region < num; region++) { 2431 if (!test_bit(region, pf_bmap)) 2432 continue; 2433 2434 if (hw->cap.per_pf_mbox_regs) { 2435 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2436 RVU_AF_PFX_BAR4_ADDR(region)); 2437 } else { 2438 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2439 RVU_AF_PF_BAR4_ADDR); 2440 bar4 += region * MBOX_SIZE; 2441 } 2442 mbox_addr[region] = ioremap_wc(bar4, MBOX_SIZE); 2443 if (!mbox_addr[region]) 2444 goto error; 2445 } 2446 return 0; 2447 2448 error: 2449 while (region--) 2450 iounmap(mbox_addr[region]); 2451 return -ENOMEM; 2452 } 2453 2454 static struct mbox_ops rvu_mbox_ops = { 2455 .pf_intr_handler = rvu_mbox_pf_intr_handler, 2456 .afvf_intr_handler = rvu_mbox_intr_handler, 2457 }; 2458 2459 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2460 int type, int num, 2461 void (mbox_handler)(struct work_struct *), 2462 void (mbox_up_handler)(struct work_struct *)) 2463 { 2464 void __iomem **mbox_regions; 2465 struct ng_rvu *ng_rvu_mbox; 2466 int err, i, dir, dir_up; 2467 void __iomem *reg_base; 2468 struct rvu_work *mwork; 2469 unsigned long *pf_bmap; 2470 const char *name; 2471 u64 cfg; 2472 2473 pf_bmap = bitmap_zalloc(num, GFP_KERNEL); 2474 if (!pf_bmap) 2475 return -ENOMEM; 2476 2477 ng_rvu_mbox = kzalloc(sizeof(*ng_rvu_mbox), GFP_KERNEL); 2478 if (!ng_rvu_mbox) { 2479 err = -ENOMEM; 2480 goto free_bitmap; 2481 } 2482 2483 /* RVU VFs */ 2484 if (type == TYPE_AFVF) 2485 bitmap_set(pf_bmap, 0, num); 2486 2487 if (type == TYPE_AFPF) { 2488 /* Mark enabled PFs in bitmap */ 2489 for (i = 0; i < num; i++) { 2490 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i)); 2491 if (cfg & BIT_ULL(20)) 2492 set_bit(i, pf_bmap); 2493 } 2494 } 2495 2496 rvu->ng_rvu = ng_rvu_mbox; 2497 2498 rvu->ng_rvu->rvu_mbox_ops = &rvu_mbox_ops; 2499 2500 err = cn20k_rvu_mbox_init(rvu, type, num); 2501 if (err) 2502 goto free_mem; 2503 2504 mutex_init(&rvu->mbox_lock); 2505 2506 mbox_regions = kcalloc(num, sizeof(void __iomem *), GFP_KERNEL); 2507 if (!mbox_regions) { 2508 err = -ENOMEM; 2509 goto free_qmem; 2510 } 2511 2512 switch (type) { 2513 case TYPE_AFPF: 2514 name = "rvu_afpf_mailbox"; 2515 dir = MBOX_DIR_AFPF; 2516 dir_up = MBOX_DIR_AFPF_UP; 2517 reg_base = rvu->afreg_base; 2518 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap); 2519 if (err) 2520 goto free_regions; 2521 break; 2522 case TYPE_AFVF: 2523 name = "rvu_afvf_mailbox"; 2524 dir = MBOX_DIR_PFVF; 2525 dir_up = MBOX_DIR_PFVF_UP; 2526 reg_base = rvu->pfreg_base; 2527 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap); 2528 if (err) 2529 goto free_regions; 2530 break; 2531 default: 2532 err = -EINVAL; 2533 goto free_regions; 2534 } 2535 2536 mw->mbox_wq = alloc_workqueue("%s", 2537 WQ_HIGHPRI | WQ_MEM_RECLAIM, 2538 num, name); 2539 if (!mw->mbox_wq) { 2540 err = -ENOMEM; 2541 goto unmap_regions; 2542 } 2543 2544 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2545 sizeof(struct rvu_work), GFP_KERNEL); 2546 if (!mw->mbox_wrk) { 2547 err = -ENOMEM; 2548 goto exit; 2549 } 2550 2551 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2552 sizeof(struct rvu_work), GFP_KERNEL); 2553 if (!mw->mbox_wrk_up) { 2554 err = -ENOMEM; 2555 goto exit; 2556 } 2557 2558 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2559 reg_base, dir, num, pf_bmap); 2560 if (err) 2561 goto exit; 2562 2563 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2564 reg_base, dir_up, num, pf_bmap); 2565 if (err) 2566 goto exit; 2567 2568 for (i = 0; i < num; i++) { 2569 if (!test_bit(i, pf_bmap)) 2570 continue; 2571 2572 mwork = &mw->mbox_wrk[i]; 2573 mwork->rvu = rvu; 2574 INIT_WORK(&mwork->work, mbox_handler); 2575 2576 mwork = &mw->mbox_wrk_up[i]; 2577 mwork->rvu = rvu; 2578 INIT_WORK(&mwork->work, mbox_up_handler); 2579 } 2580 2581 kfree(mbox_regions); 2582 bitmap_free(pf_bmap); 2583 2584 return 0; 2585 2586 exit: 2587 destroy_workqueue(mw->mbox_wq); 2588 unmap_regions: 2589 while (num--) 2590 iounmap((void __iomem *)mbox_regions[num]); 2591 free_regions: 2592 kfree(mbox_regions); 2593 free_qmem: 2594 cn20k_free_mbox_memory(rvu); 2595 free_mem: 2596 kfree(rvu->ng_rvu); 2597 free_bitmap: 2598 bitmap_free(pf_bmap); 2599 return err; 2600 } 2601 2602 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2603 { 2604 struct otx2_mbox *mbox = &mw->mbox; 2605 struct otx2_mbox_dev *mdev; 2606 int devid; 2607 2608 if (mw->mbox_wq) { 2609 destroy_workqueue(mw->mbox_wq); 2610 mw->mbox_wq = NULL; 2611 } 2612 2613 for (devid = 0; devid < mbox->ndevs; devid++) { 2614 mdev = &mbox->dev[devid]; 2615 if (mdev->hwbase) 2616 iounmap((void __iomem *)mdev->hwbase); 2617 } 2618 2619 otx2_mbox_destroy(&mw->mbox); 2620 otx2_mbox_destroy(&mw->mbox_up); 2621 } 2622 2623 void rvu_queue_work(struct mbox_wq_info *mw, int first, 2624 int mdevs, u64 intr) 2625 { 2626 struct otx2_mbox_dev *mdev; 2627 struct otx2_mbox *mbox; 2628 struct mbox_hdr *hdr; 2629 int i; 2630 2631 for (i = first; i < mdevs; i++) { 2632 /* start from 0 */ 2633 if (!(intr & BIT_ULL(i - first))) 2634 continue; 2635 2636 mbox = &mw->mbox; 2637 mdev = &mbox->dev[i]; 2638 hdr = mdev->mbase + mbox->rx_start; 2639 2640 /*The hdr->num_msgs is set to zero immediately in the interrupt 2641 * handler to ensure that it holds a correct value next time 2642 * when the interrupt handler is called. 2643 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2644 * pf>mbox.up_num_msgs holds the data for use in 2645 * pfaf_mbox_up_handler. 2646 */ 2647 2648 if (hdr->num_msgs) { 2649 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2650 hdr->num_msgs = 0; 2651 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2652 } 2653 mbox = &mw->mbox_up; 2654 mdev = &mbox->dev[i]; 2655 hdr = mdev->mbase + mbox->rx_start; 2656 if (hdr->num_msgs) { 2657 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2658 hdr->num_msgs = 0; 2659 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2660 } 2661 } 2662 } 2663 2664 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) 2665 { 2666 struct rvu *rvu = (struct rvu *)rvu_irq; 2667 u64 intr; 2668 2669 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2670 /* Clear interrupts */ 2671 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2672 if (intr) 2673 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2674 2675 /* Sync with mbox memory region */ 2676 rmb(); 2677 2678 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2679 2680 return IRQ_HANDLED; 2681 } 2682 2683 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2684 { 2685 struct rvu *rvu = (struct rvu *)rvu_irq; 2686 int vfs = rvu->vfs; 2687 u64 intr; 2688 2689 /* Sync with mbox memory region */ 2690 rmb(); 2691 2692 /* Handle VF interrupts */ 2693 if (vfs > 64) { 2694 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2695 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2696 2697 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2698 vfs = 64; 2699 } 2700 2701 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2702 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2703 if (intr) 2704 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2705 2706 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2707 2708 return IRQ_HANDLED; 2709 } 2710 2711 static void rvu_enable_mbox_intr(struct rvu *rvu) 2712 { 2713 struct rvu_hwinfo *hw = rvu->hw; 2714 2715 if (is_cn20k(rvu->pdev)) { 2716 cn20k_rvu_enable_mbox_intr(rvu); 2717 return; 2718 } 2719 2720 /* Clear spurious irqs, if any */ 2721 rvu_write64(rvu, BLKADDR_RVUM, 2722 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2723 2724 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2725 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2726 INTR_MASK(hw->total_pfs) & ~1ULL); 2727 } 2728 2729 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2730 { 2731 struct rvu_block *block; 2732 int slot, lf, num_lfs; 2733 int err; 2734 2735 block = &rvu->hw->block[blkaddr]; 2736 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2737 block->addr); 2738 if (!num_lfs) 2739 return; 2740 for (slot = 0; slot < num_lfs; slot++) { 2741 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2742 if (lf < 0) 2743 continue; 2744 2745 /* Cleanup LF and reset it */ 2746 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2747 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2748 else if (block->addr == BLKADDR_NPA) 2749 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2750 else if ((block->addr == BLKADDR_CPT0) || 2751 (block->addr == BLKADDR_CPT1)) 2752 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, 2753 slot); 2754 2755 err = rvu_lf_reset(rvu, block, lf); 2756 if (err) { 2757 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2758 block->addr, lf); 2759 } 2760 } 2761 } 2762 2763 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2764 { 2765 if (rvu_npc_exact_has_match_table(rvu)) 2766 rvu_npc_exact_reset(rvu, pcifunc); 2767 2768 mutex_lock(&rvu->flr_lock); 2769 /* Reset order should reflect inter-block dependencies: 2770 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2771 * 2. Flush and reset SSO/SSOW 2772 * 3. Cleanup pools (NPA) 2773 */ 2774 2775 /* Free allocated BPIDs */ 2776 rvu_nix_flr_free_bpids(rvu, pcifunc); 2777 2778 /* Free multicast/mirror node associated with the 'pcifunc' */ 2779 rvu_nix_mcast_flr_free_entries(rvu, pcifunc); 2780 2781 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2782 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2783 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2784 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2785 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2786 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2787 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2788 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2789 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2790 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2791 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM 2792 * entries, check and free the MCAM entries explicitly to avoid leak. 2793 * Since LF is detached use LF number as -1. 2794 */ 2795 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); 2796 rvu_mac_reset(rvu, pcifunc); 2797 2798 if (rvu->mcs_blk_cnt) 2799 rvu_mcs_flr_handler(rvu, pcifunc); 2800 2801 mutex_unlock(&rvu->flr_lock); 2802 } 2803 2804 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2805 { 2806 int reg = 0; 2807 2808 /* pcifunc = 0(PF0) | (vf + 1) */ 2809 __rvu_flr_handler(rvu, vf + 1); 2810 2811 if (vf >= 64) { 2812 reg = 1; 2813 vf = vf - 64; 2814 } 2815 2816 /* Signal FLR finish and enable IRQ */ 2817 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2818 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2819 } 2820 2821 static void rvu_flr_handler(struct work_struct *work) 2822 { 2823 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2824 struct rvu *rvu = flrwork->rvu; 2825 u16 pcifunc, numvfs, vf; 2826 u64 cfg; 2827 int pf; 2828 2829 pf = flrwork - rvu->flr_wrk; 2830 if (pf >= rvu->hw->total_pfs) { 2831 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2832 return; 2833 } 2834 2835 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2836 numvfs = (cfg >> 12) & 0xFF; 2837 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0); 2838 2839 for (vf = 0; vf < numvfs; vf++) 2840 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2841 2842 __rvu_flr_handler(rvu, pcifunc); 2843 2844 /* Signal FLR finish */ 2845 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2846 2847 /* Enable interrupt */ 2848 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2849 } 2850 2851 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2852 { 2853 int dev, vf, reg = 0; 2854 u64 intr; 2855 2856 if (start_vf >= 64) 2857 reg = 1; 2858 2859 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2860 if (!intr) 2861 return; 2862 2863 for (vf = 0; vf < numvfs; vf++) { 2864 if (!(intr & BIT_ULL(vf))) 2865 continue; 2866 /* Clear and disable the interrupt */ 2867 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2868 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2869 2870 dev = vf + start_vf + rvu->hw->total_pfs; 2871 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2872 } 2873 } 2874 2875 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2876 { 2877 struct rvu *rvu = (struct rvu *)rvu_irq; 2878 u64 intr; 2879 u8 pf; 2880 2881 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2882 if (!intr) 2883 goto afvf_flr; 2884 2885 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2886 if (intr & (1ULL << pf)) { 2887 /* clear interrupt */ 2888 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2889 BIT_ULL(pf)); 2890 /* Disable the interrupt */ 2891 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2892 BIT_ULL(pf)); 2893 /* PF is already dead do only AF related operations */ 2894 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2895 } 2896 } 2897 2898 afvf_flr: 2899 rvu_afvf_queue_flr_work(rvu, 0, 64); 2900 if (rvu->vfs > 64) 2901 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2902 2903 return IRQ_HANDLED; 2904 } 2905 2906 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2907 { 2908 int vf; 2909 2910 /* Nothing to be done here other than clearing the 2911 * TRPEND bit. 2912 */ 2913 for (vf = 0; vf < 64; vf++) { 2914 if (intr & (1ULL << vf)) { 2915 /* clear the trpend due to ME(master enable) */ 2916 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2917 /* clear interrupt */ 2918 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2919 } 2920 } 2921 } 2922 2923 /* Handles ME interrupts from VFs of AF */ 2924 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2925 { 2926 struct rvu *rvu = (struct rvu *)rvu_irq; 2927 int vfset; 2928 u64 intr; 2929 2930 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2931 2932 for (vfset = 0; vfset <= 1; vfset++) { 2933 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2934 if (intr) 2935 rvu_me_handle_vfset(rvu, vfset, intr); 2936 } 2937 2938 return IRQ_HANDLED; 2939 } 2940 2941 /* Handles ME interrupts from PFs */ 2942 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2943 { 2944 struct rvu *rvu = (struct rvu *)rvu_irq; 2945 u64 intr; 2946 u8 pf; 2947 2948 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2949 2950 /* Nothing to be done here other than clearing the 2951 * TRPEND bit. 2952 */ 2953 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2954 if (intr & (1ULL << pf)) { 2955 /* clear the trpend due to ME(master enable) */ 2956 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2957 BIT_ULL(pf)); 2958 /* clear interrupt */ 2959 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2960 BIT_ULL(pf)); 2961 } 2962 } 2963 2964 return IRQ_HANDLED; 2965 } 2966 2967 static void rvu_unregister_interrupts(struct rvu *rvu) 2968 { 2969 int irq; 2970 2971 rvu_cpt_unregister_interrupts(rvu); 2972 2973 if (!is_cn20k(rvu->pdev)) 2974 /* Disable the Mbox interrupt */ 2975 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2976 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2977 else 2978 cn20k_rvu_unregister_interrupts(rvu); 2979 2980 /* Disable the PF FLR interrupt */ 2981 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2982 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2983 2984 /* Disable the PF ME interrupt */ 2985 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2986 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2987 2988 for (irq = 0; irq < rvu->num_vec; irq++) { 2989 if (rvu->irq_allocated[irq]) { 2990 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2991 rvu->irq_allocated[irq] = false; 2992 } 2993 } 2994 2995 pci_free_irq_vectors(rvu->pdev); 2996 rvu->num_vec = 0; 2997 } 2998 2999 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 3000 { 3001 struct rvu_pfvf *pfvf = &rvu->pf[0]; 3002 int offset; 3003 3004 pfvf = &rvu->pf[0]; 3005 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 3006 3007 /* Make sure there are enough MSIX vectors configured so that 3008 * VF interrupts can be handled. Offset equal to zero means 3009 * that PF vectors are not configured and overlapping AF vectors. 3010 */ 3011 if (is_cn20k(rvu->pdev)) 3012 return (pfvf->msix.max >= RVU_AF_CN20K_INT_VEC_CNT + 3013 RVU_MBOX_PF_INT_VEC_CNT) && offset; 3014 3015 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 3016 offset; 3017 } 3018 3019 static int rvu_register_interrupts(struct rvu *rvu) 3020 { 3021 int ret, offset, pf_vec_start; 3022 3023 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 3024 3025 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 3026 NAME_SIZE, GFP_KERNEL); 3027 if (!rvu->irq_name) 3028 return -ENOMEM; 3029 3030 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 3031 sizeof(bool), GFP_KERNEL); 3032 if (!rvu->irq_allocated) 3033 return -ENOMEM; 3034 3035 /* Enable MSI-X */ 3036 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 3037 rvu->num_vec, PCI_IRQ_MSIX); 3038 if (ret < 0) { 3039 dev_err(rvu->dev, 3040 "RVUAF: Request for %d msix vectors failed, ret %d\n", 3041 rvu->num_vec, ret); 3042 return ret; 3043 } 3044 3045 if (!is_cn20k(rvu->pdev)) { 3046 /* Register mailbox interrupt handler */ 3047 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], 3048 "RVUAF Mbox"); 3049 ret = request_irq(pci_irq_vector 3050 (rvu->pdev, RVU_AF_INT_VEC_MBOX), 3051 rvu->ng_rvu->rvu_mbox_ops->pf_intr_handler, 0, 3052 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * 3053 NAME_SIZE], rvu); 3054 if (ret) { 3055 dev_err(rvu->dev, 3056 "RVUAF: IRQ registration failed for mbox\n"); 3057 goto fail; 3058 } 3059 3060 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 3061 } else { 3062 ret = cn20k_register_afpf_mbox_intr(rvu); 3063 if (ret) { 3064 dev_err(rvu->dev, 3065 "RVUAF: IRQ registration failed for mbox\n"); 3066 goto fail; 3067 } 3068 } 3069 3070 /* Enable mailbox interrupts from all PFs */ 3071 rvu_enable_mbox_intr(rvu); 3072 3073 /* Register FLR interrupt handler */ 3074 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 3075 "RVUAF FLR"); 3076 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 3077 rvu_flr_intr_handler, 0, 3078 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 3079 rvu); 3080 if (ret) { 3081 dev_err(rvu->dev, 3082 "RVUAF: IRQ registration failed for FLR\n"); 3083 goto fail; 3084 } 3085 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 3086 3087 /* Enable FLR interrupt for all PFs*/ 3088 rvu_write64(rvu, BLKADDR_RVUM, 3089 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 3090 3091 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 3092 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3093 3094 /* Register ME interrupt handler */ 3095 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3096 "RVUAF ME"); 3097 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 3098 rvu_me_pf_intr_handler, 0, 3099 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 3100 rvu); 3101 if (ret) { 3102 dev_err(rvu->dev, 3103 "RVUAF: IRQ registration failed for ME\n"); 3104 } 3105 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 3106 3107 /* Clear TRPEND bit for all PF */ 3108 rvu_write64(rvu, BLKADDR_RVUM, 3109 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 3110 /* Enable ME interrupt for all PFs*/ 3111 rvu_write64(rvu, BLKADDR_RVUM, 3112 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 3113 3114 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 3115 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 3116 3117 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 3118 return 0; 3119 3120 /* Get PF MSIX vectors offset. */ 3121 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 3122 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 3123 if (!is_cn20k(rvu->pdev)) { 3124 /* Register MBOX0 interrupt. */ 3125 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 3126 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 3127 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3128 rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0, 3129 &rvu->irq_name[offset * NAME_SIZE], 3130 rvu); 3131 if (ret) 3132 dev_err(rvu->dev, 3133 "RVUAF: IRQ registration failed for Mbox0\n"); 3134 3135 rvu->irq_allocated[offset] = true; 3136 3137 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 3138 * simply increment current offset by 1. 3139 */ 3140 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 3141 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 3142 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3143 rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0, 3144 &rvu->irq_name[offset * NAME_SIZE], 3145 rvu); 3146 if (ret) 3147 dev_err(rvu->dev, 3148 "RVUAF: IRQ registration failed for Mbox1\n"); 3149 3150 rvu->irq_allocated[offset] = true; 3151 } else { 3152 ret = cn20k_register_afvf_mbox_intr(rvu, pf_vec_start); 3153 if (ret) 3154 dev_err(rvu->dev, 3155 "RVUAF: IRQ registration failed for Mbox\n"); 3156 } 3157 3158 /* Register FLR interrupt handler for AF's VFs */ 3159 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 3160 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 3161 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3162 rvu_flr_intr_handler, 0, 3163 &rvu->irq_name[offset * NAME_SIZE], rvu); 3164 if (ret) { 3165 dev_err(rvu->dev, 3166 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 3167 goto fail; 3168 } 3169 rvu->irq_allocated[offset] = true; 3170 3171 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 3172 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 3173 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3174 rvu_flr_intr_handler, 0, 3175 &rvu->irq_name[offset * NAME_SIZE], rvu); 3176 if (ret) { 3177 dev_err(rvu->dev, 3178 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 3179 goto fail; 3180 } 3181 rvu->irq_allocated[offset] = true; 3182 3183 /* Register ME interrupt handler for AF's VFs */ 3184 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 3185 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 3186 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3187 rvu_me_vf_intr_handler, 0, 3188 &rvu->irq_name[offset * NAME_SIZE], rvu); 3189 if (ret) { 3190 dev_err(rvu->dev, 3191 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 3192 goto fail; 3193 } 3194 rvu->irq_allocated[offset] = true; 3195 3196 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 3197 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 3198 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3199 rvu_me_vf_intr_handler, 0, 3200 &rvu->irq_name[offset * NAME_SIZE], rvu); 3201 if (ret) { 3202 dev_err(rvu->dev, 3203 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 3204 goto fail; 3205 } 3206 rvu->irq_allocated[offset] = true; 3207 3208 ret = rvu_cpt_register_interrupts(rvu); 3209 if (ret) 3210 goto fail; 3211 3212 return 0; 3213 3214 fail: 3215 rvu_unregister_interrupts(rvu); 3216 return ret; 3217 } 3218 3219 static void rvu_flr_wq_destroy(struct rvu *rvu) 3220 { 3221 if (rvu->flr_wq) { 3222 destroy_workqueue(rvu->flr_wq); 3223 rvu->flr_wq = NULL; 3224 } 3225 } 3226 3227 static int rvu_flr_init(struct rvu *rvu) 3228 { 3229 int dev, num_devs; 3230 u64 cfg; 3231 int pf; 3232 3233 /* Enable FLR for all PFs*/ 3234 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 3235 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 3236 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 3237 cfg | BIT_ULL(22)); 3238 } 3239 3240 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr", 3241 WQ_HIGHPRI | WQ_MEM_RECLAIM); 3242 if (!rvu->flr_wq) 3243 return -ENOMEM; 3244 3245 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 3246 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 3247 sizeof(struct rvu_work), GFP_KERNEL); 3248 if (!rvu->flr_wrk) { 3249 destroy_workqueue(rvu->flr_wq); 3250 return -ENOMEM; 3251 } 3252 3253 for (dev = 0; dev < num_devs; dev++) { 3254 rvu->flr_wrk[dev].rvu = rvu; 3255 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 3256 } 3257 3258 mutex_init(&rvu->flr_lock); 3259 3260 return 0; 3261 } 3262 3263 static void rvu_disable_afvf_intr(struct rvu *rvu) 3264 { 3265 int vfs = rvu->vfs; 3266 3267 if (is_cn20k(rvu->pdev)) 3268 return cn20k_rvu_disable_afvf_intr(rvu, vfs); 3269 3270 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3271 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3272 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3273 if (vfs <= 64) 3274 return; 3275 3276 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3277 INTR_MASK(vfs - 64)); 3278 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3279 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3280 } 3281 3282 static void rvu_enable_afvf_intr(struct rvu *rvu) 3283 { 3284 int vfs = rvu->vfs; 3285 3286 if (is_cn20k(rvu->pdev)) 3287 return cn20k_rvu_enable_afvf_intr(rvu, vfs); 3288 3289 /* Clear any pending interrupts and enable AF VF interrupts for 3290 * the first 64 VFs. 3291 */ 3292 /* Mbox */ 3293 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3294 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3295 3296 /* FLR */ 3297 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3298 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3299 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3300 3301 /* Same for remaining VFs, if any. */ 3302 if (vfs <= 64) 3303 return; 3304 3305 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3306 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3307 INTR_MASK(vfs - 64)); 3308 3309 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3310 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3311 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3312 } 3313 3314 int rvu_get_num_lbk_chans(void) 3315 { 3316 struct pci_dev *pdev; 3317 void __iomem *base; 3318 int ret = -EIO; 3319 3320 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3321 NULL); 3322 if (!pdev) 3323 goto err; 3324 3325 base = pci_ioremap_bar(pdev, 0); 3326 if (!base) 3327 goto err_put; 3328 3329 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3330 ret = (readq(base + 0x10) >> 32) & 0xffff; 3331 iounmap(base); 3332 err_put: 3333 pci_dev_put(pdev); 3334 err: 3335 return ret; 3336 } 3337 3338 static int rvu_enable_sriov(struct rvu *rvu) 3339 { 3340 struct pci_dev *pdev = rvu->pdev; 3341 int err, chans, vfs; 3342 int pos = 0; 3343 3344 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3345 dev_warn(&pdev->dev, 3346 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3347 return 0; 3348 } 3349 3350 /* Get RVU VFs device id */ 3351 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 3352 if (!pos) 3353 return 0; 3354 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid); 3355 3356 chans = rvu_get_num_lbk_chans(); 3357 if (chans < 0) 3358 return chans; 3359 3360 vfs = pci_sriov_get_totalvfs(pdev); 3361 3362 /* Limit VFs in case we have more VFs than LBK channels available. */ 3363 if (vfs > chans) 3364 vfs = chans; 3365 3366 if (!vfs) 3367 return 0; 3368 3369 /* LBK channel number 63 is used for switching packets between 3370 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3371 */ 3372 if (vfs > 62) 3373 vfs = 62; 3374 3375 /* Save VFs number for reference in VF interrupts handlers. 3376 * Since interrupts might start arriving during SRIOV enablement 3377 * ordinary API cannot be used to get number of enabled VFs. 3378 */ 3379 rvu->vfs = vfs; 3380 3381 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3382 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3383 if (err) 3384 return err; 3385 3386 rvu_enable_afvf_intr(rvu); 3387 /* Make sure IRQs are enabled before SRIOV. */ 3388 mb(); 3389 3390 err = pci_enable_sriov(pdev, vfs); 3391 if (err) { 3392 rvu_disable_afvf_intr(rvu); 3393 rvu_mbox_destroy(&rvu->afvf_wq_info); 3394 return err; 3395 } 3396 3397 return 0; 3398 } 3399 3400 static void rvu_disable_sriov(struct rvu *rvu) 3401 { 3402 rvu_disable_afvf_intr(rvu); 3403 rvu_mbox_destroy(&rvu->afvf_wq_info); 3404 pci_disable_sriov(rvu->pdev); 3405 } 3406 3407 static void rvu_update_module_params(struct rvu *rvu) 3408 { 3409 const char *default_pfl_name = "default"; 3410 3411 strscpy(rvu->mkex_pfl_name, 3412 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3413 strscpy(rvu->kpu_pfl_name, 3414 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3415 } 3416 3417 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3418 { 3419 struct device *dev = &pdev->dev; 3420 struct rvu *rvu; 3421 int err; 3422 3423 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3424 if (!rvu) 3425 return -ENOMEM; 3426 3427 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3428 if (!rvu->hw) { 3429 devm_kfree(dev, rvu); 3430 return -ENOMEM; 3431 } 3432 3433 pci_set_drvdata(pdev, rvu); 3434 rvu->pdev = pdev; 3435 rvu->dev = &pdev->dev; 3436 3437 err = pci_enable_device(pdev); 3438 if (err) { 3439 dev_err(dev, "Failed to enable PCI device\n"); 3440 goto err_freemem; 3441 } 3442 3443 err = pci_request_regions(pdev, DRV_NAME); 3444 if (err) { 3445 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3446 goto err_disable_device; 3447 } 3448 3449 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3450 if (err) { 3451 dev_err(dev, "DMA mask config failed, abort\n"); 3452 goto err_release_regions; 3453 } 3454 3455 pci_set_master(pdev); 3456 3457 rvu->ptp = ptp_get(); 3458 if (IS_ERR(rvu->ptp)) { 3459 err = PTR_ERR(rvu->ptp); 3460 if (err) 3461 goto err_release_regions; 3462 rvu->ptp = NULL; 3463 } 3464 3465 /* Map Admin function CSRs */ 3466 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3467 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3468 if (!rvu->afreg_base || !rvu->pfreg_base) { 3469 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3470 err = -ENOMEM; 3471 goto err_put_ptp; 3472 } 3473 3474 /* Store module params in rvu structure */ 3475 rvu_update_module_params(rvu); 3476 3477 /* Check which blocks the HW supports */ 3478 rvu_check_block_implemented(rvu); 3479 3480 rvu_reset_all_blocks(rvu); 3481 3482 rvu_setup_hw_capabilities(rvu); 3483 3484 err = rvu_setup_hw_resources(rvu); 3485 if (err) 3486 goto err_put_ptp; 3487 3488 /* Init mailbox btw AF and PFs */ 3489 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3490 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3491 rvu_afpf_mbox_up_handler); 3492 if (err) { 3493 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3494 goto err_hwsetup; 3495 } 3496 3497 err = rvu_flr_init(rvu); 3498 if (err) { 3499 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3500 goto err_mbox; 3501 } 3502 3503 err = rvu_register_interrupts(rvu); 3504 if (err) { 3505 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3506 goto err_flr; 3507 } 3508 3509 err = rvu_register_dl(rvu); 3510 if (err) { 3511 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3512 goto err_irq; 3513 } 3514 3515 rvu_setup_rvum_blk_revid(rvu); 3516 3517 /* Enable AF's VFs (if any) */ 3518 err = rvu_enable_sriov(rvu); 3519 if (err) { 3520 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3521 goto err_dl; 3522 } 3523 3524 /* Initialize debugfs */ 3525 rvu_dbg_init(rvu); 3526 3527 mutex_init(&rvu->rswitch.switch_lock); 3528 3529 if (rvu->fwdata) 3530 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3531 rvu->fwdata->ptp_ext_tstamp); 3532 3533 /* Alloc CINT and QINT memory */ 3534 rvu_alloc_cint_qint_mem(rvu, &rvu->pf[RVU_AFPF], BLKADDR_NIX0, 3535 (rvu->hw->block[BLKADDR_NIX0].lf.max)); 3536 return 0; 3537 err_dl: 3538 rvu_unregister_dl(rvu); 3539 err_irq: 3540 rvu_unregister_interrupts(rvu); 3541 err_flr: 3542 rvu_flr_wq_destroy(rvu); 3543 err_mbox: 3544 rvu_mbox_destroy(&rvu->afpf_wq_info); 3545 err_hwsetup: 3546 rvu_cgx_exit(rvu); 3547 rvu_fwdata_exit(rvu); 3548 rvu_mcs_exit(rvu); 3549 rvu_reset_all_blocks(rvu); 3550 rvu_free_hw_resources(rvu); 3551 rvu_clear_rvum_blk_revid(rvu); 3552 err_put_ptp: 3553 ptp_put(rvu->ptp); 3554 err_release_regions: 3555 pci_release_regions(pdev); 3556 err_disable_device: 3557 pci_disable_device(pdev); 3558 err_freemem: 3559 pci_set_drvdata(pdev, NULL); 3560 devm_kfree(&pdev->dev, rvu->hw); 3561 devm_kfree(dev, rvu); 3562 return err; 3563 } 3564 3565 static void rvu_remove(struct pci_dev *pdev) 3566 { 3567 struct rvu *rvu = pci_get_drvdata(pdev); 3568 3569 rvu_dbg_exit(rvu); 3570 rvu_unregister_dl(rvu); 3571 rvu_unregister_interrupts(rvu); 3572 rvu_flr_wq_destroy(rvu); 3573 rvu_cgx_exit(rvu); 3574 rvu_fwdata_exit(rvu); 3575 rvu_mcs_exit(rvu); 3576 rvu_mbox_destroy(&rvu->afpf_wq_info); 3577 rvu_disable_sriov(rvu); 3578 rvu_reset_all_blocks(rvu); 3579 rvu_free_hw_resources(rvu); 3580 rvu_clear_rvum_blk_revid(rvu); 3581 ptp_put(rvu->ptp); 3582 pci_release_regions(pdev); 3583 pci_disable_device(pdev); 3584 pci_set_drvdata(pdev, NULL); 3585 3586 devm_kfree(&pdev->dev, rvu->hw); 3587 if (is_cn20k(rvu->pdev)) 3588 cn20k_free_mbox_memory(rvu); 3589 kfree(rvu->ng_rvu); 3590 devm_kfree(&pdev->dev, rvu); 3591 } 3592 3593 static struct pci_driver rvu_driver = { 3594 .name = DRV_NAME, 3595 .id_table = rvu_id_table, 3596 .probe = rvu_probe, 3597 .remove = rvu_remove, 3598 }; 3599 3600 static int __init rvu_init_module(void) 3601 { 3602 int err; 3603 3604 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3605 3606 err = pci_register_driver(&cgx_driver); 3607 if (err < 0) 3608 return err; 3609 3610 err = pci_register_driver(&ptp_driver); 3611 if (err < 0) 3612 goto ptp_err; 3613 3614 err = pci_register_driver(&mcs_driver); 3615 if (err < 0) 3616 goto mcs_err; 3617 3618 err = pci_register_driver(&rvu_driver); 3619 if (err < 0) 3620 goto rvu_err; 3621 3622 return 0; 3623 rvu_err: 3624 pci_unregister_driver(&mcs_driver); 3625 mcs_err: 3626 pci_unregister_driver(&ptp_driver); 3627 ptp_err: 3628 pci_unregister_driver(&cgx_driver); 3629 3630 return err; 3631 } 3632 3633 static void __exit rvu_cleanup_module(void) 3634 { 3635 pci_unregister_driver(&rvu_driver); 3636 pci_unregister_driver(&mcs_driver); 3637 pci_unregister_driver(&ptp_driver); 3638 pci_unregister_driver(&cgx_driver); 3639 } 3640 3641 module_init(rvu_init_module); 3642 module_exit(rvu_cleanup_module); 3643