xref: /linux/drivers/net/ethernet/marvell/octeontx2/af/npc.h (revision e7d759f31ca295d589f7420719c311870bb3166f)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef NPC_H
9 #define NPC_H
10 
11 #define NPC_KEX_CHAN_MASK	0xFFFULL
12 
13 #define SET_KEX_LD(intf, lid, ltype, ld, cfg)	\
14 	rvu_write64(rvu, blkaddr,	\
15 		    NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
16 
17 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg)	\
18 	rvu_write64(rvu, blkaddr,	\
19 		    NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
20 
21 enum NPC_LID_E {
22 	NPC_LID_LA = 0,
23 	NPC_LID_LB,
24 	NPC_LID_LC,
25 	NPC_LID_LD,
26 	NPC_LID_LE,
27 	NPC_LID_LF,
28 	NPC_LID_LG,
29 	NPC_LID_LH,
30 };
31 
32 #define NPC_LT_NA 0
33 
34 enum npc_kpu_la_ltype {
35 	NPC_LT_LA_8023 = 1,
36 	NPC_LT_LA_ETHER,
37 	NPC_LT_LA_IH_NIX_ETHER,
38 	NPC_LT_LA_HIGIG2_ETHER = 7,
39 	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
40 	NPC_LT_LA_CUSTOM_L2_90B_ETHER,
41 	NPC_LT_LA_CPT_HDR,
42 	NPC_LT_LA_CUSTOM_L2_24B_ETHER,
43 	NPC_LT_LA_CUSTOM_PRE_L2_ETHER,
44 	NPC_LT_LA_CUSTOM0 = 0xE,
45 	NPC_LT_LA_CUSTOM1 = 0xF,
46 };
47 
48 enum npc_kpu_lb_ltype {
49 	NPC_LT_LB_ETAG = 1,
50 	NPC_LT_LB_CTAG,
51 	NPC_LT_LB_STAG_QINQ,
52 	NPC_LT_LB_BTAG,
53 	NPC_LT_LB_PPPOE,
54 	NPC_LT_LB_DSA,
55 	NPC_LT_LB_DSA_VLAN,
56 	NPC_LT_LB_EDSA,
57 	NPC_LT_LB_EDSA_VLAN,
58 	NPC_LT_LB_EXDSA,
59 	NPC_LT_LB_EXDSA_VLAN,
60 	NPC_LT_LB_FDSA,
61 	NPC_LT_LB_VLAN_EXDSA,
62 	NPC_LT_LB_CUSTOM0 = 0xE,
63 	NPC_LT_LB_CUSTOM1 = 0xF,
64 };
65 
66 enum npc_kpu_lc_ltype {
67 	NPC_LT_LC_IP = 1,
68 	NPC_LT_LC_IP_OPT,
69 	NPC_LT_LC_IP6,
70 	NPC_LT_LC_IP6_EXT,
71 	NPC_LT_LC_ARP,
72 	NPC_LT_LC_RARP,
73 	NPC_LT_LC_MPLS,
74 	NPC_LT_LC_NSH,
75 	NPC_LT_LC_PTP,
76 	NPC_LT_LC_FCOE,
77 	NPC_LT_LC_NGIO,
78 	NPC_LT_LC_CUSTOM0 = 0xE,
79 	NPC_LT_LC_CUSTOM1 = 0xF,
80 };
81 
82 /* Don't modify Ltypes upto SCTP, otherwise it will
83  * effect flow tag calculation and thus RSS.
84  */
85 enum npc_kpu_ld_ltype {
86 	NPC_LT_LD_TCP = 1,
87 	NPC_LT_LD_UDP,
88 	NPC_LT_LD_ICMP,
89 	NPC_LT_LD_SCTP,
90 	NPC_LT_LD_ICMP6,
91 	NPC_LT_LD_CUSTOM0,
92 	NPC_LT_LD_CUSTOM1,
93 	NPC_LT_LD_IGMP = 8,
94 	NPC_LT_LD_AH,
95 	NPC_LT_LD_GRE,
96 	NPC_LT_LD_NVGRE,
97 	NPC_LT_LD_NSH,
98 	NPC_LT_LD_TU_MPLS_IN_NSH,
99 	NPC_LT_LD_TU_MPLS_IN_IP,
100 };
101 
102 enum npc_kpu_le_ltype {
103 	NPC_LT_LE_VXLAN = 1,
104 	NPC_LT_LE_GENEVE,
105 	NPC_LT_LE_ESP,
106 	NPC_LT_LE_GTPU = 4,
107 	NPC_LT_LE_VXLANGPE,
108 	NPC_LT_LE_GTPC,
109 	NPC_LT_LE_NSH,
110 	NPC_LT_LE_TU_MPLS_IN_GRE,
111 	NPC_LT_LE_TU_NSH_IN_GRE,
112 	NPC_LT_LE_TU_MPLS_IN_UDP,
113 	NPC_LT_LE_CUSTOM0 = 0xE,
114 	NPC_LT_LE_CUSTOM1 = 0xF,
115 };
116 
117 enum npc_kpu_lf_ltype {
118 	NPC_LT_LF_TU_ETHER = 1,
119 	NPC_LT_LF_TU_PPP,
120 	NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
121 	NPC_LT_LF_TU_NSH_IN_VXLANGPE,
122 	NPC_LT_LF_TU_MPLS_IN_NSH,
123 	NPC_LT_LF_TU_3RD_NSH,
124 	NPC_LT_LF_CUSTOM0 = 0xE,
125 	NPC_LT_LF_CUSTOM1 = 0xF,
126 };
127 
128 enum npc_kpu_lg_ltype {
129 	NPC_LT_LG_TU_IP = 1,
130 	NPC_LT_LG_TU_IP6,
131 	NPC_LT_LG_TU_ARP,
132 	NPC_LT_LG_TU_ETHER_IN_NSH,
133 	NPC_LT_LG_CUSTOM0 = 0xE,
134 	NPC_LT_LG_CUSTOM1 = 0xF,
135 };
136 
137 /* Don't modify Ltypes upto SCTP, otherwise it will
138  * effect flow tag calculation and thus RSS.
139  */
140 enum npc_kpu_lh_ltype {
141 	NPC_LT_LH_TU_TCP = 1,
142 	NPC_LT_LH_TU_UDP,
143 	NPC_LT_LH_TU_ICMP,
144 	NPC_LT_LH_TU_SCTP,
145 	NPC_LT_LH_TU_ICMP6,
146 	NPC_LT_LH_TU_IGMP = 8,
147 	NPC_LT_LH_TU_ESP,
148 	NPC_LT_LH_TU_AH,
149 	NPC_LT_LH_CUSTOM0 = 0xE,
150 	NPC_LT_LH_CUSTOM1 = 0xF,
151 };
152 
153 /* NPC port kind defines how the incoming or outgoing packets
154  * are processed. NPC accepts packets from up to 64 pkinds.
155  * Software assigns pkind for each incoming port such as CGX
156  * Ethernet interfaces, LBK interfaces, etc.
157  */
158 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CUSTOM_PRE_L2_PKIND
159 
160 enum npc_pkind_type {
161 	NPC_RX_LBK_PKIND = 0ULL,
162 	NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
163 	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
164 	NPC_RX_CHLEN24B_PKIND = 57ULL,
165 	NPC_RX_CPT_HDR_PKIND,
166 	NPC_RX_CHLEN90B_PKIND,
167 	NPC_TX_HIGIG_PKIND,
168 	NPC_RX_HIGIG_PKIND,
169 	NPC_RX_EDSA_PKIND,
170 	NPC_TX_DEF_PKIND,	/* NIX-TX PKIND */
171 };
172 
173 enum npc_interface_type {
174 	NPC_INTF_MODE_DEF,
175 };
176 
177 /* list of known and supported fields in packet header and
178  * fields present in key structure.
179  */
180 enum key_fields {
181 	NPC_DMAC,
182 	NPC_SMAC,
183 	NPC_ETYPE,
184 	NPC_VLAN_ETYPE_CTAG, /* 0x8100 */
185 	NPC_VLAN_ETYPE_STAG, /* 0x88A8 */
186 	NPC_OUTER_VID,
187 	NPC_INNER_VID,
188 	NPC_TOS,
189 	NPC_IPFRAG_IPV4,
190 	NPC_SIP_IPV4,
191 	NPC_DIP_IPV4,
192 	NPC_IPFRAG_IPV6,
193 	NPC_SIP_IPV6,
194 	NPC_DIP_IPV6,
195 	NPC_IPPROTO_TCP,
196 	NPC_IPPROTO_UDP,
197 	NPC_IPPROTO_SCTP,
198 	NPC_IPPROTO_AH,
199 	NPC_IPPROTO_ESP,
200 	NPC_IPPROTO_ICMP,
201 	NPC_IPPROTO_ICMP6,
202 	NPC_SPORT_TCP,
203 	NPC_DPORT_TCP,
204 	NPC_SPORT_UDP,
205 	NPC_DPORT_UDP,
206 	NPC_SPORT_SCTP,
207 	NPC_DPORT_SCTP,
208 	NPC_IPSEC_SPI,
209 	NPC_MPLS1_LBTCBOS,
210 	NPC_MPLS1_TTL,
211 	NPC_MPLS2_LBTCBOS,
212 	NPC_MPLS2_TTL,
213 	NPC_MPLS3_LBTCBOS,
214 	NPC_MPLS3_TTL,
215 	NPC_MPLS4_LBTCBOS,
216 	NPC_MPLS4_TTL,
217 	NPC_TYPE_ICMP,
218 	NPC_CODE_ICMP,
219 	NPC_HEADER_FIELDS_MAX,
220 	NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
221 	NPC_PF_FUNC, /* Valid when Tx */
222 	NPC_ERRLEV,
223 	NPC_ERRCODE,
224 	NPC_LXMB,
225 	NPC_EXACT_RESULT,
226 	NPC_LA,
227 	NPC_LB,
228 	NPC_LC,
229 	NPC_LD,
230 	NPC_LE,
231 	NPC_LF,
232 	NPC_LG,
233 	NPC_LH,
234 	/* Ethertype for untagged frame */
235 	NPC_ETYPE_ETHER,
236 	/* Ethertype for single tagged frame */
237 	NPC_ETYPE_TAG1,
238 	/* Ethertype for double tagged frame */
239 	NPC_ETYPE_TAG2,
240 	/* outer vlan tci for single tagged frame */
241 	NPC_VLAN_TAG1,
242 	/* outer vlan tci for double tagged frame */
243 	NPC_VLAN_TAG2,
244 	/* inner vlan tci for double tagged frame */
245 	NPC_VLAN_TAG3,
246 	/* other header fields programmed to extract but not of our interest */
247 	NPC_UNKNOWN,
248 	NPC_KEY_FIELDS_MAX,
249 };
250 
251 struct npc_kpu_profile_cam {
252 	u8 state;
253 	u8 state_mask;
254 	u16 dp0;
255 	u16 dp0_mask;
256 	u16 dp1;
257 	u16 dp1_mask;
258 	u16 dp2;
259 	u16 dp2_mask;
260 } __packed;
261 
262 struct npc_kpu_profile_action {
263 	u8 errlev;
264 	u8 errcode;
265 	u8 dp0_offset;
266 	u8 dp1_offset;
267 	u8 dp2_offset;
268 	u8 bypass_count;
269 	u8 parse_done;
270 	u8 next_state;
271 	u8 ptr_advance;
272 	u8 cap_ena;
273 	u8 lid;
274 	u8 ltype;
275 	u8 flags;
276 	u8 offset;
277 	u8 mask;
278 	u8 right;
279 	u8 shift;
280 } __packed;
281 
282 struct npc_kpu_profile {
283 	int cam_entries;
284 	int action_entries;
285 	struct npc_kpu_profile_cam *cam;
286 	struct npc_kpu_profile_action *action;
287 };
288 
289 /* NPC KPU register formats */
290 struct npc_kpu_cam {
291 #if defined(__BIG_ENDIAN_BITFIELD)
292 	u64 rsvd_63_56     : 8;
293 	u64 state          : 8;
294 	u64 dp2_data       : 16;
295 	u64 dp1_data       : 16;
296 	u64 dp0_data       : 16;
297 #else
298 	u64 dp0_data       : 16;
299 	u64 dp1_data       : 16;
300 	u64 dp2_data       : 16;
301 	u64 state          : 8;
302 	u64 rsvd_63_56     : 8;
303 #endif
304 };
305 
306 struct npc_kpu_action0 {
307 #if defined(__BIG_ENDIAN_BITFIELD)
308 	u64 rsvd_63_57     : 7;
309 	u64 byp_count      : 3;
310 	u64 capture_ena    : 1;
311 	u64 parse_done     : 1;
312 	u64 next_state     : 8;
313 	u64 rsvd_43        : 1;
314 	u64 capture_lid    : 3;
315 	u64 capture_ltype  : 4;
316 	u64 capture_flags  : 8;
317 	u64 ptr_advance    : 8;
318 	u64 var_len_offset : 8;
319 	u64 var_len_mask   : 8;
320 	u64 var_len_right  : 1;
321 	u64 var_len_shift  : 3;
322 #else
323 	u64 var_len_shift  : 3;
324 	u64 var_len_right  : 1;
325 	u64 var_len_mask   : 8;
326 	u64 var_len_offset : 8;
327 	u64 ptr_advance    : 8;
328 	u64 capture_flags  : 8;
329 	u64 capture_ltype  : 4;
330 	u64 capture_lid    : 3;
331 	u64 rsvd_43        : 1;
332 	u64 next_state     : 8;
333 	u64 parse_done     : 1;
334 	u64 capture_ena    : 1;
335 	u64 byp_count      : 3;
336 	u64 rsvd_63_57     : 7;
337 #endif
338 };
339 
340 struct npc_kpu_action1 {
341 #if defined(__BIG_ENDIAN_BITFIELD)
342 	u64 rsvd_63_36     : 28;
343 	u64 errlev         : 4;
344 	u64 errcode        : 8;
345 	u64 dp2_offset     : 8;
346 	u64 dp1_offset     : 8;
347 	u64 dp0_offset     : 8;
348 #else
349 	u64 dp0_offset     : 8;
350 	u64 dp1_offset     : 8;
351 	u64 dp2_offset     : 8;
352 	u64 errcode        : 8;
353 	u64 errlev         : 4;
354 	u64 rsvd_63_36     : 28;
355 #endif
356 };
357 
358 struct npc_kpu_pkind_cpi_def {
359 #if defined(__BIG_ENDIAN_BITFIELD)
360 	u64 ena            : 1;
361 	u64 rsvd_62_59     : 4;
362 	u64 lid            : 3;
363 	u64 ltype_match    : 4;
364 	u64 ltype_mask     : 4;
365 	u64 flags_match    : 8;
366 	u64 flags_mask     : 8;
367 	u64 add_offset     : 8;
368 	u64 add_mask       : 8;
369 	u64 rsvd_15        : 1;
370 	u64 add_shift      : 3;
371 	u64 rsvd_11_10     : 2;
372 	u64 cpi_base       : 10;
373 #else
374 	u64 cpi_base       : 10;
375 	u64 rsvd_11_10     : 2;
376 	u64 add_shift      : 3;
377 	u64 rsvd_15        : 1;
378 	u64 add_mask       : 8;
379 	u64 add_offset     : 8;
380 	u64 flags_mask     : 8;
381 	u64 flags_match    : 8;
382 	u64 ltype_mask     : 4;
383 	u64 ltype_match    : 4;
384 	u64 lid            : 3;
385 	u64 rsvd_62_59     : 4;
386 	u64 ena            : 1;
387 #endif
388 };
389 
390 struct nix_rx_action {
391 #if defined(__BIG_ENDIAN_BITFIELD)
392 	u64	rsvd_63_61	:3;
393 	u64	flow_key_alg	:5;
394 	u64	match_id	:16;
395 	u64	index		:20;
396 	u64	pf_func		:16;
397 	u64	op		:4;
398 #else
399 	u64	op		:4;
400 	u64	pf_func		:16;
401 	u64	index		:20;
402 	u64	match_id	:16;
403 	u64	flow_key_alg	:5;
404 	u64	rsvd_63_61	:3;
405 #endif
406 };
407 
408 /* NPC_AF_INTFX_KEX_CFG field masks */
409 #define NPC_EXACT_NIBBLE_START		40
410 #define NPC_EXACT_NIBBLE_END		43
411 #define NPC_EXACT_NIBBLE		GENMASK_ULL(43, 40)
412 
413 /* NPC_EXACT_KEX_S nibble definitions for each field */
414 #define NPC_EXACT_NIBBLE_HIT		BIT_ULL(40)
415 #define NPC_EXACT_NIBBLE_OPC		BIT_ULL(40)
416 #define NPC_EXACT_NIBBLE_WAY		BIT_ULL(40)
417 #define NPC_EXACT_NIBBLE_INDEX		GENMASK_ULL(43, 41)
418 
419 #define NPC_EXACT_RESULT_HIT		BIT_ULL(0)
420 #define NPC_EXACT_RESULT_OPC		GENMASK_ULL(2, 1)
421 #define NPC_EXACT_RESULT_WAY		GENMASK_ULL(4, 3)
422 #define NPC_EXACT_RESULT_IDX		GENMASK_ULL(15, 5)
423 
424 /* NPC_AF_INTFX_KEX_CFG field masks */
425 #define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)
426 
427 /* NPC_PARSE_KEX_S nibble definitions for each field */
428 #define NPC_PARSE_NIBBLE_CHAN		GENMASK_ULL(2, 0)
429 #define NPC_PARSE_NIBBLE_ERRLEV		BIT_ULL(3)
430 #define NPC_PARSE_NIBBLE_ERRCODE	GENMASK_ULL(5, 4)
431 #define NPC_PARSE_NIBBLE_L2L3_BCAST	BIT_ULL(6)
432 #define NPC_PARSE_NIBBLE_LA_FLAGS	GENMASK_ULL(8, 7)
433 #define NPC_PARSE_NIBBLE_LA_LTYPE	BIT_ULL(9)
434 #define NPC_PARSE_NIBBLE_LB_FLAGS	GENMASK_ULL(11, 10)
435 #define NPC_PARSE_NIBBLE_LB_LTYPE	BIT_ULL(12)
436 #define NPC_PARSE_NIBBLE_LC_FLAGS	GENMASK_ULL(14, 13)
437 #define NPC_PARSE_NIBBLE_LC_LTYPE	BIT_ULL(15)
438 #define NPC_PARSE_NIBBLE_LD_FLAGS	GENMASK_ULL(17, 16)
439 #define NPC_PARSE_NIBBLE_LD_LTYPE	BIT_ULL(18)
440 #define NPC_PARSE_NIBBLE_LE_FLAGS	GENMASK_ULL(20, 19)
441 #define NPC_PARSE_NIBBLE_LE_LTYPE	BIT_ULL(21)
442 #define NPC_PARSE_NIBBLE_LF_FLAGS	GENMASK_ULL(23, 22)
443 #define NPC_PARSE_NIBBLE_LF_LTYPE	BIT_ULL(24)
444 #define NPC_PARSE_NIBBLE_LG_FLAGS	GENMASK_ULL(26, 25)
445 #define NPC_PARSE_NIBBLE_LG_LTYPE	BIT_ULL(27)
446 #define NPC_PARSE_NIBBLE_LH_FLAGS	GENMASK_ULL(29, 28)
447 #define NPC_PARSE_NIBBLE_LH_LTYPE	BIT_ULL(30)
448 
449 struct nix_tx_action {
450 #if defined(__BIG_ENDIAN_BITFIELD)
451 	u64	rsvd_63_48	:16;
452 	u64	match_id	:16;
453 	u64	index		:20;
454 	u64	rsvd_11_8	:8;
455 	u64	op		:4;
456 #else
457 	u64	op		:4;
458 	u64	rsvd_11_8	:8;
459 	u64	index		:20;
460 	u64	match_id	:16;
461 	u64	rsvd_63_48	:16;
462 #endif
463 };
464 
465 /* NIX Receive Vtag Action Structure */
466 #define RX_VTAG0_VALID_BIT		BIT_ULL(15)
467 #define RX_VTAG0_TYPE_MASK		GENMASK_ULL(14, 12)
468 #define RX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
469 #define RX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
470 #define RX_VTAG1_VALID_BIT		BIT_ULL(47)
471 #define RX_VTAG1_TYPE_MASK		GENMASK_ULL(46, 44)
472 #define RX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
473 #define RX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
474 
475 /* NIX Transmit Vtag Action Structure */
476 #define TX_VTAG0_DEF_MASK		GENMASK_ULL(25, 16)
477 #define TX_VTAG0_OP_MASK		GENMASK_ULL(13, 12)
478 #define TX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
479 #define TX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
480 #define TX_VTAG1_DEF_MASK		GENMASK_ULL(57, 48)
481 #define TX_VTAG1_OP_MASK		GENMASK_ULL(45, 44)
482 #define TX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
483 #define TX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
484 
485 /* NPC MCAM reserved entry index per nixlf */
486 #define NIXLF_UCAST_ENTRY	0
487 #define NIXLF_BCAST_ENTRY	1
488 #define NIXLF_ALLMULTI_ENTRY	2
489 #define NIXLF_PROMISC_ENTRY	3
490 
491 struct npc_coalesced_kpu_prfl {
492 #define NPC_SIGN	0x00666f727063706e
493 #define NPC_PRFL_NAME   "npc_prfls_array"
494 #define NPC_NAME_LEN	32
495 	__le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */
496 	u8 name[NPC_NAME_LEN]; /* KPU Profile name */
497 	u64 version; /* KPU firmware/profile version */
498 	u8 num_prfl; /* No of NPC profiles. */
499 	u16 prfl_sz[];
500 };
501 
502 struct npc_mcam_kex {
503 	/* MKEX Profle Header */
504 	u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
505 	u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
506 	u64 cpu_model;   /* Format as profiled by CPU hardware */
507 	u64 kpu_version; /* KPU firmware/profile version */
508 	u64 reserved; /* Reserved for extension */
509 
510 	/* MKEX Profle Data */
511 	u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
512 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
513 	u64 kex_ld_flags[NPC_MAX_LD];
514 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
515 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
516 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
517 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
518 } __packed;
519 
520 struct npc_kpu_fwdata {
521 	int	entries;
522 	/* What follows is:
523 	 * struct npc_kpu_profile_cam[entries];
524 	 * struct npc_kpu_profile_action[entries];
525 	 */
526 	u8	data[];
527 } __packed;
528 
529 struct npc_lt_def {
530 	u8	ltype_mask;
531 	u8	ltype_match;
532 	u8	lid;
533 } __packed;
534 
535 struct npc_lt_def_ipsec {
536 	u8	ltype_mask;
537 	u8	ltype_match;
538 	u8	lid;
539 	u8	spi_offset;
540 	u8	spi_nz;
541 } __packed;
542 
543 struct npc_lt_def_apad {
544 	u8	ltype_mask;
545 	u8	ltype_match;
546 	u8	lid;
547 	u8	valid;
548 } __packed;
549 
550 struct npc_lt_def_color {
551 	u8	ltype_mask;
552 	u8	ltype_match;
553 	u8	lid;
554 	u8	noffset;
555 	u8	offset;
556 } __packed;
557 
558 struct npc_lt_def_et {
559 	u8	ltype_mask;
560 	u8	ltype_match;
561 	u8	lid;
562 	u8	valid;
563 	u8	offset;
564 } __packed;
565 
566 struct npc_lt_def_cfg {
567 	struct npc_lt_def	rx_ol2;
568 	struct npc_lt_def	rx_oip4;
569 	struct npc_lt_def	rx_iip4;
570 	struct npc_lt_def	rx_oip6;
571 	struct npc_lt_def	rx_iip6;
572 	struct npc_lt_def	rx_otcp;
573 	struct npc_lt_def	rx_itcp;
574 	struct npc_lt_def	rx_oudp;
575 	struct npc_lt_def	rx_iudp;
576 	struct npc_lt_def	rx_osctp;
577 	struct npc_lt_def	rx_isctp;
578 	struct npc_lt_def_ipsec	rx_ipsec[2];
579 	struct npc_lt_def	pck_ol2;
580 	struct npc_lt_def	pck_oip4;
581 	struct npc_lt_def	pck_oip6;
582 	struct npc_lt_def	pck_iip4;
583 	struct npc_lt_def_apad	rx_apad0;
584 	struct npc_lt_def_apad	rx_apad1;
585 	struct npc_lt_def_color	ovlan;
586 	struct npc_lt_def_color	ivlan;
587 	struct npc_lt_def_color	rx_gen0_color;
588 	struct npc_lt_def_color	rx_gen1_color;
589 	struct npc_lt_def_et	rx_et[2];
590 } __packed;
591 
592 /* Loadable KPU profile firmware data */
593 struct npc_kpu_profile_fwdata {
594 #define KPU_SIGN	0x00666f727075706b
595 #define KPU_NAME_LEN	32
596 /** Maximum number of custom KPU entries supported by the built-in profile. */
597 #define KPU_MAX_CST_ENT	6
598 	/* KPU Profle Header */
599 	__le64	signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
600 	u8	name[KPU_NAME_LEN]; /* KPU Profile name */
601 	__le64	version; /* KPU profile version */
602 	u8	kpus;
603 	u8	reserved[7];
604 
605 	/* Default MKEX profile to be used with this KPU profile. May be
606 	 * overridden with mkex_profile module parameter. Format is same as for
607 	 * the MKEX profile to streamline processing.
608 	 */
609 	struct npc_mcam_kex	mkex;
610 	/* LTYPE values for specific HW offloaded protocols. */
611 	struct npc_lt_def_cfg	lt_def;
612 	/* Dynamically sized data:
613 	 *  Custom KPU CAM and ACTION configuration entries.
614 	 * struct npc_kpu_fwdata kpu[kpus];
615 	 */
616 	u8	data[];
617 } __packed;
618 
619 struct rvu_npc_mcam_rule {
620 	struct flow_msg packet;
621 	struct flow_msg mask;
622 	u8 intf;
623 	union {
624 		struct nix_tx_action tx_action;
625 		struct nix_rx_action rx_action;
626 	};
627 	u64 vtag_action;
628 	struct list_head list;
629 	u64 features;
630 	u16 owner;
631 	u16 entry;
632 	u16 cntr;
633 	bool has_cntr;
634 	u8 default_rule;
635 	bool enable;
636 	bool vfvlan_cfg;
637 	u16 chan;
638 	u16 chan_mask;
639 	u8 lxmb;
640 };
641 
642 #endif /* NPC_H */
643