1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 #define MBOX_DOWN_MSG 1 20 #define MBOX_UP_MSG 2 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x000a) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 104 struct pci_dev *pdev, void __force *reg_base, 105 int direction, int ndevs, unsigned long *bmap); 106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 111 int size, int size_rsp); 112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 113 struct mbox_msghdr *msg); 114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 116 u16 pcifunc, u16 id); 117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 118 const char *otx2_mbox_id2name(u16 id); 119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 120 int devid, int size) 121 { 122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 123 } 124 125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 126 127 /* Mailbox message types */ 128 #define MBOX_MSG_MASK 0xFFFF 129 #define MBOX_MSG_INVALID 0xFFFE 130 #define MBOX_MSG_MAX 0xFFFF 131 132 #define MBOX_MESSAGES \ 133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \ 143 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 144 msg_rsp) \ 145 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 146 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 147 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ 148 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ 149 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ 150 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 151 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 152 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 153 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 154 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 155 cgx_mac_addr_set_or_get) \ 156 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 157 cgx_mac_addr_set_or_get) \ 158 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 159 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 160 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 161 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 162 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 163 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 164 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 165 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 166 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 167 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 168 cgx_pause_frm_cfg) \ 169 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 170 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 171 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 172 cgx_mac_addr_add_rsp) \ 173 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 174 msg_rsp) \ 175 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 176 cgx_max_dmac_entries_get_rsp) \ 177 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 178 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 179 cgx_set_link_mode_rsp) \ 180 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 181 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 182 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 183 cgx_features_info_msg) \ 184 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 185 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 186 msg_rsp) \ 187 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 188 cgx_mac_addr_update_rsp) \ 189 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 190 cgx_pfc_rsp) \ 191 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 192 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 193 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 194 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 195 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 196 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 197 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 198 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 199 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 200 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 201 msg_rsp) \ 202 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 203 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 204 cpt_rd_wr_reg_msg) \ 205 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 206 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 207 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 208 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 209 msg_rsp) \ 210 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 211 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 212 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 213 cpt_flt_eng_info_rsp) \ 214 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 215 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 216 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 217 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 218 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 219 npc_mcam_alloc_entry_rsp) \ 220 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 221 npc_mcam_free_entry_req, msg_rsp) \ 222 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 223 npc_mcam_write_entry_req, msg_rsp) \ 224 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 225 npc_mcam_ena_dis_entry_req, msg_rsp) \ 226 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 227 npc_mcam_ena_dis_entry_req, msg_rsp) \ 228 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 229 npc_mcam_shift_entry_rsp) \ 230 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 231 npc_mcam_alloc_counter_req, \ 232 npc_mcam_alloc_counter_rsp) \ 233 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 234 npc_mcam_oper_counter_req, msg_rsp) \ 235 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 236 npc_mcam_unmap_counter_req, msg_rsp) \ 237 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 238 npc_mcam_oper_counter_req, msg_rsp) \ 239 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 240 npc_mcam_oper_counter_req, \ 241 npc_mcam_oper_counter_rsp) \ 242 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 243 npc_mcam_alloc_and_write_entry_req, \ 244 npc_mcam_alloc_and_write_entry_rsp) \ 245 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 246 msg_req, npc_get_kex_cfg_rsp) \ 247 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 248 npc_install_flow_req, npc_install_flow_rsp) \ 249 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 250 npc_delete_flow_req, npc_delete_flow_rsp) \ 251 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 252 npc_mcam_read_entry_req, \ 253 npc_mcam_read_entry_rsp) \ 254 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 255 npc_set_pkind, msg_rsp) \ 256 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 257 msg_req, npc_mcam_read_base_rule_rsp) \ 258 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 259 npc_mcam_get_stats_req, \ 260 npc_mcam_get_stats_rsp) \ 261 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 262 npc_get_field_hash_info_req, \ 263 npc_get_field_hash_info_rsp) \ 264 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 265 npc_get_field_status_req, \ 266 npc_get_field_status_rsp) \ 267 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 268 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 269 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 270 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 271 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 272 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 273 hwctx_disable_req, msg_rsp) \ 274 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 275 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 276 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 277 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 278 nix_txschq_config) \ 279 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 280 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 281 nix_vtag_config_rsp) \ 282 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 283 nix_rss_flowkey_cfg, \ 284 nix_rss_flowkey_cfg_rsp) \ 285 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 286 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 287 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 288 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 289 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 290 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 291 nix_mark_format_cfg, \ 292 nix_mark_format_cfg_rsp) \ 293 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 294 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 295 nix_lso_format_cfg, \ 296 nix_lso_format_cfg_rsp) \ 297 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 298 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 299 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 300 nix_bp_cfg_rsp) \ 301 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 302 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 303 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 304 nix_inline_ipsec_cfg, msg_rsp) \ 305 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 306 nix_inline_ipsec_lf_cfg, msg_rsp) \ 307 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 308 nix_cn10k_aq_enq_rsp) \ 309 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 310 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 311 nix_bandprof_alloc_rsp) \ 312 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 313 msg_rsp) \ 314 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 315 nix_bandprof_get_hwinfo_rsp) \ 316 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ 317 nix_bp_cfg_rsp) \ 318 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ 319 msg_rsp) \ 320 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 321 msg_req, nix_inline_ipsec_cfg) \ 322 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 323 nix_mcast_grp_create_rsp) \ 324 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 325 msg_rsp) \ 326 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 327 nix_mcast_grp_update_req, \ 328 nix_mcast_grp_update_rsp) \ 329 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \ 330 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 331 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 332 mcs_alloc_rsrc_rsp) \ 333 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 334 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 335 msg_rsp) \ 336 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 337 msg_rsp) \ 338 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 339 msg_rsp) \ 340 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 341 msg_rsp) \ 342 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 343 msg_rsp) \ 344 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 345 msg_rsp) \ 346 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 347 msg_rsp) \ 348 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 349 msg_rsp) \ 350 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 351 msg_rsp) \ 352 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 353 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 354 mcs_flowid_stats) \ 355 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 356 mcs_secy_stats) \ 357 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 358 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 359 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 360 mcs_port_stats) \ 361 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 362 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 363 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 364 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 365 msg_rsp) \ 366 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 367 mcs_alloc_ctrl_pkt_rule_req, \ 368 mcs_alloc_ctrl_pkt_rule_rsp) \ 369 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 370 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 371 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 372 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 373 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 374 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 375 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 376 mcs_port_cfg_get_rsp) \ 377 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 378 mcs_custom_tag_cfg_get_req, \ 379 mcs_custom_tag_cfg_get_rsp) 380 381 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 382 #define MBOX_UP_CGX_MESSAGES \ 383 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 384 385 #define MBOX_UP_CPT_MESSAGES \ 386 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 387 388 #define MBOX_UP_MCS_MESSAGES \ 389 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 390 391 #define MBOX_UP_REP_MESSAGES \ 392 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \ 393 394 enum { 395 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 396 MBOX_MESSAGES 397 MBOX_UP_CGX_MESSAGES 398 MBOX_UP_CPT_MESSAGES 399 MBOX_UP_MCS_MESSAGES 400 MBOX_UP_REP_MESSAGES 401 #undef M 402 }; 403 404 /* Mailbox message formats */ 405 406 #define RVU_DEFAULT_PF_FUNC 0xFFFF 407 408 /* Generic request msg used for those mbox messages which 409 * don't send any data in the request. 410 */ 411 struct msg_req { 412 struct mbox_msghdr hdr; 413 }; 414 415 /* Generic response msg used an ack or response for those mbox 416 * messages which don't have a specific rsp msg format. 417 */ 418 struct msg_rsp { 419 struct mbox_msghdr hdr; 420 }; 421 422 /* RVU mailbox error codes 423 * Range 256 - 300. 424 */ 425 enum rvu_af_status { 426 RVU_INVALID_VF_ID = -256, 427 }; 428 429 struct ready_msg_rsp { 430 struct mbox_msghdr hdr; 431 u16 sclk_freq; /* SCLK frequency (in MHz) */ 432 u16 rclk_freq; /* RCLK frequency (in MHz) */ 433 }; 434 435 /* Structure for requesting resource provisioning. 436 * 'modify' flag to be used when either requesting more 437 * or to detach partial of a certain resource type. 438 * Rest of the fields specify how many of what type to 439 * be attached. 440 * To request LFs from two blocks of same type this mailbox 441 * can be sent twice as below: 442 * struct rsrc_attach *attach; 443 * .. Allocate memory for message .. 444 * attach->cptlfs = 3; <3 LFs from CPT0> 445 * .. Send message .. 446 * .. Allocate memory for message .. 447 * attach->modify = 1; 448 * attach->cpt_blkaddr = BLKADDR_CPT1; 449 * attach->cptlfs = 2; <2 LFs from CPT1> 450 * .. Send message .. 451 */ 452 struct rsrc_attach { 453 struct mbox_msghdr hdr; 454 u8 modify:1; 455 u8 npalf:1; 456 u8 nixlf:1; 457 u16 sso; 458 u16 ssow; 459 u16 timlfs; 460 u16 cptlfs; 461 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 462 }; 463 464 /* Structure for relinquishing resources. 465 * 'partial' flag to be used when relinquishing all resources 466 * but only of a certain type. If not set, all resources of all 467 * types provisioned to the RVU function will be detached. 468 */ 469 struct rsrc_detach { 470 struct mbox_msghdr hdr; 471 u8 partial:1; 472 u8 npalf:1; 473 u8 nixlf:1; 474 u8 sso:1; 475 u8 ssow:1; 476 u8 timlfs:1; 477 u8 cptlfs:1; 478 }; 479 480 /* Number of resources available to the caller. 481 * In reply to MBOX_MSG_FREE_RSRC_CNT. 482 */ 483 struct free_rsrcs_rsp { 484 struct mbox_msghdr hdr; 485 u16 schq[NIX_TXSCH_LVL_CNT]; 486 u16 sso; 487 u16 tim; 488 u16 ssow; 489 u16 cpt; 490 u8 npa; 491 u8 nix; 492 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 493 u8 nix1; 494 u8 cpt1; 495 u8 ree0; 496 u8 ree1; 497 }; 498 499 #define MSIX_VECTOR_INVALID 0xFFFF 500 #define MAX_RVU_BLKLF_CNT 256 501 502 struct msix_offset_rsp { 503 struct mbox_msghdr hdr; 504 u16 npa_msixoff; 505 u16 nix_msixoff; 506 u16 sso; 507 u16 ssow; 508 u16 timlfs; 509 u16 cptlfs; 510 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 511 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 512 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 513 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 514 u16 cpt1_lfs; 515 u16 ree0_lfs; 516 u16 ree1_lfs; 517 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 518 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 519 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 520 }; 521 522 struct get_hw_cap_rsp { 523 struct mbox_msghdr hdr; 524 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 525 u8 nix_shaping; /* Is shaping and coloring supported */ 526 u8 npc_hash_extract; /* Is hash extract supported */ 527 #define HW_CAP_MACSEC BIT_ULL(1) 528 u64 hw_caps; 529 }; 530 531 /* CGX mbox message formats */ 532 533 struct cgx_stats_rsp { 534 struct mbox_msghdr hdr; 535 #define CGX_RX_STATS_COUNT 9 536 #define CGX_TX_STATS_COUNT 18 537 u64 rx_stats[CGX_RX_STATS_COUNT]; 538 u64 tx_stats[CGX_TX_STATS_COUNT]; 539 }; 540 541 struct cgx_fec_stats_rsp { 542 struct mbox_msghdr hdr; 543 u64 fec_corr_blks; 544 u64 fec_uncorr_blks; 545 }; 546 /* Structure for requesting the operation for 547 * setting/getting mac address in the CGX interface 548 */ 549 struct cgx_mac_addr_set_or_get { 550 struct mbox_msghdr hdr; 551 u8 mac_addr[ETH_ALEN]; 552 u32 index; 553 }; 554 555 /* Structure for requesting the operation to 556 * add DMAC filter entry into CGX interface 557 */ 558 struct cgx_mac_addr_add_req { 559 struct mbox_msghdr hdr; 560 u8 mac_addr[ETH_ALEN]; 561 }; 562 563 /* Structure for response against the operation to 564 * add DMAC filter entry into CGX interface 565 */ 566 struct cgx_mac_addr_add_rsp { 567 struct mbox_msghdr hdr; 568 u32 index; 569 }; 570 571 /* Structure for requesting the operation to 572 * delete DMAC filter entry from CGX interface 573 */ 574 struct cgx_mac_addr_del_req { 575 struct mbox_msghdr hdr; 576 u32 index; 577 }; 578 579 /* Structure for response against the operation to 580 * get maximum supported DMAC filter entries 581 */ 582 struct cgx_max_dmac_entries_get_rsp { 583 struct mbox_msghdr hdr; 584 u32 max_dmac_filters; 585 }; 586 587 struct cgx_link_user_info { 588 uint64_t link_up:1; 589 uint64_t full_duplex:1; 590 uint64_t lmac_type_id:4; 591 uint64_t speed:20; /* speed in Mbps */ 592 uint64_t an:1; /* AN supported or not */ 593 uint64_t fec:2; /* FEC type if enabled else 0 */ 594 #define LMACTYPE_STR_LEN 16 595 char lmac_type[LMACTYPE_STR_LEN]; 596 }; 597 598 struct cgx_link_info_msg { 599 struct mbox_msghdr hdr; 600 struct cgx_link_user_info link_info; 601 }; 602 603 struct cgx_pause_frm_cfg { 604 struct mbox_msghdr hdr; 605 u8 set; 606 /* set = 1 if the request is to config pause frames */ 607 /* set = 0 if the request is to fetch pause frames config */ 608 u8 rx_pause; 609 u8 tx_pause; 610 }; 611 612 enum fec_type { 613 OTX2_FEC_NONE, 614 OTX2_FEC_BASER, 615 OTX2_FEC_RS, 616 OTX2_FEC_STATS_CNT = 2, 617 OTX2_FEC_OFF, 618 }; 619 620 struct fec_mode { 621 struct mbox_msghdr hdr; 622 int fec; 623 }; 624 625 struct sfp_eeprom_s { 626 #define SFP_EEPROM_SIZE 256 627 u16 sff_id; 628 u8 buf[SFP_EEPROM_SIZE]; 629 u64 reserved; 630 }; 631 632 struct phy_s { 633 struct { 634 u64 can_change_mod_type:1; 635 u64 mod_type:1; 636 u64 has_fec_stats:1; 637 } misc; 638 struct fec_stats_s { 639 u32 rsfec_corr_cws; 640 u32 rsfec_uncorr_cws; 641 u32 brfec_corr_blks; 642 u32 brfec_uncorr_blks; 643 } fec_stats; 644 }; 645 646 struct cgx_lmac_fwdata_s { 647 u16 rw_valid; 648 u64 supported_fec; 649 u64 supported_an; 650 u64 supported_link_modes; 651 /* only applicable if AN is supported */ 652 u64 advertised_fec; 653 u64 advertised_link_modes; 654 /* Only applicable if SFP/QSFP slot is present */ 655 struct sfp_eeprom_s sfp_eeprom; 656 struct phy_s phy; 657 #define LMAC_FWDATA_RESERVED_MEM 1021 658 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 659 }; 660 661 struct cgx_fw_data { 662 struct mbox_msghdr hdr; 663 struct cgx_lmac_fwdata_s fwdata; 664 }; 665 666 struct cgx_set_link_mode_args { 667 u32 speed; 668 u8 duplex; 669 u8 an; 670 u8 ports; 671 u64 mode; 672 }; 673 674 struct cgx_set_link_mode_req { 675 #define AUTONEG_UNKNOWN 0xff 676 struct mbox_msghdr hdr; 677 struct cgx_set_link_mode_args args; 678 }; 679 680 struct cgx_set_link_mode_rsp { 681 struct mbox_msghdr hdr; 682 int status; 683 }; 684 685 struct cgx_mac_addr_reset_req { 686 struct mbox_msghdr hdr; 687 u32 index; 688 }; 689 690 struct cgx_mac_addr_update_req { 691 struct mbox_msghdr hdr; 692 u8 mac_addr[ETH_ALEN]; 693 u32 index; 694 }; 695 696 struct cgx_mac_addr_update_rsp { 697 struct mbox_msghdr hdr; 698 u32 index; 699 }; 700 701 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 702 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 703 /* flow control from physical link higig2 messages */ 704 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 705 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 706 #define RVU_MAC_VERSION BIT_ULL(4) 707 #define RVU_MAC_CGX BIT_ULL(5) 708 #define RVU_MAC_RPM BIT_ULL(6) 709 710 struct cgx_features_info_msg { 711 struct mbox_msghdr hdr; 712 u64 lmac_features; 713 }; 714 715 struct rpm_stats_rsp { 716 struct mbox_msghdr hdr; 717 #define RPM_RX_STATS_COUNT 43 718 #define RPM_TX_STATS_COUNT 34 719 u64 rx_stats[RPM_RX_STATS_COUNT]; 720 u64 tx_stats[RPM_TX_STATS_COUNT]; 721 }; 722 723 struct cgx_pfc_cfg { 724 struct mbox_msghdr hdr; 725 u8 rx_pause; 726 u8 tx_pause; 727 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 728 }; 729 730 struct cgx_pfc_rsp { 731 struct mbox_msghdr hdr; 732 u8 rx_pause; 733 u8 tx_pause; 734 }; 735 736 /* NPA mbox message formats */ 737 738 struct npc_set_pkind { 739 struct mbox_msghdr hdr; 740 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 741 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 742 u64 mode; 743 #define PKIND_TX BIT_ULL(0) 744 #define PKIND_RX BIT_ULL(1) 745 u8 dir; 746 u8 pkind; /* valid only in case custom flag */ 747 u8 var_len_off; /* Offset of custom header length field. 748 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 749 */ 750 u8 var_len_off_mask; /* Mask for length with in offset */ 751 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 752 }; 753 754 /* NPA mbox message formats */ 755 756 /* NPA mailbox error codes 757 * Range 301 - 400. 758 */ 759 enum npa_af_status { 760 NPA_AF_ERR_PARAM = -301, 761 NPA_AF_ERR_AQ_FULL = -302, 762 NPA_AF_ERR_AQ_ENQUEUE = -303, 763 NPA_AF_ERR_AF_LF_INVALID = -304, 764 NPA_AF_ERR_AF_LF_ALLOC = -305, 765 NPA_AF_ERR_LF_RESET = -306, 766 }; 767 768 /* For NPA LF context alloc and init */ 769 struct npa_lf_alloc_req { 770 struct mbox_msghdr hdr; 771 int node; 772 int aura_sz; /* No of auras */ 773 u32 nr_pools; /* No of pools */ 774 u64 way_mask; 775 }; 776 777 struct npa_lf_alloc_rsp { 778 struct mbox_msghdr hdr; 779 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 780 u32 stack_pg_bytes; /* Size of stack page */ 781 u16 qints; /* NPA_AF_CONST::QINTS */ 782 u8 cache_lines; /*BATCH ALLOC DMA */ 783 }; 784 785 /* NPA AQ enqueue msg */ 786 struct npa_aq_enq_req { 787 struct mbox_msghdr hdr; 788 u32 aura_id; 789 u8 ctype; 790 u8 op; 791 union { 792 /* Valid when op == WRITE/INIT and ctype == AURA. 793 * LF fills the pool_id in aura.pool_addr. AF will translate 794 * the pool_id to pool context pointer. 795 */ 796 struct npa_aura_s aura; 797 /* Valid when op == WRITE/INIT and ctype == POOL */ 798 struct npa_pool_s pool; 799 }; 800 /* Mask data when op == WRITE (1=write, 0=don't write) */ 801 union { 802 /* Valid when op == WRITE and ctype == AURA */ 803 struct npa_aura_s aura_mask; 804 /* Valid when op == WRITE and ctype == POOL */ 805 struct npa_pool_s pool_mask; 806 }; 807 }; 808 809 struct npa_aq_enq_rsp { 810 struct mbox_msghdr hdr; 811 union { 812 /* Valid when op == READ and ctype == AURA */ 813 struct npa_aura_s aura; 814 /* Valid when op == READ and ctype == POOL */ 815 struct npa_pool_s pool; 816 }; 817 }; 818 819 /* Disable all contexts of type 'ctype' */ 820 struct hwctx_disable_req { 821 struct mbox_msghdr hdr; 822 u8 ctype; 823 }; 824 825 /* NIX mbox message formats */ 826 827 /* NIX mailbox error codes 828 * Range 401 - 500. 829 */ 830 enum nix_af_status { 831 NIX_AF_ERR_PARAM = -401, 832 NIX_AF_ERR_AQ_FULL = -402, 833 NIX_AF_ERR_AQ_ENQUEUE = -403, 834 NIX_AF_ERR_AF_LF_INVALID = -404, 835 NIX_AF_ERR_AF_LF_ALLOC = -405, 836 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 837 NIX_AF_ERR_TLX_INVALID = -407, 838 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 839 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 840 NIX_AF_ERR_FRS_INVALID = -410, 841 NIX_AF_ERR_RX_LINK_INVALID = -411, 842 NIX_AF_INVAL_TXSCHQ_CFG = -412, 843 NIX_AF_SMQ_FLUSH_FAILED = -413, 844 NIX_AF_ERR_LF_RESET = -414, 845 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 846 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 847 NIX_AF_ERR_MARK_CFG_FAIL = -417, 848 NIX_AF_ERR_LSO_CFG_FAIL = -418, 849 NIX_AF_INVAL_NPA_PF_FUNC = -419, 850 NIX_AF_INVAL_SSO_PF_FUNC = -420, 851 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 852 NIX_AF_ERR_RX_VTAG_INUSE = -422, 853 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 854 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 855 NIX_AF_ERR_INVALID_NIXBLK = -425, 856 NIX_AF_ERR_INVALID_BANDPROF = -426, 857 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 858 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 859 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 860 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 861 NIX_AF_ERR_LINK_CREDITS = -431, 862 NIX_AF_ERR_INVALID_BPID = -434, 863 NIX_AF_ERR_INVALID_BPID_REQ = -435, 864 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 865 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 866 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 867 }; 868 869 /* For NIX RX vtag action */ 870 enum nix_rx_vtag0_type { 871 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 872 NIX_AF_LFX_RX_VTAG_TYPE1, 873 NIX_AF_LFX_RX_VTAG_TYPE2, 874 NIX_AF_LFX_RX_VTAG_TYPE3, 875 NIX_AF_LFX_RX_VTAG_TYPE4, 876 NIX_AF_LFX_RX_VTAG_TYPE5, 877 NIX_AF_LFX_RX_VTAG_TYPE6, 878 NIX_AF_LFX_RX_VTAG_TYPE7, 879 }; 880 881 /* For NIX LF context alloc and init */ 882 struct nix_lf_alloc_req { 883 struct mbox_msghdr hdr; 884 int node; 885 u32 rq_cnt; /* No of receive queues */ 886 u32 sq_cnt; /* No of send queues */ 887 u32 cq_cnt; /* No of completion queues */ 888 u8 xqe_sz; 889 u16 rss_sz; 890 u8 rss_grps; 891 u16 npa_func; 892 u16 sso_func; 893 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 894 u64 way_mask; 895 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 896 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 897 u64 flags; 898 }; 899 900 struct nix_lf_alloc_rsp { 901 struct mbox_msghdr hdr; 902 u16 sqb_size; 903 u16 rx_chan_base; 904 u16 tx_chan_base; 905 u8 rx_chan_cnt; /* total number of RX channels */ 906 u8 tx_chan_cnt; /* total number of TX channels */ 907 u8 lso_tsov4_idx; 908 u8 lso_tsov6_idx; 909 u8 mac_addr[ETH_ALEN]; 910 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 911 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 912 u16 cints; /* NIX_AF_CONST2::CINTS */ 913 u16 qints; /* NIX_AF_CONST2::QINTS */ 914 u8 cgx_links; /* No. of CGX links present in HW */ 915 u8 lbk_links; /* No. of LBK links present in HW */ 916 u8 sdp_links; /* No. of SDP links present in HW */ 917 u8 tx_link; /* Transmit channel link number */ 918 }; 919 920 struct nix_lf_free_req { 921 struct mbox_msghdr hdr; 922 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 923 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 924 u64 flags; 925 }; 926 927 /* CN10K NIX AQ enqueue msg */ 928 struct nix_cn10k_aq_enq_req { 929 struct mbox_msghdr hdr; 930 u32 qidx; 931 u8 ctype; 932 u8 op; 933 union { 934 struct nix_cn10k_rq_ctx_s rq; 935 struct nix_cn10k_sq_ctx_s sq; 936 struct nix_cq_ctx_s cq; 937 struct nix_rsse_s rss; 938 struct nix_rx_mce_s mce; 939 struct nix_bandprof_s prof; 940 }; 941 union { 942 struct nix_cn10k_rq_ctx_s rq_mask; 943 struct nix_cn10k_sq_ctx_s sq_mask; 944 struct nix_cq_ctx_s cq_mask; 945 struct nix_rsse_s rss_mask; 946 struct nix_rx_mce_s mce_mask; 947 struct nix_bandprof_s prof_mask; 948 }; 949 }; 950 951 struct nix_cn10k_aq_enq_rsp { 952 struct mbox_msghdr hdr; 953 union { 954 struct nix_cn10k_rq_ctx_s rq; 955 struct nix_cn10k_sq_ctx_s sq; 956 struct nix_cq_ctx_s cq; 957 struct nix_rsse_s rss; 958 struct nix_rx_mce_s mce; 959 struct nix_bandprof_s prof; 960 }; 961 }; 962 963 /* NIX AQ enqueue msg */ 964 struct nix_aq_enq_req { 965 struct mbox_msghdr hdr; 966 u32 qidx; 967 u8 ctype; 968 u8 op; 969 union { 970 struct nix_rq_ctx_s rq; 971 struct nix_sq_ctx_s sq; 972 struct nix_cq_ctx_s cq; 973 struct nix_rsse_s rss; 974 struct nix_rx_mce_s mce; 975 struct nix_bandprof_s prof; 976 }; 977 union { 978 struct nix_rq_ctx_s rq_mask; 979 struct nix_sq_ctx_s sq_mask; 980 struct nix_cq_ctx_s cq_mask; 981 struct nix_rsse_s rss_mask; 982 struct nix_rx_mce_s mce_mask; 983 struct nix_bandprof_s prof_mask; 984 }; 985 }; 986 987 struct nix_aq_enq_rsp { 988 struct mbox_msghdr hdr; 989 union { 990 struct nix_rq_ctx_s rq; 991 struct nix_sq_ctx_s sq; 992 struct nix_cq_ctx_s cq; 993 struct nix_rsse_s rss; 994 struct nix_rx_mce_s mce; 995 struct nix_bandprof_s prof; 996 }; 997 }; 998 999 /* Tx scheduler/shaper mailbox messages */ 1000 1001 #define MAX_TXSCHQ_PER_FUNC 128 1002 1003 struct nix_txsch_alloc_req { 1004 struct mbox_msghdr hdr; 1005 /* Scheduler queue count request at each level */ 1006 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 1007 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 1008 }; 1009 1010 struct nix_txsch_alloc_rsp { 1011 struct mbox_msghdr hdr; 1012 /* Scheduler queue count allocated at each level */ 1013 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 1014 u16 schq[NIX_TXSCH_LVL_CNT]; 1015 /* Scheduler queue list allocated at each level */ 1016 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1017 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1018 u8 aggr_level; /* Traffic aggregation scheduler level */ 1019 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 1020 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 1021 }; 1022 1023 struct nix_txsch_free_req { 1024 struct mbox_msghdr hdr; 1025 #define TXSCHQ_FREE_ALL BIT_ULL(0) 1026 u16 flags; 1027 /* Scheduler queue level to be freed */ 1028 u16 schq_lvl; 1029 /* List of scheduler queues to be freed */ 1030 u16 schq; 1031 }; 1032 1033 struct nix_txschq_config { 1034 struct mbox_msghdr hdr; 1035 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1036 u8 read; 1037 #define TXSCHQ_IDX_SHIFT 16 1038 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1039 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1040 u8 num_regs; 1041 #define MAX_REGS_PER_MBOX_MSG 20 1042 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1043 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1044 /* All 0's => overwrite with new value */ 1045 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1046 }; 1047 1048 struct nix_vtag_config { 1049 struct mbox_msghdr hdr; 1050 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1051 u8 vtag_size; 1052 /* cfg_type is '0' for tx vlan cfg 1053 * cfg_type is '1' for rx vlan cfg 1054 */ 1055 u8 cfg_type; 1056 union { 1057 /* valid when cfg_type is '0' */ 1058 struct { 1059 u64 vtag0; 1060 u64 vtag1; 1061 1062 /* cfg_vtag0 & cfg_vtag1 fields are valid 1063 * when free_vtag0 & free_vtag1 are '0's. 1064 */ 1065 /* cfg_vtag0 = 1 to configure vtag0 */ 1066 u8 cfg_vtag0 :1; 1067 /* cfg_vtag1 = 1 to configure vtag1 */ 1068 u8 cfg_vtag1 :1; 1069 1070 /* vtag0_idx & vtag1_idx are only valid when 1071 * both cfg_vtag0 & cfg_vtag1 are '0's, 1072 * these fields are used along with free_vtag0 1073 * & free_vtag1 to free the nix lf's tx_vlan 1074 * configuration. 1075 * 1076 * Denotes the indices of tx_vtag def registers 1077 * that needs to be cleared and freed. 1078 */ 1079 int vtag0_idx; 1080 int vtag1_idx; 1081 1082 /* free_vtag0 & free_vtag1 fields are valid 1083 * when cfg_vtag0 & cfg_vtag1 are '0's. 1084 */ 1085 /* free_vtag0 = 1 clears vtag0 configuration 1086 * vtag0_idx denotes the index to be cleared. 1087 */ 1088 u8 free_vtag0 :1; 1089 /* free_vtag1 = 1 clears vtag1 configuration 1090 * vtag1_idx denotes the index to be cleared. 1091 */ 1092 u8 free_vtag1 :1; 1093 } tx; 1094 1095 /* valid when cfg_type is '1' */ 1096 struct { 1097 /* rx vtag type index, valid values are in 0..7 range */ 1098 u8 vtag_type; 1099 /* rx vtag strip */ 1100 u8 strip_vtag :1; 1101 /* rx vtag capture */ 1102 u8 capture_vtag :1; 1103 } rx; 1104 }; 1105 }; 1106 1107 struct nix_vtag_config_rsp { 1108 struct mbox_msghdr hdr; 1109 int vtag0_idx; 1110 int vtag1_idx; 1111 /* Indices of tx_vtag def registers used to configure 1112 * tx vtag0 & vtag1 headers, these indices are valid 1113 * when nix_vtag_config mbox requested for vtag0 and/ 1114 * or vtag1 configuration. 1115 */ 1116 }; 1117 1118 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1119 1120 struct nix_rss_flowkey_cfg { 1121 struct mbox_msghdr hdr; 1122 int mcam_index; /* MCAM entry index to modify */ 1123 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1124 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1125 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1126 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1127 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1128 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1129 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1130 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1131 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1132 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1133 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1134 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1135 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1136 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1137 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1138 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1139 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1140 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1141 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1142 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1143 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1144 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1145 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1146 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1147 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1148 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1149 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1150 u32 flowkey_cfg; /* Flowkey types selected */ 1151 u8 group; /* RSS context or group */ 1152 }; 1153 1154 struct nix_rss_flowkey_cfg_rsp { 1155 struct mbox_msghdr hdr; 1156 u8 alg_idx; /* Selected algo index */ 1157 }; 1158 1159 struct nix_set_mac_addr { 1160 struct mbox_msghdr hdr; 1161 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1162 }; 1163 1164 struct nix_get_mac_addr_rsp { 1165 struct mbox_msghdr hdr; 1166 u8 mac_addr[ETH_ALEN]; 1167 }; 1168 1169 struct nix_mark_format_cfg { 1170 struct mbox_msghdr hdr; 1171 u8 offset; 1172 u8 y_mask; 1173 u8 y_val; 1174 u8 r_mask; 1175 u8 r_val; 1176 }; 1177 1178 struct nix_mark_format_cfg_rsp { 1179 struct mbox_msghdr hdr; 1180 u8 mark_format_idx; 1181 }; 1182 1183 struct nix_rx_mode { 1184 struct mbox_msghdr hdr; 1185 #define NIX_RX_MODE_UCAST BIT(0) 1186 #define NIX_RX_MODE_PROMISC BIT(1) 1187 #define NIX_RX_MODE_ALLMULTI BIT(2) 1188 #define NIX_RX_MODE_USE_MCE BIT(3) 1189 u16 mode; 1190 }; 1191 1192 struct nix_rx_cfg { 1193 struct mbox_msghdr hdr; 1194 #define NIX_RX_OL3_VERIFY BIT(0) 1195 #define NIX_RX_OL4_VERIFY BIT(1) 1196 #define NIX_RX_DROP_RE BIT(2) 1197 u8 len_verify; /* Outer L3/L4 len check */ 1198 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1199 u8 csum_verify; /* Outer L4 checksum verification */ 1200 }; 1201 1202 struct nix_frs_cfg { 1203 struct mbox_msghdr hdr; 1204 u8 update_smq; /* Update SMQ's min/max lens */ 1205 u8 update_minlen; /* Set minlen also */ 1206 u8 sdp_link; /* Set SDP RX link */ 1207 u16 maxlen; 1208 u16 minlen; 1209 }; 1210 1211 struct nix_lso_format_cfg { 1212 struct mbox_msghdr hdr; 1213 u64 field_mask; 1214 #define NIX_LSO_FIELD_MAX 8 1215 u64 fields[NIX_LSO_FIELD_MAX]; 1216 }; 1217 1218 struct nix_lso_format_cfg_rsp { 1219 struct mbox_msghdr hdr; 1220 u8 lso_format_idx; 1221 }; 1222 1223 struct nix_bp_cfg_req { 1224 struct mbox_msghdr hdr; 1225 u16 chan_base; /* Starting channel number */ 1226 u8 chan_cnt; /* Number of channels */ 1227 u8 bpid_per_chan; 1228 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1229 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1230 }; 1231 1232 /* Maximum channels any single NIX interface can have */ 1233 #define NIX_MAX_BPID_CHAN 256 1234 struct nix_bp_cfg_rsp { 1235 struct mbox_msghdr hdr; 1236 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1237 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1238 }; 1239 1240 struct nix_mcast_grp_create_req { 1241 struct mbox_msghdr hdr; 1242 #define NIX_MCAST_INGRESS 0 1243 #define NIX_MCAST_EGRESS 1 1244 u8 dir; 1245 u8 reserved[11]; 1246 /* Reserving few bytes for future requirement */ 1247 }; 1248 1249 struct nix_mcast_grp_create_rsp { 1250 struct mbox_msghdr hdr; 1251 /* This mcast_grp_idx should be passed during MCAM 1252 * write entry for multicast. AF will identify the 1253 * corresponding multicast table index associated 1254 * with the group id and program the same to MCAM entry. 1255 * This group id is also needed during group delete 1256 * and update request. 1257 */ 1258 u32 mcast_grp_idx; 1259 }; 1260 1261 struct nix_mcast_grp_destroy_req { 1262 struct mbox_msghdr hdr; 1263 /* Group id returned by nix_mcast_grp_create_rsp */ 1264 u32 mcast_grp_idx; 1265 /* If AF is requesting for destroy, then set 1266 * it to '1'. Otherwise keep it to '0' 1267 */ 1268 u8 is_af; 1269 }; 1270 1271 struct nix_mcast_grp_update_req { 1272 struct mbox_msghdr hdr; 1273 /* Group id returned by nix_mcast_grp_create_rsp */ 1274 u32 mcast_grp_idx; 1275 /* Number of multicast/mirror entries requested */ 1276 u32 num_mce_entry; 1277 #define NIX_MCE_ENTRY_MAX 64 1278 #define NIX_RX_RQ 0 1279 #define NIX_RX_RSS 1 1280 /* Receive queue or RSS index within pf_func */ 1281 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1282 /* pcifunc is required for both ingress and egress multicast */ 1283 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1284 /* channel is required for egress multicast */ 1285 u16 channel[NIX_MCE_ENTRY_MAX]; 1286 #define NIX_MCAST_OP_ADD_ENTRY 0 1287 #define NIX_MCAST_OP_DEL_ENTRY 1 1288 /* Destination type. 0:Receive queue, 1:RSS*/ 1289 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1290 u8 op; 1291 /* If AF is requesting for update, then set 1292 * it to '1'. Otherwise keep it to '0' 1293 */ 1294 u8 is_af; 1295 }; 1296 1297 struct nix_mcast_grp_update_rsp { 1298 struct mbox_msghdr hdr; 1299 u32 mce_start_index; 1300 }; 1301 1302 /* Global NIX inline IPSec configuration */ 1303 struct nix_inline_ipsec_cfg { 1304 struct mbox_msghdr hdr; 1305 u32 cpt_credit; 1306 struct { 1307 u8 egrp; 1308 u16 opcode; 1309 u16 param1; 1310 u16 param2; 1311 } gen_cfg; 1312 struct { 1313 u16 cpt_pf_func; 1314 u8 cpt_slot; 1315 } inst_qsel; 1316 u8 enable; 1317 u16 bpid; 1318 u32 credit_th; 1319 }; 1320 1321 /* Per NIX LF inline IPSec configuration */ 1322 struct nix_inline_ipsec_lf_cfg { 1323 struct mbox_msghdr hdr; 1324 u64 sa_base_addr; 1325 struct { 1326 u32 tag_const; 1327 u16 lenm1_max; 1328 u8 sa_pow2_size; 1329 u8 tt; 1330 } ipsec_cfg0; 1331 struct { 1332 u32 sa_idx_max; 1333 u8 sa_idx_w; 1334 } ipsec_cfg1; 1335 u8 enable; 1336 }; 1337 1338 struct nix_hw_info { 1339 struct mbox_msghdr hdr; 1340 u16 rsvs16; 1341 u16 max_mtu; 1342 u16 min_mtu; 1343 u32 rpm_dwrr_mtu; 1344 u32 sdp_dwrr_mtu; 1345 u32 lbk_dwrr_mtu; 1346 u32 rsvd32[1]; 1347 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1348 }; 1349 1350 struct nix_bandprof_alloc_req { 1351 struct mbox_msghdr hdr; 1352 /* Count of profiles needed per layer */ 1353 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1354 }; 1355 1356 struct nix_bandprof_alloc_rsp { 1357 struct mbox_msghdr hdr; 1358 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1359 1360 /* There is no need to allocate morethan 1 bandwidth profile 1361 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1362 * profiles to 64 per PF_FUNC. 1363 */ 1364 #define MAX_BANDPROF_PER_PFFUNC 64 1365 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1366 }; 1367 1368 struct nix_bandprof_free_req { 1369 struct mbox_msghdr hdr; 1370 u8 free_all; 1371 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1372 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1373 }; 1374 1375 struct nix_bandprof_get_hwinfo_rsp { 1376 struct mbox_msghdr hdr; 1377 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1378 u32 policer_timeunit; 1379 }; 1380 1381 struct nix_stats_req { 1382 struct mbox_msghdr hdr; 1383 u8 reset; 1384 u16 pcifunc; 1385 u64 rsvd; 1386 }; 1387 1388 struct nix_stats_rsp { 1389 struct mbox_msghdr hdr; 1390 u16 pcifunc; 1391 struct { 1392 u64 octs; 1393 u64 ucast; 1394 u64 bcast; 1395 u64 mcast; 1396 u64 drop; 1397 u64 drop_octs; 1398 u64 drop_mcast; 1399 u64 drop_bcast; 1400 u64 err; 1401 u64 rsvd[5]; 1402 } rx; 1403 struct { 1404 u64 ucast; 1405 u64 bcast; 1406 u64 mcast; 1407 u64 drop; 1408 u64 octs; 1409 } tx; 1410 }; 1411 1412 /* NPC mbox message structs */ 1413 1414 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1415 #define NPC_MCAM_INVALID_MAP 0xFFFF 1416 1417 /* NPC mailbox error codes 1418 * Range 701 - 800. 1419 */ 1420 enum npc_af_status { 1421 NPC_MCAM_INVALID_REQ = -701, 1422 NPC_MCAM_ALLOC_DENIED = -702, 1423 NPC_MCAM_ALLOC_FAILED = -703, 1424 NPC_MCAM_PERM_DENIED = -704, 1425 NPC_FLOW_INTF_INVALID = -707, 1426 NPC_FLOW_CHAN_INVALID = -708, 1427 NPC_FLOW_NO_NIXLF = -709, 1428 NPC_FLOW_NOT_SUPPORTED = -710, 1429 NPC_FLOW_VF_PERM_DENIED = -711, 1430 NPC_FLOW_VF_NOT_INIT = -712, 1431 NPC_FLOW_VF_OVERLAP = -713, 1432 }; 1433 1434 struct npc_mcam_alloc_entry_req { 1435 struct mbox_msghdr hdr; 1436 #define NPC_MAX_NONCONTIG_ENTRIES 256 1437 u8 contig; /* Contiguous entries ? */ 1438 #define NPC_MCAM_ANY_PRIO 0 1439 #define NPC_MCAM_LOWER_PRIO 1 1440 #define NPC_MCAM_HIGHER_PRIO 2 1441 u8 priority; /* Lower or higher w.r.t ref_entry */ 1442 u16 ref_entry; 1443 u16 count; /* Number of entries requested */ 1444 }; 1445 1446 struct npc_mcam_alloc_entry_rsp { 1447 struct mbox_msghdr hdr; 1448 u16 entry; /* Entry allocated or start index if contiguous. 1449 * Invalid incase of non-contiguous. 1450 */ 1451 u16 count; /* Number of entries allocated */ 1452 u16 free_count; /* Number of entries available */ 1453 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1454 }; 1455 1456 struct npc_mcam_free_entry_req { 1457 struct mbox_msghdr hdr; 1458 u16 entry; /* Entry index to be freed */ 1459 u8 all; /* If all entries allocated to this PFVF to be freed */ 1460 }; 1461 1462 struct mcam_entry { 1463 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1464 u64 kw[NPC_MAX_KWS_IN_KEY]; 1465 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1466 u64 action; 1467 u64 vtag_action; 1468 }; 1469 1470 struct npc_mcam_write_entry_req { 1471 struct mbox_msghdr hdr; 1472 struct mcam_entry entry_data; 1473 u16 entry; /* MCAM entry to write this match key */ 1474 u16 cntr; /* Counter for this MCAM entry */ 1475 u8 intf; /* Rx or Tx interface */ 1476 u8 enable_entry;/* Enable this MCAM entry ? */ 1477 u8 set_cntr; /* Set counter for this entry ? */ 1478 }; 1479 1480 /* Enable/Disable a given entry */ 1481 struct npc_mcam_ena_dis_entry_req { 1482 struct mbox_msghdr hdr; 1483 u16 entry; 1484 }; 1485 1486 struct npc_mcam_shift_entry_req { 1487 struct mbox_msghdr hdr; 1488 #define NPC_MCAM_MAX_SHIFTS 64 1489 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1490 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1491 u16 shift_count; /* Number of entries to shift */ 1492 }; 1493 1494 struct npc_mcam_shift_entry_rsp { 1495 struct mbox_msghdr hdr; 1496 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1497 }; 1498 1499 struct npc_mcam_alloc_counter_req { 1500 struct mbox_msghdr hdr; 1501 u8 contig; /* Contiguous counters ? */ 1502 #define NPC_MAX_NONCONTIG_COUNTERS 64 1503 u16 count; /* Number of counters requested */ 1504 }; 1505 1506 struct npc_mcam_alloc_counter_rsp { 1507 struct mbox_msghdr hdr; 1508 u16 cntr; /* Counter allocated or start index if contiguous. 1509 * Invalid incase of non-contiguous. 1510 */ 1511 u16 count; /* Number of counters allocated */ 1512 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1513 }; 1514 1515 struct npc_mcam_oper_counter_req { 1516 struct mbox_msghdr hdr; 1517 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1518 }; 1519 1520 struct npc_mcam_oper_counter_rsp { 1521 struct mbox_msghdr hdr; 1522 u64 stat; /* valid only while fetching counter's stats */ 1523 }; 1524 1525 struct npc_mcam_unmap_counter_req { 1526 struct mbox_msghdr hdr; 1527 u16 cntr; 1528 u16 entry; /* Entry and counter to be unmapped */ 1529 u8 all; /* Unmap all entries using this counter ? */ 1530 }; 1531 1532 struct npc_mcam_alloc_and_write_entry_req { 1533 struct mbox_msghdr hdr; 1534 struct mcam_entry entry_data; 1535 u16 ref_entry; 1536 u8 priority; /* Lower or higher w.r.t ref_entry */ 1537 u8 intf; /* Rx or Tx interface */ 1538 u8 enable_entry;/* Enable this MCAM entry ? */ 1539 u8 alloc_cntr; /* Allocate counter and map ? */ 1540 }; 1541 1542 struct npc_mcam_alloc_and_write_entry_rsp { 1543 struct mbox_msghdr hdr; 1544 u16 entry; 1545 u16 cntr; 1546 }; 1547 1548 struct npc_get_kex_cfg_rsp { 1549 struct mbox_msghdr hdr; 1550 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1551 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1552 #define NPC_MAX_INTF 2 1553 #define NPC_MAX_LID 8 1554 #define NPC_MAX_LT 16 1555 #define NPC_MAX_LD 2 1556 #define NPC_MAX_LFL 16 1557 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1558 u64 kex_ld_flags[NPC_MAX_LD]; 1559 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1560 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1561 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1562 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1563 #define MKEX_NAME_LEN 128 1564 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1565 }; 1566 1567 struct ptp_get_cap_rsp { 1568 struct mbox_msghdr hdr; 1569 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1570 u64 cap; 1571 }; 1572 1573 struct get_rep_cnt_rsp { 1574 struct mbox_msghdr hdr; 1575 u16 rep_cnt; 1576 u16 rep_pf_map[64]; 1577 u64 rsvd; 1578 }; 1579 1580 struct esw_cfg_req { 1581 struct mbox_msghdr hdr; 1582 u8 ena; 1583 u64 rsvd; 1584 }; 1585 1586 struct rep_evt_data { 1587 u8 port_state; 1588 u8 vf_state; 1589 u16 rx_mode; 1590 u16 rx_flags; 1591 u16 mtu; 1592 u8 mac[ETH_ALEN]; 1593 u64 rsvd[5]; 1594 }; 1595 1596 struct rep_event { 1597 struct mbox_msghdr hdr; 1598 u16 pcifunc; 1599 #define RVU_EVENT_PORT_STATE BIT_ULL(0) 1600 #define RVU_EVENT_PFVF_STATE BIT_ULL(1) 1601 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2) 1602 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3) 1603 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4) 1604 u16 event; 1605 struct rep_evt_data evt_data; 1606 }; 1607 1608 struct flow_msg { 1609 unsigned char dmac[6]; 1610 unsigned char smac[6]; 1611 __be16 etype; 1612 __be16 vlan_etype; 1613 __be16 vlan_tci; 1614 union { 1615 __be32 ip4src; 1616 __be32 ip6src[4]; 1617 }; 1618 union { 1619 __be32 ip4dst; 1620 __be32 ip6dst[4]; 1621 }; 1622 union { 1623 __be32 spi; 1624 }; 1625 1626 u8 tos; 1627 u8 ip_ver; 1628 u8 ip_proto; 1629 u8 tc; 1630 __be16 sport; 1631 __be16 dport; 1632 union { 1633 u8 ip_flag; 1634 u8 next_header; 1635 }; 1636 __be16 vlan_itci; 1637 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1638 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1639 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1640 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1641 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1642 u32 mpls_lse[4]; 1643 u8 icmp_type; 1644 u8 icmp_code; 1645 __be16 tcp_flags; 1646 u16 sq_id; 1647 }; 1648 1649 struct npc_install_flow_req { 1650 struct mbox_msghdr hdr; 1651 struct flow_msg packet; 1652 struct flow_msg mask; 1653 u64 features; 1654 u16 entry; 1655 u16 channel; 1656 u16 chan_mask; 1657 u8 intf; 1658 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1659 u8 default_rule; 1660 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1661 u16 vf; 1662 /* action */ 1663 u32 index; 1664 u16 match_id; 1665 u8 flow_key_alg; 1666 u8 op; 1667 /* vtag rx action */ 1668 u8 vtag0_type; 1669 u8 vtag0_valid; 1670 u8 vtag1_type; 1671 u8 vtag1_valid; 1672 /* vtag tx action */ 1673 u16 vtag0_def; 1674 u8 vtag0_op; 1675 u16 vtag1_def; 1676 u8 vtag1_op; 1677 /* old counter value */ 1678 u16 cntr_val; 1679 }; 1680 1681 struct npc_install_flow_rsp { 1682 struct mbox_msghdr hdr; 1683 int counter; /* negative if no counter else counter number */ 1684 }; 1685 1686 struct npc_delete_flow_req { 1687 struct mbox_msghdr hdr; 1688 u16 entry; 1689 u16 start;/*Disable range of entries */ 1690 u16 end; 1691 u8 all; /* PF + VFs */ 1692 }; 1693 1694 struct npc_delete_flow_rsp { 1695 struct mbox_msghdr hdr; 1696 u16 cntr_val; 1697 }; 1698 1699 struct npc_mcam_read_entry_req { 1700 struct mbox_msghdr hdr; 1701 u16 entry; /* MCAM entry to read */ 1702 }; 1703 1704 struct npc_mcam_read_entry_rsp { 1705 struct mbox_msghdr hdr; 1706 struct mcam_entry entry_data; 1707 u8 intf; 1708 u8 enable; 1709 }; 1710 1711 struct npc_mcam_read_base_rule_rsp { 1712 struct mbox_msghdr hdr; 1713 struct mcam_entry entry; 1714 }; 1715 1716 struct npc_mcam_get_stats_req { 1717 struct mbox_msghdr hdr; 1718 u16 entry; /* mcam entry */ 1719 }; 1720 1721 struct npc_mcam_get_stats_rsp { 1722 struct mbox_msghdr hdr; 1723 u64 stat; /* counter stats */ 1724 u8 stat_ena; /* enabled */ 1725 }; 1726 1727 struct npc_get_field_hash_info_req { 1728 struct mbox_msghdr hdr; 1729 u8 intf; 1730 }; 1731 1732 struct npc_get_field_hash_info_rsp { 1733 struct mbox_msghdr hdr; 1734 u64 secret_key[3]; 1735 #define NPC_MAX_HASH 2 1736 #define NPC_MAX_HASH_MASK 2 1737 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1738 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1739 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1740 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1741 }; 1742 1743 enum ptp_op { 1744 PTP_OP_ADJFINE = 0, 1745 PTP_OP_GET_CLOCK = 1, 1746 PTP_OP_GET_TSTMP = 2, 1747 PTP_OP_SET_THRESH = 3, 1748 PTP_OP_PPS_ON = 4, 1749 PTP_OP_ADJTIME = 5, 1750 PTP_OP_SET_CLOCK = 6, 1751 }; 1752 1753 struct ptp_req { 1754 struct mbox_msghdr hdr; 1755 u8 op; 1756 s64 scaled_ppm; 1757 u64 thresh; 1758 u64 period; 1759 int pps_on; 1760 s64 delta; 1761 u64 clk; 1762 }; 1763 1764 struct ptp_rsp { 1765 struct mbox_msghdr hdr; 1766 u64 clk; 1767 u64 tsc; 1768 }; 1769 1770 struct npc_get_field_status_req { 1771 struct mbox_msghdr hdr; 1772 u8 intf; 1773 u8 field; 1774 }; 1775 1776 struct npc_get_field_status_rsp { 1777 struct mbox_msghdr hdr; 1778 u8 enable; 1779 }; 1780 1781 struct set_vf_perm { 1782 struct mbox_msghdr hdr; 1783 u16 vf; 1784 #define RESET_VF_PERM BIT_ULL(0) 1785 #define VF_TRUSTED BIT_ULL(1) 1786 u64 flags; 1787 }; 1788 1789 struct lmtst_tbl_setup_req { 1790 struct mbox_msghdr hdr; 1791 u64 dis_sched_early_comp :1; 1792 u64 sch_ena :1; 1793 u64 dis_line_pref :1; 1794 u64 ssow_pf_func :13; 1795 u16 base_pcifunc; 1796 u8 use_local_lmt_region; 1797 u64 lmt_iova; 1798 u64 rsvd[4]; 1799 }; 1800 1801 struct ndc_sync_op { 1802 struct mbox_msghdr hdr; 1803 u8 nix_lf_tx_sync; 1804 u8 nix_lf_rx_sync; 1805 u8 npa_lf_sync; 1806 }; 1807 1808 /* CPT mailbox error codes 1809 * Range 901 - 1000. 1810 */ 1811 enum cpt_af_status { 1812 CPT_AF_ERR_PARAM = -901, 1813 CPT_AF_ERR_GRP_INVALID = -902, 1814 CPT_AF_ERR_LF_INVALID = -903, 1815 CPT_AF_ERR_ACCESS_DENIED = -904, 1816 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1817 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1818 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1819 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1820 }; 1821 1822 /* CPT mbox message formats */ 1823 struct cpt_rd_wr_reg_msg { 1824 struct mbox_msghdr hdr; 1825 u64 reg_offset; 1826 u64 *ret_val; 1827 u64 val; 1828 u8 is_write; 1829 int blkaddr; 1830 }; 1831 1832 struct cpt_lf_alloc_req_msg { 1833 struct mbox_msghdr hdr; 1834 u16 nix_pf_func; 1835 u16 sso_pf_func; 1836 u16 eng_grpmsk; 1837 u8 blkaddr; 1838 u8 ctx_ilen_valid : 1; 1839 u8 ctx_ilen : 7; 1840 }; 1841 1842 #define CPT_INLINE_INBOUND 0 1843 #define CPT_INLINE_OUTBOUND 1 1844 1845 /* Mailbox message request format for CPT IPsec 1846 * inline inbound and outbound configuration. 1847 */ 1848 struct cpt_inline_ipsec_cfg_msg { 1849 struct mbox_msghdr hdr; 1850 u8 enable; 1851 u8 slot; 1852 u8 dir; 1853 u8 sso_pf_func_ovrd; 1854 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1855 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1856 }; 1857 1858 /* Mailbox message request and response format for CPT stats. */ 1859 struct cpt_sts_req { 1860 struct mbox_msghdr hdr; 1861 u8 blkaddr; 1862 }; 1863 1864 struct cpt_sts_rsp { 1865 struct mbox_msghdr hdr; 1866 u64 inst_req_pc; 1867 u64 inst_lat_pc; 1868 u64 rd_req_pc; 1869 u64 rd_lat_pc; 1870 u64 rd_uc_pc; 1871 u64 active_cycles_pc; 1872 u64 ctx_mis_pc; 1873 u64 ctx_hit_pc; 1874 u64 ctx_aop_pc; 1875 u64 ctx_aop_lat_pc; 1876 u64 ctx_ifetch_pc; 1877 u64 ctx_ifetch_lat_pc; 1878 u64 ctx_ffetch_pc; 1879 u64 ctx_ffetch_lat_pc; 1880 u64 ctx_wback_pc; 1881 u64 ctx_wback_lat_pc; 1882 u64 ctx_psh_pc; 1883 u64 ctx_psh_lat_pc; 1884 u64 ctx_err; 1885 u64 ctx_enc_id; 1886 u64 ctx_flush_timer; 1887 u64 rxc_time; 1888 u64 rxc_time_cfg; 1889 u64 rxc_active_sts; 1890 u64 rxc_zombie_sts; 1891 u64 busy_sts_ae; 1892 u64 free_sts_ae; 1893 u64 busy_sts_se; 1894 u64 free_sts_se; 1895 u64 busy_sts_ie; 1896 u64 free_sts_ie; 1897 u64 exe_err_info; 1898 u64 cptclk_cnt; 1899 u64 diag; 1900 u64 rxc_dfrg; 1901 u64 x2p_link_cfg0; 1902 u64 x2p_link_cfg1; 1903 }; 1904 1905 /* Mailbox message request format to configure reassembly timeout. */ 1906 struct cpt_rxc_time_cfg_req { 1907 struct mbox_msghdr hdr; 1908 int blkaddr; 1909 u32 step; 1910 u16 zombie_thres; 1911 u16 zombie_limit; 1912 u16 active_thres; 1913 u16 active_limit; 1914 }; 1915 1916 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1917 struct cpt_inst_lmtst_req { 1918 struct mbox_msghdr hdr; 1919 u64 inst[8]; 1920 u64 rsvd; 1921 }; 1922 1923 /* Mailbox message format to request for CPT LF reset */ 1924 struct cpt_lf_rst_req { 1925 struct mbox_msghdr hdr; 1926 u32 slot; 1927 u32 rsvd; 1928 }; 1929 1930 /* Mailbox message format to request for CPT faulted engines */ 1931 struct cpt_flt_eng_info_req { 1932 struct mbox_msghdr hdr; 1933 int blkaddr; 1934 bool reset; 1935 u32 rsvd; 1936 }; 1937 1938 struct cpt_flt_eng_info_rsp { 1939 struct mbox_msghdr hdr; 1940 #define CPT_AF_MAX_FLT_INT_VECS 3 1941 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1942 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1943 u64 rsvd; 1944 }; 1945 1946 struct sdp_node_info { 1947 /* Node to which this PF belons to */ 1948 u8 node_id; 1949 u8 max_vfs; 1950 u8 num_pf_rings; 1951 u8 pf_srn; 1952 #define SDP_MAX_VFS 128 1953 u8 vf_rings[SDP_MAX_VFS]; 1954 }; 1955 1956 struct sdp_chan_info_msg { 1957 struct mbox_msghdr hdr; 1958 struct sdp_node_info info; 1959 }; 1960 1961 struct sdp_get_chan_info_msg { 1962 struct mbox_msghdr hdr; 1963 u16 chan_base; 1964 u16 num_chan; 1965 }; 1966 1967 /* CGX mailbox error codes 1968 * Range 1101 - 1200. 1969 */ 1970 enum cgx_af_status { 1971 LMAC_AF_ERR_INVALID_PARAM = -1101, 1972 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1973 LMAC_AF_ERR_PERM_DENIED = -1103, 1974 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1975 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1976 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1977 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1978 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1979 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1980 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1981 }; 1982 1983 enum mcs_direction { 1984 MCS_RX, 1985 MCS_TX, 1986 }; 1987 1988 enum mcs_rsrc_type { 1989 MCS_RSRC_TYPE_FLOWID, 1990 MCS_RSRC_TYPE_SECY, 1991 MCS_RSRC_TYPE_SC, 1992 MCS_RSRC_TYPE_SA, 1993 }; 1994 1995 struct mcs_alloc_rsrc_req { 1996 struct mbox_msghdr hdr; 1997 u8 rsrc_type; 1998 u8 rsrc_cnt; /* Resources count */ 1999 u8 mcs_id; /* MCS block ID */ 2000 u8 dir; /* Macsec ingress or egress side */ 2001 u8 all; /* Allocate all resource type one each */ 2002 u64 rsvd; 2003 }; 2004 2005 struct mcs_alloc_rsrc_rsp { 2006 struct mbox_msghdr hdr; 2007 u8 flow_ids[128]; /* Index of reserved entries */ 2008 u8 secy_ids[128]; 2009 u8 sc_ids[128]; 2010 u8 sa_ids[256]; 2011 u8 rsrc_type; 2012 u8 rsrc_cnt; /* No of entries reserved */ 2013 u8 mcs_id; 2014 u8 dir; 2015 u8 all; 2016 u8 rsvd[256]; /* reserved fields for future expansion */ 2017 }; 2018 2019 struct mcs_free_rsrc_req { 2020 struct mbox_msghdr hdr; 2021 u8 rsrc_id; /* Index of the entry to be freed */ 2022 u8 rsrc_type; 2023 u8 mcs_id; 2024 u8 dir; 2025 u8 all; /* Free all the cam resources */ 2026 u64 rsvd; 2027 }; 2028 2029 struct mcs_flowid_entry_write_req { 2030 struct mbox_msghdr hdr; 2031 u64 data[4]; 2032 u64 mask[4]; 2033 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 2034 u8 flow_id; 2035 u8 secy_id; /* secyid for which flowid is mapped */ 2036 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 2037 u8 ena; /* Enable tcam entry */ 2038 u8 ctrl_pkt; 2039 u8 mcs_id; 2040 u8 dir; 2041 u64 rsvd; 2042 }; 2043 2044 struct mcs_secy_plcy_write_req { 2045 struct mbox_msghdr hdr; 2046 u64 plcy; 2047 u8 secy_id; 2048 u8 mcs_id; 2049 u8 dir; 2050 u64 rsvd; 2051 }; 2052 2053 /* RX SC_CAM mapping */ 2054 struct mcs_rx_sc_cam_write_req { 2055 struct mbox_msghdr hdr; 2056 u64 sci; /* SCI */ 2057 u64 secy_id; /* secy index mapped to SC */ 2058 u8 sc_id; /* SC CAM entry index */ 2059 u8 mcs_id; 2060 u64 rsvd; 2061 }; 2062 2063 struct mcs_sa_plcy_write_req { 2064 struct mbox_msghdr hdr; 2065 u64 plcy[2][9]; /* Support 2 SA policy */ 2066 u8 sa_index[2]; 2067 u8 sa_cnt; 2068 u8 mcs_id; 2069 u8 dir; 2070 u64 rsvd; 2071 }; 2072 2073 struct mcs_tx_sc_sa_map { 2074 struct mbox_msghdr hdr; 2075 u8 sa_index0; 2076 u8 sa_index1; 2077 u8 rekey_ena; 2078 u8 sa_index0_vld; 2079 u8 sa_index1_vld; 2080 u8 tx_sa_active; 2081 u64 sectag_sci; 2082 u8 sc_id; /* used as index for SA_MEM_MAP */ 2083 u8 mcs_id; 2084 u64 rsvd; 2085 }; 2086 2087 struct mcs_rx_sc_sa_map { 2088 struct mbox_msghdr hdr; 2089 u8 sa_index; 2090 u8 sa_in_use; 2091 u8 sc_id; 2092 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 2093 u8 mcs_id; 2094 u64 rsvd; 2095 }; 2096 2097 struct mcs_flowid_ena_dis_entry { 2098 struct mbox_msghdr hdr; 2099 u8 flow_id; 2100 u8 ena; 2101 u8 mcs_id; 2102 u8 dir; 2103 u64 rsvd; 2104 }; 2105 2106 struct mcs_pn_table_write_req { 2107 struct mbox_msghdr hdr; 2108 u64 next_pn; 2109 u8 pn_id; 2110 u8 mcs_id; 2111 u8 dir; 2112 u64 rsvd; 2113 }; 2114 2115 struct mcs_hw_info { 2116 struct mbox_msghdr hdr; 2117 u8 num_mcs_blks; /* Number of MCS blocks */ 2118 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2119 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2120 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2121 u16 sa_entries; /* PN table entries = SA entries */ 2122 u64 rsvd[16]; 2123 }; 2124 2125 struct mcs_set_active_lmac { 2126 struct mbox_msghdr hdr; 2127 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2128 u8 mcs_id; 2129 u16 chan_base; /* MCS channel base */ 2130 u64 rsvd; 2131 }; 2132 2133 struct mcs_set_lmac_mode { 2134 struct mbox_msghdr hdr; 2135 u8 mode; /* 1:Bypass 0:Operational */ 2136 u8 lmac_id; 2137 u8 mcs_id; 2138 u64 rsvd; 2139 }; 2140 2141 struct mcs_port_reset_req { 2142 struct mbox_msghdr hdr; 2143 u8 reset; 2144 u8 mcs_id; 2145 u8 port_id; 2146 u64 rsvd; 2147 }; 2148 2149 struct mcs_port_cfg_set_req { 2150 struct mbox_msghdr hdr; 2151 u8 cstm_tag_rel_mode_sel; 2152 u8 custom_hdr_enb; 2153 u8 fifo_skid; 2154 u8 port_mode; 2155 u8 port_id; 2156 u8 mcs_id; 2157 u64 rsvd; 2158 }; 2159 2160 struct mcs_port_cfg_get_req { 2161 struct mbox_msghdr hdr; 2162 u8 port_id; 2163 u8 mcs_id; 2164 u64 rsvd; 2165 }; 2166 2167 struct mcs_port_cfg_get_rsp { 2168 struct mbox_msghdr hdr; 2169 u8 cstm_tag_rel_mode_sel; 2170 u8 custom_hdr_enb; 2171 u8 fifo_skid; 2172 u8 port_mode; 2173 u8 port_id; 2174 u8 mcs_id; 2175 u64 rsvd; 2176 }; 2177 2178 struct mcs_custom_tag_cfg_get_req { 2179 struct mbox_msghdr hdr; 2180 u8 mcs_id; 2181 u8 dir; 2182 u64 rsvd; 2183 }; 2184 2185 struct mcs_custom_tag_cfg_get_rsp { 2186 struct mbox_msghdr hdr; 2187 u16 cstm_etype[8]; 2188 u8 cstm_indx[8]; 2189 u8 cstm_etype_en; 2190 u8 mcs_id; 2191 u8 dir; 2192 u64 rsvd; 2193 }; 2194 2195 /* MCS mailbox error codes 2196 * Range 1201 - 1300. 2197 */ 2198 enum mcs_af_status { 2199 MCS_AF_ERR_INVALID_MCSID = -1201, 2200 MCS_AF_ERR_NOT_MAPPED = -1202, 2201 }; 2202 2203 struct mcs_set_pn_threshold { 2204 struct mbox_msghdr hdr; 2205 u64 threshold; 2206 u8 xpn; /* '1' for setting xpn threshold */ 2207 u8 mcs_id; 2208 u8 dir; 2209 u64 rsvd; 2210 }; 2211 2212 enum mcs_ctrl_pkt_rulew_type { 2213 MCS_CTRL_PKT_RULE_TYPE_ETH, 2214 MCS_CTRL_PKT_RULE_TYPE_DA, 2215 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2216 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2217 MCS_CTRL_PKT_RULE_TYPE_MAC, 2218 }; 2219 2220 struct mcs_alloc_ctrl_pkt_rule_req { 2221 struct mbox_msghdr hdr; 2222 u8 rule_type; 2223 u8 mcs_id; /* MCS block ID */ 2224 u8 dir; /* Macsec ingress or egress side */ 2225 u64 rsvd; 2226 }; 2227 2228 struct mcs_alloc_ctrl_pkt_rule_rsp { 2229 struct mbox_msghdr hdr; 2230 u8 rule_idx; 2231 u8 rule_type; 2232 u8 mcs_id; 2233 u8 dir; 2234 u64 rsvd; 2235 }; 2236 2237 struct mcs_free_ctrl_pkt_rule_req { 2238 struct mbox_msghdr hdr; 2239 u8 rule_idx; 2240 u8 rule_type; 2241 u8 mcs_id; 2242 u8 dir; 2243 u8 all; 2244 u64 rsvd; 2245 }; 2246 2247 struct mcs_ctrl_pkt_rule_write_req { 2248 struct mbox_msghdr hdr; 2249 u64 data0; 2250 u64 data1; 2251 u64 data2; 2252 u8 rule_idx; 2253 u8 rule_type; 2254 u8 mcs_id; 2255 u8 dir; 2256 u64 rsvd; 2257 }; 2258 2259 struct mcs_stats_req { 2260 struct mbox_msghdr hdr; 2261 u8 id; 2262 u8 mcs_id; 2263 u8 dir; 2264 u64 rsvd; 2265 }; 2266 2267 struct mcs_flowid_stats { 2268 struct mbox_msghdr hdr; 2269 u64 tcam_hit_cnt; 2270 u64 rsvd; 2271 }; 2272 2273 struct mcs_secy_stats { 2274 struct mbox_msghdr hdr; 2275 u64 ctl_pkt_bcast_cnt; 2276 u64 ctl_pkt_mcast_cnt; 2277 u64 ctl_pkt_ucast_cnt; 2278 u64 ctl_octet_cnt; 2279 u64 unctl_pkt_bcast_cnt; 2280 u64 unctl_pkt_mcast_cnt; 2281 u64 unctl_pkt_ucast_cnt; 2282 u64 unctl_octet_cnt; 2283 /* Valid only for RX */ 2284 u64 octet_decrypted_cnt; 2285 u64 octet_validated_cnt; 2286 u64 pkt_port_disabled_cnt; 2287 u64 pkt_badtag_cnt; 2288 u64 pkt_nosa_cnt; 2289 u64 pkt_nosaerror_cnt; 2290 u64 pkt_tagged_ctl_cnt; 2291 u64 pkt_untaged_cnt; 2292 u64 pkt_ctl_cnt; /* CN10K-B */ 2293 u64 pkt_notag_cnt; /* CNF10K-B */ 2294 /* Valid only for TX */ 2295 u64 octet_encrypted_cnt; 2296 u64 octet_protected_cnt; 2297 u64 pkt_noactivesa_cnt; 2298 u64 pkt_toolong_cnt; 2299 u64 pkt_untagged_cnt; 2300 u64 rsvd[4]; 2301 }; 2302 2303 struct mcs_port_stats { 2304 struct mbox_msghdr hdr; 2305 u64 tcam_miss_cnt; 2306 u64 parser_err_cnt; 2307 u64 preempt_err_cnt; /* CNF10K-B */ 2308 u64 sectag_insert_err_cnt; 2309 u64 rsvd[4]; 2310 }; 2311 2312 /* Only for CN10K-B */ 2313 struct mcs_sa_stats { 2314 struct mbox_msghdr hdr; 2315 /* RX */ 2316 u64 pkt_invalid_cnt; 2317 u64 pkt_nosaerror_cnt; 2318 u64 pkt_notvalid_cnt; 2319 u64 pkt_ok_cnt; 2320 u64 pkt_nosa_cnt; 2321 /* TX */ 2322 u64 pkt_encrypt_cnt; 2323 u64 pkt_protected_cnt; 2324 u64 rsvd[4]; 2325 }; 2326 2327 struct mcs_sc_stats { 2328 struct mbox_msghdr hdr; 2329 /* RX */ 2330 u64 hit_cnt; 2331 u64 pkt_invalid_cnt; 2332 u64 pkt_late_cnt; 2333 u64 pkt_notvalid_cnt; 2334 u64 pkt_unchecked_cnt; 2335 u64 pkt_delay_cnt; /* CNF10K-B */ 2336 u64 pkt_ok_cnt; /* CNF10K-B */ 2337 u64 octet_decrypt_cnt; /* CN10K-B */ 2338 u64 octet_validate_cnt; /* CN10K-B */ 2339 /* TX */ 2340 u64 pkt_encrypt_cnt; 2341 u64 pkt_protected_cnt; 2342 u64 octet_encrypt_cnt; /* CN10K-B */ 2343 u64 octet_protected_cnt; /* CN10K-B */ 2344 u64 rsvd[4]; 2345 }; 2346 2347 struct mcs_clear_stats { 2348 struct mbox_msghdr hdr; 2349 #define MCS_FLOWID_STATS 0 2350 #define MCS_SECY_STATS 1 2351 #define MCS_SC_STATS 2 2352 #define MCS_SA_STATS 3 2353 #define MCS_PORT_STATS 4 2354 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2355 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2356 u8 mcs_id; 2357 u8 dir; 2358 u8 all; /* All resources stats mapped to PF are cleared */ 2359 }; 2360 2361 struct mcs_intr_cfg { 2362 struct mbox_msghdr hdr; 2363 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2364 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2365 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2366 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2367 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2368 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2369 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2370 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2371 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2372 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2373 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2374 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2375 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2376 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2377 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2378 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2379 u64 intr_mask; /* Interrupt enable mask */ 2380 u8 mcs_id; 2381 u8 lmac_id; 2382 u64 rsvd; 2383 }; 2384 2385 struct mcs_intr_info { 2386 struct mbox_msghdr hdr; 2387 u64 intr_mask; 2388 int sa_id; 2389 u8 mcs_id; 2390 u8 lmac_id; 2391 u64 rsvd; 2392 }; 2393 2394 #endif /* MBOX_H */ 2395