xref: /linux/drivers/net/ethernet/marvell/octeontx2/af/mbox.h (revision f9bff0e31881d03badf191d3b0005839391f5f2b)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef MBOX_H
9 #define MBOX_H
10 
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13 
14 #include "rvu_struct.h"
15 #include "common.h"
16 
17 #define MBOX_SIZE		SZ_64K
18 
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START	0
21 #define MBOX_DOWN_RX_SIZE	(46 * SZ_1K)
22 #define MBOX_DOWN_TX_START	(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE	(16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START	(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE		SZ_1K
27 #define MBOX_UP_TX_START	(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE		SZ_1K
29 
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33 
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35 
36 #define MBOX_RSP_TIMEOUT	6000 /* Time(ms) to wait for mbox response */
37 
38 #define MBOX_MSG_ALIGN		16  /* Align mbox msg start to 16bytes */
39 
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF		0  /* AF replies to PF */
42 #define MBOX_DIR_PFAF		1  /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF		2  /* PF replies to VF */
44 #define MBOX_DIR_VFPF		3  /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP	4  /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP	5  /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP	6  /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP	7  /* VF replies to PF */
49 
50 struct otx2_mbox_dev {
51 	void	    *mbase;   /* This dev's mbox region */
52 	void	    *hwbase;
53 	spinlock_t  mbox_lock;
54 	u16         msg_size; /* Total msg size to be sent */
55 	u16         rsp_size; /* Total rsp size to be sure the reply is ok */
56 	u16         num_msgs; /* No of msgs sent or waiting for response */
57 	u16         msgs_acked; /* No of msgs for which response is received */
58 };
59 
60 struct otx2_mbox {
61 	struct pci_dev *pdev;
62 	void   *hwbase;  /* Mbox region advertised by HW */
63 	void   *reg_base;/* CSR base for this dev */
64 	u64    trigger;  /* Trigger mbox notification */
65 	u16    tr_shift; /* Mbox trigger shift */
66 	u64    rx_start; /* Offset of Rx region in mbox memory */
67 	u64    tx_start; /* Offset of Tx region in mbox memory */
68 	u16    rx_size;  /* Size of Rx region */
69 	u16    tx_size;  /* Size of Tx region */
70 	u16    ndevs;    /* The number of peers */
71 	struct otx2_mbox_dev *dev;
72 };
73 
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 	u64 msg_size;	/* Total msgs size embedded */
77 	u16  num_msgs;   /* No of msgs embedded */
78 };
79 
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 	u16 pcifunc;     /* Who's sending this msg */
83 	u16 id;          /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 	u16 sig;         /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 	u16 ver;         /* Version of msg's structure for this ID */
89 	u16 next_msgoff; /* Offset of next msg within mailbox region */
90 	int rc;          /* Msg process'ed response code */
91 };
92 
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 		   struct pci_dev *pdev, void __force *reg_base,
98 		   int direction, int ndevs);
99 
100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
101 			   struct pci_dev *pdev, void __force *reg_base,
102 			   int direction, int ndevs, unsigned long *bmap);
103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
107 					    int size, int size_rsp);
108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
109 				      struct mbox_msghdr *msg);
110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
112 			   u16 pcifunc, u16 id);
113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
114 const char *otx2_mbox_id2name(u16 id);
115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
116 						      int devid, int size)
117 {
118 	return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
119 }
120 
121 /* Mailbox message types */
122 #define MBOX_MSG_MASK				0xFFFF
123 #define MBOX_MSG_INVALID			0xFFFE
124 #define MBOX_MSG_MAX				0xFFFF
125 
126 #define MBOX_MESSAGES							\
127 /* Generic mbox IDs (range 0x000 - 0x1FF) */				\
128 M(READY,		0x001, ready, msg_req, ready_msg_rsp)		\
129 M(ATTACH_RESOURCES,	0x002, attach_resources, rsrc_attach, msg_rsp)	\
130 M(DETACH_RESOURCES,	0x003, detach_resources, rsrc_detach, msg_rsp)	\
131 M(FREE_RSRC_CNT,	0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)	\
132 M(MSIX_OFFSET,		0x005, msix_offset, msg_req, msix_offset_rsp)	\
133 M(VF_FLR,		0x006, vf_flr, msg_req, msg_rsp)		\
134 M(PTP_OP,		0x007, ptp_op, ptp_req, ptp_rsp)		\
135 M(GET_HW_CAP,		0x008, get_hw_cap, msg_req, get_hw_cap_rsp)	\
136 M(LMTST_TBL_SETUP,	0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req,    \
137 				msg_rsp)				\
138 M(SET_VF_PERM,		0x00b, set_vf_perm, set_vf_perm, msg_rsp)	\
139 /* CGX mbox IDs (range 0x200 - 0x3FF) */				\
140 M(CGX_START_RXTX,	0x200, cgx_start_rxtx, msg_req, msg_rsp)	\
141 M(CGX_STOP_RXTX,	0x201, cgx_stop_rxtx, msg_req, msg_rsp)		\
142 M(CGX_STATS,		0x202, cgx_stats, msg_req, cgx_stats_rsp)	\
143 M(CGX_MAC_ADDR_SET,	0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,    \
144 				cgx_mac_addr_set_or_get)		\
145 M(CGX_MAC_ADDR_GET,	0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,    \
146 				cgx_mac_addr_set_or_get)		\
147 M(CGX_PROMISC_ENABLE,	0x205, cgx_promisc_enable, msg_req, msg_rsp)	\
148 M(CGX_PROMISC_DISABLE,	0x206, cgx_promisc_disable, msg_req, msg_rsp)	\
149 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)	\
150 M(CGX_STOP_LINKEVENTS,	0x208, cgx_stop_linkevents, msg_req, msg_rsp)	\
151 M(CGX_GET_LINKINFO,	0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
152 M(CGX_INTLBK_ENABLE,	0x20A, cgx_intlbk_enable, msg_req, msg_rsp)	\
153 M(CGX_INTLBK_DISABLE,	0x20B, cgx_intlbk_disable, msg_req, msg_rsp)	\
154 M(CGX_PTP_RX_ENABLE,	0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)	\
155 M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\
156 M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\
157 			       cgx_pause_frm_cfg)			\
158 M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
159 M(CGX_FEC_SET,		0x210, cgx_set_fec_param, fec_mode, fec_mode) \
160 M(CGX_MAC_ADDR_ADD,	0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \
161 				cgx_mac_addr_add_rsp)		\
162 M(CGX_MAC_ADDR_DEL,	0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \
163 			       msg_rsp)		\
164 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \
165 				  cgx_max_dmac_entries_get_rsp)		\
166 M(CGX_FEC_STATS,	0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
167 M(CGX_SET_LINK_MODE,	0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
168 			       cgx_set_link_mode_rsp)	\
169 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
170 M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\
171 			       cgx_features_info_msg)			\
172 M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\
173 M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
174 							msg_rsp) \
175 M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
176 						    cgx_mac_addr_update_rsp) \
177 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \
178 				 cgx_pfc_rsp)                               \
179 /* NPA mbox IDs (range 0x400 - 0x5FF) */				\
180 M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\
181 				npa_lf_alloc_req, npa_lf_alloc_rsp)	\
182 M(NPA_LF_FREE,		0x401, npa_lf_free, msg_req, msg_rsp)		\
183 M(NPA_AQ_ENQ,		0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)   \
184 M(NPA_HWCTX_DISABLE,	0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
185 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\
186 /* TIM mbox IDs (range 0x800 - 0x9FF) */				\
187 /* CPT mbox IDs (range 0xA00 - 0xBFF) */				\
188 M(CPT_LF_ALLOC,		0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,	\
189 			       msg_rsp)					\
190 M(CPT_LF_FREE,		0xA01, cpt_lf_free, msg_req, msg_rsp)		\
191 M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,	\
192 			       cpt_rd_wr_reg_msg)			\
193 M(CPT_INLINE_IPSEC_CFG,	0xA04, cpt_inline_ipsec_cfg,			\
194 			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\
195 M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\
196 M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \
197 			       msg_rsp)                                 \
198 M(CPT_CTX_CACHE_SYNC,   0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp)    \
199 M(CPT_LF_RESET,         0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp)	\
200 M(CPT_FLT_ENG_INFO,     0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req,	\
201 			       cpt_flt_eng_info_rsp)			\
202 /* SDP mbox IDs (range 0x1000 - 0x11FF) */				\
203 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
204 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
205 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
206 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
207 				npc_mcam_alloc_entry_rsp)		\
208 M(NPC_MCAM_FREE_ENTRY,	0x6001, npc_mcam_free_entry,			\
209 				 npc_mcam_free_entry_req, msg_rsp)	\
210 M(NPC_MCAM_WRITE_ENTRY,	0x6002, npc_mcam_write_entry,			\
211 				 npc_mcam_write_entry_req, msg_rsp)	\
212 M(NPC_MCAM_ENA_ENTRY,   0x6003, npc_mcam_ena_entry,			\
213 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
214 M(NPC_MCAM_DIS_ENTRY,   0x6004, npc_mcam_dis_entry,			\
215 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
216 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
217 				npc_mcam_shift_entry_rsp)		\
218 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter,		\
219 					npc_mcam_alloc_counter_req,	\
220 					npc_mcam_alloc_counter_rsp)	\
221 M(NPC_MCAM_FREE_COUNTER,  0x6007, npc_mcam_free_counter,		\
222 				    npc_mcam_oper_counter_req, msg_rsp)	\
223 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter,		\
224 				   npc_mcam_unmap_counter_req, msg_rsp)	\
225 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter,		\
226 				   npc_mcam_oper_counter_req, msg_rsp)	\
227 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats,		\
228 				   npc_mcam_oper_counter_req,		\
229 				   npc_mcam_oper_counter_rsp)		\
230 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,      \
231 					  npc_mcam_alloc_and_write_entry_req,  \
232 					  npc_mcam_alloc_and_write_entry_rsp)  \
233 M(NPC_GET_KEX_CFG,	  0x600c, npc_get_kex_cfg,			\
234 				   msg_req, npc_get_kex_cfg_rsp)	\
235 M(NPC_INSTALL_FLOW,	  0x600d, npc_install_flow,			       \
236 				  npc_install_flow_req, npc_install_flow_rsp)  \
237 M(NPC_DELETE_FLOW,	  0x600e, npc_delete_flow,			\
238 				  npc_delete_flow_req, msg_rsp)		\
239 M(NPC_MCAM_READ_ENTRY,	  0x600f, npc_mcam_read_entry,			\
240 				  npc_mcam_read_entry_req,		\
241 				  npc_mcam_read_entry_rsp)		\
242 M(NPC_SET_PKIND,        0x6010,   npc_set_pkind,                        \
243 				  npc_set_pkind, msg_rsp)               \
244 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule,            \
245 				   msg_req, npc_mcam_read_base_rule_rsp)  \
246 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \
247 				   npc_mcam_get_stats_req,              \
248 				   npc_mcam_get_stats_rsp)              \
249 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info,                     \
250 				   npc_get_field_hash_info_req,              \
251 				   npc_get_field_hash_info_rsp)              \
252 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status,                     \
253 				   npc_get_field_status_req,              \
254 				   npc_get_field_status_rsp)              \
255 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
256 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc,				\
257 				 nix_lf_alloc_req, nix_lf_alloc_rsp)	\
258 M(NIX_LF_FREE,		0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)	\
259 M(NIX_AQ_ENQ,		0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp)  \
260 M(NIX_HWCTX_DISABLE,	0x8003, nix_hwctx_disable,			\
261 				 hwctx_disable_req, msg_rsp)		\
262 M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc,			\
263 				 nix_txsch_alloc_req, nix_txsch_alloc_rsp)   \
264 M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
265 M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config,	\
266 				nix_txschq_config)			\
267 M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\
268 M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config,		\
269 				 nix_vtag_config_rsp)			\
270 M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg,			\
271 				 nix_rss_flowkey_cfg,			\
272 				 nix_rss_flowkey_cfg_rsp)		\
273 M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
274 M(NIX_SET_RX_MODE,	0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)	\
275 M(NIX_SET_HW_FRS,	0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp)	\
276 M(NIX_LF_START_RX,	0x800d, nix_lf_start_rx, msg_req, msg_rsp)	\
277 M(NIX_LF_STOP_RX,	0x800e, nix_lf_stop_rx, msg_req, msg_rsp)	\
278 M(NIX_MARK_FORMAT_CFG,	0x800f, nix_mark_format_cfg,			\
279 				 nix_mark_format_cfg,			\
280 				 nix_mark_format_cfg_rsp)		\
281 M(NIX_SET_RX_CFG,	0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)	\
282 M(NIX_LSO_FORMAT_CFG,	0x8011, nix_lso_format_cfg,			\
283 				 nix_lso_format_cfg,			\
284 				 nix_lso_format_cfg_rsp)		\
285 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp)	\
286 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
287 M(NIX_BP_ENABLE,	0x8016, nix_bp_enable, nix_bp_cfg_req,	\
288 				nix_bp_cfg_rsp)	\
289 M(NIX_BP_DISABLE,	0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
290 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
291 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg,			\
292 				nix_inline_ipsec_cfg, msg_rsp)		\
293 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg,		\
294 				nix_inline_ipsec_lf_cfg, msg_rsp)	\
295 M(NIX_CN10K_AQ_ENQ,	0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
296 				nix_cn10k_aq_enq_rsp)			\
297 M(NIX_GET_HW_INFO,	0x801c, nix_get_hw_info, msg_req, nix_hw_info)	\
298 M(NIX_BANDPROF_ALLOC,	0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
299 				nix_bandprof_alloc_rsp)			    \
300 M(NIX_BANDPROF_FREE,	0x801e, nix_bandprof_free, nix_bandprof_free_req,   \
301 				msg_rsp)				    \
302 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,		\
303 				nix_bandprof_get_hwinfo_rsp)		    \
304 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg,		\
305 				msg_req, nix_inline_ipsec_cfg)		\
306 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */					\
307 M(MCS_ALLOC_RESOURCES,	0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,	\
308 				mcs_alloc_rsrc_rsp)				\
309 M(MCS_FREE_RESOURCES,	0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
310 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req,	\
311 				msg_rsp)					\
312 M(MCS_SECY_PLCY_WRITE,	0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req,	\
313 				msg_rsp)					\
314 M(MCS_RX_SC_CAM_WRITE,	0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req,	\
315 				msg_rsp)					\
316 M(MCS_SA_PLCY_WRITE,	0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req,	\
317 				msg_rsp)					\
318 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map,	\
319 				  msg_rsp)					\
320 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map,	\
321 				  msg_rsp)					\
322 M(MCS_FLOWID_ENA_ENTRY,	0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry,	\
323 				msg_rsp)					\
324 M(MCS_PN_TABLE_WRITE,	0xa009, mcs_pn_table_write, mcs_pn_table_write_req,	\
325 				msg_rsp)					\
326 M(MCS_SET_ACTIVE_LMAC,	0xa00a,	mcs_set_active_lmac, mcs_set_active_lmac,	\
327 				msg_rsp)					\
328 M(MCS_GET_HW_INFO,	0xa00b,	mcs_get_hw_info, msg_req, mcs_hw_info)		\
329 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req,		\
330 				mcs_flowid_stats)				\
331 M(MCS_GET_SECY_STATS,	0xa00d, mcs_get_secy_stats, mcs_stats_req,		\
332 				mcs_secy_stats)					\
333 M(MCS_GET_SC_STATS,	0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats)	\
334 M(MCS_GET_SA_STATS,	0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats)	\
335 M(MCS_GET_PORT_STATS,	0xa010, mcs_get_port_stats, mcs_stats_req,		\
336 				mcs_port_stats)					\
337 M(MCS_CLEAR_STATS,	0xa011,	mcs_clear_stats, mcs_clear_stats, msg_rsp)	\
338 M(MCS_INTR_CFG,		0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp)		\
339 M(MCS_SET_LMAC_MODE,	0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp)	\
340 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold,	\
341 				msg_rsp)					\
342 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule,			\
343 				   mcs_alloc_ctrl_pkt_rule_req,			\
344 				   mcs_alloc_ctrl_pkt_rule_rsp)			\
345 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule,			\
346 				  mcs_free_ctrl_pkt_rule_req, msg_rsp)		\
347 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write,			\
348 				   mcs_ctrl_pkt_rule_write_req, msg_rsp)	\
349 M(MCS_PORT_RESET,	0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp)	\
350 M(MCS_PORT_CFG_SET,	0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
351 M(MCS_PORT_CFG_GET,	0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req,		\
352 				mcs_port_cfg_get_rsp)				\
353 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get,			\
354 				  mcs_custom_tag_cfg_get_req,			\
355 				  mcs_custom_tag_cfg_get_rsp)
356 
357 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
358 #define MBOX_UP_CGX_MESSAGES						\
359 M(CGX_LINK_EVENT,	0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
360 
361 #define MBOX_UP_CPT_MESSAGES						\
362 M(CPT_INST_LMTST,	0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
363 
364 #define MBOX_UP_MCS_MESSAGES						\
365 M(MCS_INTR_NOTIFY,	0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
366 
367 enum {
368 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
369 MBOX_MESSAGES
370 MBOX_UP_CGX_MESSAGES
371 MBOX_UP_CPT_MESSAGES
372 MBOX_UP_MCS_MESSAGES
373 #undef M
374 };
375 
376 /* Mailbox message formats */
377 
378 #define RVU_DEFAULT_PF_FUNC     0xFFFF
379 
380 /* Generic request msg used for those mbox messages which
381  * don't send any data in the request.
382  */
383 struct msg_req {
384 	struct mbox_msghdr hdr;
385 };
386 
387 /* Generic response msg used an ack or response for those mbox
388  * messages which don't have a specific rsp msg format.
389  */
390 struct msg_rsp {
391 	struct mbox_msghdr hdr;
392 };
393 
394 /* RVU mailbox error codes
395  * Range 256 - 300.
396  */
397 enum rvu_af_status {
398 	RVU_INVALID_VF_ID           = -256,
399 };
400 
401 struct ready_msg_rsp {
402 	struct mbox_msghdr hdr;
403 	u16    sclk_freq;	/* SCLK frequency (in MHz) */
404 	u16    rclk_freq;	/* RCLK frequency (in MHz) */
405 };
406 
407 /* Structure for requesting resource provisioning.
408  * 'modify' flag to be used when either requesting more
409  * or to detach partial of a certain resource type.
410  * Rest of the fields specify how many of what type to
411  * be attached.
412  * To request LFs from two blocks of same type this mailbox
413  * can be sent twice as below:
414  *      struct rsrc_attach *attach;
415  *       .. Allocate memory for message ..
416  *       attach->cptlfs = 3; <3 LFs from CPT0>
417  *       .. Send message ..
418  *       .. Allocate memory for message ..
419  *       attach->modify = 1;
420  *       attach->cpt_blkaddr = BLKADDR_CPT1;
421  *       attach->cptlfs = 2; <2 LFs from CPT1>
422  *       .. Send message ..
423  */
424 struct rsrc_attach {
425 	struct mbox_msghdr hdr;
426 	u8   modify:1;
427 	u8   npalf:1;
428 	u8   nixlf:1;
429 	u16  sso;
430 	u16  ssow;
431 	u16  timlfs;
432 	u16  cptlfs;
433 	int  cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
434 };
435 
436 /* Structure for relinquishing resources.
437  * 'partial' flag to be used when relinquishing all resources
438  * but only of a certain type. If not set, all resources of all
439  * types provisioned to the RVU function will be detached.
440  */
441 struct rsrc_detach {
442 	struct mbox_msghdr hdr;
443 	u8 partial:1;
444 	u8 npalf:1;
445 	u8 nixlf:1;
446 	u8 sso:1;
447 	u8 ssow:1;
448 	u8 timlfs:1;
449 	u8 cptlfs:1;
450 };
451 
452 /* Number of resources available to the caller.
453  * In reply to MBOX_MSG_FREE_RSRC_CNT.
454  */
455 struct free_rsrcs_rsp {
456 	struct mbox_msghdr hdr;
457 	u16 schq[NIX_TXSCH_LVL_CNT];
458 	u16  sso;
459 	u16  tim;
460 	u16  ssow;
461 	u16  cpt;
462 	u8   npa;
463 	u8   nix;
464 	u16  schq_nix1[NIX_TXSCH_LVL_CNT];
465 	u8   nix1;
466 	u8   cpt1;
467 	u8   ree0;
468 	u8   ree1;
469 };
470 
471 #define MSIX_VECTOR_INVALID	0xFFFF
472 #define MAX_RVU_BLKLF_CNT	256
473 
474 struct msix_offset_rsp {
475 	struct mbox_msghdr hdr;
476 	u16  npa_msixoff;
477 	u16  nix_msixoff;
478 	u16  sso;
479 	u16  ssow;
480 	u16  timlfs;
481 	u16  cptlfs;
482 	u16  sso_msixoff[MAX_RVU_BLKLF_CNT];
483 	u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];
484 	u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];
485 	u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];
486 	u16  cpt1_lfs;
487 	u16  ree0_lfs;
488 	u16  ree1_lfs;
489 	u16  cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
490 	u16  ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
491 	u16  ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
492 };
493 
494 struct get_hw_cap_rsp {
495 	struct mbox_msghdr hdr;
496 	u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
497 	u8 nix_shaping;		     /* Is shaping and coloring supported */
498 	u8 npc_hash_extract;	/* Is hash extract supported */
499 };
500 
501 /* CGX mbox message formats */
502 
503 struct cgx_stats_rsp {
504 	struct mbox_msghdr hdr;
505 #define CGX_RX_STATS_COUNT	9
506 #define CGX_TX_STATS_COUNT	18
507 	u64 rx_stats[CGX_RX_STATS_COUNT];
508 	u64 tx_stats[CGX_TX_STATS_COUNT];
509 };
510 
511 struct cgx_fec_stats_rsp {
512 	struct mbox_msghdr hdr;
513 	u64 fec_corr_blks;
514 	u64 fec_uncorr_blks;
515 };
516 /* Structure for requesting the operation for
517  * setting/getting mac address in the CGX interface
518  */
519 struct cgx_mac_addr_set_or_get {
520 	struct mbox_msghdr hdr;
521 	u8 mac_addr[ETH_ALEN];
522 	u32 index;
523 };
524 
525 /* Structure for requesting the operation to
526  * add DMAC filter entry into CGX interface
527  */
528 struct cgx_mac_addr_add_req {
529 	struct mbox_msghdr hdr;
530 	u8 mac_addr[ETH_ALEN];
531 };
532 
533 /* Structure for response against the operation to
534  * add DMAC filter entry into CGX interface
535  */
536 struct cgx_mac_addr_add_rsp {
537 	struct mbox_msghdr hdr;
538 	u32 index;
539 };
540 
541 /* Structure for requesting the operation to
542  * delete DMAC filter entry from CGX interface
543  */
544 struct cgx_mac_addr_del_req {
545 	struct mbox_msghdr hdr;
546 	u32 index;
547 };
548 
549 /* Structure for response against the operation to
550  * get maximum supported DMAC filter entries
551  */
552 struct cgx_max_dmac_entries_get_rsp {
553 	struct mbox_msghdr hdr;
554 	u32 max_dmac_filters;
555 };
556 
557 struct cgx_link_user_info {
558 	uint64_t link_up:1;
559 	uint64_t full_duplex:1;
560 	uint64_t lmac_type_id:4;
561 	uint64_t speed:20; /* speed in Mbps */
562 	uint64_t an:1;		/* AN supported or not */
563 	uint64_t fec:2;	 /* FEC type if enabled else 0 */
564 #define LMACTYPE_STR_LEN 16
565 	char lmac_type[LMACTYPE_STR_LEN];
566 };
567 
568 struct cgx_link_info_msg {
569 	struct mbox_msghdr hdr;
570 	struct cgx_link_user_info link_info;
571 };
572 
573 struct cgx_pause_frm_cfg {
574 	struct mbox_msghdr hdr;
575 	u8 set;
576 	/* set = 1 if the request is to config pause frames */
577 	/* set = 0 if the request is to fetch pause frames config */
578 	u8 rx_pause;
579 	u8 tx_pause;
580 };
581 
582 enum fec_type {
583 	OTX2_FEC_NONE,
584 	OTX2_FEC_BASER,
585 	OTX2_FEC_RS,
586 	OTX2_FEC_STATS_CNT = 2,
587 	OTX2_FEC_OFF,
588 };
589 
590 struct fec_mode {
591 	struct mbox_msghdr hdr;
592 	int fec;
593 };
594 
595 struct sfp_eeprom_s {
596 #define SFP_EEPROM_SIZE 256
597 	u16 sff_id;
598 	u8 buf[SFP_EEPROM_SIZE];
599 	u64 reserved;
600 };
601 
602 struct phy_s {
603 	struct {
604 		u64 can_change_mod_type:1;
605 		u64 mod_type:1;
606 		u64 has_fec_stats:1;
607 	} misc;
608 	struct fec_stats_s {
609 		u32 rsfec_corr_cws;
610 		u32 rsfec_uncorr_cws;
611 		u32 brfec_corr_blks;
612 		u32 brfec_uncorr_blks;
613 	} fec_stats;
614 };
615 
616 struct cgx_lmac_fwdata_s {
617 	u16 rw_valid;
618 	u64 supported_fec;
619 	u64 supported_an;
620 	u64 supported_link_modes;
621 	/* only applicable if AN is supported */
622 	u64 advertised_fec;
623 	u64 advertised_link_modes;
624 	/* Only applicable if SFP/QSFP slot is present */
625 	struct sfp_eeprom_s sfp_eeprom;
626 	struct phy_s phy;
627 #define LMAC_FWDATA_RESERVED_MEM 1021
628 	u64 reserved[LMAC_FWDATA_RESERVED_MEM];
629 };
630 
631 struct cgx_fw_data {
632 	struct mbox_msghdr hdr;
633 	struct cgx_lmac_fwdata_s fwdata;
634 };
635 
636 struct cgx_set_link_mode_args {
637 	u32 speed;
638 	u8 duplex;
639 	u8 an;
640 	u8 ports;
641 	u64 mode;
642 };
643 
644 struct cgx_set_link_mode_req {
645 #define AUTONEG_UNKNOWN		0xff
646 	struct mbox_msghdr hdr;
647 	struct cgx_set_link_mode_args args;
648 };
649 
650 struct cgx_set_link_mode_rsp {
651 	struct mbox_msghdr hdr;
652 	int status;
653 };
654 
655 struct cgx_mac_addr_reset_req {
656 	struct mbox_msghdr hdr;
657 	u32 index;
658 };
659 
660 struct cgx_mac_addr_update_req {
661 	struct mbox_msghdr hdr;
662 	u8 mac_addr[ETH_ALEN];
663 	u32 index;
664 };
665 
666 struct cgx_mac_addr_update_rsp {
667 	struct mbox_msghdr hdr;
668 	u32 index;
669 };
670 
671 #define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */
672 #define	RVU_LMAC_FEAT_HIGIG2		BIT_ULL(1)
673 			/* flow control from physical link higig2 messages */
674 #define RVU_LMAC_FEAT_PTP		BIT_ULL(2) /* precison time protocol */
675 #define RVU_LMAC_FEAT_DMACF		BIT_ULL(3) /* DMAC FILTER */
676 #define RVU_MAC_VERSION			BIT_ULL(4)
677 #define RVU_MAC_CGX			BIT_ULL(5)
678 #define RVU_MAC_RPM			BIT_ULL(6)
679 
680 struct cgx_features_info_msg {
681 	struct mbox_msghdr hdr;
682 	u64    lmac_features;
683 };
684 
685 struct rpm_stats_rsp {
686 	struct mbox_msghdr hdr;
687 #define RPM_RX_STATS_COUNT		43
688 #define RPM_TX_STATS_COUNT		34
689 	u64 rx_stats[RPM_RX_STATS_COUNT];
690 	u64 tx_stats[RPM_TX_STATS_COUNT];
691 };
692 
693 struct cgx_pfc_cfg {
694 	struct mbox_msghdr hdr;
695 	u8 rx_pause;
696 	u8 tx_pause;
697 	u16 pfc_en; /*  bitmap indicating pfc enabled traffic classes */
698 };
699 
700 struct cgx_pfc_rsp {
701 	struct mbox_msghdr hdr;
702 	u8 rx_pause;
703 	u8 tx_pause;
704 };
705 
706  /* NPA mbox message formats */
707 
708 struct npc_set_pkind {
709 	struct mbox_msghdr hdr;
710 #define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
711 #define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
712 	u64 mode;
713 #define PKIND_TX		BIT_ULL(0)
714 #define PKIND_RX		BIT_ULL(1)
715 	u8 dir;
716 	u8 pkind; /* valid only in case custom flag */
717 	u8 var_len_off; /* Offset of custom header length field.
718 			 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
719 			 */
720 	u8 var_len_off_mask; /* Mask for length with in offset */
721 	u8 shift_dir; /* shift direction to get length of the header at var_len_off */
722 };
723 
724 /* NPA mbox message formats */
725 
726 /* NPA mailbox error codes
727  * Range 301 - 400.
728  */
729 enum npa_af_status {
730 	NPA_AF_ERR_PARAM            = -301,
731 	NPA_AF_ERR_AQ_FULL          = -302,
732 	NPA_AF_ERR_AQ_ENQUEUE       = -303,
733 	NPA_AF_ERR_AF_LF_INVALID    = -304,
734 	NPA_AF_ERR_AF_LF_ALLOC      = -305,
735 	NPA_AF_ERR_LF_RESET         = -306,
736 };
737 
738 /* For NPA LF context alloc and init */
739 struct npa_lf_alloc_req {
740 	struct mbox_msghdr hdr;
741 	int node;
742 	int aura_sz;  /* No of auras */
743 	u32 nr_pools; /* No of pools */
744 	u64 way_mask;
745 };
746 
747 struct npa_lf_alloc_rsp {
748 	struct mbox_msghdr hdr;
749 	u32 stack_pg_ptrs;  /* No of ptrs per stack page */
750 	u32 stack_pg_bytes; /* Size of stack page */
751 	u16 qints; /* NPA_AF_CONST::QINTS */
752 	u8 cache_lines; /*BATCH ALLOC DMA */
753 };
754 
755 /* NPA AQ enqueue msg */
756 struct npa_aq_enq_req {
757 	struct mbox_msghdr hdr;
758 	u32 aura_id;
759 	u8 ctype;
760 	u8 op;
761 	union {
762 		/* Valid when op == WRITE/INIT and ctype == AURA.
763 		 * LF fills the pool_id in aura.pool_addr. AF will translate
764 		 * the pool_id to pool context pointer.
765 		 */
766 		struct npa_aura_s aura;
767 		/* Valid when op == WRITE/INIT and ctype == POOL */
768 		struct npa_pool_s pool;
769 	};
770 	/* Mask data when op == WRITE (1=write, 0=don't write) */
771 	union {
772 		/* Valid when op == WRITE and ctype == AURA */
773 		struct npa_aura_s aura_mask;
774 		/* Valid when op == WRITE and ctype == POOL */
775 		struct npa_pool_s pool_mask;
776 	};
777 };
778 
779 struct npa_aq_enq_rsp {
780 	struct mbox_msghdr hdr;
781 	union {
782 		/* Valid when op == READ and ctype == AURA */
783 		struct npa_aura_s aura;
784 		/* Valid when op == READ and ctype == POOL */
785 		struct npa_pool_s pool;
786 	};
787 };
788 
789 /* Disable all contexts of type 'ctype' */
790 struct hwctx_disable_req {
791 	struct mbox_msghdr hdr;
792 	u8 ctype;
793 };
794 
795 /* NIX mbox message formats */
796 
797 /* NIX mailbox error codes
798  * Range 401 - 500.
799  */
800 enum nix_af_status {
801 	NIX_AF_ERR_PARAM            = -401,
802 	NIX_AF_ERR_AQ_FULL          = -402,
803 	NIX_AF_ERR_AQ_ENQUEUE       = -403,
804 	NIX_AF_ERR_AF_LF_INVALID    = -404,
805 	NIX_AF_ERR_AF_LF_ALLOC      = -405,
806 	NIX_AF_ERR_TLX_ALLOC_FAIL   = -406,
807 	NIX_AF_ERR_TLX_INVALID      = -407,
808 	NIX_AF_ERR_RSS_SIZE_INVALID = -408,
809 	NIX_AF_ERR_RSS_GRPS_INVALID = -409,
810 	NIX_AF_ERR_FRS_INVALID      = -410,
811 	NIX_AF_ERR_RX_LINK_INVALID  = -411,
812 	NIX_AF_INVAL_TXSCHQ_CFG     = -412,
813 	NIX_AF_SMQ_FLUSH_FAILED     = -413,
814 	NIX_AF_ERR_LF_RESET         = -414,
815 	NIX_AF_ERR_RSS_NOSPC_FIELD  = -415,
816 	NIX_AF_ERR_RSS_NOSPC_ALGO   = -416,
817 	NIX_AF_ERR_MARK_CFG_FAIL    = -417,
818 	NIX_AF_ERR_LSO_CFG_FAIL     = -418,
819 	NIX_AF_INVAL_NPA_PF_FUNC    = -419,
820 	NIX_AF_INVAL_SSO_PF_FUNC    = -420,
821 	NIX_AF_ERR_TX_VTAG_NOSPC    = -421,
822 	NIX_AF_ERR_RX_VTAG_INUSE    = -422,
823 	NIX_AF_ERR_PTP_CONFIG_FAIL  = -423,
824 	NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
825 	NIX_AF_ERR_INVALID_NIXBLK   = -425,
826 	NIX_AF_ERR_INVALID_BANDPROF = -426,
827 	NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
828 	NIX_AF_ERR_BANDPROF_INVAL_REQ  = -428,
829 	NIX_AF_ERR_CQ_CTX_WRITE_ERR  = -429,
830 	NIX_AF_ERR_AQ_CTX_RETRY_WRITE  = -430,
831 	NIX_AF_ERR_LINK_CREDITS  = -431,
832 };
833 
834 /* For NIX RX vtag action  */
835 enum nix_rx_vtag0_type {
836 	NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
837 	NIX_AF_LFX_RX_VTAG_TYPE1,
838 	NIX_AF_LFX_RX_VTAG_TYPE2,
839 	NIX_AF_LFX_RX_VTAG_TYPE3,
840 	NIX_AF_LFX_RX_VTAG_TYPE4,
841 	NIX_AF_LFX_RX_VTAG_TYPE5,
842 	NIX_AF_LFX_RX_VTAG_TYPE6,
843 	NIX_AF_LFX_RX_VTAG_TYPE7,
844 };
845 
846 /* For NIX LF context alloc and init */
847 struct nix_lf_alloc_req {
848 	struct mbox_msghdr hdr;
849 	int node;
850 	u32 rq_cnt;   /* No of receive queues */
851 	u32 sq_cnt;   /* No of send queues */
852 	u32 cq_cnt;   /* No of completion queues */
853 	u8  xqe_sz;
854 	u16 rss_sz;
855 	u8  rss_grps;
856 	u16 npa_func;
857 	u16 sso_func;
858 	u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */
859 	u64 way_mask;
860 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
861 #define NIX_LF_LBK_BLK_SEL	    BIT_ULL(1)
862 	u64 flags;
863 };
864 
865 struct nix_lf_alloc_rsp {
866 	struct mbox_msghdr hdr;
867 	u16	sqb_size;
868 	u16	rx_chan_base;
869 	u16	tx_chan_base;
870 	u8      rx_chan_cnt; /* total number of RX channels */
871 	u8      tx_chan_cnt; /* total number of TX channels */
872 	u8	lso_tsov4_idx;
873 	u8	lso_tsov6_idx;
874 	u8      mac_addr[ETH_ALEN];
875 	u8	lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
876 	u8	lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
877 	u16	cints; /* NIX_AF_CONST2::CINTS */
878 	u16	qints; /* NIX_AF_CONST2::QINTS */
879 	u8	cgx_links;  /* No. of CGX links present in HW */
880 	u8	lbk_links;  /* No. of LBK links present in HW */
881 	u8	sdp_links;  /* No. of SDP links present in HW */
882 	u8	tx_link;    /* Transmit channel link number */
883 };
884 
885 struct nix_lf_free_req {
886 	struct mbox_msghdr hdr;
887 #define NIX_LF_DISABLE_FLOWS		BIT_ULL(0)
888 #define NIX_LF_DONT_FREE_TX_VTAG	BIT_ULL(1)
889 	u64 flags;
890 };
891 
892 /* CN10K NIX AQ enqueue msg */
893 struct nix_cn10k_aq_enq_req {
894 	struct mbox_msghdr hdr;
895 	u32  qidx;
896 	u8 ctype;
897 	u8 op;
898 	union {
899 		struct nix_cn10k_rq_ctx_s rq;
900 		struct nix_cn10k_sq_ctx_s sq;
901 		struct nix_cq_ctx_s cq;
902 		struct nix_rsse_s   rss;
903 		struct nix_rx_mce_s mce;
904 		struct nix_bandprof_s prof;
905 	};
906 	union {
907 		struct nix_cn10k_rq_ctx_s rq_mask;
908 		struct nix_cn10k_sq_ctx_s sq_mask;
909 		struct nix_cq_ctx_s cq_mask;
910 		struct nix_rsse_s   rss_mask;
911 		struct nix_rx_mce_s mce_mask;
912 		struct nix_bandprof_s prof_mask;
913 	};
914 };
915 
916 struct nix_cn10k_aq_enq_rsp {
917 	struct mbox_msghdr hdr;
918 	union {
919 		struct nix_cn10k_rq_ctx_s rq;
920 		struct nix_cn10k_sq_ctx_s sq;
921 		struct nix_cq_ctx_s cq;
922 		struct nix_rsse_s   rss;
923 		struct nix_rx_mce_s mce;
924 		struct nix_bandprof_s prof;
925 	};
926 };
927 
928 /* NIX AQ enqueue msg */
929 struct nix_aq_enq_req {
930 	struct mbox_msghdr hdr;
931 	u32  qidx;
932 	u8 ctype;
933 	u8 op;
934 	union {
935 		struct nix_rq_ctx_s rq;
936 		struct nix_sq_ctx_s sq;
937 		struct nix_cq_ctx_s cq;
938 		struct nix_rsse_s   rss;
939 		struct nix_rx_mce_s mce;
940 		struct nix_bandprof_s prof;
941 	};
942 	union {
943 		struct nix_rq_ctx_s rq_mask;
944 		struct nix_sq_ctx_s sq_mask;
945 		struct nix_cq_ctx_s cq_mask;
946 		struct nix_rsse_s   rss_mask;
947 		struct nix_rx_mce_s mce_mask;
948 		struct nix_bandprof_s prof_mask;
949 	};
950 };
951 
952 struct nix_aq_enq_rsp {
953 	struct mbox_msghdr hdr;
954 	union {
955 		struct nix_rq_ctx_s rq;
956 		struct nix_sq_ctx_s sq;
957 		struct nix_cq_ctx_s cq;
958 		struct nix_rsse_s   rss;
959 		struct nix_rx_mce_s mce;
960 		struct nix_bandprof_s prof;
961 	};
962 };
963 
964 /* Tx scheduler/shaper mailbox messages */
965 
966 #define MAX_TXSCHQ_PER_FUNC		128
967 
968 struct nix_txsch_alloc_req {
969 	struct mbox_msghdr hdr;
970 	/* Scheduler queue count request at each level */
971 	u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
972 	u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
973 };
974 
975 struct nix_txsch_alloc_rsp {
976 	struct mbox_msghdr hdr;
977 	/* Scheduler queue count allocated at each level */
978 	u16 schq_contig[NIX_TXSCH_LVL_CNT];
979 	u16 schq[NIX_TXSCH_LVL_CNT];
980 	/* Scheduler queue list allocated at each level */
981 	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
982 	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
983 	u8  aggr_level; /* Traffic aggregation scheduler level */
984 	u8  aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
985 	u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
986 };
987 
988 struct nix_txsch_free_req {
989 	struct mbox_msghdr hdr;
990 #define TXSCHQ_FREE_ALL BIT_ULL(0)
991 	u16 flags;
992 	/* Scheduler queue level to be freed */
993 	u16 schq_lvl;
994 	/* List of scheduler queues to be freed */
995 	u16 schq;
996 };
997 
998 struct nix_txschq_config {
999 	struct mbox_msghdr hdr;
1000 	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1001 	u8 read;
1002 #define TXSCHQ_IDX_SHIFT	16
1003 #define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)
1004 #define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1005 	u8 num_regs;
1006 #define MAX_REGS_PER_MBOX_MSG	20
1007 	u64 reg[MAX_REGS_PER_MBOX_MSG];
1008 	u64 regval[MAX_REGS_PER_MBOX_MSG];
1009 	/* All 0's => overwrite with new value */
1010 	u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1011 };
1012 
1013 struct nix_vtag_config {
1014 	struct mbox_msghdr hdr;
1015 	/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1016 	u8 vtag_size;
1017 	/* cfg_type is '0' for tx vlan cfg
1018 	 * cfg_type is '1' for rx vlan cfg
1019 	 */
1020 	u8 cfg_type;
1021 	union {
1022 		/* valid when cfg_type is '0' */
1023 		struct {
1024 			u64 vtag0;
1025 			u64 vtag1;
1026 
1027 			/* cfg_vtag0 & cfg_vtag1 fields are valid
1028 			 * when free_vtag0 & free_vtag1 are '0's.
1029 			 */
1030 			/* cfg_vtag0 = 1 to configure vtag0 */
1031 			u8 cfg_vtag0 :1;
1032 			/* cfg_vtag1 = 1 to configure vtag1 */
1033 			u8 cfg_vtag1 :1;
1034 
1035 			/* vtag0_idx & vtag1_idx are only valid when
1036 			 * both cfg_vtag0 & cfg_vtag1 are '0's,
1037 			 * these fields are used along with free_vtag0
1038 			 * & free_vtag1 to free the nix lf's tx_vlan
1039 			 * configuration.
1040 			 *
1041 			 * Denotes the indices of tx_vtag def registers
1042 			 * that needs to be cleared and freed.
1043 			 */
1044 			int vtag0_idx;
1045 			int vtag1_idx;
1046 
1047 			/* free_vtag0 & free_vtag1 fields are valid
1048 			 * when cfg_vtag0 & cfg_vtag1 are '0's.
1049 			 */
1050 			/* free_vtag0 = 1 clears vtag0 configuration
1051 			 * vtag0_idx denotes the index to be cleared.
1052 			 */
1053 			u8 free_vtag0 :1;
1054 			/* free_vtag1 = 1 clears vtag1 configuration
1055 			 * vtag1_idx denotes the index to be cleared.
1056 			 */
1057 			u8 free_vtag1 :1;
1058 		} tx;
1059 
1060 		/* valid when cfg_type is '1' */
1061 		struct {
1062 			/* rx vtag type index, valid values are in 0..7 range */
1063 			u8 vtag_type;
1064 			/* rx vtag strip */
1065 			u8 strip_vtag :1;
1066 			/* rx vtag capture */
1067 			u8 capture_vtag :1;
1068 		} rx;
1069 	};
1070 };
1071 
1072 struct nix_vtag_config_rsp {
1073 	struct mbox_msghdr hdr;
1074 	int vtag0_idx;
1075 	int vtag1_idx;
1076 	/* Indices of tx_vtag def registers used to configure
1077 	 * tx vtag0 & vtag1 headers, these indices are valid
1078 	 * when nix_vtag_config mbox requested for vtag0 and/
1079 	 * or vtag1 configuration.
1080 	 */
1081 };
1082 
1083 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1084 
1085 struct nix_rss_flowkey_cfg {
1086 	struct mbox_msghdr hdr;
1087 	int	mcam_index;  /* MCAM entry index to modify */
1088 #define NIX_FLOW_KEY_TYPE_PORT	BIT(0)
1089 #define NIX_FLOW_KEY_TYPE_IPV4	BIT(1)
1090 #define NIX_FLOW_KEY_TYPE_IPV6	BIT(2)
1091 #define NIX_FLOW_KEY_TYPE_TCP	BIT(3)
1092 #define NIX_FLOW_KEY_TYPE_UDP	BIT(4)
1093 #define NIX_FLOW_KEY_TYPE_SCTP	BIT(5)
1094 #define NIX_FLOW_KEY_TYPE_NVGRE    BIT(6)
1095 #define NIX_FLOW_KEY_TYPE_VXLAN    BIT(7)
1096 #define NIX_FLOW_KEY_TYPE_GENEVE   BIT(8)
1097 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1098 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1099 #define NIX_FLOW_KEY_TYPE_GTPU       BIT(11)
1100 #define NIX_FLOW_KEY_TYPE_INNR_IPV4     BIT(12)
1101 #define NIX_FLOW_KEY_TYPE_INNR_IPV6     BIT(13)
1102 #define NIX_FLOW_KEY_TYPE_INNR_TCP      BIT(14)
1103 #define NIX_FLOW_KEY_TYPE_INNR_UDP      BIT(15)
1104 #define NIX_FLOW_KEY_TYPE_INNR_SCTP     BIT(16)
1105 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1106 #define NIX_FLOW_KEY_TYPE_VLAN		BIT(20)
1107 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO	BIT(21)
1108 #define NIX_FLOW_KEY_TYPE_AH		BIT(22)
1109 #define NIX_FLOW_KEY_TYPE_ESP		BIT(23)
1110 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1111 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1112 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1113 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1114 	u32	flowkey_cfg; /* Flowkey types selected */
1115 	u8	group;       /* RSS context or group */
1116 };
1117 
1118 struct nix_rss_flowkey_cfg_rsp {
1119 	struct mbox_msghdr hdr;
1120 	u8	alg_idx; /* Selected algo index */
1121 };
1122 
1123 struct nix_set_mac_addr {
1124 	struct mbox_msghdr hdr;
1125 	u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1126 };
1127 
1128 struct nix_get_mac_addr_rsp {
1129 	struct mbox_msghdr hdr;
1130 	u8 mac_addr[ETH_ALEN];
1131 };
1132 
1133 struct nix_mark_format_cfg {
1134 	struct mbox_msghdr hdr;
1135 	u8 offset;
1136 	u8 y_mask;
1137 	u8 y_val;
1138 	u8 r_mask;
1139 	u8 r_val;
1140 };
1141 
1142 struct nix_mark_format_cfg_rsp {
1143 	struct mbox_msghdr hdr;
1144 	u8 mark_format_idx;
1145 };
1146 
1147 struct nix_rx_mode {
1148 	struct mbox_msghdr hdr;
1149 #define NIX_RX_MODE_UCAST	BIT(0)
1150 #define NIX_RX_MODE_PROMISC	BIT(1)
1151 #define NIX_RX_MODE_ALLMULTI	BIT(2)
1152 #define NIX_RX_MODE_USE_MCE	BIT(3)
1153 	u16	mode;
1154 };
1155 
1156 struct nix_rx_cfg {
1157 	struct mbox_msghdr hdr;
1158 #define NIX_RX_OL3_VERIFY   BIT(0)
1159 #define NIX_RX_OL4_VERIFY   BIT(1)
1160 #define NIX_RX_DROP_RE      BIT(2)
1161 	u8 len_verify; /* Outer L3/L4 len check */
1162 #define NIX_RX_CSUM_OL4_VERIFY  BIT(0)
1163 	u8 csum_verify; /* Outer L4 checksum verification */
1164 };
1165 
1166 struct nix_frs_cfg {
1167 	struct mbox_msghdr hdr;
1168 	u8	update_smq;    /* Update SMQ's min/max lens */
1169 	u8	update_minlen; /* Set minlen also */
1170 	u8	sdp_link;      /* Set SDP RX link */
1171 	u16	maxlen;
1172 	u16	minlen;
1173 };
1174 
1175 struct nix_lso_format_cfg {
1176 	struct mbox_msghdr hdr;
1177 	u64 field_mask;
1178 #define NIX_LSO_FIELD_MAX	8
1179 	u64 fields[NIX_LSO_FIELD_MAX];
1180 };
1181 
1182 struct nix_lso_format_cfg_rsp {
1183 	struct mbox_msghdr hdr;
1184 	u8 lso_format_idx;
1185 };
1186 
1187 struct nix_bp_cfg_req {
1188 	struct mbox_msghdr hdr;
1189 	u16	chan_base; /* Starting channel number */
1190 	u8	chan_cnt; /* Number of channels */
1191 	u8	bpid_per_chan;
1192 	/* bpid_per_chan = 0 assigns single bp id for range of channels */
1193 	/* bpid_per_chan = 1 assigns separate bp id for each channel */
1194 };
1195 
1196 /* PF can be mapped to either CGX or LBK interface,
1197  * so maximum 64 channels are possible.
1198  */
1199 #define NIX_MAX_BPID_CHAN	64
1200 struct nix_bp_cfg_rsp {
1201 	struct mbox_msghdr hdr;
1202 	u16	chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1203 	u8	chan_cnt; /* Number of channel for which bpids are assigned */
1204 };
1205 
1206 /* Global NIX inline IPSec configuration */
1207 struct nix_inline_ipsec_cfg {
1208 	struct mbox_msghdr hdr;
1209 	u32 cpt_credit;
1210 	struct {
1211 		u8 egrp;
1212 		u16 opcode;
1213 		u16 param1;
1214 		u16 param2;
1215 	} gen_cfg;
1216 	struct {
1217 		u16 cpt_pf_func;
1218 		u8 cpt_slot;
1219 	} inst_qsel;
1220 	u8 enable;
1221 	u16 bpid;
1222 	u32 credit_th;
1223 };
1224 
1225 /* Per NIX LF inline IPSec configuration */
1226 struct nix_inline_ipsec_lf_cfg {
1227 	struct mbox_msghdr hdr;
1228 	u64 sa_base_addr;
1229 	struct {
1230 		u32 tag_const;
1231 		u16 lenm1_max;
1232 		u8 sa_pow2_size;
1233 		u8 tt;
1234 	} ipsec_cfg0;
1235 	struct {
1236 		u32 sa_idx_max;
1237 		u8 sa_idx_w;
1238 	} ipsec_cfg1;
1239 	u8 enable;
1240 };
1241 
1242 struct nix_hw_info {
1243 	struct mbox_msghdr hdr;
1244 	u16 rsvs16;
1245 	u16 max_mtu;
1246 	u16 min_mtu;
1247 	u32 rpm_dwrr_mtu;
1248 	u32 sdp_dwrr_mtu;
1249 	u32 lbk_dwrr_mtu;
1250 	u32 rsvd32[1];
1251 	u64 rsvd[15]; /* Add reserved fields for future expansion */
1252 };
1253 
1254 struct nix_bandprof_alloc_req {
1255 	struct mbox_msghdr hdr;
1256 	/* Count of profiles needed per layer */
1257 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1258 };
1259 
1260 struct nix_bandprof_alloc_rsp {
1261 	struct mbox_msghdr hdr;
1262 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1263 
1264 	/* There is no need to allocate morethan 1 bandwidth profile
1265 	 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1266 	 * profiles to 64 per PF_FUNC.
1267 	 */
1268 #define MAX_BANDPROF_PER_PFFUNC	64
1269 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1270 };
1271 
1272 struct nix_bandprof_free_req {
1273 	struct mbox_msghdr hdr;
1274 	u8 free_all;
1275 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1276 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1277 };
1278 
1279 struct nix_bandprof_get_hwinfo_rsp {
1280 	struct mbox_msghdr hdr;
1281 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1282 	u32 policer_timeunit;
1283 };
1284 
1285 /* NPC mbox message structs */
1286 
1287 #define NPC_MCAM_ENTRY_INVALID	0xFFFF
1288 #define NPC_MCAM_INVALID_MAP	0xFFFF
1289 
1290 /* NPC mailbox error codes
1291  * Range 701 - 800.
1292  */
1293 enum npc_af_status {
1294 	NPC_MCAM_INVALID_REQ	= -701,
1295 	NPC_MCAM_ALLOC_DENIED	= -702,
1296 	NPC_MCAM_ALLOC_FAILED	= -703,
1297 	NPC_MCAM_PERM_DENIED	= -704,
1298 	NPC_FLOW_INTF_INVALID	= -707,
1299 	NPC_FLOW_CHAN_INVALID	= -708,
1300 	NPC_FLOW_NO_NIXLF	= -709,
1301 	NPC_FLOW_NOT_SUPPORTED	= -710,
1302 	NPC_FLOW_VF_PERM_DENIED	= -711,
1303 	NPC_FLOW_VF_NOT_INIT	= -712,
1304 	NPC_FLOW_VF_OVERLAP	= -713,
1305 };
1306 
1307 struct npc_mcam_alloc_entry_req {
1308 	struct mbox_msghdr hdr;
1309 #define NPC_MAX_NONCONTIG_ENTRIES	256
1310 	u8  contig;   /* Contiguous entries ? */
1311 #define NPC_MCAM_ANY_PRIO		0
1312 #define NPC_MCAM_LOWER_PRIO		1
1313 #define NPC_MCAM_HIGHER_PRIO		2
1314 	u8  priority; /* Lower or higher w.r.t ref_entry */
1315 	u16 ref_entry;
1316 	u16 count;    /* Number of entries requested */
1317 };
1318 
1319 struct npc_mcam_alloc_entry_rsp {
1320 	struct mbox_msghdr hdr;
1321 	u16 entry; /* Entry allocated or start index if contiguous.
1322 		    * Invalid incase of non-contiguous.
1323 		    */
1324 	u16 count; /* Number of entries allocated */
1325 	u16 free_count; /* Number of entries available */
1326 	u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1327 };
1328 
1329 struct npc_mcam_free_entry_req {
1330 	struct mbox_msghdr hdr;
1331 	u16 entry; /* Entry index to be freed */
1332 	u8  all;   /* If all entries allocated to this PFVF to be freed */
1333 };
1334 
1335 struct mcam_entry {
1336 #define NPC_MAX_KWS_IN_KEY	7 /* Number of keywords in max keywidth */
1337 	u64	kw[NPC_MAX_KWS_IN_KEY];
1338 	u64	kw_mask[NPC_MAX_KWS_IN_KEY];
1339 	u64	action;
1340 	u64	vtag_action;
1341 };
1342 
1343 struct npc_mcam_write_entry_req {
1344 	struct mbox_msghdr hdr;
1345 	struct mcam_entry entry_data;
1346 	u16 entry;	 /* MCAM entry to write this match key */
1347 	u16 cntr;	 /* Counter for this MCAM entry */
1348 	u8  intf;	 /* Rx or Tx interface */
1349 	u8  enable_entry;/* Enable this MCAM entry ? */
1350 	u8  set_cntr;    /* Set counter for this entry ? */
1351 };
1352 
1353 /* Enable/Disable a given entry */
1354 struct npc_mcam_ena_dis_entry_req {
1355 	struct mbox_msghdr hdr;
1356 	u16 entry;
1357 };
1358 
1359 struct npc_mcam_shift_entry_req {
1360 	struct mbox_msghdr hdr;
1361 #define NPC_MCAM_MAX_SHIFTS	64
1362 	u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1363 	u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1364 	u16 shift_count; /* Number of entries to shift */
1365 };
1366 
1367 struct npc_mcam_shift_entry_rsp {
1368 	struct mbox_msghdr hdr;
1369 	u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1370 };
1371 
1372 struct npc_mcam_alloc_counter_req {
1373 	struct mbox_msghdr hdr;
1374 	u8  contig;	/* Contiguous counters ? */
1375 #define NPC_MAX_NONCONTIG_COUNTERS       64
1376 	u16 count;	/* Number of counters requested */
1377 };
1378 
1379 struct npc_mcam_alloc_counter_rsp {
1380 	struct mbox_msghdr hdr;
1381 	u16 cntr;   /* Counter allocated or start index if contiguous.
1382 		     * Invalid incase of non-contiguous.
1383 		     */
1384 	u16 count;  /* Number of counters allocated */
1385 	u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1386 };
1387 
1388 struct npc_mcam_oper_counter_req {
1389 	struct mbox_msghdr hdr;
1390 	u16 cntr;   /* Free a counter or clear/fetch it's stats */
1391 };
1392 
1393 struct npc_mcam_oper_counter_rsp {
1394 	struct mbox_msghdr hdr;
1395 	u64 stat;  /* valid only while fetching counter's stats */
1396 };
1397 
1398 struct npc_mcam_unmap_counter_req {
1399 	struct mbox_msghdr hdr;
1400 	u16 cntr;
1401 	u16 entry; /* Entry and counter to be unmapped */
1402 	u8  all;   /* Unmap all entries using this counter ? */
1403 };
1404 
1405 struct npc_mcam_alloc_and_write_entry_req {
1406 	struct mbox_msghdr hdr;
1407 	struct mcam_entry entry_data;
1408 	u16 ref_entry;
1409 	u8  priority;    /* Lower or higher w.r.t ref_entry */
1410 	u8  intf;	 /* Rx or Tx interface */
1411 	u8  enable_entry;/* Enable this MCAM entry ? */
1412 	u8  alloc_cntr;  /* Allocate counter and map ? */
1413 };
1414 
1415 struct npc_mcam_alloc_and_write_entry_rsp {
1416 	struct mbox_msghdr hdr;
1417 	u16 entry;
1418 	u16 cntr;
1419 };
1420 
1421 struct npc_get_kex_cfg_rsp {
1422 	struct mbox_msghdr hdr;
1423 	u64 rx_keyx_cfg;   /* NPC_AF_INTF(0)_KEX_CFG */
1424 	u64 tx_keyx_cfg;   /* NPC_AF_INTF(1)_KEX_CFG */
1425 #define NPC_MAX_INTF	2
1426 #define NPC_MAX_LID	8
1427 #define NPC_MAX_LT	16
1428 #define NPC_MAX_LD	2
1429 #define NPC_MAX_LFL	16
1430 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1431 	u64 kex_ld_flags[NPC_MAX_LD];
1432 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1433 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1434 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1435 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1436 #define MKEX_NAME_LEN 128
1437 	u8 mkex_pfl_name[MKEX_NAME_LEN];
1438 };
1439 
1440 struct flow_msg {
1441 	unsigned char dmac[6];
1442 	unsigned char smac[6];
1443 	__be16 etype;
1444 	__be16 vlan_etype;
1445 	__be16 vlan_tci;
1446 	union {
1447 		__be32 ip4src;
1448 		__be32 ip6src[4];
1449 	};
1450 	union {
1451 		__be32 ip4dst;
1452 		__be32 ip6dst[4];
1453 	};
1454 	u8 tos;
1455 	u8 ip_ver;
1456 	u8 ip_proto;
1457 	u8 tc;
1458 	__be16 sport;
1459 	__be16 dport;
1460 	union {
1461 		u8 ip_flag;
1462 		u8 next_header;
1463 	};
1464 };
1465 
1466 struct npc_install_flow_req {
1467 	struct mbox_msghdr hdr;
1468 	struct flow_msg packet;
1469 	struct flow_msg mask;
1470 	u64 features;
1471 	u16 entry;
1472 	u16 channel;
1473 	u16 chan_mask;
1474 	u8 intf;
1475 	u8 set_cntr; /* If counter is available set counter for this entry ? */
1476 	u8 default_rule;
1477 	u8 append; /* overwrite(0) or append(1) flow to default rule? */
1478 	u16 vf;
1479 	/* action */
1480 	u32 index;
1481 	u16 match_id;
1482 	u8 flow_key_alg;
1483 	u8 op;
1484 	/* vtag rx action */
1485 	u8 vtag0_type;
1486 	u8 vtag0_valid;
1487 	u8 vtag1_type;
1488 	u8 vtag1_valid;
1489 	/* vtag tx action */
1490 	u16 vtag0_def;
1491 	u8  vtag0_op;
1492 	u16 vtag1_def;
1493 	u8  vtag1_op;
1494 };
1495 
1496 struct npc_install_flow_rsp {
1497 	struct mbox_msghdr hdr;
1498 	int counter; /* negative if no counter else counter number */
1499 };
1500 
1501 struct npc_delete_flow_req {
1502 	struct mbox_msghdr hdr;
1503 	u16 entry;
1504 	u16 start;/*Disable range of entries */
1505 	u16 end;
1506 	u8 all; /* PF + VFs */
1507 };
1508 
1509 struct npc_mcam_read_entry_req {
1510 	struct mbox_msghdr hdr;
1511 	u16 entry;	 /* MCAM entry to read */
1512 };
1513 
1514 struct npc_mcam_read_entry_rsp {
1515 	struct mbox_msghdr hdr;
1516 	struct mcam_entry entry_data;
1517 	u8 intf;
1518 	u8 enable;
1519 };
1520 
1521 struct npc_mcam_read_base_rule_rsp {
1522 	struct mbox_msghdr hdr;
1523 	struct mcam_entry entry;
1524 };
1525 
1526 struct npc_mcam_get_stats_req {
1527 	struct mbox_msghdr hdr;
1528 	u16 entry; /* mcam entry */
1529 };
1530 
1531 struct npc_mcam_get_stats_rsp {
1532 	struct mbox_msghdr hdr;
1533 	u64 stat;  /* counter stats */
1534 	u8 stat_ena; /* enabled */
1535 };
1536 
1537 struct npc_get_field_hash_info_req {
1538 	struct mbox_msghdr hdr;
1539 	u8 intf;
1540 };
1541 
1542 struct npc_get_field_hash_info_rsp {
1543 	struct mbox_msghdr hdr;
1544 	u64 secret_key[3];
1545 #define NPC_MAX_HASH 2
1546 #define NPC_MAX_HASH_MASK 2
1547 	/* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1548 	u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1549 	/* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1550 	u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1551 };
1552 
1553 enum ptp_op {
1554 	PTP_OP_ADJFINE = 0,
1555 	PTP_OP_GET_CLOCK = 1,
1556 	PTP_OP_GET_TSTMP = 2,
1557 	PTP_OP_SET_THRESH = 3,
1558 	PTP_OP_EXTTS_ON = 4,
1559 };
1560 
1561 struct ptp_req {
1562 	struct mbox_msghdr hdr;
1563 	u8 op;
1564 	s64 scaled_ppm;
1565 	u64 thresh;
1566 	int extts_on;
1567 };
1568 
1569 struct ptp_rsp {
1570 	struct mbox_msghdr hdr;
1571 	u64 clk;
1572 };
1573 
1574 struct npc_get_field_status_req {
1575 	struct mbox_msghdr hdr;
1576 	u8 intf;
1577 	u8 field;
1578 };
1579 
1580 struct npc_get_field_status_rsp {
1581 	struct mbox_msghdr hdr;
1582 	u8 enable;
1583 };
1584 
1585 struct set_vf_perm  {
1586 	struct  mbox_msghdr hdr;
1587 	u16	vf;
1588 #define RESET_VF_PERM		BIT_ULL(0)
1589 #define	VF_TRUSTED		BIT_ULL(1)
1590 	u64	flags;
1591 };
1592 
1593 struct lmtst_tbl_setup_req {
1594 	struct mbox_msghdr hdr;
1595 	u64 dis_sched_early_comp :1;
1596 	u64 sch_ena		 :1;
1597 	u64 dis_line_pref	 :1;
1598 	u64 ssow_pf_func	 :13;
1599 	u16 base_pcifunc;
1600 	u8  use_local_lmt_region;
1601 	u64 lmt_iova;
1602 	u64 rsvd[4];
1603 };
1604 
1605 /* CPT mailbox error codes
1606  * Range 901 - 1000.
1607  */
1608 enum cpt_af_status {
1609 	CPT_AF_ERR_PARAM		= -901,
1610 	CPT_AF_ERR_GRP_INVALID		= -902,
1611 	CPT_AF_ERR_LF_INVALID		= -903,
1612 	CPT_AF_ERR_ACCESS_DENIED	= -904,
1613 	CPT_AF_ERR_SSO_PF_FUNC_INVALID	= -905,
1614 	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906,
1615 	CPT_AF_ERR_INLINE_IPSEC_INB_ENA	= -907,
1616 	CPT_AF_ERR_INLINE_IPSEC_OUT_ENA	= -908
1617 };
1618 
1619 /* CPT mbox message formats */
1620 struct cpt_rd_wr_reg_msg {
1621 	struct mbox_msghdr hdr;
1622 	u64 reg_offset;
1623 	u64 *ret_val;
1624 	u64 val;
1625 	u8 is_write;
1626 	int blkaddr;
1627 };
1628 
1629 struct cpt_lf_alloc_req_msg {
1630 	struct mbox_msghdr hdr;
1631 	u16 nix_pf_func;
1632 	u16 sso_pf_func;
1633 	u16 eng_grpmsk;
1634 	int blkaddr;
1635 	u8 ctx_ilen_valid : 1;
1636 	u8 ctx_ilen : 7;
1637 };
1638 
1639 #define CPT_INLINE_INBOUND      0
1640 #define CPT_INLINE_OUTBOUND     1
1641 
1642 /* Mailbox message request format for CPT IPsec
1643  * inline inbound and outbound configuration.
1644  */
1645 struct cpt_inline_ipsec_cfg_msg {
1646 	struct mbox_msghdr hdr;
1647 	u8 enable;
1648 	u8 slot;
1649 	u8 dir;
1650 	u8 sso_pf_func_ovrd;
1651 	u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1652 	u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1653 };
1654 
1655 /* Mailbox message request and response format for CPT stats. */
1656 struct cpt_sts_req {
1657 	struct mbox_msghdr hdr;
1658 	u8 blkaddr;
1659 };
1660 
1661 struct cpt_sts_rsp {
1662 	struct mbox_msghdr hdr;
1663 	u64 inst_req_pc;
1664 	u64 inst_lat_pc;
1665 	u64 rd_req_pc;
1666 	u64 rd_lat_pc;
1667 	u64 rd_uc_pc;
1668 	u64 active_cycles_pc;
1669 	u64 ctx_mis_pc;
1670 	u64 ctx_hit_pc;
1671 	u64 ctx_aop_pc;
1672 	u64 ctx_aop_lat_pc;
1673 	u64 ctx_ifetch_pc;
1674 	u64 ctx_ifetch_lat_pc;
1675 	u64 ctx_ffetch_pc;
1676 	u64 ctx_ffetch_lat_pc;
1677 	u64 ctx_wback_pc;
1678 	u64 ctx_wback_lat_pc;
1679 	u64 ctx_psh_pc;
1680 	u64 ctx_psh_lat_pc;
1681 	u64 ctx_err;
1682 	u64 ctx_enc_id;
1683 	u64 ctx_flush_timer;
1684 	u64 rxc_time;
1685 	u64 rxc_time_cfg;
1686 	u64 rxc_active_sts;
1687 	u64 rxc_zombie_sts;
1688 	u64 busy_sts_ae;
1689 	u64 free_sts_ae;
1690 	u64 busy_sts_se;
1691 	u64 free_sts_se;
1692 	u64 busy_sts_ie;
1693 	u64 free_sts_ie;
1694 	u64 exe_err_info;
1695 	u64 cptclk_cnt;
1696 	u64 diag;
1697 	u64 rxc_dfrg;
1698 	u64 x2p_link_cfg0;
1699 	u64 x2p_link_cfg1;
1700 };
1701 
1702 /* Mailbox message request format to configure reassembly timeout. */
1703 struct cpt_rxc_time_cfg_req {
1704 	struct mbox_msghdr hdr;
1705 	int blkaddr;
1706 	u32 step;
1707 	u16 zombie_thres;
1708 	u16 zombie_limit;
1709 	u16 active_thres;
1710 	u16 active_limit;
1711 };
1712 
1713 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1714 struct cpt_inst_lmtst_req {
1715 	struct mbox_msghdr hdr;
1716 	u64 inst[8];
1717 	u64 rsvd;
1718 };
1719 
1720 /* Mailbox message format to request for CPT LF reset */
1721 struct cpt_lf_rst_req {
1722 	struct mbox_msghdr hdr;
1723 	u32 slot;
1724 	u32 rsvd;
1725 };
1726 
1727 /* Mailbox message format to request for CPT faulted engines */
1728 struct cpt_flt_eng_info_req {
1729 	struct mbox_msghdr hdr;
1730 	int blkaddr;
1731 	bool reset;
1732 	u32 rsvd;
1733 };
1734 
1735 struct cpt_flt_eng_info_rsp {
1736 	struct mbox_msghdr hdr;
1737 	u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU];
1738 	u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU];
1739 	u64 rsvd;
1740 };
1741 
1742 struct sdp_node_info {
1743 	/* Node to which this PF belons to */
1744 	u8 node_id;
1745 	u8 max_vfs;
1746 	u8 num_pf_rings;
1747 	u8 pf_srn;
1748 #define SDP_MAX_VFS	128
1749 	u8 vf_rings[SDP_MAX_VFS];
1750 };
1751 
1752 struct sdp_chan_info_msg {
1753 	struct mbox_msghdr hdr;
1754 	struct sdp_node_info info;
1755 };
1756 
1757 struct sdp_get_chan_info_msg {
1758 	struct mbox_msghdr hdr;
1759 	u16 chan_base;
1760 	u16 num_chan;
1761 };
1762 
1763 /* CGX mailbox error codes
1764  * Range 1101 - 1200.
1765  */
1766 enum cgx_af_status {
1767 	LMAC_AF_ERR_INVALID_PARAM	= -1101,
1768 	LMAC_AF_ERR_PF_NOT_MAPPED	= -1102,
1769 	LMAC_AF_ERR_PERM_DENIED		= -1103,
1770 	LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,
1771 	LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1772 	LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1773 	LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1774 	LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1775 	LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1776 	LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1777 };
1778 
1779 enum mcs_direction {
1780 	MCS_RX,
1781 	MCS_TX,
1782 };
1783 
1784 enum mcs_rsrc_type {
1785 	MCS_RSRC_TYPE_FLOWID,
1786 	MCS_RSRC_TYPE_SECY,
1787 	MCS_RSRC_TYPE_SC,
1788 	MCS_RSRC_TYPE_SA,
1789 };
1790 
1791 struct mcs_alloc_rsrc_req {
1792 	struct mbox_msghdr hdr;
1793 	u8 rsrc_type;
1794 	u8 rsrc_cnt;	/* Resources count */
1795 	u8 mcs_id;	/* MCS block ID	*/
1796 	u8 dir;		/* Macsec ingress or egress side */
1797 	u8 all;		/* Allocate all resource type one each */
1798 	u64 rsvd;
1799 };
1800 
1801 struct mcs_alloc_rsrc_rsp {
1802 	struct mbox_msghdr hdr;
1803 	u8 flow_ids[128];	/* Index of reserved entries */
1804 	u8 secy_ids[128];
1805 	u8 sc_ids[128];
1806 	u8 sa_ids[256];
1807 	u8 rsrc_type;
1808 	u8 rsrc_cnt;		/* No of entries reserved */
1809 	u8 mcs_id;
1810 	u8 dir;
1811 	u8 all;
1812 	u8 rsvd[256];		/* reserved fields for future expansion */
1813 };
1814 
1815 struct mcs_free_rsrc_req {
1816 	struct mbox_msghdr hdr;
1817 	u8 rsrc_id;		/* Index of the entry to be freed */
1818 	u8 rsrc_type;
1819 	u8 mcs_id;
1820 	u8 dir;
1821 	u8 all;			/* Free all the cam resources */
1822 	u64 rsvd;
1823 };
1824 
1825 struct mcs_flowid_entry_write_req {
1826 	struct mbox_msghdr hdr;
1827 	u64 data[4];
1828 	u64 mask[4];
1829 	u64 sci;	/* CNF10K-B for tx_secy_mem_map */
1830 	u8 flow_id;
1831 	u8 secy_id;	/* secyid for which flowid is mapped */
1832 	u8 sc_id;	/* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1833 	u8 ena;		/* Enable tcam entry */
1834 	u8 ctrl_pkt;
1835 	u8 mcs_id;
1836 	u8 dir;
1837 	u64 rsvd;
1838 };
1839 
1840 struct mcs_secy_plcy_write_req {
1841 	struct mbox_msghdr hdr;
1842 	u64 plcy;
1843 	u8 secy_id;
1844 	u8 mcs_id;
1845 	u8 dir;
1846 	u64 rsvd;
1847 };
1848 
1849 /* RX SC_CAM mapping */
1850 struct mcs_rx_sc_cam_write_req {
1851 	struct mbox_msghdr hdr;
1852 	u64 sci;	/* SCI */
1853 	u64 secy_id;	/* secy index mapped to SC */
1854 	u8 sc_id;	/* SC CAM entry index */
1855 	u8 mcs_id;
1856 	u64 rsvd;
1857 };
1858 
1859 struct mcs_sa_plcy_write_req {
1860 	struct mbox_msghdr hdr;
1861 	u64 plcy[2][9];		/* Support 2 SA policy */
1862 	u8 sa_index[2];
1863 	u8 sa_cnt;
1864 	u8 mcs_id;
1865 	u8 dir;
1866 	u64 rsvd;
1867 };
1868 
1869 struct mcs_tx_sc_sa_map {
1870 	struct mbox_msghdr hdr;
1871 	u8 sa_index0;
1872 	u8 sa_index1;
1873 	u8 rekey_ena;
1874 	u8 sa_index0_vld;
1875 	u8 sa_index1_vld;
1876 	u8 tx_sa_active;
1877 	u64 sectag_sci;
1878 	u8 sc_id;	/* used as index for SA_MEM_MAP */
1879 	u8 mcs_id;
1880 	u64 rsvd;
1881 };
1882 
1883 struct mcs_rx_sc_sa_map {
1884 	struct mbox_msghdr hdr;
1885 	u8 sa_index;
1886 	u8 sa_in_use;
1887 	u8 sc_id;
1888 	u8 an;		/* value range 0-3, sc_id + an used as index SA_MEM_MAP */
1889 	u8 mcs_id;
1890 	u64 rsvd;
1891 };
1892 
1893 struct mcs_flowid_ena_dis_entry {
1894 	struct mbox_msghdr hdr;
1895 	u8 flow_id;
1896 	u8 ena;
1897 	u8 mcs_id;
1898 	u8 dir;
1899 	u64 rsvd;
1900 };
1901 
1902 struct mcs_pn_table_write_req {
1903 	struct mbox_msghdr hdr;
1904 	u64 next_pn;
1905 	u8 pn_id;
1906 	u8 mcs_id;
1907 	u8 dir;
1908 	u64 rsvd;
1909 };
1910 
1911 struct mcs_hw_info {
1912 	struct mbox_msghdr hdr;
1913 	u8 num_mcs_blks;	/* Number of MCS blocks */
1914 	u8 tcam_entries;	/* RX/TX Tcam entries per mcs block */
1915 	u8 secy_entries;	/* RX/TX SECY entries per mcs block */
1916 	u8 sc_entries;		/* RX/TX SC CAM entries per mcs block */
1917 	u8 sa_entries;		/* PN table entries = SA entries */
1918 	u64 rsvd[16];
1919 };
1920 
1921 struct mcs_set_active_lmac {
1922 	struct mbox_msghdr hdr;
1923 	u32 lmac_bmap;	/* bitmap of active lmac per mcs block */
1924 	u8 mcs_id;
1925 	u16 chan_base; /* MCS channel base */
1926 	u64 rsvd;
1927 };
1928 
1929 struct mcs_set_lmac_mode {
1930 	struct mbox_msghdr hdr;
1931 	u8 mode;	/* 1:Bypass 0:Operational */
1932 	u8 lmac_id;
1933 	u8 mcs_id;
1934 	u64 rsvd;
1935 };
1936 
1937 struct mcs_port_reset_req {
1938 	struct mbox_msghdr hdr;
1939 	u8 reset;
1940 	u8 mcs_id;
1941 	u8 port_id;
1942 	u64 rsvd;
1943 };
1944 
1945 struct mcs_port_cfg_set_req {
1946 	struct mbox_msghdr hdr;
1947 	u8 cstm_tag_rel_mode_sel;
1948 	u8 custom_hdr_enb;
1949 	u8 fifo_skid;
1950 	u8 port_mode;
1951 	u8 port_id;
1952 	u8 mcs_id;
1953 	u64 rsvd;
1954 };
1955 
1956 struct mcs_port_cfg_get_req {
1957 	struct mbox_msghdr hdr;
1958 	u8 port_id;
1959 	u8 mcs_id;
1960 	u64 rsvd;
1961 };
1962 
1963 struct mcs_port_cfg_get_rsp {
1964 	struct mbox_msghdr hdr;
1965 	u8 cstm_tag_rel_mode_sel;
1966 	u8 custom_hdr_enb;
1967 	u8 fifo_skid;
1968 	u8 port_mode;
1969 	u8 port_id;
1970 	u8 mcs_id;
1971 	u64 rsvd;
1972 };
1973 
1974 struct mcs_custom_tag_cfg_get_req {
1975 	struct mbox_msghdr hdr;
1976 	u8 mcs_id;
1977 	u8 dir;
1978 	u64 rsvd;
1979 };
1980 
1981 struct mcs_custom_tag_cfg_get_rsp {
1982 	struct mbox_msghdr hdr;
1983 	u16 cstm_etype[8];
1984 	u8 cstm_indx[8];
1985 	u8 cstm_etype_en;
1986 	u8 mcs_id;
1987 	u8 dir;
1988 	u64 rsvd;
1989 };
1990 
1991 /* MCS mailbox error codes
1992  * Range 1201 - 1300.
1993  */
1994 enum mcs_af_status {
1995 	MCS_AF_ERR_INVALID_MCSID        = -1201,
1996 	MCS_AF_ERR_NOT_MAPPED           = -1202,
1997 };
1998 
1999 struct mcs_set_pn_threshold {
2000 	struct mbox_msghdr hdr;
2001 	u64 threshold;
2002 	u8 xpn; /* '1' for setting xpn threshold */
2003 	u8 mcs_id;
2004 	u8 dir;
2005 	u64 rsvd;
2006 };
2007 
2008 enum mcs_ctrl_pkt_rulew_type {
2009 	MCS_CTRL_PKT_RULE_TYPE_ETH,
2010 	MCS_CTRL_PKT_RULE_TYPE_DA,
2011 	MCS_CTRL_PKT_RULE_TYPE_RANGE,
2012 	MCS_CTRL_PKT_RULE_TYPE_COMBO,
2013 	MCS_CTRL_PKT_RULE_TYPE_MAC,
2014 };
2015 
2016 struct mcs_alloc_ctrl_pkt_rule_req {
2017 	struct mbox_msghdr hdr;
2018 	u8 rule_type;
2019 	u8 mcs_id;	/* MCS block ID	*/
2020 	u8 dir;		/* Macsec ingress or egress side */
2021 	u64 rsvd;
2022 };
2023 
2024 struct mcs_alloc_ctrl_pkt_rule_rsp {
2025 	struct mbox_msghdr hdr;
2026 	u8 rule_idx;
2027 	u8 rule_type;
2028 	u8 mcs_id;
2029 	u8 dir;
2030 	u64 rsvd;
2031 };
2032 
2033 struct mcs_free_ctrl_pkt_rule_req {
2034 	struct mbox_msghdr hdr;
2035 	u8 rule_idx;
2036 	u8 rule_type;
2037 	u8 mcs_id;
2038 	u8 dir;
2039 	u8 all;
2040 	u64 rsvd;
2041 };
2042 
2043 struct mcs_ctrl_pkt_rule_write_req {
2044 	struct mbox_msghdr hdr;
2045 	u64 data0;
2046 	u64 data1;
2047 	u64 data2;
2048 	u8 rule_idx;
2049 	u8 rule_type;
2050 	u8 mcs_id;
2051 	u8 dir;
2052 	u64 rsvd;
2053 };
2054 
2055 struct mcs_stats_req {
2056 	struct mbox_msghdr hdr;
2057 	u8 id;
2058 	u8 mcs_id;
2059 	u8 dir;
2060 	u64 rsvd;
2061 };
2062 
2063 struct mcs_flowid_stats {
2064 	struct mbox_msghdr hdr;
2065 	u64 tcam_hit_cnt;
2066 	u64 rsvd;
2067 };
2068 
2069 struct mcs_secy_stats {
2070 	struct mbox_msghdr hdr;
2071 	u64 ctl_pkt_bcast_cnt;
2072 	u64 ctl_pkt_mcast_cnt;
2073 	u64 ctl_pkt_ucast_cnt;
2074 	u64 ctl_octet_cnt;
2075 	u64 unctl_pkt_bcast_cnt;
2076 	u64 unctl_pkt_mcast_cnt;
2077 	u64 unctl_pkt_ucast_cnt;
2078 	u64 unctl_octet_cnt;
2079 	/* Valid only for RX */
2080 	u64 octet_decrypted_cnt;
2081 	u64 octet_validated_cnt;
2082 	u64 pkt_port_disabled_cnt;
2083 	u64 pkt_badtag_cnt;
2084 	u64 pkt_nosa_cnt;
2085 	u64 pkt_nosaerror_cnt;
2086 	u64 pkt_tagged_ctl_cnt;
2087 	u64 pkt_untaged_cnt;
2088 	u64 pkt_ctl_cnt;	/* CN10K-B */
2089 	u64 pkt_notag_cnt;	/* CNF10K-B */
2090 	/* Valid only for TX */
2091 	u64 octet_encrypted_cnt;
2092 	u64 octet_protected_cnt;
2093 	u64 pkt_noactivesa_cnt;
2094 	u64 pkt_toolong_cnt;
2095 	u64 pkt_untagged_cnt;
2096 	u64 rsvd[4];
2097 };
2098 
2099 struct mcs_port_stats {
2100 	struct mbox_msghdr hdr;
2101 	u64 tcam_miss_cnt;
2102 	u64 parser_err_cnt;
2103 	u64 preempt_err_cnt;  /* CNF10K-B */
2104 	u64 sectag_insert_err_cnt;
2105 	u64 rsvd[4];
2106 };
2107 
2108 /* Only for CN10K-B */
2109 struct mcs_sa_stats {
2110 	struct mbox_msghdr hdr;
2111 	/* RX */
2112 	u64 pkt_invalid_cnt;
2113 	u64 pkt_nosaerror_cnt;
2114 	u64 pkt_notvalid_cnt;
2115 	u64 pkt_ok_cnt;
2116 	u64 pkt_nosa_cnt;
2117 	/* TX */
2118 	u64 pkt_encrypt_cnt;
2119 	u64 pkt_protected_cnt;
2120 	u64 rsvd[4];
2121 };
2122 
2123 struct mcs_sc_stats {
2124 	struct mbox_msghdr hdr;
2125 	/* RX */
2126 	u64 hit_cnt;
2127 	u64 pkt_invalid_cnt;
2128 	u64 pkt_late_cnt;
2129 	u64 pkt_notvalid_cnt;
2130 	u64 pkt_unchecked_cnt;
2131 	u64 pkt_delay_cnt;	/* CNF10K-B */
2132 	u64 pkt_ok_cnt;		/* CNF10K-B */
2133 	u64 octet_decrypt_cnt;	/* CN10K-B */
2134 	u64 octet_validate_cnt;	/* CN10K-B */
2135 	/* TX */
2136 	u64 pkt_encrypt_cnt;
2137 	u64 pkt_protected_cnt;
2138 	u64 octet_encrypt_cnt;		/* CN10K-B */
2139 	u64 octet_protected_cnt;	/* CN10K-B */
2140 	u64 rsvd[4];
2141 };
2142 
2143 struct mcs_clear_stats {
2144 	struct mbox_msghdr hdr;
2145 #define MCS_FLOWID_STATS	0
2146 #define MCS_SECY_STATS		1
2147 #define MCS_SC_STATS		2
2148 #define MCS_SA_STATS		3
2149 #define MCS_PORT_STATS		4
2150 	u8 type;	/* FLOWID, SECY, SC, SA, PORT */
2151 	u8 id;		/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2152 	u8 mcs_id;
2153 	u8 dir;
2154 	u8 all;		/* All resources stats mapped to PF are cleared */
2155 };
2156 
2157 struct mcs_intr_cfg {
2158 	struct mbox_msghdr hdr;
2159 #define MCS_CPM_RX_SECTAG_V_EQ1_INT		BIT_ULL(0)
2160 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT	BIT_ULL(1)
2161 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT		BIT_ULL(2)
2162 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT	BIT_ULL(3)
2163 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT	BIT_ULL(4)
2164 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT		BIT_ULL(5)
2165 #define MCS_CPM_RX_PN_THRESH_REACHED_INT	BIT_ULL(6)
2166 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT		BIT_ULL(7)
2167 #define MCS_CPM_TX_PN_THRESH_REACHED_INT	BIT_ULL(8)
2168 #define MCS_CPM_TX_SA_NOT_VALID_INT		BIT_ULL(9)
2169 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT		BIT_ULL(10)
2170 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT		BIT_ULL(11)
2171 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT		BIT_ULL(12)
2172 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT		BIT_ULL(13)
2173 #define MCS_PAB_RX_CHAN_OVERFLOW_INT		BIT_ULL(14)
2174 #define MCS_PAB_TX_CHAN_OVERFLOW_INT		BIT_ULL(15)
2175 	u64 intr_mask;		/* Interrupt enable mask */
2176 	u8 mcs_id;
2177 	u8 lmac_id;
2178 	u64 rsvd;
2179 };
2180 
2181 struct mcs_intr_info {
2182 	struct mbox_msghdr hdr;
2183 	u64 intr_mask;
2184 	int sa_id;
2185 	u8 mcs_id;
2186 	u8 lmac_id;
2187 	u64 rsvd;
2188 };
2189 
2190 #endif /* MBOX_H */
2191