1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 101 struct pci_dev *pdev, void __force *reg_base, 102 int direction, int ndevs, unsigned long *bmap); 103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 107 int size, int size_rsp); 108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 109 struct mbox_msghdr *msg); 110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 112 u16 pcifunc, u16 id); 113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 114 const char *otx2_mbox_id2name(u16 id); 115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 116 int devid, int size) 117 { 118 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 119 } 120 121 /* Mailbox message types */ 122 #define MBOX_MSG_MASK 0xFFFF 123 #define MBOX_MSG_INVALID 0xFFFE 124 #define MBOX_MSG_MAX 0xFFFF 125 126 #define MBOX_MESSAGES \ 127 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 128 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 129 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 130 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 131 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 132 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 133 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 134 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 135 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 136 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 137 msg_rsp) \ 138 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 139 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 140 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 141 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 142 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 143 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 144 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 147 cgx_mac_addr_set_or_get) \ 148 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 149 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 150 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 151 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 152 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 153 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 154 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 155 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 156 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 157 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 158 cgx_pause_frm_cfg) \ 159 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 160 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 161 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 162 cgx_mac_addr_add_rsp) \ 163 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 164 msg_rsp) \ 165 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 166 cgx_max_dmac_entries_get_rsp) \ 167 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 168 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 169 cgx_set_link_mode_rsp) \ 170 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 171 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 172 cgx_features_info_msg) \ 173 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 174 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 175 msg_rsp) \ 176 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 177 cgx_mac_addr_update_rsp) \ 178 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 179 cgx_pfc_rsp) \ 180 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 181 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 182 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 183 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 184 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 185 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 186 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 187 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 190 msg_rsp) \ 191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 193 cpt_rd_wr_reg_msg) \ 194 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 195 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 196 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 197 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 198 msg_rsp) \ 199 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 200 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 201 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 202 cpt_flt_eng_info_rsp) \ 203 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 204 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 205 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 206 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 207 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 208 npc_mcam_alloc_entry_rsp) \ 209 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 210 npc_mcam_free_entry_req, msg_rsp) \ 211 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 212 npc_mcam_write_entry_req, msg_rsp) \ 213 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 214 npc_mcam_ena_dis_entry_req, msg_rsp) \ 215 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 216 npc_mcam_ena_dis_entry_req, msg_rsp) \ 217 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 218 npc_mcam_shift_entry_rsp) \ 219 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 220 npc_mcam_alloc_counter_req, \ 221 npc_mcam_alloc_counter_rsp) \ 222 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 223 npc_mcam_oper_counter_req, msg_rsp) \ 224 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 225 npc_mcam_unmap_counter_req, msg_rsp) \ 226 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 227 npc_mcam_oper_counter_req, msg_rsp) \ 228 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 229 npc_mcam_oper_counter_req, \ 230 npc_mcam_oper_counter_rsp) \ 231 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 232 npc_mcam_alloc_and_write_entry_req, \ 233 npc_mcam_alloc_and_write_entry_rsp) \ 234 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 235 msg_req, npc_get_kex_cfg_rsp) \ 236 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 237 npc_install_flow_req, npc_install_flow_rsp) \ 238 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 239 npc_delete_flow_req, npc_delete_flow_rsp) \ 240 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 241 npc_mcam_read_entry_req, \ 242 npc_mcam_read_entry_rsp) \ 243 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 244 npc_set_pkind, msg_rsp) \ 245 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 246 msg_req, npc_mcam_read_base_rule_rsp) \ 247 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 248 npc_mcam_get_stats_req, \ 249 npc_mcam_get_stats_rsp) \ 250 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 251 npc_get_field_hash_info_req, \ 252 npc_get_field_hash_info_rsp) \ 253 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 254 npc_get_field_status_req, \ 255 npc_get_field_status_rsp) \ 256 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 257 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 258 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 259 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 260 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 261 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 262 hwctx_disable_req, msg_rsp) \ 263 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 264 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 265 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 266 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 267 nix_txschq_config) \ 268 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 269 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 270 nix_vtag_config_rsp) \ 271 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 272 nix_rss_flowkey_cfg, \ 273 nix_rss_flowkey_cfg_rsp) \ 274 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 275 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 276 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 277 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 278 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 279 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 280 nix_mark_format_cfg, \ 281 nix_mark_format_cfg_rsp) \ 282 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 283 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 284 nix_lso_format_cfg, \ 285 nix_lso_format_cfg_rsp) \ 286 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 287 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 288 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 289 nix_bp_cfg_rsp) \ 290 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 291 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 292 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 293 nix_inline_ipsec_cfg, msg_rsp) \ 294 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 295 nix_inline_ipsec_lf_cfg, msg_rsp) \ 296 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 297 nix_cn10k_aq_enq_rsp) \ 298 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 299 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 300 nix_bandprof_alloc_rsp) \ 301 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 302 msg_rsp) \ 303 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 304 nix_bandprof_get_hwinfo_rsp) \ 305 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 306 msg_req, nix_inline_ipsec_cfg) \ 307 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 308 nix_mcast_grp_create_rsp) \ 309 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 310 msg_rsp) \ 311 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 312 nix_mcast_grp_update_req, \ 313 nix_mcast_grp_update_rsp) \ 314 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 315 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 316 mcs_alloc_rsrc_rsp) \ 317 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 318 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 319 msg_rsp) \ 320 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 321 msg_rsp) \ 322 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 323 msg_rsp) \ 324 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 325 msg_rsp) \ 326 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 327 msg_rsp) \ 328 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 329 msg_rsp) \ 330 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 331 msg_rsp) \ 332 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 333 msg_rsp) \ 334 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 335 msg_rsp) \ 336 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 337 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 338 mcs_flowid_stats) \ 339 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 340 mcs_secy_stats) \ 341 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 342 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 343 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 344 mcs_port_stats) \ 345 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 346 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 347 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 348 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 349 msg_rsp) \ 350 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 351 mcs_alloc_ctrl_pkt_rule_req, \ 352 mcs_alloc_ctrl_pkt_rule_rsp) \ 353 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 354 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 355 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 356 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 357 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 358 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 359 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 360 mcs_port_cfg_get_rsp) \ 361 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 362 mcs_custom_tag_cfg_get_req, \ 363 mcs_custom_tag_cfg_get_rsp) 364 365 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 366 #define MBOX_UP_CGX_MESSAGES \ 367 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 368 369 #define MBOX_UP_CPT_MESSAGES \ 370 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 371 372 #define MBOX_UP_MCS_MESSAGES \ 373 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 374 375 enum { 376 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 377 MBOX_MESSAGES 378 MBOX_UP_CGX_MESSAGES 379 MBOX_UP_CPT_MESSAGES 380 MBOX_UP_MCS_MESSAGES 381 #undef M 382 }; 383 384 /* Mailbox message formats */ 385 386 #define RVU_DEFAULT_PF_FUNC 0xFFFF 387 388 /* Generic request msg used for those mbox messages which 389 * don't send any data in the request. 390 */ 391 struct msg_req { 392 struct mbox_msghdr hdr; 393 }; 394 395 /* Generic response msg used an ack or response for those mbox 396 * messages which don't have a specific rsp msg format. 397 */ 398 struct msg_rsp { 399 struct mbox_msghdr hdr; 400 }; 401 402 /* RVU mailbox error codes 403 * Range 256 - 300. 404 */ 405 enum rvu_af_status { 406 RVU_INVALID_VF_ID = -256, 407 }; 408 409 struct ready_msg_rsp { 410 struct mbox_msghdr hdr; 411 u16 sclk_freq; /* SCLK frequency (in MHz) */ 412 u16 rclk_freq; /* RCLK frequency (in MHz) */ 413 }; 414 415 /* Structure for requesting resource provisioning. 416 * 'modify' flag to be used when either requesting more 417 * or to detach partial of a certain resource type. 418 * Rest of the fields specify how many of what type to 419 * be attached. 420 * To request LFs from two blocks of same type this mailbox 421 * can be sent twice as below: 422 * struct rsrc_attach *attach; 423 * .. Allocate memory for message .. 424 * attach->cptlfs = 3; <3 LFs from CPT0> 425 * .. Send message .. 426 * .. Allocate memory for message .. 427 * attach->modify = 1; 428 * attach->cpt_blkaddr = BLKADDR_CPT1; 429 * attach->cptlfs = 2; <2 LFs from CPT1> 430 * .. Send message .. 431 */ 432 struct rsrc_attach { 433 struct mbox_msghdr hdr; 434 u8 modify:1; 435 u8 npalf:1; 436 u8 nixlf:1; 437 u16 sso; 438 u16 ssow; 439 u16 timlfs; 440 u16 cptlfs; 441 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 442 }; 443 444 /* Structure for relinquishing resources. 445 * 'partial' flag to be used when relinquishing all resources 446 * but only of a certain type. If not set, all resources of all 447 * types provisioned to the RVU function will be detached. 448 */ 449 struct rsrc_detach { 450 struct mbox_msghdr hdr; 451 u8 partial:1; 452 u8 npalf:1; 453 u8 nixlf:1; 454 u8 sso:1; 455 u8 ssow:1; 456 u8 timlfs:1; 457 u8 cptlfs:1; 458 }; 459 460 /* Number of resources available to the caller. 461 * In reply to MBOX_MSG_FREE_RSRC_CNT. 462 */ 463 struct free_rsrcs_rsp { 464 struct mbox_msghdr hdr; 465 u16 schq[NIX_TXSCH_LVL_CNT]; 466 u16 sso; 467 u16 tim; 468 u16 ssow; 469 u16 cpt; 470 u8 npa; 471 u8 nix; 472 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 473 u8 nix1; 474 u8 cpt1; 475 u8 ree0; 476 u8 ree1; 477 }; 478 479 #define MSIX_VECTOR_INVALID 0xFFFF 480 #define MAX_RVU_BLKLF_CNT 256 481 482 struct msix_offset_rsp { 483 struct mbox_msghdr hdr; 484 u16 npa_msixoff; 485 u16 nix_msixoff; 486 u16 sso; 487 u16 ssow; 488 u16 timlfs; 489 u16 cptlfs; 490 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 491 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 492 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 493 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 494 u16 cpt1_lfs; 495 u16 ree0_lfs; 496 u16 ree1_lfs; 497 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 498 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 499 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 500 }; 501 502 struct get_hw_cap_rsp { 503 struct mbox_msghdr hdr; 504 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 505 u8 nix_shaping; /* Is shaping and coloring supported */ 506 u8 npc_hash_extract; /* Is hash extract supported */ 507 }; 508 509 /* CGX mbox message formats */ 510 511 struct cgx_stats_rsp { 512 struct mbox_msghdr hdr; 513 #define CGX_RX_STATS_COUNT 9 514 #define CGX_TX_STATS_COUNT 18 515 u64 rx_stats[CGX_RX_STATS_COUNT]; 516 u64 tx_stats[CGX_TX_STATS_COUNT]; 517 }; 518 519 struct cgx_fec_stats_rsp { 520 struct mbox_msghdr hdr; 521 u64 fec_corr_blks; 522 u64 fec_uncorr_blks; 523 }; 524 /* Structure for requesting the operation for 525 * setting/getting mac address in the CGX interface 526 */ 527 struct cgx_mac_addr_set_or_get { 528 struct mbox_msghdr hdr; 529 u8 mac_addr[ETH_ALEN]; 530 u32 index; 531 }; 532 533 /* Structure for requesting the operation to 534 * add DMAC filter entry into CGX interface 535 */ 536 struct cgx_mac_addr_add_req { 537 struct mbox_msghdr hdr; 538 u8 mac_addr[ETH_ALEN]; 539 }; 540 541 /* Structure for response against the operation to 542 * add DMAC filter entry into CGX interface 543 */ 544 struct cgx_mac_addr_add_rsp { 545 struct mbox_msghdr hdr; 546 u32 index; 547 }; 548 549 /* Structure for requesting the operation to 550 * delete DMAC filter entry from CGX interface 551 */ 552 struct cgx_mac_addr_del_req { 553 struct mbox_msghdr hdr; 554 u32 index; 555 }; 556 557 /* Structure for response against the operation to 558 * get maximum supported DMAC filter entries 559 */ 560 struct cgx_max_dmac_entries_get_rsp { 561 struct mbox_msghdr hdr; 562 u32 max_dmac_filters; 563 }; 564 565 struct cgx_link_user_info { 566 uint64_t link_up:1; 567 uint64_t full_duplex:1; 568 uint64_t lmac_type_id:4; 569 uint64_t speed:20; /* speed in Mbps */ 570 uint64_t an:1; /* AN supported or not */ 571 uint64_t fec:2; /* FEC type if enabled else 0 */ 572 #define LMACTYPE_STR_LEN 16 573 char lmac_type[LMACTYPE_STR_LEN]; 574 }; 575 576 struct cgx_link_info_msg { 577 struct mbox_msghdr hdr; 578 struct cgx_link_user_info link_info; 579 }; 580 581 struct cgx_pause_frm_cfg { 582 struct mbox_msghdr hdr; 583 u8 set; 584 /* set = 1 if the request is to config pause frames */ 585 /* set = 0 if the request is to fetch pause frames config */ 586 u8 rx_pause; 587 u8 tx_pause; 588 }; 589 590 enum fec_type { 591 OTX2_FEC_NONE, 592 OTX2_FEC_BASER, 593 OTX2_FEC_RS, 594 OTX2_FEC_STATS_CNT = 2, 595 OTX2_FEC_OFF, 596 }; 597 598 struct fec_mode { 599 struct mbox_msghdr hdr; 600 int fec; 601 }; 602 603 struct sfp_eeprom_s { 604 #define SFP_EEPROM_SIZE 256 605 u16 sff_id; 606 u8 buf[SFP_EEPROM_SIZE]; 607 u64 reserved; 608 }; 609 610 struct phy_s { 611 struct { 612 u64 can_change_mod_type:1; 613 u64 mod_type:1; 614 u64 has_fec_stats:1; 615 } misc; 616 struct fec_stats_s { 617 u32 rsfec_corr_cws; 618 u32 rsfec_uncorr_cws; 619 u32 brfec_corr_blks; 620 u32 brfec_uncorr_blks; 621 } fec_stats; 622 }; 623 624 struct cgx_lmac_fwdata_s { 625 u16 rw_valid; 626 u64 supported_fec; 627 u64 supported_an; 628 u64 supported_link_modes; 629 /* only applicable if AN is supported */ 630 u64 advertised_fec; 631 u64 advertised_link_modes; 632 /* Only applicable if SFP/QSFP slot is present */ 633 struct sfp_eeprom_s sfp_eeprom; 634 struct phy_s phy; 635 #define LMAC_FWDATA_RESERVED_MEM 1021 636 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 637 }; 638 639 struct cgx_fw_data { 640 struct mbox_msghdr hdr; 641 struct cgx_lmac_fwdata_s fwdata; 642 }; 643 644 struct cgx_set_link_mode_args { 645 u32 speed; 646 u8 duplex; 647 u8 an; 648 u8 ports; 649 u64 mode; 650 }; 651 652 struct cgx_set_link_mode_req { 653 #define AUTONEG_UNKNOWN 0xff 654 struct mbox_msghdr hdr; 655 struct cgx_set_link_mode_args args; 656 }; 657 658 struct cgx_set_link_mode_rsp { 659 struct mbox_msghdr hdr; 660 int status; 661 }; 662 663 struct cgx_mac_addr_reset_req { 664 struct mbox_msghdr hdr; 665 u32 index; 666 }; 667 668 struct cgx_mac_addr_update_req { 669 struct mbox_msghdr hdr; 670 u8 mac_addr[ETH_ALEN]; 671 u32 index; 672 }; 673 674 struct cgx_mac_addr_update_rsp { 675 struct mbox_msghdr hdr; 676 u32 index; 677 }; 678 679 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 680 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 681 /* flow control from physical link higig2 messages */ 682 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 683 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 684 #define RVU_MAC_VERSION BIT_ULL(4) 685 #define RVU_MAC_CGX BIT_ULL(5) 686 #define RVU_MAC_RPM BIT_ULL(6) 687 688 struct cgx_features_info_msg { 689 struct mbox_msghdr hdr; 690 u64 lmac_features; 691 }; 692 693 struct rpm_stats_rsp { 694 struct mbox_msghdr hdr; 695 #define RPM_RX_STATS_COUNT 43 696 #define RPM_TX_STATS_COUNT 34 697 u64 rx_stats[RPM_RX_STATS_COUNT]; 698 u64 tx_stats[RPM_TX_STATS_COUNT]; 699 }; 700 701 struct cgx_pfc_cfg { 702 struct mbox_msghdr hdr; 703 u8 rx_pause; 704 u8 tx_pause; 705 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 706 }; 707 708 struct cgx_pfc_rsp { 709 struct mbox_msghdr hdr; 710 u8 rx_pause; 711 u8 tx_pause; 712 }; 713 714 /* NPA mbox message formats */ 715 716 struct npc_set_pkind { 717 struct mbox_msghdr hdr; 718 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 719 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 720 u64 mode; 721 #define PKIND_TX BIT_ULL(0) 722 #define PKIND_RX BIT_ULL(1) 723 u8 dir; 724 u8 pkind; /* valid only in case custom flag */ 725 u8 var_len_off; /* Offset of custom header length field. 726 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 727 */ 728 u8 var_len_off_mask; /* Mask for length with in offset */ 729 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 730 }; 731 732 /* NPA mbox message formats */ 733 734 /* NPA mailbox error codes 735 * Range 301 - 400. 736 */ 737 enum npa_af_status { 738 NPA_AF_ERR_PARAM = -301, 739 NPA_AF_ERR_AQ_FULL = -302, 740 NPA_AF_ERR_AQ_ENQUEUE = -303, 741 NPA_AF_ERR_AF_LF_INVALID = -304, 742 NPA_AF_ERR_AF_LF_ALLOC = -305, 743 NPA_AF_ERR_LF_RESET = -306, 744 }; 745 746 /* For NPA LF context alloc and init */ 747 struct npa_lf_alloc_req { 748 struct mbox_msghdr hdr; 749 int node; 750 int aura_sz; /* No of auras */ 751 u32 nr_pools; /* No of pools */ 752 u64 way_mask; 753 }; 754 755 struct npa_lf_alloc_rsp { 756 struct mbox_msghdr hdr; 757 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 758 u32 stack_pg_bytes; /* Size of stack page */ 759 u16 qints; /* NPA_AF_CONST::QINTS */ 760 u8 cache_lines; /*BATCH ALLOC DMA */ 761 }; 762 763 /* NPA AQ enqueue msg */ 764 struct npa_aq_enq_req { 765 struct mbox_msghdr hdr; 766 u32 aura_id; 767 u8 ctype; 768 u8 op; 769 union { 770 /* Valid when op == WRITE/INIT and ctype == AURA. 771 * LF fills the pool_id in aura.pool_addr. AF will translate 772 * the pool_id to pool context pointer. 773 */ 774 struct npa_aura_s aura; 775 /* Valid when op == WRITE/INIT and ctype == POOL */ 776 struct npa_pool_s pool; 777 }; 778 /* Mask data when op == WRITE (1=write, 0=don't write) */ 779 union { 780 /* Valid when op == WRITE and ctype == AURA */ 781 struct npa_aura_s aura_mask; 782 /* Valid when op == WRITE and ctype == POOL */ 783 struct npa_pool_s pool_mask; 784 }; 785 }; 786 787 struct npa_aq_enq_rsp { 788 struct mbox_msghdr hdr; 789 union { 790 /* Valid when op == READ and ctype == AURA */ 791 struct npa_aura_s aura; 792 /* Valid when op == READ and ctype == POOL */ 793 struct npa_pool_s pool; 794 }; 795 }; 796 797 /* Disable all contexts of type 'ctype' */ 798 struct hwctx_disable_req { 799 struct mbox_msghdr hdr; 800 u8 ctype; 801 }; 802 803 /* NIX mbox message formats */ 804 805 /* NIX mailbox error codes 806 * Range 401 - 500. 807 */ 808 enum nix_af_status { 809 NIX_AF_ERR_PARAM = -401, 810 NIX_AF_ERR_AQ_FULL = -402, 811 NIX_AF_ERR_AQ_ENQUEUE = -403, 812 NIX_AF_ERR_AF_LF_INVALID = -404, 813 NIX_AF_ERR_AF_LF_ALLOC = -405, 814 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 815 NIX_AF_ERR_TLX_INVALID = -407, 816 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 817 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 818 NIX_AF_ERR_FRS_INVALID = -410, 819 NIX_AF_ERR_RX_LINK_INVALID = -411, 820 NIX_AF_INVAL_TXSCHQ_CFG = -412, 821 NIX_AF_SMQ_FLUSH_FAILED = -413, 822 NIX_AF_ERR_LF_RESET = -414, 823 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 824 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 825 NIX_AF_ERR_MARK_CFG_FAIL = -417, 826 NIX_AF_ERR_LSO_CFG_FAIL = -418, 827 NIX_AF_INVAL_NPA_PF_FUNC = -419, 828 NIX_AF_INVAL_SSO_PF_FUNC = -420, 829 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 830 NIX_AF_ERR_RX_VTAG_INUSE = -422, 831 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 832 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 833 NIX_AF_ERR_INVALID_NIXBLK = -425, 834 NIX_AF_ERR_INVALID_BANDPROF = -426, 835 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 836 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 837 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 838 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 839 NIX_AF_ERR_LINK_CREDITS = -431, 840 NIX_AF_ERR_INVALID_BPID = -434, 841 NIX_AF_ERR_INVALID_BPID_REQ = -435, 842 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 843 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 844 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 845 }; 846 847 /* For NIX RX vtag action */ 848 enum nix_rx_vtag0_type { 849 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 850 NIX_AF_LFX_RX_VTAG_TYPE1, 851 NIX_AF_LFX_RX_VTAG_TYPE2, 852 NIX_AF_LFX_RX_VTAG_TYPE3, 853 NIX_AF_LFX_RX_VTAG_TYPE4, 854 NIX_AF_LFX_RX_VTAG_TYPE5, 855 NIX_AF_LFX_RX_VTAG_TYPE6, 856 NIX_AF_LFX_RX_VTAG_TYPE7, 857 }; 858 859 /* For NIX LF context alloc and init */ 860 struct nix_lf_alloc_req { 861 struct mbox_msghdr hdr; 862 int node; 863 u32 rq_cnt; /* No of receive queues */ 864 u32 sq_cnt; /* No of send queues */ 865 u32 cq_cnt; /* No of completion queues */ 866 u8 xqe_sz; 867 u16 rss_sz; 868 u8 rss_grps; 869 u16 npa_func; 870 u16 sso_func; 871 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 872 u64 way_mask; 873 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 874 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 875 u64 flags; 876 }; 877 878 struct nix_lf_alloc_rsp { 879 struct mbox_msghdr hdr; 880 u16 sqb_size; 881 u16 rx_chan_base; 882 u16 tx_chan_base; 883 u8 rx_chan_cnt; /* total number of RX channels */ 884 u8 tx_chan_cnt; /* total number of TX channels */ 885 u8 lso_tsov4_idx; 886 u8 lso_tsov6_idx; 887 u8 mac_addr[ETH_ALEN]; 888 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 889 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 890 u16 cints; /* NIX_AF_CONST2::CINTS */ 891 u16 qints; /* NIX_AF_CONST2::QINTS */ 892 u8 cgx_links; /* No. of CGX links present in HW */ 893 u8 lbk_links; /* No. of LBK links present in HW */ 894 u8 sdp_links; /* No. of SDP links present in HW */ 895 u8 tx_link; /* Transmit channel link number */ 896 }; 897 898 struct nix_lf_free_req { 899 struct mbox_msghdr hdr; 900 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 901 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 902 u64 flags; 903 }; 904 905 /* CN10K NIX AQ enqueue msg */ 906 struct nix_cn10k_aq_enq_req { 907 struct mbox_msghdr hdr; 908 u32 qidx; 909 u8 ctype; 910 u8 op; 911 union { 912 struct nix_cn10k_rq_ctx_s rq; 913 struct nix_cn10k_sq_ctx_s sq; 914 struct nix_cq_ctx_s cq; 915 struct nix_rsse_s rss; 916 struct nix_rx_mce_s mce; 917 struct nix_bandprof_s prof; 918 }; 919 union { 920 struct nix_cn10k_rq_ctx_s rq_mask; 921 struct nix_cn10k_sq_ctx_s sq_mask; 922 struct nix_cq_ctx_s cq_mask; 923 struct nix_rsse_s rss_mask; 924 struct nix_rx_mce_s mce_mask; 925 struct nix_bandprof_s prof_mask; 926 }; 927 }; 928 929 struct nix_cn10k_aq_enq_rsp { 930 struct mbox_msghdr hdr; 931 union { 932 struct nix_cn10k_rq_ctx_s rq; 933 struct nix_cn10k_sq_ctx_s sq; 934 struct nix_cq_ctx_s cq; 935 struct nix_rsse_s rss; 936 struct nix_rx_mce_s mce; 937 struct nix_bandprof_s prof; 938 }; 939 }; 940 941 /* NIX AQ enqueue msg */ 942 struct nix_aq_enq_req { 943 struct mbox_msghdr hdr; 944 u32 qidx; 945 u8 ctype; 946 u8 op; 947 union { 948 struct nix_rq_ctx_s rq; 949 struct nix_sq_ctx_s sq; 950 struct nix_cq_ctx_s cq; 951 struct nix_rsse_s rss; 952 struct nix_rx_mce_s mce; 953 struct nix_bandprof_s prof; 954 }; 955 union { 956 struct nix_rq_ctx_s rq_mask; 957 struct nix_sq_ctx_s sq_mask; 958 struct nix_cq_ctx_s cq_mask; 959 struct nix_rsse_s rss_mask; 960 struct nix_rx_mce_s mce_mask; 961 struct nix_bandprof_s prof_mask; 962 }; 963 }; 964 965 struct nix_aq_enq_rsp { 966 struct mbox_msghdr hdr; 967 union { 968 struct nix_rq_ctx_s rq; 969 struct nix_sq_ctx_s sq; 970 struct nix_cq_ctx_s cq; 971 struct nix_rsse_s rss; 972 struct nix_rx_mce_s mce; 973 struct nix_bandprof_s prof; 974 }; 975 }; 976 977 /* Tx scheduler/shaper mailbox messages */ 978 979 #define MAX_TXSCHQ_PER_FUNC 128 980 981 struct nix_txsch_alloc_req { 982 struct mbox_msghdr hdr; 983 /* Scheduler queue count request at each level */ 984 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 985 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 986 }; 987 988 struct nix_txsch_alloc_rsp { 989 struct mbox_msghdr hdr; 990 /* Scheduler queue count allocated at each level */ 991 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 992 u16 schq[NIX_TXSCH_LVL_CNT]; 993 /* Scheduler queue list allocated at each level */ 994 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 995 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 996 u8 aggr_level; /* Traffic aggregation scheduler level */ 997 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 998 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 999 }; 1000 1001 struct nix_txsch_free_req { 1002 struct mbox_msghdr hdr; 1003 #define TXSCHQ_FREE_ALL BIT_ULL(0) 1004 u16 flags; 1005 /* Scheduler queue level to be freed */ 1006 u16 schq_lvl; 1007 /* List of scheduler queues to be freed */ 1008 u16 schq; 1009 }; 1010 1011 struct nix_txschq_config { 1012 struct mbox_msghdr hdr; 1013 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1014 u8 read; 1015 #define TXSCHQ_IDX_SHIFT 16 1016 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1017 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1018 u8 num_regs; 1019 #define MAX_REGS_PER_MBOX_MSG 20 1020 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1021 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1022 /* All 0's => overwrite with new value */ 1023 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1024 }; 1025 1026 struct nix_vtag_config { 1027 struct mbox_msghdr hdr; 1028 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1029 u8 vtag_size; 1030 /* cfg_type is '0' for tx vlan cfg 1031 * cfg_type is '1' for rx vlan cfg 1032 */ 1033 u8 cfg_type; 1034 union { 1035 /* valid when cfg_type is '0' */ 1036 struct { 1037 u64 vtag0; 1038 u64 vtag1; 1039 1040 /* cfg_vtag0 & cfg_vtag1 fields are valid 1041 * when free_vtag0 & free_vtag1 are '0's. 1042 */ 1043 /* cfg_vtag0 = 1 to configure vtag0 */ 1044 u8 cfg_vtag0 :1; 1045 /* cfg_vtag1 = 1 to configure vtag1 */ 1046 u8 cfg_vtag1 :1; 1047 1048 /* vtag0_idx & vtag1_idx are only valid when 1049 * both cfg_vtag0 & cfg_vtag1 are '0's, 1050 * these fields are used along with free_vtag0 1051 * & free_vtag1 to free the nix lf's tx_vlan 1052 * configuration. 1053 * 1054 * Denotes the indices of tx_vtag def registers 1055 * that needs to be cleared and freed. 1056 */ 1057 int vtag0_idx; 1058 int vtag1_idx; 1059 1060 /* free_vtag0 & free_vtag1 fields are valid 1061 * when cfg_vtag0 & cfg_vtag1 are '0's. 1062 */ 1063 /* free_vtag0 = 1 clears vtag0 configuration 1064 * vtag0_idx denotes the index to be cleared. 1065 */ 1066 u8 free_vtag0 :1; 1067 /* free_vtag1 = 1 clears vtag1 configuration 1068 * vtag1_idx denotes the index to be cleared. 1069 */ 1070 u8 free_vtag1 :1; 1071 } tx; 1072 1073 /* valid when cfg_type is '1' */ 1074 struct { 1075 /* rx vtag type index, valid values are in 0..7 range */ 1076 u8 vtag_type; 1077 /* rx vtag strip */ 1078 u8 strip_vtag :1; 1079 /* rx vtag capture */ 1080 u8 capture_vtag :1; 1081 } rx; 1082 }; 1083 }; 1084 1085 struct nix_vtag_config_rsp { 1086 struct mbox_msghdr hdr; 1087 int vtag0_idx; 1088 int vtag1_idx; 1089 /* Indices of tx_vtag def registers used to configure 1090 * tx vtag0 & vtag1 headers, these indices are valid 1091 * when nix_vtag_config mbox requested for vtag0 and/ 1092 * or vtag1 configuration. 1093 */ 1094 }; 1095 1096 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1097 1098 struct nix_rss_flowkey_cfg { 1099 struct mbox_msghdr hdr; 1100 int mcam_index; /* MCAM entry index to modify */ 1101 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1102 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1103 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1104 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1105 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1106 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1107 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1108 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1109 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1110 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1111 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1112 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1113 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1114 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1115 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1116 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1117 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1118 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1119 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1120 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1121 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1122 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1123 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1124 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1125 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1126 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1127 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1128 u32 flowkey_cfg; /* Flowkey types selected */ 1129 u8 group; /* RSS context or group */ 1130 }; 1131 1132 struct nix_rss_flowkey_cfg_rsp { 1133 struct mbox_msghdr hdr; 1134 u8 alg_idx; /* Selected algo index */ 1135 }; 1136 1137 struct nix_set_mac_addr { 1138 struct mbox_msghdr hdr; 1139 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1140 }; 1141 1142 struct nix_get_mac_addr_rsp { 1143 struct mbox_msghdr hdr; 1144 u8 mac_addr[ETH_ALEN]; 1145 }; 1146 1147 struct nix_mark_format_cfg { 1148 struct mbox_msghdr hdr; 1149 u8 offset; 1150 u8 y_mask; 1151 u8 y_val; 1152 u8 r_mask; 1153 u8 r_val; 1154 }; 1155 1156 struct nix_mark_format_cfg_rsp { 1157 struct mbox_msghdr hdr; 1158 u8 mark_format_idx; 1159 }; 1160 1161 struct nix_rx_mode { 1162 struct mbox_msghdr hdr; 1163 #define NIX_RX_MODE_UCAST BIT(0) 1164 #define NIX_RX_MODE_PROMISC BIT(1) 1165 #define NIX_RX_MODE_ALLMULTI BIT(2) 1166 #define NIX_RX_MODE_USE_MCE BIT(3) 1167 u16 mode; 1168 }; 1169 1170 struct nix_rx_cfg { 1171 struct mbox_msghdr hdr; 1172 #define NIX_RX_OL3_VERIFY BIT(0) 1173 #define NIX_RX_OL4_VERIFY BIT(1) 1174 #define NIX_RX_DROP_RE BIT(2) 1175 u8 len_verify; /* Outer L3/L4 len check */ 1176 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1177 u8 csum_verify; /* Outer L4 checksum verification */ 1178 }; 1179 1180 struct nix_frs_cfg { 1181 struct mbox_msghdr hdr; 1182 u8 update_smq; /* Update SMQ's min/max lens */ 1183 u8 update_minlen; /* Set minlen also */ 1184 u8 sdp_link; /* Set SDP RX link */ 1185 u16 maxlen; 1186 u16 minlen; 1187 }; 1188 1189 struct nix_lso_format_cfg { 1190 struct mbox_msghdr hdr; 1191 u64 field_mask; 1192 #define NIX_LSO_FIELD_MAX 8 1193 u64 fields[NIX_LSO_FIELD_MAX]; 1194 }; 1195 1196 struct nix_lso_format_cfg_rsp { 1197 struct mbox_msghdr hdr; 1198 u8 lso_format_idx; 1199 }; 1200 1201 struct nix_bp_cfg_req { 1202 struct mbox_msghdr hdr; 1203 u16 chan_base; /* Starting channel number */ 1204 u8 chan_cnt; /* Number of channels */ 1205 u8 bpid_per_chan; 1206 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1207 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1208 }; 1209 1210 /* PF can be mapped to either CGX or LBK interface, 1211 * so maximum 64 channels are possible. 1212 */ 1213 #define NIX_MAX_BPID_CHAN 64 1214 struct nix_bp_cfg_rsp { 1215 struct mbox_msghdr hdr; 1216 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1217 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1218 }; 1219 1220 struct nix_mcast_grp_create_req { 1221 struct mbox_msghdr hdr; 1222 #define NIX_MCAST_INGRESS 0 1223 #define NIX_MCAST_EGRESS 1 1224 u8 dir; 1225 u8 reserved[11]; 1226 /* Reserving few bytes for future requirement */ 1227 }; 1228 1229 struct nix_mcast_grp_create_rsp { 1230 struct mbox_msghdr hdr; 1231 /* This mcast_grp_idx should be passed during MCAM 1232 * write entry for multicast. AF will identify the 1233 * corresponding multicast table index associated 1234 * with the group id and program the same to MCAM entry. 1235 * This group id is also needed during group delete 1236 * and update request. 1237 */ 1238 u32 mcast_grp_idx; 1239 }; 1240 1241 struct nix_mcast_grp_destroy_req { 1242 struct mbox_msghdr hdr; 1243 /* Group id returned by nix_mcast_grp_create_rsp */ 1244 u32 mcast_grp_idx; 1245 /* If AF is requesting for destroy, then set 1246 * it to '1'. Otherwise keep it to '0' 1247 */ 1248 u8 is_af; 1249 }; 1250 1251 struct nix_mcast_grp_update_req { 1252 struct mbox_msghdr hdr; 1253 /* Group id returned by nix_mcast_grp_create_rsp */ 1254 u32 mcast_grp_idx; 1255 /* Number of multicast/mirror entries requested */ 1256 u32 num_mce_entry; 1257 #define NIX_MCE_ENTRY_MAX 64 1258 #define NIX_RX_RQ 0 1259 #define NIX_RX_RSS 1 1260 /* Receive queue or RSS index within pf_func */ 1261 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1262 /* pcifunc is required for both ingress and egress multicast */ 1263 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1264 /* channel is required for egress multicast */ 1265 u16 channel[NIX_MCE_ENTRY_MAX]; 1266 #define NIX_MCAST_OP_ADD_ENTRY 0 1267 #define NIX_MCAST_OP_DEL_ENTRY 1 1268 /* Destination type. 0:Receive queue, 1:RSS*/ 1269 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1270 u8 op; 1271 /* If AF is requesting for update, then set 1272 * it to '1'. Otherwise keep it to '0' 1273 */ 1274 u8 is_af; 1275 }; 1276 1277 struct nix_mcast_grp_update_rsp { 1278 struct mbox_msghdr hdr; 1279 u32 mce_start_index; 1280 }; 1281 1282 /* Global NIX inline IPSec configuration */ 1283 struct nix_inline_ipsec_cfg { 1284 struct mbox_msghdr hdr; 1285 u32 cpt_credit; 1286 struct { 1287 u8 egrp; 1288 u16 opcode; 1289 u16 param1; 1290 u16 param2; 1291 } gen_cfg; 1292 struct { 1293 u16 cpt_pf_func; 1294 u8 cpt_slot; 1295 } inst_qsel; 1296 u8 enable; 1297 u16 bpid; 1298 u32 credit_th; 1299 }; 1300 1301 /* Per NIX LF inline IPSec configuration */ 1302 struct nix_inline_ipsec_lf_cfg { 1303 struct mbox_msghdr hdr; 1304 u64 sa_base_addr; 1305 struct { 1306 u32 tag_const; 1307 u16 lenm1_max; 1308 u8 sa_pow2_size; 1309 u8 tt; 1310 } ipsec_cfg0; 1311 struct { 1312 u32 sa_idx_max; 1313 u8 sa_idx_w; 1314 } ipsec_cfg1; 1315 u8 enable; 1316 }; 1317 1318 struct nix_hw_info { 1319 struct mbox_msghdr hdr; 1320 u16 rsvs16; 1321 u16 max_mtu; 1322 u16 min_mtu; 1323 u32 rpm_dwrr_mtu; 1324 u32 sdp_dwrr_mtu; 1325 u32 lbk_dwrr_mtu; 1326 u32 rsvd32[1]; 1327 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1328 }; 1329 1330 struct nix_bandprof_alloc_req { 1331 struct mbox_msghdr hdr; 1332 /* Count of profiles needed per layer */ 1333 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1334 }; 1335 1336 struct nix_bandprof_alloc_rsp { 1337 struct mbox_msghdr hdr; 1338 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1339 1340 /* There is no need to allocate morethan 1 bandwidth profile 1341 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1342 * profiles to 64 per PF_FUNC. 1343 */ 1344 #define MAX_BANDPROF_PER_PFFUNC 64 1345 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1346 }; 1347 1348 struct nix_bandprof_free_req { 1349 struct mbox_msghdr hdr; 1350 u8 free_all; 1351 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1352 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1353 }; 1354 1355 struct nix_bandprof_get_hwinfo_rsp { 1356 struct mbox_msghdr hdr; 1357 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1358 u32 policer_timeunit; 1359 }; 1360 1361 /* NPC mbox message structs */ 1362 1363 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1364 #define NPC_MCAM_INVALID_MAP 0xFFFF 1365 1366 /* NPC mailbox error codes 1367 * Range 701 - 800. 1368 */ 1369 enum npc_af_status { 1370 NPC_MCAM_INVALID_REQ = -701, 1371 NPC_MCAM_ALLOC_DENIED = -702, 1372 NPC_MCAM_ALLOC_FAILED = -703, 1373 NPC_MCAM_PERM_DENIED = -704, 1374 NPC_FLOW_INTF_INVALID = -707, 1375 NPC_FLOW_CHAN_INVALID = -708, 1376 NPC_FLOW_NO_NIXLF = -709, 1377 NPC_FLOW_NOT_SUPPORTED = -710, 1378 NPC_FLOW_VF_PERM_DENIED = -711, 1379 NPC_FLOW_VF_NOT_INIT = -712, 1380 NPC_FLOW_VF_OVERLAP = -713, 1381 }; 1382 1383 struct npc_mcam_alloc_entry_req { 1384 struct mbox_msghdr hdr; 1385 #define NPC_MAX_NONCONTIG_ENTRIES 256 1386 u8 contig; /* Contiguous entries ? */ 1387 #define NPC_MCAM_ANY_PRIO 0 1388 #define NPC_MCAM_LOWER_PRIO 1 1389 #define NPC_MCAM_HIGHER_PRIO 2 1390 u8 priority; /* Lower or higher w.r.t ref_entry */ 1391 u16 ref_entry; 1392 u16 count; /* Number of entries requested */ 1393 }; 1394 1395 struct npc_mcam_alloc_entry_rsp { 1396 struct mbox_msghdr hdr; 1397 u16 entry; /* Entry allocated or start index if contiguous. 1398 * Invalid incase of non-contiguous. 1399 */ 1400 u16 count; /* Number of entries allocated */ 1401 u16 free_count; /* Number of entries available */ 1402 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1403 }; 1404 1405 struct npc_mcam_free_entry_req { 1406 struct mbox_msghdr hdr; 1407 u16 entry; /* Entry index to be freed */ 1408 u8 all; /* If all entries allocated to this PFVF to be freed */ 1409 }; 1410 1411 struct mcam_entry { 1412 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1413 u64 kw[NPC_MAX_KWS_IN_KEY]; 1414 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1415 u64 action; 1416 u64 vtag_action; 1417 }; 1418 1419 struct npc_mcam_write_entry_req { 1420 struct mbox_msghdr hdr; 1421 struct mcam_entry entry_data; 1422 u16 entry; /* MCAM entry to write this match key */ 1423 u16 cntr; /* Counter for this MCAM entry */ 1424 u8 intf; /* Rx or Tx interface */ 1425 u8 enable_entry;/* Enable this MCAM entry ? */ 1426 u8 set_cntr; /* Set counter for this entry ? */ 1427 }; 1428 1429 /* Enable/Disable a given entry */ 1430 struct npc_mcam_ena_dis_entry_req { 1431 struct mbox_msghdr hdr; 1432 u16 entry; 1433 }; 1434 1435 struct npc_mcam_shift_entry_req { 1436 struct mbox_msghdr hdr; 1437 #define NPC_MCAM_MAX_SHIFTS 64 1438 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1439 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1440 u16 shift_count; /* Number of entries to shift */ 1441 }; 1442 1443 struct npc_mcam_shift_entry_rsp { 1444 struct mbox_msghdr hdr; 1445 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1446 }; 1447 1448 struct npc_mcam_alloc_counter_req { 1449 struct mbox_msghdr hdr; 1450 u8 contig; /* Contiguous counters ? */ 1451 #define NPC_MAX_NONCONTIG_COUNTERS 64 1452 u16 count; /* Number of counters requested */ 1453 }; 1454 1455 struct npc_mcam_alloc_counter_rsp { 1456 struct mbox_msghdr hdr; 1457 u16 cntr; /* Counter allocated or start index if contiguous. 1458 * Invalid incase of non-contiguous. 1459 */ 1460 u16 count; /* Number of counters allocated */ 1461 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1462 }; 1463 1464 struct npc_mcam_oper_counter_req { 1465 struct mbox_msghdr hdr; 1466 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1467 }; 1468 1469 struct npc_mcam_oper_counter_rsp { 1470 struct mbox_msghdr hdr; 1471 u64 stat; /* valid only while fetching counter's stats */ 1472 }; 1473 1474 struct npc_mcam_unmap_counter_req { 1475 struct mbox_msghdr hdr; 1476 u16 cntr; 1477 u16 entry; /* Entry and counter to be unmapped */ 1478 u8 all; /* Unmap all entries using this counter ? */ 1479 }; 1480 1481 struct npc_mcam_alloc_and_write_entry_req { 1482 struct mbox_msghdr hdr; 1483 struct mcam_entry entry_data; 1484 u16 ref_entry; 1485 u8 priority; /* Lower or higher w.r.t ref_entry */ 1486 u8 intf; /* Rx or Tx interface */ 1487 u8 enable_entry;/* Enable this MCAM entry ? */ 1488 u8 alloc_cntr; /* Allocate counter and map ? */ 1489 }; 1490 1491 struct npc_mcam_alloc_and_write_entry_rsp { 1492 struct mbox_msghdr hdr; 1493 u16 entry; 1494 u16 cntr; 1495 }; 1496 1497 struct npc_get_kex_cfg_rsp { 1498 struct mbox_msghdr hdr; 1499 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1500 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1501 #define NPC_MAX_INTF 2 1502 #define NPC_MAX_LID 8 1503 #define NPC_MAX_LT 16 1504 #define NPC_MAX_LD 2 1505 #define NPC_MAX_LFL 16 1506 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1507 u64 kex_ld_flags[NPC_MAX_LD]; 1508 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1509 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1510 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1511 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1512 #define MKEX_NAME_LEN 128 1513 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1514 }; 1515 1516 struct ptp_get_cap_rsp { 1517 struct mbox_msghdr hdr; 1518 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1519 u64 cap; 1520 }; 1521 1522 struct flow_msg { 1523 unsigned char dmac[6]; 1524 unsigned char smac[6]; 1525 __be16 etype; 1526 __be16 vlan_etype; 1527 __be16 vlan_tci; 1528 union { 1529 __be32 ip4src; 1530 __be32 ip6src[4]; 1531 }; 1532 union { 1533 __be32 ip4dst; 1534 __be32 ip6dst[4]; 1535 }; 1536 union { 1537 __be32 spi; 1538 }; 1539 1540 u8 tos; 1541 u8 ip_ver; 1542 u8 ip_proto; 1543 u8 tc; 1544 __be16 sport; 1545 __be16 dport; 1546 union { 1547 u8 ip_flag; 1548 u8 next_header; 1549 }; 1550 __be16 vlan_itci; 1551 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1552 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1553 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1554 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1555 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1556 u32 mpls_lse[4]; 1557 u8 icmp_type; 1558 u8 icmp_code; 1559 __be16 tcp_flags; 1560 }; 1561 1562 struct npc_install_flow_req { 1563 struct mbox_msghdr hdr; 1564 struct flow_msg packet; 1565 struct flow_msg mask; 1566 u64 features; 1567 u16 entry; 1568 u16 channel; 1569 u16 chan_mask; 1570 u8 intf; 1571 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1572 u8 default_rule; 1573 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1574 u16 vf; 1575 /* action */ 1576 u32 index; 1577 u16 match_id; 1578 u8 flow_key_alg; 1579 u8 op; 1580 /* vtag rx action */ 1581 u8 vtag0_type; 1582 u8 vtag0_valid; 1583 u8 vtag1_type; 1584 u8 vtag1_valid; 1585 /* vtag tx action */ 1586 u16 vtag0_def; 1587 u8 vtag0_op; 1588 u16 vtag1_def; 1589 u8 vtag1_op; 1590 /* old counter value */ 1591 u16 cntr_val; 1592 }; 1593 1594 struct npc_install_flow_rsp { 1595 struct mbox_msghdr hdr; 1596 int counter; /* negative if no counter else counter number */ 1597 }; 1598 1599 struct npc_delete_flow_req { 1600 struct mbox_msghdr hdr; 1601 u16 entry; 1602 u16 start;/*Disable range of entries */ 1603 u16 end; 1604 u8 all; /* PF + VFs */ 1605 }; 1606 1607 struct npc_delete_flow_rsp { 1608 struct mbox_msghdr hdr; 1609 u16 cntr_val; 1610 }; 1611 1612 struct npc_mcam_read_entry_req { 1613 struct mbox_msghdr hdr; 1614 u16 entry; /* MCAM entry to read */ 1615 }; 1616 1617 struct npc_mcam_read_entry_rsp { 1618 struct mbox_msghdr hdr; 1619 struct mcam_entry entry_data; 1620 u8 intf; 1621 u8 enable; 1622 }; 1623 1624 struct npc_mcam_read_base_rule_rsp { 1625 struct mbox_msghdr hdr; 1626 struct mcam_entry entry; 1627 }; 1628 1629 struct npc_mcam_get_stats_req { 1630 struct mbox_msghdr hdr; 1631 u16 entry; /* mcam entry */ 1632 }; 1633 1634 struct npc_mcam_get_stats_rsp { 1635 struct mbox_msghdr hdr; 1636 u64 stat; /* counter stats */ 1637 u8 stat_ena; /* enabled */ 1638 }; 1639 1640 struct npc_get_field_hash_info_req { 1641 struct mbox_msghdr hdr; 1642 u8 intf; 1643 }; 1644 1645 struct npc_get_field_hash_info_rsp { 1646 struct mbox_msghdr hdr; 1647 u64 secret_key[3]; 1648 #define NPC_MAX_HASH 2 1649 #define NPC_MAX_HASH_MASK 2 1650 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1651 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1652 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1653 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1654 }; 1655 1656 enum ptp_op { 1657 PTP_OP_ADJFINE = 0, 1658 PTP_OP_GET_CLOCK = 1, 1659 PTP_OP_GET_TSTMP = 2, 1660 PTP_OP_SET_THRESH = 3, 1661 PTP_OP_PPS_ON = 4, 1662 PTP_OP_ADJTIME = 5, 1663 PTP_OP_SET_CLOCK = 6, 1664 }; 1665 1666 struct ptp_req { 1667 struct mbox_msghdr hdr; 1668 u8 op; 1669 s64 scaled_ppm; 1670 u64 thresh; 1671 u64 period; 1672 int pps_on; 1673 s64 delta; 1674 u64 clk; 1675 }; 1676 1677 struct ptp_rsp { 1678 struct mbox_msghdr hdr; 1679 u64 clk; 1680 u64 tsc; 1681 }; 1682 1683 struct npc_get_field_status_req { 1684 struct mbox_msghdr hdr; 1685 u8 intf; 1686 u8 field; 1687 }; 1688 1689 struct npc_get_field_status_rsp { 1690 struct mbox_msghdr hdr; 1691 u8 enable; 1692 }; 1693 1694 struct set_vf_perm { 1695 struct mbox_msghdr hdr; 1696 u16 vf; 1697 #define RESET_VF_PERM BIT_ULL(0) 1698 #define VF_TRUSTED BIT_ULL(1) 1699 u64 flags; 1700 }; 1701 1702 struct lmtst_tbl_setup_req { 1703 struct mbox_msghdr hdr; 1704 u64 dis_sched_early_comp :1; 1705 u64 sch_ena :1; 1706 u64 dis_line_pref :1; 1707 u64 ssow_pf_func :13; 1708 u16 base_pcifunc; 1709 u8 use_local_lmt_region; 1710 u64 lmt_iova; 1711 u64 rsvd[4]; 1712 }; 1713 1714 /* CPT mailbox error codes 1715 * Range 901 - 1000. 1716 */ 1717 enum cpt_af_status { 1718 CPT_AF_ERR_PARAM = -901, 1719 CPT_AF_ERR_GRP_INVALID = -902, 1720 CPT_AF_ERR_LF_INVALID = -903, 1721 CPT_AF_ERR_ACCESS_DENIED = -904, 1722 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1723 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1724 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1725 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1726 }; 1727 1728 /* CPT mbox message formats */ 1729 struct cpt_rd_wr_reg_msg { 1730 struct mbox_msghdr hdr; 1731 u64 reg_offset; 1732 u64 *ret_val; 1733 u64 val; 1734 u8 is_write; 1735 int blkaddr; 1736 }; 1737 1738 struct cpt_lf_alloc_req_msg { 1739 struct mbox_msghdr hdr; 1740 u16 nix_pf_func; 1741 u16 sso_pf_func; 1742 u16 eng_grpmsk; 1743 int blkaddr; 1744 u8 ctx_ilen_valid : 1; 1745 u8 ctx_ilen : 7; 1746 }; 1747 1748 #define CPT_INLINE_INBOUND 0 1749 #define CPT_INLINE_OUTBOUND 1 1750 1751 /* Mailbox message request format for CPT IPsec 1752 * inline inbound and outbound configuration. 1753 */ 1754 struct cpt_inline_ipsec_cfg_msg { 1755 struct mbox_msghdr hdr; 1756 u8 enable; 1757 u8 slot; 1758 u8 dir; 1759 u8 sso_pf_func_ovrd; 1760 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1761 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1762 }; 1763 1764 /* Mailbox message request and response format for CPT stats. */ 1765 struct cpt_sts_req { 1766 struct mbox_msghdr hdr; 1767 u8 blkaddr; 1768 }; 1769 1770 struct cpt_sts_rsp { 1771 struct mbox_msghdr hdr; 1772 u64 inst_req_pc; 1773 u64 inst_lat_pc; 1774 u64 rd_req_pc; 1775 u64 rd_lat_pc; 1776 u64 rd_uc_pc; 1777 u64 active_cycles_pc; 1778 u64 ctx_mis_pc; 1779 u64 ctx_hit_pc; 1780 u64 ctx_aop_pc; 1781 u64 ctx_aop_lat_pc; 1782 u64 ctx_ifetch_pc; 1783 u64 ctx_ifetch_lat_pc; 1784 u64 ctx_ffetch_pc; 1785 u64 ctx_ffetch_lat_pc; 1786 u64 ctx_wback_pc; 1787 u64 ctx_wback_lat_pc; 1788 u64 ctx_psh_pc; 1789 u64 ctx_psh_lat_pc; 1790 u64 ctx_err; 1791 u64 ctx_enc_id; 1792 u64 ctx_flush_timer; 1793 u64 rxc_time; 1794 u64 rxc_time_cfg; 1795 u64 rxc_active_sts; 1796 u64 rxc_zombie_sts; 1797 u64 busy_sts_ae; 1798 u64 free_sts_ae; 1799 u64 busy_sts_se; 1800 u64 free_sts_se; 1801 u64 busy_sts_ie; 1802 u64 free_sts_ie; 1803 u64 exe_err_info; 1804 u64 cptclk_cnt; 1805 u64 diag; 1806 u64 rxc_dfrg; 1807 u64 x2p_link_cfg0; 1808 u64 x2p_link_cfg1; 1809 }; 1810 1811 /* Mailbox message request format to configure reassembly timeout. */ 1812 struct cpt_rxc_time_cfg_req { 1813 struct mbox_msghdr hdr; 1814 int blkaddr; 1815 u32 step; 1816 u16 zombie_thres; 1817 u16 zombie_limit; 1818 u16 active_thres; 1819 u16 active_limit; 1820 }; 1821 1822 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1823 struct cpt_inst_lmtst_req { 1824 struct mbox_msghdr hdr; 1825 u64 inst[8]; 1826 u64 rsvd; 1827 }; 1828 1829 /* Mailbox message format to request for CPT LF reset */ 1830 struct cpt_lf_rst_req { 1831 struct mbox_msghdr hdr; 1832 u32 slot; 1833 u32 rsvd; 1834 }; 1835 1836 /* Mailbox message format to request for CPT faulted engines */ 1837 struct cpt_flt_eng_info_req { 1838 struct mbox_msghdr hdr; 1839 int blkaddr; 1840 bool reset; 1841 u32 rsvd; 1842 }; 1843 1844 struct cpt_flt_eng_info_rsp { 1845 struct mbox_msghdr hdr; 1846 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1847 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1848 u64 rsvd; 1849 }; 1850 1851 struct sdp_node_info { 1852 /* Node to which this PF belons to */ 1853 u8 node_id; 1854 u8 max_vfs; 1855 u8 num_pf_rings; 1856 u8 pf_srn; 1857 #define SDP_MAX_VFS 128 1858 u8 vf_rings[SDP_MAX_VFS]; 1859 }; 1860 1861 struct sdp_chan_info_msg { 1862 struct mbox_msghdr hdr; 1863 struct sdp_node_info info; 1864 }; 1865 1866 struct sdp_get_chan_info_msg { 1867 struct mbox_msghdr hdr; 1868 u16 chan_base; 1869 u16 num_chan; 1870 }; 1871 1872 /* CGX mailbox error codes 1873 * Range 1101 - 1200. 1874 */ 1875 enum cgx_af_status { 1876 LMAC_AF_ERR_INVALID_PARAM = -1101, 1877 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1878 LMAC_AF_ERR_PERM_DENIED = -1103, 1879 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1880 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1881 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1882 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1883 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1884 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1885 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1886 }; 1887 1888 enum mcs_direction { 1889 MCS_RX, 1890 MCS_TX, 1891 }; 1892 1893 enum mcs_rsrc_type { 1894 MCS_RSRC_TYPE_FLOWID, 1895 MCS_RSRC_TYPE_SECY, 1896 MCS_RSRC_TYPE_SC, 1897 MCS_RSRC_TYPE_SA, 1898 }; 1899 1900 struct mcs_alloc_rsrc_req { 1901 struct mbox_msghdr hdr; 1902 u8 rsrc_type; 1903 u8 rsrc_cnt; /* Resources count */ 1904 u8 mcs_id; /* MCS block ID */ 1905 u8 dir; /* Macsec ingress or egress side */ 1906 u8 all; /* Allocate all resource type one each */ 1907 u64 rsvd; 1908 }; 1909 1910 struct mcs_alloc_rsrc_rsp { 1911 struct mbox_msghdr hdr; 1912 u8 flow_ids[128]; /* Index of reserved entries */ 1913 u8 secy_ids[128]; 1914 u8 sc_ids[128]; 1915 u8 sa_ids[256]; 1916 u8 rsrc_type; 1917 u8 rsrc_cnt; /* No of entries reserved */ 1918 u8 mcs_id; 1919 u8 dir; 1920 u8 all; 1921 u8 rsvd[256]; /* reserved fields for future expansion */ 1922 }; 1923 1924 struct mcs_free_rsrc_req { 1925 struct mbox_msghdr hdr; 1926 u8 rsrc_id; /* Index of the entry to be freed */ 1927 u8 rsrc_type; 1928 u8 mcs_id; 1929 u8 dir; 1930 u8 all; /* Free all the cam resources */ 1931 u64 rsvd; 1932 }; 1933 1934 struct mcs_flowid_entry_write_req { 1935 struct mbox_msghdr hdr; 1936 u64 data[4]; 1937 u64 mask[4]; 1938 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1939 u8 flow_id; 1940 u8 secy_id; /* secyid for which flowid is mapped */ 1941 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1942 u8 ena; /* Enable tcam entry */ 1943 u8 ctrl_pkt; 1944 u8 mcs_id; 1945 u8 dir; 1946 u64 rsvd; 1947 }; 1948 1949 struct mcs_secy_plcy_write_req { 1950 struct mbox_msghdr hdr; 1951 u64 plcy; 1952 u8 secy_id; 1953 u8 mcs_id; 1954 u8 dir; 1955 u64 rsvd; 1956 }; 1957 1958 /* RX SC_CAM mapping */ 1959 struct mcs_rx_sc_cam_write_req { 1960 struct mbox_msghdr hdr; 1961 u64 sci; /* SCI */ 1962 u64 secy_id; /* secy index mapped to SC */ 1963 u8 sc_id; /* SC CAM entry index */ 1964 u8 mcs_id; 1965 u64 rsvd; 1966 }; 1967 1968 struct mcs_sa_plcy_write_req { 1969 struct mbox_msghdr hdr; 1970 u64 plcy[2][9]; /* Support 2 SA policy */ 1971 u8 sa_index[2]; 1972 u8 sa_cnt; 1973 u8 mcs_id; 1974 u8 dir; 1975 u64 rsvd; 1976 }; 1977 1978 struct mcs_tx_sc_sa_map { 1979 struct mbox_msghdr hdr; 1980 u8 sa_index0; 1981 u8 sa_index1; 1982 u8 rekey_ena; 1983 u8 sa_index0_vld; 1984 u8 sa_index1_vld; 1985 u8 tx_sa_active; 1986 u64 sectag_sci; 1987 u8 sc_id; /* used as index for SA_MEM_MAP */ 1988 u8 mcs_id; 1989 u64 rsvd; 1990 }; 1991 1992 struct mcs_rx_sc_sa_map { 1993 struct mbox_msghdr hdr; 1994 u8 sa_index; 1995 u8 sa_in_use; 1996 u8 sc_id; 1997 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1998 u8 mcs_id; 1999 u64 rsvd; 2000 }; 2001 2002 struct mcs_flowid_ena_dis_entry { 2003 struct mbox_msghdr hdr; 2004 u8 flow_id; 2005 u8 ena; 2006 u8 mcs_id; 2007 u8 dir; 2008 u64 rsvd; 2009 }; 2010 2011 struct mcs_pn_table_write_req { 2012 struct mbox_msghdr hdr; 2013 u64 next_pn; 2014 u8 pn_id; 2015 u8 mcs_id; 2016 u8 dir; 2017 u64 rsvd; 2018 }; 2019 2020 struct mcs_hw_info { 2021 struct mbox_msghdr hdr; 2022 u8 num_mcs_blks; /* Number of MCS blocks */ 2023 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2024 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2025 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2026 u16 sa_entries; /* PN table entries = SA entries */ 2027 u64 rsvd[16]; 2028 }; 2029 2030 struct mcs_set_active_lmac { 2031 struct mbox_msghdr hdr; 2032 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2033 u8 mcs_id; 2034 u16 chan_base; /* MCS channel base */ 2035 u64 rsvd; 2036 }; 2037 2038 struct mcs_set_lmac_mode { 2039 struct mbox_msghdr hdr; 2040 u8 mode; /* 1:Bypass 0:Operational */ 2041 u8 lmac_id; 2042 u8 mcs_id; 2043 u64 rsvd; 2044 }; 2045 2046 struct mcs_port_reset_req { 2047 struct mbox_msghdr hdr; 2048 u8 reset; 2049 u8 mcs_id; 2050 u8 port_id; 2051 u64 rsvd; 2052 }; 2053 2054 struct mcs_port_cfg_set_req { 2055 struct mbox_msghdr hdr; 2056 u8 cstm_tag_rel_mode_sel; 2057 u8 custom_hdr_enb; 2058 u8 fifo_skid; 2059 u8 port_mode; 2060 u8 port_id; 2061 u8 mcs_id; 2062 u64 rsvd; 2063 }; 2064 2065 struct mcs_port_cfg_get_req { 2066 struct mbox_msghdr hdr; 2067 u8 port_id; 2068 u8 mcs_id; 2069 u64 rsvd; 2070 }; 2071 2072 struct mcs_port_cfg_get_rsp { 2073 struct mbox_msghdr hdr; 2074 u8 cstm_tag_rel_mode_sel; 2075 u8 custom_hdr_enb; 2076 u8 fifo_skid; 2077 u8 port_mode; 2078 u8 port_id; 2079 u8 mcs_id; 2080 u64 rsvd; 2081 }; 2082 2083 struct mcs_custom_tag_cfg_get_req { 2084 struct mbox_msghdr hdr; 2085 u8 mcs_id; 2086 u8 dir; 2087 u64 rsvd; 2088 }; 2089 2090 struct mcs_custom_tag_cfg_get_rsp { 2091 struct mbox_msghdr hdr; 2092 u16 cstm_etype[8]; 2093 u8 cstm_indx[8]; 2094 u8 cstm_etype_en; 2095 u8 mcs_id; 2096 u8 dir; 2097 u64 rsvd; 2098 }; 2099 2100 /* MCS mailbox error codes 2101 * Range 1201 - 1300. 2102 */ 2103 enum mcs_af_status { 2104 MCS_AF_ERR_INVALID_MCSID = -1201, 2105 MCS_AF_ERR_NOT_MAPPED = -1202, 2106 }; 2107 2108 struct mcs_set_pn_threshold { 2109 struct mbox_msghdr hdr; 2110 u64 threshold; 2111 u8 xpn; /* '1' for setting xpn threshold */ 2112 u8 mcs_id; 2113 u8 dir; 2114 u64 rsvd; 2115 }; 2116 2117 enum mcs_ctrl_pkt_rulew_type { 2118 MCS_CTRL_PKT_RULE_TYPE_ETH, 2119 MCS_CTRL_PKT_RULE_TYPE_DA, 2120 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2121 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2122 MCS_CTRL_PKT_RULE_TYPE_MAC, 2123 }; 2124 2125 struct mcs_alloc_ctrl_pkt_rule_req { 2126 struct mbox_msghdr hdr; 2127 u8 rule_type; 2128 u8 mcs_id; /* MCS block ID */ 2129 u8 dir; /* Macsec ingress or egress side */ 2130 u64 rsvd; 2131 }; 2132 2133 struct mcs_alloc_ctrl_pkt_rule_rsp { 2134 struct mbox_msghdr hdr; 2135 u8 rule_idx; 2136 u8 rule_type; 2137 u8 mcs_id; 2138 u8 dir; 2139 u64 rsvd; 2140 }; 2141 2142 struct mcs_free_ctrl_pkt_rule_req { 2143 struct mbox_msghdr hdr; 2144 u8 rule_idx; 2145 u8 rule_type; 2146 u8 mcs_id; 2147 u8 dir; 2148 u8 all; 2149 u64 rsvd; 2150 }; 2151 2152 struct mcs_ctrl_pkt_rule_write_req { 2153 struct mbox_msghdr hdr; 2154 u64 data0; 2155 u64 data1; 2156 u64 data2; 2157 u8 rule_idx; 2158 u8 rule_type; 2159 u8 mcs_id; 2160 u8 dir; 2161 u64 rsvd; 2162 }; 2163 2164 struct mcs_stats_req { 2165 struct mbox_msghdr hdr; 2166 u8 id; 2167 u8 mcs_id; 2168 u8 dir; 2169 u64 rsvd; 2170 }; 2171 2172 struct mcs_flowid_stats { 2173 struct mbox_msghdr hdr; 2174 u64 tcam_hit_cnt; 2175 u64 rsvd; 2176 }; 2177 2178 struct mcs_secy_stats { 2179 struct mbox_msghdr hdr; 2180 u64 ctl_pkt_bcast_cnt; 2181 u64 ctl_pkt_mcast_cnt; 2182 u64 ctl_pkt_ucast_cnt; 2183 u64 ctl_octet_cnt; 2184 u64 unctl_pkt_bcast_cnt; 2185 u64 unctl_pkt_mcast_cnt; 2186 u64 unctl_pkt_ucast_cnt; 2187 u64 unctl_octet_cnt; 2188 /* Valid only for RX */ 2189 u64 octet_decrypted_cnt; 2190 u64 octet_validated_cnt; 2191 u64 pkt_port_disabled_cnt; 2192 u64 pkt_badtag_cnt; 2193 u64 pkt_nosa_cnt; 2194 u64 pkt_nosaerror_cnt; 2195 u64 pkt_tagged_ctl_cnt; 2196 u64 pkt_untaged_cnt; 2197 u64 pkt_ctl_cnt; /* CN10K-B */ 2198 u64 pkt_notag_cnt; /* CNF10K-B */ 2199 /* Valid only for TX */ 2200 u64 octet_encrypted_cnt; 2201 u64 octet_protected_cnt; 2202 u64 pkt_noactivesa_cnt; 2203 u64 pkt_toolong_cnt; 2204 u64 pkt_untagged_cnt; 2205 u64 rsvd[4]; 2206 }; 2207 2208 struct mcs_port_stats { 2209 struct mbox_msghdr hdr; 2210 u64 tcam_miss_cnt; 2211 u64 parser_err_cnt; 2212 u64 preempt_err_cnt; /* CNF10K-B */ 2213 u64 sectag_insert_err_cnt; 2214 u64 rsvd[4]; 2215 }; 2216 2217 /* Only for CN10K-B */ 2218 struct mcs_sa_stats { 2219 struct mbox_msghdr hdr; 2220 /* RX */ 2221 u64 pkt_invalid_cnt; 2222 u64 pkt_nosaerror_cnt; 2223 u64 pkt_notvalid_cnt; 2224 u64 pkt_ok_cnt; 2225 u64 pkt_nosa_cnt; 2226 /* TX */ 2227 u64 pkt_encrypt_cnt; 2228 u64 pkt_protected_cnt; 2229 u64 rsvd[4]; 2230 }; 2231 2232 struct mcs_sc_stats { 2233 struct mbox_msghdr hdr; 2234 /* RX */ 2235 u64 hit_cnt; 2236 u64 pkt_invalid_cnt; 2237 u64 pkt_late_cnt; 2238 u64 pkt_notvalid_cnt; 2239 u64 pkt_unchecked_cnt; 2240 u64 pkt_delay_cnt; /* CNF10K-B */ 2241 u64 pkt_ok_cnt; /* CNF10K-B */ 2242 u64 octet_decrypt_cnt; /* CN10K-B */ 2243 u64 octet_validate_cnt; /* CN10K-B */ 2244 /* TX */ 2245 u64 pkt_encrypt_cnt; 2246 u64 pkt_protected_cnt; 2247 u64 octet_encrypt_cnt; /* CN10K-B */ 2248 u64 octet_protected_cnt; /* CN10K-B */ 2249 u64 rsvd[4]; 2250 }; 2251 2252 struct mcs_clear_stats { 2253 struct mbox_msghdr hdr; 2254 #define MCS_FLOWID_STATS 0 2255 #define MCS_SECY_STATS 1 2256 #define MCS_SC_STATS 2 2257 #define MCS_SA_STATS 3 2258 #define MCS_PORT_STATS 4 2259 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2260 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2261 u8 mcs_id; 2262 u8 dir; 2263 u8 all; /* All resources stats mapped to PF are cleared */ 2264 }; 2265 2266 struct mcs_intr_cfg { 2267 struct mbox_msghdr hdr; 2268 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2269 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2270 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2271 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2272 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2273 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2274 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2275 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2276 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2277 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2278 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2279 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2280 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2281 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2282 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2283 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2284 u64 intr_mask; /* Interrupt enable mask */ 2285 u8 mcs_id; 2286 u8 lmac_id; 2287 u64 rsvd; 2288 }; 2289 2290 struct mcs_intr_info { 2291 struct mbox_msghdr hdr; 2292 u64 intr_mask; 2293 int sa_id; 2294 u8 mcs_id; 2295 u8 lmac_id; 2296 u64 rsvd; 2297 }; 2298 2299 #endif /* MBOX_H */ 2300