1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 #define MBOX_DOWN_MSG 1 20 #define MBOX_UP_MSG 2 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x000a) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 104 struct pci_dev *pdev, void __force *reg_base, 105 int direction, int ndevs, unsigned long *bmap); 106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 111 int size, int size_rsp); 112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 113 struct mbox_msghdr *msg); 114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 116 u16 pcifunc, u16 id); 117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 118 const char *otx2_mbox_id2name(u16 id); 119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 120 int devid, int size) 121 { 122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 123 } 124 125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 126 127 /* Mailbox message types */ 128 #define MBOX_MSG_MASK 0xFFFF 129 #define MBOX_MSG_INVALID 0xFFFE 130 #define MBOX_MSG_MAX 0xFFFF 131 132 #define MBOX_MESSAGES \ 133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \ 143 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 144 msg_rsp) \ 145 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 146 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 147 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 148 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 149 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 150 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 151 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 152 cgx_mac_addr_set_or_get) \ 153 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 154 cgx_mac_addr_set_or_get) \ 155 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 156 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 157 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 158 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 159 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 160 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 161 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 162 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 163 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 164 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 165 cgx_pause_frm_cfg) \ 166 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 167 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 168 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 169 cgx_mac_addr_add_rsp) \ 170 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 171 msg_rsp) \ 172 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 173 cgx_max_dmac_entries_get_rsp) \ 174 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 175 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 176 cgx_set_link_mode_rsp) \ 177 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 178 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 179 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 180 cgx_features_info_msg) \ 181 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 182 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 183 msg_rsp) \ 184 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 185 cgx_mac_addr_update_rsp) \ 186 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 187 cgx_pfc_rsp) \ 188 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 189 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 190 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 191 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 192 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 193 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 194 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 195 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 196 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 197 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 198 msg_rsp) \ 199 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 200 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 201 cpt_rd_wr_reg_msg) \ 202 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 203 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 204 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 205 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 206 msg_rsp) \ 207 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 208 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 209 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 210 cpt_flt_eng_info_rsp) \ 211 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 212 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 213 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 214 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 215 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 216 npc_mcam_alloc_entry_rsp) \ 217 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 218 npc_mcam_free_entry_req, msg_rsp) \ 219 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 220 npc_mcam_write_entry_req, msg_rsp) \ 221 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 222 npc_mcam_ena_dis_entry_req, msg_rsp) \ 223 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 224 npc_mcam_ena_dis_entry_req, msg_rsp) \ 225 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 226 npc_mcam_shift_entry_rsp) \ 227 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 228 npc_mcam_alloc_counter_req, \ 229 npc_mcam_alloc_counter_rsp) \ 230 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 231 npc_mcam_oper_counter_req, msg_rsp) \ 232 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 233 npc_mcam_unmap_counter_req, msg_rsp) \ 234 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 235 npc_mcam_oper_counter_req, msg_rsp) \ 236 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 237 npc_mcam_oper_counter_req, \ 238 npc_mcam_oper_counter_rsp) \ 239 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 240 npc_mcam_alloc_and_write_entry_req, \ 241 npc_mcam_alloc_and_write_entry_rsp) \ 242 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 243 msg_req, npc_get_kex_cfg_rsp) \ 244 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 245 npc_install_flow_req, npc_install_flow_rsp) \ 246 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 247 npc_delete_flow_req, npc_delete_flow_rsp) \ 248 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 249 npc_mcam_read_entry_req, \ 250 npc_mcam_read_entry_rsp) \ 251 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 252 npc_set_pkind, msg_rsp) \ 253 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 254 msg_req, npc_mcam_read_base_rule_rsp) \ 255 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 256 npc_mcam_get_stats_req, \ 257 npc_mcam_get_stats_rsp) \ 258 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 259 npc_get_field_hash_info_req, \ 260 npc_get_field_hash_info_rsp) \ 261 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 262 npc_get_field_status_req, \ 263 npc_get_field_status_rsp) \ 264 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 265 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 266 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 267 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 268 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 269 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 270 hwctx_disable_req, msg_rsp) \ 271 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 272 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 273 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 274 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 275 nix_txschq_config) \ 276 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 277 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 278 nix_vtag_config_rsp) \ 279 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 280 nix_rss_flowkey_cfg, \ 281 nix_rss_flowkey_cfg_rsp) \ 282 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 283 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 284 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 285 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 286 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 287 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 288 nix_mark_format_cfg, \ 289 nix_mark_format_cfg_rsp) \ 290 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 291 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 292 nix_lso_format_cfg, \ 293 nix_lso_format_cfg_rsp) \ 294 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 295 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 296 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 297 nix_bp_cfg_rsp) \ 298 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 299 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 300 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 301 nix_inline_ipsec_cfg, msg_rsp) \ 302 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 303 nix_inline_ipsec_lf_cfg, msg_rsp) \ 304 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 305 nix_cn10k_aq_enq_rsp) \ 306 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 307 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 308 nix_bandprof_alloc_rsp) \ 309 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 310 msg_rsp) \ 311 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 312 nix_bandprof_get_hwinfo_rsp) \ 313 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 314 msg_req, nix_inline_ipsec_cfg) \ 315 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 316 nix_mcast_grp_create_rsp) \ 317 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 318 msg_rsp) \ 319 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 320 nix_mcast_grp_update_req, \ 321 nix_mcast_grp_update_rsp) \ 322 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 323 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 324 mcs_alloc_rsrc_rsp) \ 325 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 326 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 327 msg_rsp) \ 328 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 329 msg_rsp) \ 330 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 331 msg_rsp) \ 332 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 333 msg_rsp) \ 334 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 335 msg_rsp) \ 336 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 337 msg_rsp) \ 338 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 339 msg_rsp) \ 340 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 341 msg_rsp) \ 342 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 343 msg_rsp) \ 344 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 345 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 346 mcs_flowid_stats) \ 347 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 348 mcs_secy_stats) \ 349 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 350 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 351 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 352 mcs_port_stats) \ 353 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 354 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 355 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 356 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 357 msg_rsp) \ 358 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 359 mcs_alloc_ctrl_pkt_rule_req, \ 360 mcs_alloc_ctrl_pkt_rule_rsp) \ 361 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 362 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 363 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 364 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 365 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 366 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 367 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 368 mcs_port_cfg_get_rsp) \ 369 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 370 mcs_custom_tag_cfg_get_req, \ 371 mcs_custom_tag_cfg_get_rsp) 372 373 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 374 #define MBOX_UP_CGX_MESSAGES \ 375 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 376 377 #define MBOX_UP_CPT_MESSAGES \ 378 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 379 380 #define MBOX_UP_MCS_MESSAGES \ 381 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 382 383 enum { 384 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 385 MBOX_MESSAGES 386 MBOX_UP_CGX_MESSAGES 387 MBOX_UP_CPT_MESSAGES 388 MBOX_UP_MCS_MESSAGES 389 #undef M 390 }; 391 392 /* Mailbox message formats */ 393 394 #define RVU_DEFAULT_PF_FUNC 0xFFFF 395 396 /* Generic request msg used for those mbox messages which 397 * don't send any data in the request. 398 */ 399 struct msg_req { 400 struct mbox_msghdr hdr; 401 }; 402 403 /* Generic response msg used an ack or response for those mbox 404 * messages which don't have a specific rsp msg format. 405 */ 406 struct msg_rsp { 407 struct mbox_msghdr hdr; 408 }; 409 410 /* RVU mailbox error codes 411 * Range 256 - 300. 412 */ 413 enum rvu_af_status { 414 RVU_INVALID_VF_ID = -256, 415 }; 416 417 struct ready_msg_rsp { 418 struct mbox_msghdr hdr; 419 u16 sclk_freq; /* SCLK frequency (in MHz) */ 420 u16 rclk_freq; /* RCLK frequency (in MHz) */ 421 }; 422 423 /* Structure for requesting resource provisioning. 424 * 'modify' flag to be used when either requesting more 425 * or to detach partial of a certain resource type. 426 * Rest of the fields specify how many of what type to 427 * be attached. 428 * To request LFs from two blocks of same type this mailbox 429 * can be sent twice as below: 430 * struct rsrc_attach *attach; 431 * .. Allocate memory for message .. 432 * attach->cptlfs = 3; <3 LFs from CPT0> 433 * .. Send message .. 434 * .. Allocate memory for message .. 435 * attach->modify = 1; 436 * attach->cpt_blkaddr = BLKADDR_CPT1; 437 * attach->cptlfs = 2; <2 LFs from CPT1> 438 * .. Send message .. 439 */ 440 struct rsrc_attach { 441 struct mbox_msghdr hdr; 442 u8 modify:1; 443 u8 npalf:1; 444 u8 nixlf:1; 445 u16 sso; 446 u16 ssow; 447 u16 timlfs; 448 u16 cptlfs; 449 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 450 }; 451 452 /* Structure for relinquishing resources. 453 * 'partial' flag to be used when relinquishing all resources 454 * but only of a certain type. If not set, all resources of all 455 * types provisioned to the RVU function will be detached. 456 */ 457 struct rsrc_detach { 458 struct mbox_msghdr hdr; 459 u8 partial:1; 460 u8 npalf:1; 461 u8 nixlf:1; 462 u8 sso:1; 463 u8 ssow:1; 464 u8 timlfs:1; 465 u8 cptlfs:1; 466 }; 467 468 /* Number of resources available to the caller. 469 * In reply to MBOX_MSG_FREE_RSRC_CNT. 470 */ 471 struct free_rsrcs_rsp { 472 struct mbox_msghdr hdr; 473 u16 schq[NIX_TXSCH_LVL_CNT]; 474 u16 sso; 475 u16 tim; 476 u16 ssow; 477 u16 cpt; 478 u8 npa; 479 u8 nix; 480 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 481 u8 nix1; 482 u8 cpt1; 483 u8 ree0; 484 u8 ree1; 485 }; 486 487 #define MSIX_VECTOR_INVALID 0xFFFF 488 #define MAX_RVU_BLKLF_CNT 256 489 490 struct msix_offset_rsp { 491 struct mbox_msghdr hdr; 492 u16 npa_msixoff; 493 u16 nix_msixoff; 494 u16 sso; 495 u16 ssow; 496 u16 timlfs; 497 u16 cptlfs; 498 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 499 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 500 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 501 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 502 u16 cpt1_lfs; 503 u16 ree0_lfs; 504 u16 ree1_lfs; 505 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 506 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 507 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 508 }; 509 510 struct get_hw_cap_rsp { 511 struct mbox_msghdr hdr; 512 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 513 u8 nix_shaping; /* Is shaping and coloring supported */ 514 u8 npc_hash_extract; /* Is hash extract supported */ 515 }; 516 517 /* CGX mbox message formats */ 518 519 struct cgx_stats_rsp { 520 struct mbox_msghdr hdr; 521 #define CGX_RX_STATS_COUNT 9 522 #define CGX_TX_STATS_COUNT 18 523 u64 rx_stats[CGX_RX_STATS_COUNT]; 524 u64 tx_stats[CGX_TX_STATS_COUNT]; 525 }; 526 527 struct cgx_fec_stats_rsp { 528 struct mbox_msghdr hdr; 529 u64 fec_corr_blks; 530 u64 fec_uncorr_blks; 531 }; 532 /* Structure for requesting the operation for 533 * setting/getting mac address in the CGX interface 534 */ 535 struct cgx_mac_addr_set_or_get { 536 struct mbox_msghdr hdr; 537 u8 mac_addr[ETH_ALEN]; 538 u32 index; 539 }; 540 541 /* Structure for requesting the operation to 542 * add DMAC filter entry into CGX interface 543 */ 544 struct cgx_mac_addr_add_req { 545 struct mbox_msghdr hdr; 546 u8 mac_addr[ETH_ALEN]; 547 }; 548 549 /* Structure for response against the operation to 550 * add DMAC filter entry into CGX interface 551 */ 552 struct cgx_mac_addr_add_rsp { 553 struct mbox_msghdr hdr; 554 u32 index; 555 }; 556 557 /* Structure for requesting the operation to 558 * delete DMAC filter entry from CGX interface 559 */ 560 struct cgx_mac_addr_del_req { 561 struct mbox_msghdr hdr; 562 u32 index; 563 }; 564 565 /* Structure for response against the operation to 566 * get maximum supported DMAC filter entries 567 */ 568 struct cgx_max_dmac_entries_get_rsp { 569 struct mbox_msghdr hdr; 570 u32 max_dmac_filters; 571 }; 572 573 struct cgx_link_user_info { 574 uint64_t link_up:1; 575 uint64_t full_duplex:1; 576 uint64_t lmac_type_id:4; 577 uint64_t speed:20; /* speed in Mbps */ 578 uint64_t an:1; /* AN supported or not */ 579 uint64_t fec:2; /* FEC type if enabled else 0 */ 580 #define LMACTYPE_STR_LEN 16 581 char lmac_type[LMACTYPE_STR_LEN]; 582 }; 583 584 struct cgx_link_info_msg { 585 struct mbox_msghdr hdr; 586 struct cgx_link_user_info link_info; 587 }; 588 589 struct cgx_pause_frm_cfg { 590 struct mbox_msghdr hdr; 591 u8 set; 592 /* set = 1 if the request is to config pause frames */ 593 /* set = 0 if the request is to fetch pause frames config */ 594 u8 rx_pause; 595 u8 tx_pause; 596 }; 597 598 enum fec_type { 599 OTX2_FEC_NONE, 600 OTX2_FEC_BASER, 601 OTX2_FEC_RS, 602 OTX2_FEC_STATS_CNT = 2, 603 OTX2_FEC_OFF, 604 }; 605 606 struct fec_mode { 607 struct mbox_msghdr hdr; 608 int fec; 609 }; 610 611 struct sfp_eeprom_s { 612 #define SFP_EEPROM_SIZE 256 613 u16 sff_id; 614 u8 buf[SFP_EEPROM_SIZE]; 615 u64 reserved; 616 }; 617 618 struct phy_s { 619 struct { 620 u64 can_change_mod_type:1; 621 u64 mod_type:1; 622 u64 has_fec_stats:1; 623 } misc; 624 struct fec_stats_s { 625 u32 rsfec_corr_cws; 626 u32 rsfec_uncorr_cws; 627 u32 brfec_corr_blks; 628 u32 brfec_uncorr_blks; 629 } fec_stats; 630 }; 631 632 struct cgx_lmac_fwdata_s { 633 u16 rw_valid; 634 u64 supported_fec; 635 u64 supported_an; 636 u64 supported_link_modes; 637 /* only applicable if AN is supported */ 638 u64 advertised_fec; 639 u64 advertised_link_modes; 640 /* Only applicable if SFP/QSFP slot is present */ 641 struct sfp_eeprom_s sfp_eeprom; 642 struct phy_s phy; 643 #define LMAC_FWDATA_RESERVED_MEM 1021 644 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 645 }; 646 647 struct cgx_fw_data { 648 struct mbox_msghdr hdr; 649 struct cgx_lmac_fwdata_s fwdata; 650 }; 651 652 struct cgx_set_link_mode_args { 653 u32 speed; 654 u8 duplex; 655 u8 an; 656 u8 ports; 657 u64 mode; 658 }; 659 660 struct cgx_set_link_mode_req { 661 #define AUTONEG_UNKNOWN 0xff 662 struct mbox_msghdr hdr; 663 struct cgx_set_link_mode_args args; 664 }; 665 666 struct cgx_set_link_mode_rsp { 667 struct mbox_msghdr hdr; 668 int status; 669 }; 670 671 struct cgx_mac_addr_reset_req { 672 struct mbox_msghdr hdr; 673 u32 index; 674 }; 675 676 struct cgx_mac_addr_update_req { 677 struct mbox_msghdr hdr; 678 u8 mac_addr[ETH_ALEN]; 679 u32 index; 680 }; 681 682 struct cgx_mac_addr_update_rsp { 683 struct mbox_msghdr hdr; 684 u32 index; 685 }; 686 687 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 688 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 689 /* flow control from physical link higig2 messages */ 690 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 691 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 692 #define RVU_MAC_VERSION BIT_ULL(4) 693 #define RVU_MAC_CGX BIT_ULL(5) 694 #define RVU_MAC_RPM BIT_ULL(6) 695 696 struct cgx_features_info_msg { 697 struct mbox_msghdr hdr; 698 u64 lmac_features; 699 }; 700 701 struct rpm_stats_rsp { 702 struct mbox_msghdr hdr; 703 #define RPM_RX_STATS_COUNT 43 704 #define RPM_TX_STATS_COUNT 34 705 u64 rx_stats[RPM_RX_STATS_COUNT]; 706 u64 tx_stats[RPM_TX_STATS_COUNT]; 707 }; 708 709 struct cgx_pfc_cfg { 710 struct mbox_msghdr hdr; 711 u8 rx_pause; 712 u8 tx_pause; 713 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 714 }; 715 716 struct cgx_pfc_rsp { 717 struct mbox_msghdr hdr; 718 u8 rx_pause; 719 u8 tx_pause; 720 }; 721 722 /* NPA mbox message formats */ 723 724 struct npc_set_pkind { 725 struct mbox_msghdr hdr; 726 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 727 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 728 u64 mode; 729 #define PKIND_TX BIT_ULL(0) 730 #define PKIND_RX BIT_ULL(1) 731 u8 dir; 732 u8 pkind; /* valid only in case custom flag */ 733 u8 var_len_off; /* Offset of custom header length field. 734 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 735 */ 736 u8 var_len_off_mask; /* Mask for length with in offset */ 737 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 738 }; 739 740 /* NPA mbox message formats */ 741 742 /* NPA mailbox error codes 743 * Range 301 - 400. 744 */ 745 enum npa_af_status { 746 NPA_AF_ERR_PARAM = -301, 747 NPA_AF_ERR_AQ_FULL = -302, 748 NPA_AF_ERR_AQ_ENQUEUE = -303, 749 NPA_AF_ERR_AF_LF_INVALID = -304, 750 NPA_AF_ERR_AF_LF_ALLOC = -305, 751 NPA_AF_ERR_LF_RESET = -306, 752 }; 753 754 /* For NPA LF context alloc and init */ 755 struct npa_lf_alloc_req { 756 struct mbox_msghdr hdr; 757 int node; 758 int aura_sz; /* No of auras */ 759 u32 nr_pools; /* No of pools */ 760 u64 way_mask; 761 }; 762 763 struct npa_lf_alloc_rsp { 764 struct mbox_msghdr hdr; 765 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 766 u32 stack_pg_bytes; /* Size of stack page */ 767 u16 qints; /* NPA_AF_CONST::QINTS */ 768 u8 cache_lines; /*BATCH ALLOC DMA */ 769 }; 770 771 /* NPA AQ enqueue msg */ 772 struct npa_aq_enq_req { 773 struct mbox_msghdr hdr; 774 u32 aura_id; 775 u8 ctype; 776 u8 op; 777 union { 778 /* Valid when op == WRITE/INIT and ctype == AURA. 779 * LF fills the pool_id in aura.pool_addr. AF will translate 780 * the pool_id to pool context pointer. 781 */ 782 struct npa_aura_s aura; 783 /* Valid when op == WRITE/INIT and ctype == POOL */ 784 struct npa_pool_s pool; 785 }; 786 /* Mask data when op == WRITE (1=write, 0=don't write) */ 787 union { 788 /* Valid when op == WRITE and ctype == AURA */ 789 struct npa_aura_s aura_mask; 790 /* Valid when op == WRITE and ctype == POOL */ 791 struct npa_pool_s pool_mask; 792 }; 793 }; 794 795 struct npa_aq_enq_rsp { 796 struct mbox_msghdr hdr; 797 union { 798 /* Valid when op == READ and ctype == AURA */ 799 struct npa_aura_s aura; 800 /* Valid when op == READ and ctype == POOL */ 801 struct npa_pool_s pool; 802 }; 803 }; 804 805 /* Disable all contexts of type 'ctype' */ 806 struct hwctx_disable_req { 807 struct mbox_msghdr hdr; 808 u8 ctype; 809 }; 810 811 /* NIX mbox message formats */ 812 813 /* NIX mailbox error codes 814 * Range 401 - 500. 815 */ 816 enum nix_af_status { 817 NIX_AF_ERR_PARAM = -401, 818 NIX_AF_ERR_AQ_FULL = -402, 819 NIX_AF_ERR_AQ_ENQUEUE = -403, 820 NIX_AF_ERR_AF_LF_INVALID = -404, 821 NIX_AF_ERR_AF_LF_ALLOC = -405, 822 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 823 NIX_AF_ERR_TLX_INVALID = -407, 824 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 825 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 826 NIX_AF_ERR_FRS_INVALID = -410, 827 NIX_AF_ERR_RX_LINK_INVALID = -411, 828 NIX_AF_INVAL_TXSCHQ_CFG = -412, 829 NIX_AF_SMQ_FLUSH_FAILED = -413, 830 NIX_AF_ERR_LF_RESET = -414, 831 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 832 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 833 NIX_AF_ERR_MARK_CFG_FAIL = -417, 834 NIX_AF_ERR_LSO_CFG_FAIL = -418, 835 NIX_AF_INVAL_NPA_PF_FUNC = -419, 836 NIX_AF_INVAL_SSO_PF_FUNC = -420, 837 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 838 NIX_AF_ERR_RX_VTAG_INUSE = -422, 839 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 840 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 841 NIX_AF_ERR_INVALID_NIXBLK = -425, 842 NIX_AF_ERR_INVALID_BANDPROF = -426, 843 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 844 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 845 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 846 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 847 NIX_AF_ERR_LINK_CREDITS = -431, 848 NIX_AF_ERR_INVALID_BPID = -434, 849 NIX_AF_ERR_INVALID_BPID_REQ = -435, 850 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 851 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 852 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 853 }; 854 855 /* For NIX RX vtag action */ 856 enum nix_rx_vtag0_type { 857 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 858 NIX_AF_LFX_RX_VTAG_TYPE1, 859 NIX_AF_LFX_RX_VTAG_TYPE2, 860 NIX_AF_LFX_RX_VTAG_TYPE3, 861 NIX_AF_LFX_RX_VTAG_TYPE4, 862 NIX_AF_LFX_RX_VTAG_TYPE5, 863 NIX_AF_LFX_RX_VTAG_TYPE6, 864 NIX_AF_LFX_RX_VTAG_TYPE7, 865 }; 866 867 /* For NIX LF context alloc and init */ 868 struct nix_lf_alloc_req { 869 struct mbox_msghdr hdr; 870 int node; 871 u32 rq_cnt; /* No of receive queues */ 872 u32 sq_cnt; /* No of send queues */ 873 u32 cq_cnt; /* No of completion queues */ 874 u8 xqe_sz; 875 u16 rss_sz; 876 u8 rss_grps; 877 u16 npa_func; 878 u16 sso_func; 879 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 880 u64 way_mask; 881 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 882 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 883 u64 flags; 884 }; 885 886 struct nix_lf_alloc_rsp { 887 struct mbox_msghdr hdr; 888 u16 sqb_size; 889 u16 rx_chan_base; 890 u16 tx_chan_base; 891 u8 rx_chan_cnt; /* total number of RX channels */ 892 u8 tx_chan_cnt; /* total number of TX channels */ 893 u8 lso_tsov4_idx; 894 u8 lso_tsov6_idx; 895 u8 mac_addr[ETH_ALEN]; 896 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 897 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 898 u16 cints; /* NIX_AF_CONST2::CINTS */ 899 u16 qints; /* NIX_AF_CONST2::QINTS */ 900 u8 cgx_links; /* No. of CGX links present in HW */ 901 u8 lbk_links; /* No. of LBK links present in HW */ 902 u8 sdp_links; /* No. of SDP links present in HW */ 903 u8 tx_link; /* Transmit channel link number */ 904 }; 905 906 struct nix_lf_free_req { 907 struct mbox_msghdr hdr; 908 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 909 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 910 u64 flags; 911 }; 912 913 /* CN10K NIX AQ enqueue msg */ 914 struct nix_cn10k_aq_enq_req { 915 struct mbox_msghdr hdr; 916 u32 qidx; 917 u8 ctype; 918 u8 op; 919 union { 920 struct nix_cn10k_rq_ctx_s rq; 921 struct nix_cn10k_sq_ctx_s sq; 922 struct nix_cq_ctx_s cq; 923 struct nix_rsse_s rss; 924 struct nix_rx_mce_s mce; 925 struct nix_bandprof_s prof; 926 }; 927 union { 928 struct nix_cn10k_rq_ctx_s rq_mask; 929 struct nix_cn10k_sq_ctx_s sq_mask; 930 struct nix_cq_ctx_s cq_mask; 931 struct nix_rsse_s rss_mask; 932 struct nix_rx_mce_s mce_mask; 933 struct nix_bandprof_s prof_mask; 934 }; 935 }; 936 937 struct nix_cn10k_aq_enq_rsp { 938 struct mbox_msghdr hdr; 939 union { 940 struct nix_cn10k_rq_ctx_s rq; 941 struct nix_cn10k_sq_ctx_s sq; 942 struct nix_cq_ctx_s cq; 943 struct nix_rsse_s rss; 944 struct nix_rx_mce_s mce; 945 struct nix_bandprof_s prof; 946 }; 947 }; 948 949 /* NIX AQ enqueue msg */ 950 struct nix_aq_enq_req { 951 struct mbox_msghdr hdr; 952 u32 qidx; 953 u8 ctype; 954 u8 op; 955 union { 956 struct nix_rq_ctx_s rq; 957 struct nix_sq_ctx_s sq; 958 struct nix_cq_ctx_s cq; 959 struct nix_rsse_s rss; 960 struct nix_rx_mce_s mce; 961 struct nix_bandprof_s prof; 962 }; 963 union { 964 struct nix_rq_ctx_s rq_mask; 965 struct nix_sq_ctx_s sq_mask; 966 struct nix_cq_ctx_s cq_mask; 967 struct nix_rsse_s rss_mask; 968 struct nix_rx_mce_s mce_mask; 969 struct nix_bandprof_s prof_mask; 970 }; 971 }; 972 973 struct nix_aq_enq_rsp { 974 struct mbox_msghdr hdr; 975 union { 976 struct nix_rq_ctx_s rq; 977 struct nix_sq_ctx_s sq; 978 struct nix_cq_ctx_s cq; 979 struct nix_rsse_s rss; 980 struct nix_rx_mce_s mce; 981 struct nix_bandprof_s prof; 982 }; 983 }; 984 985 /* Tx scheduler/shaper mailbox messages */ 986 987 #define MAX_TXSCHQ_PER_FUNC 128 988 989 struct nix_txsch_alloc_req { 990 struct mbox_msghdr hdr; 991 /* Scheduler queue count request at each level */ 992 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 993 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 994 }; 995 996 struct nix_txsch_alloc_rsp { 997 struct mbox_msghdr hdr; 998 /* Scheduler queue count allocated at each level */ 999 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 1000 u16 schq[NIX_TXSCH_LVL_CNT]; 1001 /* Scheduler queue list allocated at each level */ 1002 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1003 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1004 u8 aggr_level; /* Traffic aggregation scheduler level */ 1005 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 1006 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 1007 }; 1008 1009 struct nix_txsch_free_req { 1010 struct mbox_msghdr hdr; 1011 #define TXSCHQ_FREE_ALL BIT_ULL(0) 1012 u16 flags; 1013 /* Scheduler queue level to be freed */ 1014 u16 schq_lvl; 1015 /* List of scheduler queues to be freed */ 1016 u16 schq; 1017 }; 1018 1019 struct nix_txschq_config { 1020 struct mbox_msghdr hdr; 1021 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1022 u8 read; 1023 #define TXSCHQ_IDX_SHIFT 16 1024 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1025 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1026 u8 num_regs; 1027 #define MAX_REGS_PER_MBOX_MSG 20 1028 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1029 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1030 /* All 0's => overwrite with new value */ 1031 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1032 }; 1033 1034 struct nix_vtag_config { 1035 struct mbox_msghdr hdr; 1036 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1037 u8 vtag_size; 1038 /* cfg_type is '0' for tx vlan cfg 1039 * cfg_type is '1' for rx vlan cfg 1040 */ 1041 u8 cfg_type; 1042 union { 1043 /* valid when cfg_type is '0' */ 1044 struct { 1045 u64 vtag0; 1046 u64 vtag1; 1047 1048 /* cfg_vtag0 & cfg_vtag1 fields are valid 1049 * when free_vtag0 & free_vtag1 are '0's. 1050 */ 1051 /* cfg_vtag0 = 1 to configure vtag0 */ 1052 u8 cfg_vtag0 :1; 1053 /* cfg_vtag1 = 1 to configure vtag1 */ 1054 u8 cfg_vtag1 :1; 1055 1056 /* vtag0_idx & vtag1_idx are only valid when 1057 * both cfg_vtag0 & cfg_vtag1 are '0's, 1058 * these fields are used along with free_vtag0 1059 * & free_vtag1 to free the nix lf's tx_vlan 1060 * configuration. 1061 * 1062 * Denotes the indices of tx_vtag def registers 1063 * that needs to be cleared and freed. 1064 */ 1065 int vtag0_idx; 1066 int vtag1_idx; 1067 1068 /* free_vtag0 & free_vtag1 fields are valid 1069 * when cfg_vtag0 & cfg_vtag1 are '0's. 1070 */ 1071 /* free_vtag0 = 1 clears vtag0 configuration 1072 * vtag0_idx denotes the index to be cleared. 1073 */ 1074 u8 free_vtag0 :1; 1075 /* free_vtag1 = 1 clears vtag1 configuration 1076 * vtag1_idx denotes the index to be cleared. 1077 */ 1078 u8 free_vtag1 :1; 1079 } tx; 1080 1081 /* valid when cfg_type is '1' */ 1082 struct { 1083 /* rx vtag type index, valid values are in 0..7 range */ 1084 u8 vtag_type; 1085 /* rx vtag strip */ 1086 u8 strip_vtag :1; 1087 /* rx vtag capture */ 1088 u8 capture_vtag :1; 1089 } rx; 1090 }; 1091 }; 1092 1093 struct nix_vtag_config_rsp { 1094 struct mbox_msghdr hdr; 1095 int vtag0_idx; 1096 int vtag1_idx; 1097 /* Indices of tx_vtag def registers used to configure 1098 * tx vtag0 & vtag1 headers, these indices are valid 1099 * when nix_vtag_config mbox requested for vtag0 and/ 1100 * or vtag1 configuration. 1101 */ 1102 }; 1103 1104 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1105 1106 struct nix_rss_flowkey_cfg { 1107 struct mbox_msghdr hdr; 1108 int mcam_index; /* MCAM entry index to modify */ 1109 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1110 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1111 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1112 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1113 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1114 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1115 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1116 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1117 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1118 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1119 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1120 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1121 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1122 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1123 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1124 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1125 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1126 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1127 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1128 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1129 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1130 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1131 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1132 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1133 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1134 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1135 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1136 u32 flowkey_cfg; /* Flowkey types selected */ 1137 u8 group; /* RSS context or group */ 1138 }; 1139 1140 struct nix_rss_flowkey_cfg_rsp { 1141 struct mbox_msghdr hdr; 1142 u8 alg_idx; /* Selected algo index */ 1143 }; 1144 1145 struct nix_set_mac_addr { 1146 struct mbox_msghdr hdr; 1147 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1148 }; 1149 1150 struct nix_get_mac_addr_rsp { 1151 struct mbox_msghdr hdr; 1152 u8 mac_addr[ETH_ALEN]; 1153 }; 1154 1155 struct nix_mark_format_cfg { 1156 struct mbox_msghdr hdr; 1157 u8 offset; 1158 u8 y_mask; 1159 u8 y_val; 1160 u8 r_mask; 1161 u8 r_val; 1162 }; 1163 1164 struct nix_mark_format_cfg_rsp { 1165 struct mbox_msghdr hdr; 1166 u8 mark_format_idx; 1167 }; 1168 1169 struct nix_rx_mode { 1170 struct mbox_msghdr hdr; 1171 #define NIX_RX_MODE_UCAST BIT(0) 1172 #define NIX_RX_MODE_PROMISC BIT(1) 1173 #define NIX_RX_MODE_ALLMULTI BIT(2) 1174 #define NIX_RX_MODE_USE_MCE BIT(3) 1175 u16 mode; 1176 }; 1177 1178 struct nix_rx_cfg { 1179 struct mbox_msghdr hdr; 1180 #define NIX_RX_OL3_VERIFY BIT(0) 1181 #define NIX_RX_OL4_VERIFY BIT(1) 1182 #define NIX_RX_DROP_RE BIT(2) 1183 u8 len_verify; /* Outer L3/L4 len check */ 1184 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1185 u8 csum_verify; /* Outer L4 checksum verification */ 1186 }; 1187 1188 struct nix_frs_cfg { 1189 struct mbox_msghdr hdr; 1190 u8 update_smq; /* Update SMQ's min/max lens */ 1191 u8 update_minlen; /* Set minlen also */ 1192 u8 sdp_link; /* Set SDP RX link */ 1193 u16 maxlen; 1194 u16 minlen; 1195 }; 1196 1197 struct nix_lso_format_cfg { 1198 struct mbox_msghdr hdr; 1199 u64 field_mask; 1200 #define NIX_LSO_FIELD_MAX 8 1201 u64 fields[NIX_LSO_FIELD_MAX]; 1202 }; 1203 1204 struct nix_lso_format_cfg_rsp { 1205 struct mbox_msghdr hdr; 1206 u8 lso_format_idx; 1207 }; 1208 1209 struct nix_bp_cfg_req { 1210 struct mbox_msghdr hdr; 1211 u16 chan_base; /* Starting channel number */ 1212 u8 chan_cnt; /* Number of channels */ 1213 u8 bpid_per_chan; 1214 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1215 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1216 }; 1217 1218 /* Maximum channels any single NIX interface can have */ 1219 #define NIX_MAX_BPID_CHAN 256 1220 struct nix_bp_cfg_rsp { 1221 struct mbox_msghdr hdr; 1222 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1223 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1224 }; 1225 1226 struct nix_mcast_grp_create_req { 1227 struct mbox_msghdr hdr; 1228 #define NIX_MCAST_INGRESS 0 1229 #define NIX_MCAST_EGRESS 1 1230 u8 dir; 1231 u8 reserved[11]; 1232 /* Reserving few bytes for future requirement */ 1233 }; 1234 1235 struct nix_mcast_grp_create_rsp { 1236 struct mbox_msghdr hdr; 1237 /* This mcast_grp_idx should be passed during MCAM 1238 * write entry for multicast. AF will identify the 1239 * corresponding multicast table index associated 1240 * with the group id and program the same to MCAM entry. 1241 * This group id is also needed during group delete 1242 * and update request. 1243 */ 1244 u32 mcast_grp_idx; 1245 }; 1246 1247 struct nix_mcast_grp_destroy_req { 1248 struct mbox_msghdr hdr; 1249 /* Group id returned by nix_mcast_grp_create_rsp */ 1250 u32 mcast_grp_idx; 1251 /* If AF is requesting for destroy, then set 1252 * it to '1'. Otherwise keep it to '0' 1253 */ 1254 u8 is_af; 1255 }; 1256 1257 struct nix_mcast_grp_update_req { 1258 struct mbox_msghdr hdr; 1259 /* Group id returned by nix_mcast_grp_create_rsp */ 1260 u32 mcast_grp_idx; 1261 /* Number of multicast/mirror entries requested */ 1262 u32 num_mce_entry; 1263 #define NIX_MCE_ENTRY_MAX 64 1264 #define NIX_RX_RQ 0 1265 #define NIX_RX_RSS 1 1266 /* Receive queue or RSS index within pf_func */ 1267 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1268 /* pcifunc is required for both ingress and egress multicast */ 1269 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1270 /* channel is required for egress multicast */ 1271 u16 channel[NIX_MCE_ENTRY_MAX]; 1272 #define NIX_MCAST_OP_ADD_ENTRY 0 1273 #define NIX_MCAST_OP_DEL_ENTRY 1 1274 /* Destination type. 0:Receive queue, 1:RSS*/ 1275 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1276 u8 op; 1277 /* If AF is requesting for update, then set 1278 * it to '1'. Otherwise keep it to '0' 1279 */ 1280 u8 is_af; 1281 }; 1282 1283 struct nix_mcast_grp_update_rsp { 1284 struct mbox_msghdr hdr; 1285 u32 mce_start_index; 1286 }; 1287 1288 /* Global NIX inline IPSec configuration */ 1289 struct nix_inline_ipsec_cfg { 1290 struct mbox_msghdr hdr; 1291 u32 cpt_credit; 1292 struct { 1293 u8 egrp; 1294 u16 opcode; 1295 u16 param1; 1296 u16 param2; 1297 } gen_cfg; 1298 struct { 1299 u16 cpt_pf_func; 1300 u8 cpt_slot; 1301 } inst_qsel; 1302 u8 enable; 1303 u16 bpid; 1304 u32 credit_th; 1305 }; 1306 1307 /* Per NIX LF inline IPSec configuration */ 1308 struct nix_inline_ipsec_lf_cfg { 1309 struct mbox_msghdr hdr; 1310 u64 sa_base_addr; 1311 struct { 1312 u32 tag_const; 1313 u16 lenm1_max; 1314 u8 sa_pow2_size; 1315 u8 tt; 1316 } ipsec_cfg0; 1317 struct { 1318 u32 sa_idx_max; 1319 u8 sa_idx_w; 1320 } ipsec_cfg1; 1321 u8 enable; 1322 }; 1323 1324 struct nix_hw_info { 1325 struct mbox_msghdr hdr; 1326 u16 rsvs16; 1327 u16 max_mtu; 1328 u16 min_mtu; 1329 u32 rpm_dwrr_mtu; 1330 u32 sdp_dwrr_mtu; 1331 u32 lbk_dwrr_mtu; 1332 u32 rsvd32[1]; 1333 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1334 }; 1335 1336 struct nix_bandprof_alloc_req { 1337 struct mbox_msghdr hdr; 1338 /* Count of profiles needed per layer */ 1339 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1340 }; 1341 1342 struct nix_bandprof_alloc_rsp { 1343 struct mbox_msghdr hdr; 1344 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1345 1346 /* There is no need to allocate morethan 1 bandwidth profile 1347 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1348 * profiles to 64 per PF_FUNC. 1349 */ 1350 #define MAX_BANDPROF_PER_PFFUNC 64 1351 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1352 }; 1353 1354 struct nix_bandprof_free_req { 1355 struct mbox_msghdr hdr; 1356 u8 free_all; 1357 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1358 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1359 }; 1360 1361 struct nix_bandprof_get_hwinfo_rsp { 1362 struct mbox_msghdr hdr; 1363 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1364 u32 policer_timeunit; 1365 }; 1366 1367 /* NPC mbox message structs */ 1368 1369 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1370 #define NPC_MCAM_INVALID_MAP 0xFFFF 1371 1372 /* NPC mailbox error codes 1373 * Range 701 - 800. 1374 */ 1375 enum npc_af_status { 1376 NPC_MCAM_INVALID_REQ = -701, 1377 NPC_MCAM_ALLOC_DENIED = -702, 1378 NPC_MCAM_ALLOC_FAILED = -703, 1379 NPC_MCAM_PERM_DENIED = -704, 1380 NPC_FLOW_INTF_INVALID = -707, 1381 NPC_FLOW_CHAN_INVALID = -708, 1382 NPC_FLOW_NO_NIXLF = -709, 1383 NPC_FLOW_NOT_SUPPORTED = -710, 1384 NPC_FLOW_VF_PERM_DENIED = -711, 1385 NPC_FLOW_VF_NOT_INIT = -712, 1386 NPC_FLOW_VF_OVERLAP = -713, 1387 }; 1388 1389 struct npc_mcam_alloc_entry_req { 1390 struct mbox_msghdr hdr; 1391 #define NPC_MAX_NONCONTIG_ENTRIES 256 1392 u8 contig; /* Contiguous entries ? */ 1393 #define NPC_MCAM_ANY_PRIO 0 1394 #define NPC_MCAM_LOWER_PRIO 1 1395 #define NPC_MCAM_HIGHER_PRIO 2 1396 u8 priority; /* Lower or higher w.r.t ref_entry */ 1397 u16 ref_entry; 1398 u16 count; /* Number of entries requested */ 1399 }; 1400 1401 struct npc_mcam_alloc_entry_rsp { 1402 struct mbox_msghdr hdr; 1403 u16 entry; /* Entry allocated or start index if contiguous. 1404 * Invalid incase of non-contiguous. 1405 */ 1406 u16 count; /* Number of entries allocated */ 1407 u16 free_count; /* Number of entries available */ 1408 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1409 }; 1410 1411 struct npc_mcam_free_entry_req { 1412 struct mbox_msghdr hdr; 1413 u16 entry; /* Entry index to be freed */ 1414 u8 all; /* If all entries allocated to this PFVF to be freed */ 1415 }; 1416 1417 struct mcam_entry { 1418 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1419 u64 kw[NPC_MAX_KWS_IN_KEY]; 1420 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1421 u64 action; 1422 u64 vtag_action; 1423 }; 1424 1425 struct npc_mcam_write_entry_req { 1426 struct mbox_msghdr hdr; 1427 struct mcam_entry entry_data; 1428 u16 entry; /* MCAM entry to write this match key */ 1429 u16 cntr; /* Counter for this MCAM entry */ 1430 u8 intf; /* Rx or Tx interface */ 1431 u8 enable_entry;/* Enable this MCAM entry ? */ 1432 u8 set_cntr; /* Set counter for this entry ? */ 1433 }; 1434 1435 /* Enable/Disable a given entry */ 1436 struct npc_mcam_ena_dis_entry_req { 1437 struct mbox_msghdr hdr; 1438 u16 entry; 1439 }; 1440 1441 struct npc_mcam_shift_entry_req { 1442 struct mbox_msghdr hdr; 1443 #define NPC_MCAM_MAX_SHIFTS 64 1444 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1445 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1446 u16 shift_count; /* Number of entries to shift */ 1447 }; 1448 1449 struct npc_mcam_shift_entry_rsp { 1450 struct mbox_msghdr hdr; 1451 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1452 }; 1453 1454 struct npc_mcam_alloc_counter_req { 1455 struct mbox_msghdr hdr; 1456 u8 contig; /* Contiguous counters ? */ 1457 #define NPC_MAX_NONCONTIG_COUNTERS 64 1458 u16 count; /* Number of counters requested */ 1459 }; 1460 1461 struct npc_mcam_alloc_counter_rsp { 1462 struct mbox_msghdr hdr; 1463 u16 cntr; /* Counter allocated or start index if contiguous. 1464 * Invalid incase of non-contiguous. 1465 */ 1466 u16 count; /* Number of counters allocated */ 1467 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1468 }; 1469 1470 struct npc_mcam_oper_counter_req { 1471 struct mbox_msghdr hdr; 1472 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1473 }; 1474 1475 struct npc_mcam_oper_counter_rsp { 1476 struct mbox_msghdr hdr; 1477 u64 stat; /* valid only while fetching counter's stats */ 1478 }; 1479 1480 struct npc_mcam_unmap_counter_req { 1481 struct mbox_msghdr hdr; 1482 u16 cntr; 1483 u16 entry; /* Entry and counter to be unmapped */ 1484 u8 all; /* Unmap all entries using this counter ? */ 1485 }; 1486 1487 struct npc_mcam_alloc_and_write_entry_req { 1488 struct mbox_msghdr hdr; 1489 struct mcam_entry entry_data; 1490 u16 ref_entry; 1491 u8 priority; /* Lower or higher w.r.t ref_entry */ 1492 u8 intf; /* Rx or Tx interface */ 1493 u8 enable_entry;/* Enable this MCAM entry ? */ 1494 u8 alloc_cntr; /* Allocate counter and map ? */ 1495 }; 1496 1497 struct npc_mcam_alloc_and_write_entry_rsp { 1498 struct mbox_msghdr hdr; 1499 u16 entry; 1500 u16 cntr; 1501 }; 1502 1503 struct npc_get_kex_cfg_rsp { 1504 struct mbox_msghdr hdr; 1505 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1506 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1507 #define NPC_MAX_INTF 2 1508 #define NPC_MAX_LID 8 1509 #define NPC_MAX_LT 16 1510 #define NPC_MAX_LD 2 1511 #define NPC_MAX_LFL 16 1512 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1513 u64 kex_ld_flags[NPC_MAX_LD]; 1514 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1515 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1516 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1517 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1518 #define MKEX_NAME_LEN 128 1519 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1520 }; 1521 1522 struct ptp_get_cap_rsp { 1523 struct mbox_msghdr hdr; 1524 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1525 u64 cap; 1526 }; 1527 1528 struct flow_msg { 1529 unsigned char dmac[6]; 1530 unsigned char smac[6]; 1531 __be16 etype; 1532 __be16 vlan_etype; 1533 __be16 vlan_tci; 1534 union { 1535 __be32 ip4src; 1536 __be32 ip6src[4]; 1537 }; 1538 union { 1539 __be32 ip4dst; 1540 __be32 ip6dst[4]; 1541 }; 1542 union { 1543 __be32 spi; 1544 }; 1545 1546 u8 tos; 1547 u8 ip_ver; 1548 u8 ip_proto; 1549 u8 tc; 1550 __be16 sport; 1551 __be16 dport; 1552 union { 1553 u8 ip_flag; 1554 u8 next_header; 1555 }; 1556 __be16 vlan_itci; 1557 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1558 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1559 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1560 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1561 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1562 u32 mpls_lse[4]; 1563 u8 icmp_type; 1564 u8 icmp_code; 1565 __be16 tcp_flags; 1566 }; 1567 1568 struct npc_install_flow_req { 1569 struct mbox_msghdr hdr; 1570 struct flow_msg packet; 1571 struct flow_msg mask; 1572 u64 features; 1573 u16 entry; 1574 u16 channel; 1575 u16 chan_mask; 1576 u8 intf; 1577 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1578 u8 default_rule; 1579 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1580 u16 vf; 1581 /* action */ 1582 u32 index; 1583 u16 match_id; 1584 u8 flow_key_alg; 1585 u8 op; 1586 /* vtag rx action */ 1587 u8 vtag0_type; 1588 u8 vtag0_valid; 1589 u8 vtag1_type; 1590 u8 vtag1_valid; 1591 /* vtag tx action */ 1592 u16 vtag0_def; 1593 u8 vtag0_op; 1594 u16 vtag1_def; 1595 u8 vtag1_op; 1596 /* old counter value */ 1597 u16 cntr_val; 1598 }; 1599 1600 struct npc_install_flow_rsp { 1601 struct mbox_msghdr hdr; 1602 int counter; /* negative if no counter else counter number */ 1603 }; 1604 1605 struct npc_delete_flow_req { 1606 struct mbox_msghdr hdr; 1607 u16 entry; 1608 u16 start;/*Disable range of entries */ 1609 u16 end; 1610 u8 all; /* PF + VFs */ 1611 }; 1612 1613 struct npc_delete_flow_rsp { 1614 struct mbox_msghdr hdr; 1615 u16 cntr_val; 1616 }; 1617 1618 struct npc_mcam_read_entry_req { 1619 struct mbox_msghdr hdr; 1620 u16 entry; /* MCAM entry to read */ 1621 }; 1622 1623 struct npc_mcam_read_entry_rsp { 1624 struct mbox_msghdr hdr; 1625 struct mcam_entry entry_data; 1626 u8 intf; 1627 u8 enable; 1628 }; 1629 1630 struct npc_mcam_read_base_rule_rsp { 1631 struct mbox_msghdr hdr; 1632 struct mcam_entry entry; 1633 }; 1634 1635 struct npc_mcam_get_stats_req { 1636 struct mbox_msghdr hdr; 1637 u16 entry; /* mcam entry */ 1638 }; 1639 1640 struct npc_mcam_get_stats_rsp { 1641 struct mbox_msghdr hdr; 1642 u64 stat; /* counter stats */ 1643 u8 stat_ena; /* enabled */ 1644 }; 1645 1646 struct npc_get_field_hash_info_req { 1647 struct mbox_msghdr hdr; 1648 u8 intf; 1649 }; 1650 1651 struct npc_get_field_hash_info_rsp { 1652 struct mbox_msghdr hdr; 1653 u64 secret_key[3]; 1654 #define NPC_MAX_HASH 2 1655 #define NPC_MAX_HASH_MASK 2 1656 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1657 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1658 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1659 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1660 }; 1661 1662 enum ptp_op { 1663 PTP_OP_ADJFINE = 0, 1664 PTP_OP_GET_CLOCK = 1, 1665 PTP_OP_GET_TSTMP = 2, 1666 PTP_OP_SET_THRESH = 3, 1667 PTP_OP_PPS_ON = 4, 1668 PTP_OP_ADJTIME = 5, 1669 PTP_OP_SET_CLOCK = 6, 1670 }; 1671 1672 struct ptp_req { 1673 struct mbox_msghdr hdr; 1674 u8 op; 1675 s64 scaled_ppm; 1676 u64 thresh; 1677 u64 period; 1678 int pps_on; 1679 s64 delta; 1680 u64 clk; 1681 }; 1682 1683 struct ptp_rsp { 1684 struct mbox_msghdr hdr; 1685 u64 clk; 1686 u64 tsc; 1687 }; 1688 1689 struct npc_get_field_status_req { 1690 struct mbox_msghdr hdr; 1691 u8 intf; 1692 u8 field; 1693 }; 1694 1695 struct npc_get_field_status_rsp { 1696 struct mbox_msghdr hdr; 1697 u8 enable; 1698 }; 1699 1700 struct set_vf_perm { 1701 struct mbox_msghdr hdr; 1702 u16 vf; 1703 #define RESET_VF_PERM BIT_ULL(0) 1704 #define VF_TRUSTED BIT_ULL(1) 1705 u64 flags; 1706 }; 1707 1708 struct lmtst_tbl_setup_req { 1709 struct mbox_msghdr hdr; 1710 u64 dis_sched_early_comp :1; 1711 u64 sch_ena :1; 1712 u64 dis_line_pref :1; 1713 u64 ssow_pf_func :13; 1714 u16 base_pcifunc; 1715 u8 use_local_lmt_region; 1716 u64 lmt_iova; 1717 u64 rsvd[4]; 1718 }; 1719 1720 struct ndc_sync_op { 1721 struct mbox_msghdr hdr; 1722 u8 nix_lf_tx_sync; 1723 u8 nix_lf_rx_sync; 1724 u8 npa_lf_sync; 1725 }; 1726 1727 /* CPT mailbox error codes 1728 * Range 901 - 1000. 1729 */ 1730 enum cpt_af_status { 1731 CPT_AF_ERR_PARAM = -901, 1732 CPT_AF_ERR_GRP_INVALID = -902, 1733 CPT_AF_ERR_LF_INVALID = -903, 1734 CPT_AF_ERR_ACCESS_DENIED = -904, 1735 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1736 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1737 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1738 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1739 }; 1740 1741 /* CPT mbox message formats */ 1742 struct cpt_rd_wr_reg_msg { 1743 struct mbox_msghdr hdr; 1744 u64 reg_offset; 1745 u64 *ret_val; 1746 u64 val; 1747 u8 is_write; 1748 int blkaddr; 1749 }; 1750 1751 struct cpt_lf_alloc_req_msg { 1752 struct mbox_msghdr hdr; 1753 u16 nix_pf_func; 1754 u16 sso_pf_func; 1755 u16 eng_grpmsk; 1756 u8 blkaddr; 1757 u8 ctx_ilen_valid : 1; 1758 u8 ctx_ilen : 7; 1759 }; 1760 1761 #define CPT_INLINE_INBOUND 0 1762 #define CPT_INLINE_OUTBOUND 1 1763 1764 /* Mailbox message request format for CPT IPsec 1765 * inline inbound and outbound configuration. 1766 */ 1767 struct cpt_inline_ipsec_cfg_msg { 1768 struct mbox_msghdr hdr; 1769 u8 enable; 1770 u8 slot; 1771 u8 dir; 1772 u8 sso_pf_func_ovrd; 1773 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1774 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1775 }; 1776 1777 /* Mailbox message request and response format for CPT stats. */ 1778 struct cpt_sts_req { 1779 struct mbox_msghdr hdr; 1780 u8 blkaddr; 1781 }; 1782 1783 struct cpt_sts_rsp { 1784 struct mbox_msghdr hdr; 1785 u64 inst_req_pc; 1786 u64 inst_lat_pc; 1787 u64 rd_req_pc; 1788 u64 rd_lat_pc; 1789 u64 rd_uc_pc; 1790 u64 active_cycles_pc; 1791 u64 ctx_mis_pc; 1792 u64 ctx_hit_pc; 1793 u64 ctx_aop_pc; 1794 u64 ctx_aop_lat_pc; 1795 u64 ctx_ifetch_pc; 1796 u64 ctx_ifetch_lat_pc; 1797 u64 ctx_ffetch_pc; 1798 u64 ctx_ffetch_lat_pc; 1799 u64 ctx_wback_pc; 1800 u64 ctx_wback_lat_pc; 1801 u64 ctx_psh_pc; 1802 u64 ctx_psh_lat_pc; 1803 u64 ctx_err; 1804 u64 ctx_enc_id; 1805 u64 ctx_flush_timer; 1806 u64 rxc_time; 1807 u64 rxc_time_cfg; 1808 u64 rxc_active_sts; 1809 u64 rxc_zombie_sts; 1810 u64 busy_sts_ae; 1811 u64 free_sts_ae; 1812 u64 busy_sts_se; 1813 u64 free_sts_se; 1814 u64 busy_sts_ie; 1815 u64 free_sts_ie; 1816 u64 exe_err_info; 1817 u64 cptclk_cnt; 1818 u64 diag; 1819 u64 rxc_dfrg; 1820 u64 x2p_link_cfg0; 1821 u64 x2p_link_cfg1; 1822 }; 1823 1824 /* Mailbox message request format to configure reassembly timeout. */ 1825 struct cpt_rxc_time_cfg_req { 1826 struct mbox_msghdr hdr; 1827 int blkaddr; 1828 u32 step; 1829 u16 zombie_thres; 1830 u16 zombie_limit; 1831 u16 active_thres; 1832 u16 active_limit; 1833 }; 1834 1835 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1836 struct cpt_inst_lmtst_req { 1837 struct mbox_msghdr hdr; 1838 u64 inst[8]; 1839 u64 rsvd; 1840 }; 1841 1842 /* Mailbox message format to request for CPT LF reset */ 1843 struct cpt_lf_rst_req { 1844 struct mbox_msghdr hdr; 1845 u32 slot; 1846 u32 rsvd; 1847 }; 1848 1849 /* Mailbox message format to request for CPT faulted engines */ 1850 struct cpt_flt_eng_info_req { 1851 struct mbox_msghdr hdr; 1852 int blkaddr; 1853 bool reset; 1854 u32 rsvd; 1855 }; 1856 1857 struct cpt_flt_eng_info_rsp { 1858 struct mbox_msghdr hdr; 1859 #define CPT_AF_MAX_FLT_INT_VECS 3 1860 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1861 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1862 u64 rsvd; 1863 }; 1864 1865 struct sdp_node_info { 1866 /* Node to which this PF belons to */ 1867 u8 node_id; 1868 u8 max_vfs; 1869 u8 num_pf_rings; 1870 u8 pf_srn; 1871 #define SDP_MAX_VFS 128 1872 u8 vf_rings[SDP_MAX_VFS]; 1873 }; 1874 1875 struct sdp_chan_info_msg { 1876 struct mbox_msghdr hdr; 1877 struct sdp_node_info info; 1878 }; 1879 1880 struct sdp_get_chan_info_msg { 1881 struct mbox_msghdr hdr; 1882 u16 chan_base; 1883 u16 num_chan; 1884 }; 1885 1886 /* CGX mailbox error codes 1887 * Range 1101 - 1200. 1888 */ 1889 enum cgx_af_status { 1890 LMAC_AF_ERR_INVALID_PARAM = -1101, 1891 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1892 LMAC_AF_ERR_PERM_DENIED = -1103, 1893 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1894 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1895 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1896 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1897 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1898 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1899 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1900 }; 1901 1902 enum mcs_direction { 1903 MCS_RX, 1904 MCS_TX, 1905 }; 1906 1907 enum mcs_rsrc_type { 1908 MCS_RSRC_TYPE_FLOWID, 1909 MCS_RSRC_TYPE_SECY, 1910 MCS_RSRC_TYPE_SC, 1911 MCS_RSRC_TYPE_SA, 1912 }; 1913 1914 struct mcs_alloc_rsrc_req { 1915 struct mbox_msghdr hdr; 1916 u8 rsrc_type; 1917 u8 rsrc_cnt; /* Resources count */ 1918 u8 mcs_id; /* MCS block ID */ 1919 u8 dir; /* Macsec ingress or egress side */ 1920 u8 all; /* Allocate all resource type one each */ 1921 u64 rsvd; 1922 }; 1923 1924 struct mcs_alloc_rsrc_rsp { 1925 struct mbox_msghdr hdr; 1926 u8 flow_ids[128]; /* Index of reserved entries */ 1927 u8 secy_ids[128]; 1928 u8 sc_ids[128]; 1929 u8 sa_ids[256]; 1930 u8 rsrc_type; 1931 u8 rsrc_cnt; /* No of entries reserved */ 1932 u8 mcs_id; 1933 u8 dir; 1934 u8 all; 1935 u8 rsvd[256]; /* reserved fields for future expansion */ 1936 }; 1937 1938 struct mcs_free_rsrc_req { 1939 struct mbox_msghdr hdr; 1940 u8 rsrc_id; /* Index of the entry to be freed */ 1941 u8 rsrc_type; 1942 u8 mcs_id; 1943 u8 dir; 1944 u8 all; /* Free all the cam resources */ 1945 u64 rsvd; 1946 }; 1947 1948 struct mcs_flowid_entry_write_req { 1949 struct mbox_msghdr hdr; 1950 u64 data[4]; 1951 u64 mask[4]; 1952 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1953 u8 flow_id; 1954 u8 secy_id; /* secyid for which flowid is mapped */ 1955 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1956 u8 ena; /* Enable tcam entry */ 1957 u8 ctrl_pkt; 1958 u8 mcs_id; 1959 u8 dir; 1960 u64 rsvd; 1961 }; 1962 1963 struct mcs_secy_plcy_write_req { 1964 struct mbox_msghdr hdr; 1965 u64 plcy; 1966 u8 secy_id; 1967 u8 mcs_id; 1968 u8 dir; 1969 u64 rsvd; 1970 }; 1971 1972 /* RX SC_CAM mapping */ 1973 struct mcs_rx_sc_cam_write_req { 1974 struct mbox_msghdr hdr; 1975 u64 sci; /* SCI */ 1976 u64 secy_id; /* secy index mapped to SC */ 1977 u8 sc_id; /* SC CAM entry index */ 1978 u8 mcs_id; 1979 u64 rsvd; 1980 }; 1981 1982 struct mcs_sa_plcy_write_req { 1983 struct mbox_msghdr hdr; 1984 u64 plcy[2][9]; /* Support 2 SA policy */ 1985 u8 sa_index[2]; 1986 u8 sa_cnt; 1987 u8 mcs_id; 1988 u8 dir; 1989 u64 rsvd; 1990 }; 1991 1992 struct mcs_tx_sc_sa_map { 1993 struct mbox_msghdr hdr; 1994 u8 sa_index0; 1995 u8 sa_index1; 1996 u8 rekey_ena; 1997 u8 sa_index0_vld; 1998 u8 sa_index1_vld; 1999 u8 tx_sa_active; 2000 u64 sectag_sci; 2001 u8 sc_id; /* used as index for SA_MEM_MAP */ 2002 u8 mcs_id; 2003 u64 rsvd; 2004 }; 2005 2006 struct mcs_rx_sc_sa_map { 2007 struct mbox_msghdr hdr; 2008 u8 sa_index; 2009 u8 sa_in_use; 2010 u8 sc_id; 2011 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 2012 u8 mcs_id; 2013 u64 rsvd; 2014 }; 2015 2016 struct mcs_flowid_ena_dis_entry { 2017 struct mbox_msghdr hdr; 2018 u8 flow_id; 2019 u8 ena; 2020 u8 mcs_id; 2021 u8 dir; 2022 u64 rsvd; 2023 }; 2024 2025 struct mcs_pn_table_write_req { 2026 struct mbox_msghdr hdr; 2027 u64 next_pn; 2028 u8 pn_id; 2029 u8 mcs_id; 2030 u8 dir; 2031 u64 rsvd; 2032 }; 2033 2034 struct mcs_hw_info { 2035 struct mbox_msghdr hdr; 2036 u8 num_mcs_blks; /* Number of MCS blocks */ 2037 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2038 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2039 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2040 u16 sa_entries; /* PN table entries = SA entries */ 2041 u64 rsvd[16]; 2042 }; 2043 2044 struct mcs_set_active_lmac { 2045 struct mbox_msghdr hdr; 2046 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2047 u8 mcs_id; 2048 u16 chan_base; /* MCS channel base */ 2049 u64 rsvd; 2050 }; 2051 2052 struct mcs_set_lmac_mode { 2053 struct mbox_msghdr hdr; 2054 u8 mode; /* 1:Bypass 0:Operational */ 2055 u8 lmac_id; 2056 u8 mcs_id; 2057 u64 rsvd; 2058 }; 2059 2060 struct mcs_port_reset_req { 2061 struct mbox_msghdr hdr; 2062 u8 reset; 2063 u8 mcs_id; 2064 u8 port_id; 2065 u64 rsvd; 2066 }; 2067 2068 struct mcs_port_cfg_set_req { 2069 struct mbox_msghdr hdr; 2070 u8 cstm_tag_rel_mode_sel; 2071 u8 custom_hdr_enb; 2072 u8 fifo_skid; 2073 u8 port_mode; 2074 u8 port_id; 2075 u8 mcs_id; 2076 u64 rsvd; 2077 }; 2078 2079 struct mcs_port_cfg_get_req { 2080 struct mbox_msghdr hdr; 2081 u8 port_id; 2082 u8 mcs_id; 2083 u64 rsvd; 2084 }; 2085 2086 struct mcs_port_cfg_get_rsp { 2087 struct mbox_msghdr hdr; 2088 u8 cstm_tag_rel_mode_sel; 2089 u8 custom_hdr_enb; 2090 u8 fifo_skid; 2091 u8 port_mode; 2092 u8 port_id; 2093 u8 mcs_id; 2094 u64 rsvd; 2095 }; 2096 2097 struct mcs_custom_tag_cfg_get_req { 2098 struct mbox_msghdr hdr; 2099 u8 mcs_id; 2100 u8 dir; 2101 u64 rsvd; 2102 }; 2103 2104 struct mcs_custom_tag_cfg_get_rsp { 2105 struct mbox_msghdr hdr; 2106 u16 cstm_etype[8]; 2107 u8 cstm_indx[8]; 2108 u8 cstm_etype_en; 2109 u8 mcs_id; 2110 u8 dir; 2111 u64 rsvd; 2112 }; 2113 2114 /* MCS mailbox error codes 2115 * Range 1201 - 1300. 2116 */ 2117 enum mcs_af_status { 2118 MCS_AF_ERR_INVALID_MCSID = -1201, 2119 MCS_AF_ERR_NOT_MAPPED = -1202, 2120 }; 2121 2122 struct mcs_set_pn_threshold { 2123 struct mbox_msghdr hdr; 2124 u64 threshold; 2125 u8 xpn; /* '1' for setting xpn threshold */ 2126 u8 mcs_id; 2127 u8 dir; 2128 u64 rsvd; 2129 }; 2130 2131 enum mcs_ctrl_pkt_rulew_type { 2132 MCS_CTRL_PKT_RULE_TYPE_ETH, 2133 MCS_CTRL_PKT_RULE_TYPE_DA, 2134 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2135 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2136 MCS_CTRL_PKT_RULE_TYPE_MAC, 2137 }; 2138 2139 struct mcs_alloc_ctrl_pkt_rule_req { 2140 struct mbox_msghdr hdr; 2141 u8 rule_type; 2142 u8 mcs_id; /* MCS block ID */ 2143 u8 dir; /* Macsec ingress or egress side */ 2144 u64 rsvd; 2145 }; 2146 2147 struct mcs_alloc_ctrl_pkt_rule_rsp { 2148 struct mbox_msghdr hdr; 2149 u8 rule_idx; 2150 u8 rule_type; 2151 u8 mcs_id; 2152 u8 dir; 2153 u64 rsvd; 2154 }; 2155 2156 struct mcs_free_ctrl_pkt_rule_req { 2157 struct mbox_msghdr hdr; 2158 u8 rule_idx; 2159 u8 rule_type; 2160 u8 mcs_id; 2161 u8 dir; 2162 u8 all; 2163 u64 rsvd; 2164 }; 2165 2166 struct mcs_ctrl_pkt_rule_write_req { 2167 struct mbox_msghdr hdr; 2168 u64 data0; 2169 u64 data1; 2170 u64 data2; 2171 u8 rule_idx; 2172 u8 rule_type; 2173 u8 mcs_id; 2174 u8 dir; 2175 u64 rsvd; 2176 }; 2177 2178 struct mcs_stats_req { 2179 struct mbox_msghdr hdr; 2180 u8 id; 2181 u8 mcs_id; 2182 u8 dir; 2183 u64 rsvd; 2184 }; 2185 2186 struct mcs_flowid_stats { 2187 struct mbox_msghdr hdr; 2188 u64 tcam_hit_cnt; 2189 u64 rsvd; 2190 }; 2191 2192 struct mcs_secy_stats { 2193 struct mbox_msghdr hdr; 2194 u64 ctl_pkt_bcast_cnt; 2195 u64 ctl_pkt_mcast_cnt; 2196 u64 ctl_pkt_ucast_cnt; 2197 u64 ctl_octet_cnt; 2198 u64 unctl_pkt_bcast_cnt; 2199 u64 unctl_pkt_mcast_cnt; 2200 u64 unctl_pkt_ucast_cnt; 2201 u64 unctl_octet_cnt; 2202 /* Valid only for RX */ 2203 u64 octet_decrypted_cnt; 2204 u64 octet_validated_cnt; 2205 u64 pkt_port_disabled_cnt; 2206 u64 pkt_badtag_cnt; 2207 u64 pkt_nosa_cnt; 2208 u64 pkt_nosaerror_cnt; 2209 u64 pkt_tagged_ctl_cnt; 2210 u64 pkt_untaged_cnt; 2211 u64 pkt_ctl_cnt; /* CN10K-B */ 2212 u64 pkt_notag_cnt; /* CNF10K-B */ 2213 /* Valid only for TX */ 2214 u64 octet_encrypted_cnt; 2215 u64 octet_protected_cnt; 2216 u64 pkt_noactivesa_cnt; 2217 u64 pkt_toolong_cnt; 2218 u64 pkt_untagged_cnt; 2219 u64 rsvd[4]; 2220 }; 2221 2222 struct mcs_port_stats { 2223 struct mbox_msghdr hdr; 2224 u64 tcam_miss_cnt; 2225 u64 parser_err_cnt; 2226 u64 preempt_err_cnt; /* CNF10K-B */ 2227 u64 sectag_insert_err_cnt; 2228 u64 rsvd[4]; 2229 }; 2230 2231 /* Only for CN10K-B */ 2232 struct mcs_sa_stats { 2233 struct mbox_msghdr hdr; 2234 /* RX */ 2235 u64 pkt_invalid_cnt; 2236 u64 pkt_nosaerror_cnt; 2237 u64 pkt_notvalid_cnt; 2238 u64 pkt_ok_cnt; 2239 u64 pkt_nosa_cnt; 2240 /* TX */ 2241 u64 pkt_encrypt_cnt; 2242 u64 pkt_protected_cnt; 2243 u64 rsvd[4]; 2244 }; 2245 2246 struct mcs_sc_stats { 2247 struct mbox_msghdr hdr; 2248 /* RX */ 2249 u64 hit_cnt; 2250 u64 pkt_invalid_cnt; 2251 u64 pkt_late_cnt; 2252 u64 pkt_notvalid_cnt; 2253 u64 pkt_unchecked_cnt; 2254 u64 pkt_delay_cnt; /* CNF10K-B */ 2255 u64 pkt_ok_cnt; /* CNF10K-B */ 2256 u64 octet_decrypt_cnt; /* CN10K-B */ 2257 u64 octet_validate_cnt; /* CN10K-B */ 2258 /* TX */ 2259 u64 pkt_encrypt_cnt; 2260 u64 pkt_protected_cnt; 2261 u64 octet_encrypt_cnt; /* CN10K-B */ 2262 u64 octet_protected_cnt; /* CN10K-B */ 2263 u64 rsvd[4]; 2264 }; 2265 2266 struct mcs_clear_stats { 2267 struct mbox_msghdr hdr; 2268 #define MCS_FLOWID_STATS 0 2269 #define MCS_SECY_STATS 1 2270 #define MCS_SC_STATS 2 2271 #define MCS_SA_STATS 3 2272 #define MCS_PORT_STATS 4 2273 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2274 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2275 u8 mcs_id; 2276 u8 dir; 2277 u8 all; /* All resources stats mapped to PF are cleared */ 2278 }; 2279 2280 struct mcs_intr_cfg { 2281 struct mbox_msghdr hdr; 2282 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2283 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2284 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2285 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2286 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2287 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2288 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2289 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2290 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2291 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2292 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2293 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2294 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2295 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2296 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2297 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2298 u64 intr_mask; /* Interrupt enable mask */ 2299 u8 mcs_id; 2300 u8 lmac_id; 2301 u64 rsvd; 2302 }; 2303 2304 struct mcs_intr_info { 2305 struct mbox_msghdr hdr; 2306 u64 intr_mask; 2307 int sa_id; 2308 u8 mcs_id; 2309 u8 lmac_id; 2310 u64 rsvd; 2311 }; 2312 2313 #endif /* MBOX_H */ 2314