1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 138 msg_rsp) \ 139 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 140 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 141 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 142 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 143 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 144 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 147 cgx_mac_addr_set_or_get) \ 148 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 149 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 150 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 151 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 152 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 153 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 154 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 155 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 156 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 157 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 158 cgx_pause_frm_cfg) \ 159 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 160 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 161 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 162 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 163 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 164 cgx_set_link_mode_rsp) \ 165 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 166 cgx_features_info_msg) \ 167 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 168 M(CGX_MAC_ADDR_ADD, 0x217, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 169 cgx_mac_addr_add_rsp) \ 170 M(CGX_MAC_ADDR_DEL, 0x218, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 171 msg_rsp) \ 172 M(CGX_MAC_MAX_ENTRIES_GET, 0x219, cgx_mac_max_entries_get, msg_req, \ 173 cgx_max_dmac_entries_get_rsp) \ 174 M(CGX_MAC_ADDR_RESET, 0x21A, cgx_mac_addr_reset, msg_req, msg_rsp) \ 175 M(CGX_MAC_ADDR_UPDATE, 0x21B, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 176 msg_rsp) \ 177 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 178 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 179 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 180 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 181 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 182 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 183 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 184 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 185 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 186 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 187 msg_rsp) \ 188 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 189 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 190 cpt_rd_wr_reg_msg) \ 191 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 192 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 193 msg_rsp) \ 194 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 195 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 196 npc_mcam_alloc_entry_rsp) \ 197 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 198 npc_mcam_free_entry_req, msg_rsp) \ 199 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 200 npc_mcam_write_entry_req, msg_rsp) \ 201 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 202 npc_mcam_ena_dis_entry_req, msg_rsp) \ 203 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 204 npc_mcam_ena_dis_entry_req, msg_rsp) \ 205 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 206 npc_mcam_shift_entry_rsp) \ 207 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 208 npc_mcam_alloc_counter_req, \ 209 npc_mcam_alloc_counter_rsp) \ 210 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 211 npc_mcam_oper_counter_req, msg_rsp) \ 212 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 213 npc_mcam_unmap_counter_req, msg_rsp) \ 214 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 215 npc_mcam_oper_counter_req, msg_rsp) \ 216 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 217 npc_mcam_oper_counter_req, \ 218 npc_mcam_oper_counter_rsp) \ 219 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 220 npc_mcam_alloc_and_write_entry_req, \ 221 npc_mcam_alloc_and_write_entry_rsp) \ 222 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 223 msg_req, npc_get_kex_cfg_rsp) \ 224 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 225 npc_install_flow_req, npc_install_flow_rsp) \ 226 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 227 npc_delete_flow_req, msg_rsp) \ 228 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 229 npc_mcam_read_entry_req, \ 230 npc_mcam_read_entry_rsp) \ 231 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 232 msg_req, npc_mcam_read_base_rule_rsp) \ 233 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 234 npc_mcam_get_stats_req, \ 235 npc_mcam_get_stats_rsp) \ 236 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 237 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 238 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 239 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 240 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 241 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 242 hwctx_disable_req, msg_rsp) \ 243 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 244 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 245 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 246 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 247 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 248 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 249 nix_vtag_config_rsp) \ 250 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 251 nix_rss_flowkey_cfg, \ 252 nix_rss_flowkey_cfg_rsp) \ 253 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 254 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 255 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 256 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 257 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 258 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 259 nix_mark_format_cfg, \ 260 nix_mark_format_cfg_rsp) \ 261 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 262 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 263 nix_lso_format_cfg, \ 264 nix_lso_format_cfg_rsp) \ 265 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 266 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 267 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 268 nix_bp_cfg_rsp) \ 269 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 270 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 271 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 272 nix_cn10k_aq_enq_rsp) \ 273 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 274 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 275 nix_bandprof_alloc_rsp) \ 276 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 277 msg_rsp) 278 279 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 280 #define MBOX_UP_CGX_MESSAGES \ 281 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 282 283 enum { 284 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 285 MBOX_MESSAGES 286 MBOX_UP_CGX_MESSAGES 287 #undef M 288 }; 289 290 /* Mailbox message formats */ 291 292 #define RVU_DEFAULT_PF_FUNC 0xFFFF 293 294 /* Generic request msg used for those mbox messages which 295 * don't send any data in the request. 296 */ 297 struct msg_req { 298 struct mbox_msghdr hdr; 299 }; 300 301 /* Generic response msg used an ack or response for those mbox 302 * messages which don't have a specific rsp msg format. 303 */ 304 struct msg_rsp { 305 struct mbox_msghdr hdr; 306 }; 307 308 /* RVU mailbox error codes 309 * Range 256 - 300. 310 */ 311 enum rvu_af_status { 312 RVU_INVALID_VF_ID = -256, 313 }; 314 315 struct ready_msg_rsp { 316 struct mbox_msghdr hdr; 317 u16 sclk_freq; /* SCLK frequency (in MHz) */ 318 u16 rclk_freq; /* RCLK frequency (in MHz) */ 319 }; 320 321 /* Structure for requesting resource provisioning. 322 * 'modify' flag to be used when either requesting more 323 * or to detach partial of a certain resource type. 324 * Rest of the fields specify how many of what type to 325 * be attached. 326 * To request LFs from two blocks of same type this mailbox 327 * can be sent twice as below: 328 * struct rsrc_attach *attach; 329 * .. Allocate memory for message .. 330 * attach->cptlfs = 3; <3 LFs from CPT0> 331 * .. Send message .. 332 * .. Allocate memory for message .. 333 * attach->modify = 1; 334 * attach->cpt_blkaddr = BLKADDR_CPT1; 335 * attach->cptlfs = 2; <2 LFs from CPT1> 336 * .. Send message .. 337 */ 338 struct rsrc_attach { 339 struct mbox_msghdr hdr; 340 u8 modify:1; 341 u8 npalf:1; 342 u8 nixlf:1; 343 u16 sso; 344 u16 ssow; 345 u16 timlfs; 346 u16 cptlfs; 347 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 348 }; 349 350 /* Structure for relinquishing resources. 351 * 'partial' flag to be used when relinquishing all resources 352 * but only of a certain type. If not set, all resources of all 353 * types provisioned to the RVU function will be detached. 354 */ 355 struct rsrc_detach { 356 struct mbox_msghdr hdr; 357 u8 partial:1; 358 u8 npalf:1; 359 u8 nixlf:1; 360 u8 sso:1; 361 u8 ssow:1; 362 u8 timlfs:1; 363 u8 cptlfs:1; 364 }; 365 366 #define MSIX_VECTOR_INVALID 0xFFFF 367 #define MAX_RVU_BLKLF_CNT 256 368 369 struct msix_offset_rsp { 370 struct mbox_msghdr hdr; 371 u16 npa_msixoff; 372 u16 nix_msixoff; 373 u8 sso; 374 u8 ssow; 375 u8 timlfs; 376 u8 cptlfs; 377 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 378 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 379 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 380 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 381 u8 cpt1_lfs; 382 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 383 }; 384 385 struct get_hw_cap_rsp { 386 struct mbox_msghdr hdr; 387 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 388 u8 nix_shaping; /* Is shaping and coloring supported */ 389 }; 390 391 /* CGX mbox message formats */ 392 393 struct cgx_stats_rsp { 394 struct mbox_msghdr hdr; 395 #define CGX_RX_STATS_COUNT 9 396 #define CGX_TX_STATS_COUNT 18 397 u64 rx_stats[CGX_RX_STATS_COUNT]; 398 u64 tx_stats[CGX_TX_STATS_COUNT]; 399 }; 400 401 struct cgx_fec_stats_rsp { 402 struct mbox_msghdr hdr; 403 u64 fec_corr_blks; 404 u64 fec_uncorr_blks; 405 }; 406 /* Structure for requesting the operation for 407 * setting/getting mac address in the CGX interface 408 */ 409 struct cgx_mac_addr_set_or_get { 410 struct mbox_msghdr hdr; 411 u8 mac_addr[ETH_ALEN]; 412 }; 413 414 /* Structure for requesting the operation to 415 * add DMAC filter entry into CGX interface 416 */ 417 struct cgx_mac_addr_add_req { 418 struct mbox_msghdr hdr; 419 u8 mac_addr[ETH_ALEN]; 420 }; 421 422 /* Structure for response against the operation to 423 * add DMAC filter entry into CGX interface 424 */ 425 struct cgx_mac_addr_add_rsp { 426 struct mbox_msghdr hdr; 427 u8 index; 428 }; 429 430 /* Structure for requesting the operation to 431 * delete DMAC filter entry from CGX interface 432 */ 433 struct cgx_mac_addr_del_req { 434 struct mbox_msghdr hdr; 435 u8 index; 436 }; 437 438 /* Structure for response against the operation to 439 * get maximum supported DMAC filter entries 440 */ 441 struct cgx_max_dmac_entries_get_rsp { 442 struct mbox_msghdr hdr; 443 u8 max_dmac_filters; 444 }; 445 446 struct cgx_link_user_info { 447 uint64_t link_up:1; 448 uint64_t full_duplex:1; 449 uint64_t lmac_type_id:4; 450 uint64_t speed:20; /* speed in Mbps */ 451 uint64_t an:1; /* AN supported or not */ 452 uint64_t fec:2; /* FEC type if enabled else 0 */ 453 #define LMACTYPE_STR_LEN 16 454 char lmac_type[LMACTYPE_STR_LEN]; 455 }; 456 457 struct cgx_link_info_msg { 458 struct mbox_msghdr hdr; 459 struct cgx_link_user_info link_info; 460 }; 461 462 struct cgx_pause_frm_cfg { 463 struct mbox_msghdr hdr; 464 u8 set; 465 /* set = 1 if the request is to config pause frames */ 466 /* set = 0 if the request is to fetch pause frames config */ 467 u8 rx_pause; 468 u8 tx_pause; 469 }; 470 471 enum fec_type { 472 OTX2_FEC_NONE, 473 OTX2_FEC_BASER, 474 OTX2_FEC_RS, 475 OTX2_FEC_STATS_CNT = 2, 476 OTX2_FEC_OFF, 477 }; 478 479 struct fec_mode { 480 struct mbox_msghdr hdr; 481 int fec; 482 }; 483 484 struct sfp_eeprom_s { 485 #define SFP_EEPROM_SIZE 256 486 u16 sff_id; 487 u8 buf[SFP_EEPROM_SIZE]; 488 u64 reserved; 489 }; 490 491 struct phy_s { 492 struct { 493 u64 can_change_mod_type:1; 494 u64 mod_type:1; 495 u64 has_fec_stats:1; 496 } misc; 497 struct fec_stats_s { 498 u32 rsfec_corr_cws; 499 u32 rsfec_uncorr_cws; 500 u32 brfec_corr_blks; 501 u32 brfec_uncorr_blks; 502 } fec_stats; 503 }; 504 505 struct cgx_lmac_fwdata_s { 506 u16 rw_valid; 507 u64 supported_fec; 508 u64 supported_an; 509 u64 supported_link_modes; 510 /* only applicable if AN is supported */ 511 u64 advertised_fec; 512 u64 advertised_link_modes; 513 /* Only applicable if SFP/QSFP slot is present */ 514 struct sfp_eeprom_s sfp_eeprom; 515 struct phy_s phy; 516 #define LMAC_FWDATA_RESERVED_MEM 1021 517 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 518 }; 519 520 struct cgx_fw_data { 521 struct mbox_msghdr hdr; 522 struct cgx_lmac_fwdata_s fwdata; 523 }; 524 525 struct cgx_set_link_mode_args { 526 u32 speed; 527 u8 duplex; 528 u8 an; 529 u8 ports; 530 u64 mode; 531 }; 532 533 struct cgx_set_link_mode_req { 534 #define AUTONEG_UNKNOWN 0xff 535 struct mbox_msghdr hdr; 536 struct cgx_set_link_mode_args args; 537 }; 538 539 struct cgx_set_link_mode_rsp { 540 struct mbox_msghdr hdr; 541 int status; 542 }; 543 544 struct cgx_mac_addr_update_req { 545 struct mbox_msghdr hdr; 546 u8 mac_addr[ETH_ALEN]; 547 u8 index; 548 }; 549 550 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 551 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 552 #define RVU_MAC_VERSION BIT_ULL(2) 553 #define RVU_MAC_CGX BIT_ULL(3) 554 #define RVU_MAC_RPM BIT_ULL(4) 555 556 struct cgx_features_info_msg { 557 struct mbox_msghdr hdr; 558 u64 lmac_features; 559 }; 560 561 struct rpm_stats_rsp { 562 struct mbox_msghdr hdr; 563 #define RPM_RX_STATS_COUNT 43 564 #define RPM_TX_STATS_COUNT 34 565 u64 rx_stats[RPM_RX_STATS_COUNT]; 566 u64 tx_stats[RPM_TX_STATS_COUNT]; 567 }; 568 569 /* NPA mbox message formats */ 570 571 /* NPA mailbox error codes 572 * Range 301 - 400. 573 */ 574 enum npa_af_status { 575 NPA_AF_ERR_PARAM = -301, 576 NPA_AF_ERR_AQ_FULL = -302, 577 NPA_AF_ERR_AQ_ENQUEUE = -303, 578 NPA_AF_ERR_AF_LF_INVALID = -304, 579 NPA_AF_ERR_AF_LF_ALLOC = -305, 580 NPA_AF_ERR_LF_RESET = -306, 581 }; 582 583 /* For NPA LF context alloc and init */ 584 struct npa_lf_alloc_req { 585 struct mbox_msghdr hdr; 586 int node; 587 int aura_sz; /* No of auras */ 588 u32 nr_pools; /* No of pools */ 589 u64 way_mask; 590 }; 591 592 struct npa_lf_alloc_rsp { 593 struct mbox_msghdr hdr; 594 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 595 u32 stack_pg_bytes; /* Size of stack page */ 596 u16 qints; /* NPA_AF_CONST::QINTS */ 597 }; 598 599 /* NPA AQ enqueue msg */ 600 struct npa_aq_enq_req { 601 struct mbox_msghdr hdr; 602 u32 aura_id; 603 u8 ctype; 604 u8 op; 605 union { 606 /* Valid when op == WRITE/INIT and ctype == AURA. 607 * LF fills the pool_id in aura.pool_addr. AF will translate 608 * the pool_id to pool context pointer. 609 */ 610 struct npa_aura_s aura; 611 /* Valid when op == WRITE/INIT and ctype == POOL */ 612 struct npa_pool_s pool; 613 }; 614 /* Mask data when op == WRITE (1=write, 0=don't write) */ 615 union { 616 /* Valid when op == WRITE and ctype == AURA */ 617 struct npa_aura_s aura_mask; 618 /* Valid when op == WRITE and ctype == POOL */ 619 struct npa_pool_s pool_mask; 620 }; 621 }; 622 623 struct npa_aq_enq_rsp { 624 struct mbox_msghdr hdr; 625 union { 626 /* Valid when op == READ and ctype == AURA */ 627 struct npa_aura_s aura; 628 /* Valid when op == READ and ctype == POOL */ 629 struct npa_pool_s pool; 630 }; 631 }; 632 633 /* Disable all contexts of type 'ctype' */ 634 struct hwctx_disable_req { 635 struct mbox_msghdr hdr; 636 u8 ctype; 637 }; 638 639 /* NIX mbox message formats */ 640 641 /* NIX mailbox error codes 642 * Range 401 - 500. 643 */ 644 enum nix_af_status { 645 NIX_AF_ERR_PARAM = -401, 646 NIX_AF_ERR_AQ_FULL = -402, 647 NIX_AF_ERR_AQ_ENQUEUE = -403, 648 NIX_AF_ERR_AF_LF_INVALID = -404, 649 NIX_AF_ERR_AF_LF_ALLOC = -405, 650 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 651 NIX_AF_ERR_TLX_INVALID = -407, 652 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 653 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 654 NIX_AF_ERR_FRS_INVALID = -410, 655 NIX_AF_ERR_RX_LINK_INVALID = -411, 656 NIX_AF_INVAL_TXSCHQ_CFG = -412, 657 NIX_AF_SMQ_FLUSH_FAILED = -413, 658 NIX_AF_ERR_LF_RESET = -414, 659 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 660 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 661 NIX_AF_ERR_MARK_CFG_FAIL = -417, 662 NIX_AF_ERR_LSO_CFG_FAIL = -418, 663 NIX_AF_INVAL_NPA_PF_FUNC = -419, 664 NIX_AF_INVAL_SSO_PF_FUNC = -420, 665 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 666 NIX_AF_ERR_RX_VTAG_INUSE = -422, 667 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 668 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 669 NIX_AF_ERR_INVALID_NIXBLK = -425, 670 NIX_AF_ERR_INVALID_BANDPROF = -426, 671 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 672 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 673 }; 674 675 /* For NIX RX vtag action */ 676 enum nix_rx_vtag0_type { 677 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 678 NIX_AF_LFX_RX_VTAG_TYPE1, 679 NIX_AF_LFX_RX_VTAG_TYPE2, 680 NIX_AF_LFX_RX_VTAG_TYPE3, 681 NIX_AF_LFX_RX_VTAG_TYPE4, 682 NIX_AF_LFX_RX_VTAG_TYPE5, 683 NIX_AF_LFX_RX_VTAG_TYPE6, 684 NIX_AF_LFX_RX_VTAG_TYPE7, 685 }; 686 687 /* For NIX LF context alloc and init */ 688 struct nix_lf_alloc_req { 689 struct mbox_msghdr hdr; 690 int node; 691 u32 rq_cnt; /* No of receive queues */ 692 u32 sq_cnt; /* No of send queues */ 693 u32 cq_cnt; /* No of completion queues */ 694 u8 xqe_sz; 695 u16 rss_sz; 696 u8 rss_grps; 697 u16 npa_func; 698 u16 sso_func; 699 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 700 u64 way_mask; 701 }; 702 703 struct nix_lf_alloc_rsp { 704 struct mbox_msghdr hdr; 705 u16 sqb_size; 706 u16 rx_chan_base; 707 u16 tx_chan_base; 708 u8 rx_chan_cnt; /* total number of RX channels */ 709 u8 tx_chan_cnt; /* total number of TX channels */ 710 u8 lso_tsov4_idx; 711 u8 lso_tsov6_idx; 712 u8 mac_addr[ETH_ALEN]; 713 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 714 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 715 u16 cints; /* NIX_AF_CONST2::CINTS */ 716 u16 qints; /* NIX_AF_CONST2::QINTS */ 717 u8 cgx_links; /* No. of CGX links present in HW */ 718 u8 lbk_links; /* No. of LBK links present in HW */ 719 u8 sdp_links; /* No. of SDP links present in HW */ 720 }; 721 722 struct nix_lf_free_req { 723 struct mbox_msghdr hdr; 724 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 725 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 726 u64 flags; 727 }; 728 729 /* CN10K NIX AQ enqueue msg */ 730 struct nix_cn10k_aq_enq_req { 731 struct mbox_msghdr hdr; 732 u32 qidx; 733 u8 ctype; 734 u8 op; 735 union { 736 struct nix_cn10k_rq_ctx_s rq; 737 struct nix_cn10k_sq_ctx_s sq; 738 struct nix_cq_ctx_s cq; 739 struct nix_rsse_s rss; 740 struct nix_rx_mce_s mce; 741 struct nix_bandprof_s prof; 742 }; 743 union { 744 struct nix_cn10k_rq_ctx_s rq_mask; 745 struct nix_cn10k_sq_ctx_s sq_mask; 746 struct nix_cq_ctx_s cq_mask; 747 struct nix_rsse_s rss_mask; 748 struct nix_rx_mce_s mce_mask; 749 struct nix_bandprof_s prof_mask; 750 }; 751 }; 752 753 struct nix_cn10k_aq_enq_rsp { 754 struct mbox_msghdr hdr; 755 union { 756 struct nix_cn10k_rq_ctx_s rq; 757 struct nix_cn10k_sq_ctx_s sq; 758 struct nix_cq_ctx_s cq; 759 struct nix_rsse_s rss; 760 struct nix_rx_mce_s mce; 761 struct nix_bandprof_s prof; 762 }; 763 }; 764 765 /* NIX AQ enqueue msg */ 766 struct nix_aq_enq_req { 767 struct mbox_msghdr hdr; 768 u32 qidx; 769 u8 ctype; 770 u8 op; 771 union { 772 struct nix_rq_ctx_s rq; 773 struct nix_sq_ctx_s sq; 774 struct nix_cq_ctx_s cq; 775 struct nix_rsse_s rss; 776 struct nix_rx_mce_s mce; 777 u64 prof; 778 }; 779 union { 780 struct nix_rq_ctx_s rq_mask; 781 struct nix_sq_ctx_s sq_mask; 782 struct nix_cq_ctx_s cq_mask; 783 struct nix_rsse_s rss_mask; 784 struct nix_rx_mce_s mce_mask; 785 u64 prof_mask; 786 }; 787 }; 788 789 struct nix_aq_enq_rsp { 790 struct mbox_msghdr hdr; 791 union { 792 struct nix_rq_ctx_s rq; 793 struct nix_sq_ctx_s sq; 794 struct nix_cq_ctx_s cq; 795 struct nix_rsse_s rss; 796 struct nix_rx_mce_s mce; 797 struct nix_bandprof_s prof; 798 }; 799 }; 800 801 /* Tx scheduler/shaper mailbox messages */ 802 803 #define MAX_TXSCHQ_PER_FUNC 128 804 805 struct nix_txsch_alloc_req { 806 struct mbox_msghdr hdr; 807 /* Scheduler queue count request at each level */ 808 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 809 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 810 }; 811 812 struct nix_txsch_alloc_rsp { 813 struct mbox_msghdr hdr; 814 /* Scheduler queue count allocated at each level */ 815 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 816 u16 schq[NIX_TXSCH_LVL_CNT]; 817 /* Scheduler queue list allocated at each level */ 818 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 819 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 820 u8 aggr_level; /* Traffic aggregation scheduler level */ 821 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 822 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 823 }; 824 825 struct nix_txsch_free_req { 826 struct mbox_msghdr hdr; 827 #define TXSCHQ_FREE_ALL BIT_ULL(0) 828 u16 flags; 829 /* Scheduler queue level to be freed */ 830 u16 schq_lvl; 831 /* List of scheduler queues to be freed */ 832 u16 schq; 833 }; 834 835 struct nix_txschq_config { 836 struct mbox_msghdr hdr; 837 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 838 #define TXSCHQ_IDX_SHIFT 16 839 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 840 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 841 u8 num_regs; 842 #define MAX_REGS_PER_MBOX_MSG 20 843 u64 reg[MAX_REGS_PER_MBOX_MSG]; 844 u64 regval[MAX_REGS_PER_MBOX_MSG]; 845 }; 846 847 struct nix_vtag_config { 848 struct mbox_msghdr hdr; 849 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 850 u8 vtag_size; 851 /* cfg_type is '0' for tx vlan cfg 852 * cfg_type is '1' for rx vlan cfg 853 */ 854 u8 cfg_type; 855 union { 856 /* valid when cfg_type is '0' */ 857 struct { 858 u64 vtag0; 859 u64 vtag1; 860 861 /* cfg_vtag0 & cfg_vtag1 fields are valid 862 * when free_vtag0 & free_vtag1 are '0's. 863 */ 864 /* cfg_vtag0 = 1 to configure vtag0 */ 865 u8 cfg_vtag0 :1; 866 /* cfg_vtag1 = 1 to configure vtag1 */ 867 u8 cfg_vtag1 :1; 868 869 /* vtag0_idx & vtag1_idx are only valid when 870 * both cfg_vtag0 & cfg_vtag1 are '0's, 871 * these fields are used along with free_vtag0 872 * & free_vtag1 to free the nix lf's tx_vlan 873 * configuration. 874 * 875 * Denotes the indices of tx_vtag def registers 876 * that needs to be cleared and freed. 877 */ 878 int vtag0_idx; 879 int vtag1_idx; 880 881 /* free_vtag0 & free_vtag1 fields are valid 882 * when cfg_vtag0 & cfg_vtag1 are '0's. 883 */ 884 /* free_vtag0 = 1 clears vtag0 configuration 885 * vtag0_idx denotes the index to be cleared. 886 */ 887 u8 free_vtag0 :1; 888 /* free_vtag1 = 1 clears vtag1 configuration 889 * vtag1_idx denotes the index to be cleared. 890 */ 891 u8 free_vtag1 :1; 892 } tx; 893 894 /* valid when cfg_type is '1' */ 895 struct { 896 /* rx vtag type index, valid values are in 0..7 range */ 897 u8 vtag_type; 898 /* rx vtag strip */ 899 u8 strip_vtag :1; 900 /* rx vtag capture */ 901 u8 capture_vtag :1; 902 } rx; 903 }; 904 }; 905 906 struct nix_vtag_config_rsp { 907 struct mbox_msghdr hdr; 908 int vtag0_idx; 909 int vtag1_idx; 910 /* Indices of tx_vtag def registers used to configure 911 * tx vtag0 & vtag1 headers, these indices are valid 912 * when nix_vtag_config mbox requested for vtag0 and/ 913 * or vtag1 configuration. 914 */ 915 }; 916 917 struct nix_rss_flowkey_cfg { 918 struct mbox_msghdr hdr; 919 int mcam_index; /* MCAM entry index to modify */ 920 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 921 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 922 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 923 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 924 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 925 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 926 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 927 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 928 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 929 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 930 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 931 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 932 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 933 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 934 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 935 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 936 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 937 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 938 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 939 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 940 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 941 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 942 u32 flowkey_cfg; /* Flowkey types selected */ 943 u8 group; /* RSS context or group */ 944 }; 945 946 struct nix_rss_flowkey_cfg_rsp { 947 struct mbox_msghdr hdr; 948 u8 alg_idx; /* Selected algo index */ 949 }; 950 951 struct nix_set_mac_addr { 952 struct mbox_msghdr hdr; 953 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 954 }; 955 956 struct nix_get_mac_addr_rsp { 957 struct mbox_msghdr hdr; 958 u8 mac_addr[ETH_ALEN]; 959 }; 960 961 struct nix_mark_format_cfg { 962 struct mbox_msghdr hdr; 963 u8 offset; 964 u8 y_mask; 965 u8 y_val; 966 u8 r_mask; 967 u8 r_val; 968 }; 969 970 struct nix_mark_format_cfg_rsp { 971 struct mbox_msghdr hdr; 972 u8 mark_format_idx; 973 }; 974 975 struct nix_rx_mode { 976 struct mbox_msghdr hdr; 977 #define NIX_RX_MODE_UCAST BIT(0) 978 #define NIX_RX_MODE_PROMISC BIT(1) 979 #define NIX_RX_MODE_ALLMULTI BIT(2) 980 #define NIX_RX_MODE_USE_MCE BIT(3) 981 u16 mode; 982 }; 983 984 struct nix_rx_cfg { 985 struct mbox_msghdr hdr; 986 #define NIX_RX_OL3_VERIFY BIT(0) 987 #define NIX_RX_OL4_VERIFY BIT(1) 988 u8 len_verify; /* Outer L3/L4 len check */ 989 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 990 u8 csum_verify; /* Outer L4 checksum verification */ 991 }; 992 993 struct nix_frs_cfg { 994 struct mbox_msghdr hdr; 995 u8 update_smq; /* Update SMQ's min/max lens */ 996 u8 update_minlen; /* Set minlen also */ 997 u8 sdp_link; /* Set SDP RX link */ 998 u16 maxlen; 999 u16 minlen; 1000 }; 1001 1002 struct nix_lso_format_cfg { 1003 struct mbox_msghdr hdr; 1004 u64 field_mask; 1005 #define NIX_LSO_FIELD_MAX 8 1006 u64 fields[NIX_LSO_FIELD_MAX]; 1007 }; 1008 1009 struct nix_lso_format_cfg_rsp { 1010 struct mbox_msghdr hdr; 1011 u8 lso_format_idx; 1012 }; 1013 1014 struct nix_bp_cfg_req { 1015 struct mbox_msghdr hdr; 1016 u16 chan_base; /* Starting channel number */ 1017 u8 chan_cnt; /* Number of channels */ 1018 u8 bpid_per_chan; 1019 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1020 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1021 }; 1022 1023 /* PF can be mapped to either CGX or LBK interface, 1024 * so maximum 64 channels are possible. 1025 */ 1026 #define NIX_MAX_BPID_CHAN 64 1027 struct nix_bp_cfg_rsp { 1028 struct mbox_msghdr hdr; 1029 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1030 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1031 }; 1032 1033 struct nix_hw_info { 1034 struct mbox_msghdr hdr; 1035 u16 max_mtu; 1036 u16 min_mtu; 1037 }; 1038 1039 struct nix_bandprof_alloc_req { 1040 struct mbox_msghdr hdr; 1041 /* Count of profiles needed per layer */ 1042 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1043 }; 1044 1045 struct nix_bandprof_alloc_rsp { 1046 struct mbox_msghdr hdr; 1047 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1048 1049 /* There is no need to allocate morethan 1 bandwidth profile 1050 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1051 * profiles to 64 per PF_FUNC. 1052 */ 1053 #define MAX_BANDPROF_PER_PFFUNC 64 1054 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1055 }; 1056 1057 struct nix_bandprof_free_req { 1058 struct mbox_msghdr hdr; 1059 u8 free_all; 1060 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1061 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1062 }; 1063 1064 /* NPC mbox message structs */ 1065 1066 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1067 #define NPC_MCAM_INVALID_MAP 0xFFFF 1068 1069 /* NPC mailbox error codes 1070 * Range 701 - 800. 1071 */ 1072 enum npc_af_status { 1073 NPC_MCAM_INVALID_REQ = -701, 1074 NPC_MCAM_ALLOC_DENIED = -702, 1075 NPC_MCAM_ALLOC_FAILED = -703, 1076 NPC_MCAM_PERM_DENIED = -704, 1077 }; 1078 1079 struct npc_mcam_alloc_entry_req { 1080 struct mbox_msghdr hdr; 1081 #define NPC_MAX_NONCONTIG_ENTRIES 256 1082 u8 contig; /* Contiguous entries ? */ 1083 #define NPC_MCAM_ANY_PRIO 0 1084 #define NPC_MCAM_LOWER_PRIO 1 1085 #define NPC_MCAM_HIGHER_PRIO 2 1086 u8 priority; /* Lower or higher w.r.t ref_entry */ 1087 u16 ref_entry; 1088 u16 count; /* Number of entries requested */ 1089 }; 1090 1091 struct npc_mcam_alloc_entry_rsp { 1092 struct mbox_msghdr hdr; 1093 u16 entry; /* Entry allocated or start index if contiguous. 1094 * Invalid incase of non-contiguous. 1095 */ 1096 u16 count; /* Number of entries allocated */ 1097 u16 free_count; /* Number of entries available */ 1098 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1099 }; 1100 1101 struct npc_mcam_free_entry_req { 1102 struct mbox_msghdr hdr; 1103 u16 entry; /* Entry index to be freed */ 1104 u8 all; /* If all entries allocated to this PFVF to be freed */ 1105 }; 1106 1107 struct mcam_entry { 1108 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1109 u64 kw[NPC_MAX_KWS_IN_KEY]; 1110 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1111 u64 action; 1112 u64 vtag_action; 1113 }; 1114 1115 struct npc_mcam_write_entry_req { 1116 struct mbox_msghdr hdr; 1117 struct mcam_entry entry_data; 1118 u16 entry; /* MCAM entry to write this match key */ 1119 u16 cntr; /* Counter for this MCAM entry */ 1120 u8 intf; /* Rx or Tx interface */ 1121 u8 enable_entry;/* Enable this MCAM entry ? */ 1122 u8 set_cntr; /* Set counter for this entry ? */ 1123 }; 1124 1125 /* Enable/Disable a given entry */ 1126 struct npc_mcam_ena_dis_entry_req { 1127 struct mbox_msghdr hdr; 1128 u16 entry; 1129 }; 1130 1131 struct npc_mcam_shift_entry_req { 1132 struct mbox_msghdr hdr; 1133 #define NPC_MCAM_MAX_SHIFTS 64 1134 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1135 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1136 u16 shift_count; /* Number of entries to shift */ 1137 }; 1138 1139 struct npc_mcam_shift_entry_rsp { 1140 struct mbox_msghdr hdr; 1141 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1142 }; 1143 1144 struct npc_mcam_alloc_counter_req { 1145 struct mbox_msghdr hdr; 1146 u8 contig; /* Contiguous counters ? */ 1147 #define NPC_MAX_NONCONTIG_COUNTERS 64 1148 u16 count; /* Number of counters requested */ 1149 }; 1150 1151 struct npc_mcam_alloc_counter_rsp { 1152 struct mbox_msghdr hdr; 1153 u16 cntr; /* Counter allocated or start index if contiguous. 1154 * Invalid incase of non-contiguous. 1155 */ 1156 u16 count; /* Number of counters allocated */ 1157 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1158 }; 1159 1160 struct npc_mcam_oper_counter_req { 1161 struct mbox_msghdr hdr; 1162 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1163 }; 1164 1165 struct npc_mcam_oper_counter_rsp { 1166 struct mbox_msghdr hdr; 1167 u64 stat; /* valid only while fetching counter's stats */ 1168 }; 1169 1170 struct npc_mcam_unmap_counter_req { 1171 struct mbox_msghdr hdr; 1172 u16 cntr; 1173 u16 entry; /* Entry and counter to be unmapped */ 1174 u8 all; /* Unmap all entries using this counter ? */ 1175 }; 1176 1177 struct npc_mcam_alloc_and_write_entry_req { 1178 struct mbox_msghdr hdr; 1179 struct mcam_entry entry_data; 1180 u16 ref_entry; 1181 u8 priority; /* Lower or higher w.r.t ref_entry */ 1182 u8 intf; /* Rx or Tx interface */ 1183 u8 enable_entry;/* Enable this MCAM entry ? */ 1184 u8 alloc_cntr; /* Allocate counter and map ? */ 1185 }; 1186 1187 struct npc_mcam_alloc_and_write_entry_rsp { 1188 struct mbox_msghdr hdr; 1189 u16 entry; 1190 u16 cntr; 1191 }; 1192 1193 struct npc_get_kex_cfg_rsp { 1194 struct mbox_msghdr hdr; 1195 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1196 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1197 #define NPC_MAX_INTF 2 1198 #define NPC_MAX_LID 8 1199 #define NPC_MAX_LT 16 1200 #define NPC_MAX_LD 2 1201 #define NPC_MAX_LFL 16 1202 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1203 u64 kex_ld_flags[NPC_MAX_LD]; 1204 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1205 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1206 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1207 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1208 #define MKEX_NAME_LEN 128 1209 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1210 }; 1211 1212 struct flow_msg { 1213 unsigned char dmac[6]; 1214 unsigned char smac[6]; 1215 __be16 etype; 1216 __be16 vlan_etype; 1217 __be16 vlan_tci; 1218 union { 1219 __be32 ip4src; 1220 __be32 ip6src[4]; 1221 }; 1222 union { 1223 __be32 ip4dst; 1224 __be32 ip6dst[4]; 1225 }; 1226 u8 tos; 1227 u8 ip_ver; 1228 u8 ip_proto; 1229 u8 tc; 1230 __be16 sport; 1231 __be16 dport; 1232 }; 1233 1234 struct npc_install_flow_req { 1235 struct mbox_msghdr hdr; 1236 struct flow_msg packet; 1237 struct flow_msg mask; 1238 u64 features; 1239 u16 entry; 1240 u16 channel; 1241 u16 chan_mask; 1242 u8 intf; 1243 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1244 u8 default_rule; 1245 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1246 u16 vf; 1247 /* action */ 1248 u32 index; 1249 u16 match_id; 1250 u8 flow_key_alg; 1251 u8 op; 1252 /* vtag rx action */ 1253 u8 vtag0_type; 1254 u8 vtag0_valid; 1255 u8 vtag1_type; 1256 u8 vtag1_valid; 1257 /* vtag tx action */ 1258 u16 vtag0_def; 1259 u8 vtag0_op; 1260 u16 vtag1_def; 1261 u8 vtag1_op; 1262 }; 1263 1264 struct npc_install_flow_rsp { 1265 struct mbox_msghdr hdr; 1266 int counter; /* negative if no counter else counter number */ 1267 }; 1268 1269 struct npc_delete_flow_req { 1270 struct mbox_msghdr hdr; 1271 u16 entry; 1272 u16 start;/*Disable range of entries */ 1273 u16 end; 1274 u8 all; /* PF + VFs */ 1275 }; 1276 1277 struct npc_mcam_read_entry_req { 1278 struct mbox_msghdr hdr; 1279 u16 entry; /* MCAM entry to read */ 1280 }; 1281 1282 struct npc_mcam_read_entry_rsp { 1283 struct mbox_msghdr hdr; 1284 struct mcam_entry entry_data; 1285 u8 intf; 1286 u8 enable; 1287 }; 1288 1289 struct npc_mcam_read_base_rule_rsp { 1290 struct mbox_msghdr hdr; 1291 struct mcam_entry entry; 1292 }; 1293 1294 struct npc_mcam_get_stats_req { 1295 struct mbox_msghdr hdr; 1296 u16 entry; /* mcam entry */ 1297 }; 1298 1299 struct npc_mcam_get_stats_rsp { 1300 struct mbox_msghdr hdr; 1301 u64 stat; /* counter stats */ 1302 u8 stat_ena; /* enabled */ 1303 }; 1304 1305 enum ptp_op { 1306 PTP_OP_ADJFINE = 0, 1307 PTP_OP_GET_CLOCK = 1, 1308 }; 1309 1310 struct ptp_req { 1311 struct mbox_msghdr hdr; 1312 u8 op; 1313 s64 scaled_ppm; 1314 }; 1315 1316 struct ptp_rsp { 1317 struct mbox_msghdr hdr; 1318 u64 clk; 1319 }; 1320 1321 struct set_vf_perm { 1322 struct mbox_msghdr hdr; 1323 u16 vf; 1324 #define RESET_VF_PERM BIT_ULL(0) 1325 #define VF_TRUSTED BIT_ULL(1) 1326 u64 flags; 1327 }; 1328 1329 struct lmtst_tbl_setup_req { 1330 struct mbox_msghdr hdr; 1331 u16 base_pcifunc; 1332 u8 use_local_lmt_region; 1333 u64 lmt_iova; 1334 u64 rsvd[4]; 1335 }; 1336 1337 /* CPT mailbox error codes 1338 * Range 901 - 1000. 1339 */ 1340 enum cpt_af_status { 1341 CPT_AF_ERR_PARAM = -901, 1342 CPT_AF_ERR_GRP_INVALID = -902, 1343 CPT_AF_ERR_LF_INVALID = -903, 1344 CPT_AF_ERR_ACCESS_DENIED = -904, 1345 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1346 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1347 }; 1348 1349 /* CPT mbox message formats */ 1350 struct cpt_rd_wr_reg_msg { 1351 struct mbox_msghdr hdr; 1352 u64 reg_offset; 1353 u64 *ret_val; 1354 u64 val; 1355 u8 is_write; 1356 int blkaddr; 1357 }; 1358 1359 struct cpt_lf_alloc_req_msg { 1360 struct mbox_msghdr hdr; 1361 u16 nix_pf_func; 1362 u16 sso_pf_func; 1363 u16 eng_grpmsk; 1364 int blkaddr; 1365 }; 1366 1367 /* Mailbox message request and response format for CPT stats. */ 1368 struct cpt_sts_req { 1369 struct mbox_msghdr hdr; 1370 u8 blkaddr; 1371 }; 1372 1373 struct cpt_sts_rsp { 1374 struct mbox_msghdr hdr; 1375 u64 inst_req_pc; 1376 u64 inst_lat_pc; 1377 u64 rd_req_pc; 1378 u64 rd_lat_pc; 1379 u64 rd_uc_pc; 1380 u64 active_cycles_pc; 1381 u64 ctx_mis_pc; 1382 u64 ctx_hit_pc; 1383 u64 ctx_aop_pc; 1384 u64 ctx_aop_lat_pc; 1385 u64 ctx_ifetch_pc; 1386 u64 ctx_ifetch_lat_pc; 1387 u64 ctx_ffetch_pc; 1388 u64 ctx_ffetch_lat_pc; 1389 u64 ctx_wback_pc; 1390 u64 ctx_wback_lat_pc; 1391 u64 ctx_psh_pc; 1392 u64 ctx_psh_lat_pc; 1393 u64 ctx_err; 1394 u64 ctx_enc_id; 1395 u64 ctx_flush_timer; 1396 u64 rxc_time; 1397 u64 rxc_time_cfg; 1398 u64 rxc_active_sts; 1399 u64 rxc_zombie_sts; 1400 u64 busy_sts_ae; 1401 u64 free_sts_ae; 1402 u64 busy_sts_se; 1403 u64 free_sts_se; 1404 u64 busy_sts_ie; 1405 u64 free_sts_ie; 1406 u64 exe_err_info; 1407 u64 cptclk_cnt; 1408 u64 diag; 1409 u64 rxc_dfrg; 1410 u64 x2p_link_cfg0; 1411 u64 x2p_link_cfg1; 1412 }; 1413 1414 /* Mailbox message request format to configure reassembly timeout. */ 1415 struct cpt_rxc_time_cfg_req { 1416 struct mbox_msghdr hdr; 1417 int blkaddr; 1418 u32 step; 1419 u16 zombie_thres; 1420 u16 zombie_limit; 1421 u16 active_thres; 1422 u16 active_limit; 1423 }; 1424 1425 #endif /* MBOX_H */ 1426