1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 #define MBOX_DOWN_MSG 1 20 #define MBOX_UP_MSG 2 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x000a) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 104 struct pci_dev *pdev, void __force *reg_base, 105 int direction, int ndevs, unsigned long *bmap); 106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 111 int size, int size_rsp); 112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 113 struct mbox_msghdr *msg); 114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 116 u16 pcifunc, u16 id); 117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 118 const char *otx2_mbox_id2name(u16 id); 119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 120 int devid, int size) 121 { 122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 123 } 124 125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 126 127 /* Mailbox message types */ 128 #define MBOX_MSG_MASK 0xFFFF 129 #define MBOX_MSG_INVALID 0xFFFE 130 #define MBOX_MSG_MAX 0xFFFF 131 132 #define MBOX_MESSAGES \ 133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 143 msg_rsp) \ 144 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 145 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 146 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 147 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 148 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 149 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 150 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 151 cgx_mac_addr_set_or_get) \ 152 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 153 cgx_mac_addr_set_or_get) \ 154 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 155 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 156 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 157 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 158 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 159 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 160 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 161 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 162 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 163 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 164 cgx_pause_frm_cfg) \ 165 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 166 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 167 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 168 cgx_mac_addr_add_rsp) \ 169 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 170 msg_rsp) \ 171 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 172 cgx_max_dmac_entries_get_rsp) \ 173 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 174 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 175 cgx_set_link_mode_rsp) \ 176 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 177 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 178 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 179 cgx_features_info_msg) \ 180 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 181 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 182 msg_rsp) \ 183 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 184 cgx_mac_addr_update_rsp) \ 185 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 186 cgx_pfc_rsp) \ 187 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 188 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 189 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 190 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 191 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 192 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 193 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 194 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 195 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 196 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 197 msg_rsp) \ 198 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 199 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 200 cpt_rd_wr_reg_msg) \ 201 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 202 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 203 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 204 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 205 msg_rsp) \ 206 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 207 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 208 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 209 cpt_flt_eng_info_rsp) \ 210 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 211 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 212 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 213 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 214 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 215 npc_mcam_alloc_entry_rsp) \ 216 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 217 npc_mcam_free_entry_req, msg_rsp) \ 218 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 219 npc_mcam_write_entry_req, msg_rsp) \ 220 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 221 npc_mcam_ena_dis_entry_req, msg_rsp) \ 222 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 223 npc_mcam_ena_dis_entry_req, msg_rsp) \ 224 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 225 npc_mcam_shift_entry_rsp) \ 226 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 227 npc_mcam_alloc_counter_req, \ 228 npc_mcam_alloc_counter_rsp) \ 229 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 230 npc_mcam_oper_counter_req, msg_rsp) \ 231 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 232 npc_mcam_unmap_counter_req, msg_rsp) \ 233 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 234 npc_mcam_oper_counter_req, msg_rsp) \ 235 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 236 npc_mcam_oper_counter_req, \ 237 npc_mcam_oper_counter_rsp) \ 238 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 239 npc_mcam_alloc_and_write_entry_req, \ 240 npc_mcam_alloc_and_write_entry_rsp) \ 241 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 242 msg_req, npc_get_kex_cfg_rsp) \ 243 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 244 npc_install_flow_req, npc_install_flow_rsp) \ 245 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 246 npc_delete_flow_req, npc_delete_flow_rsp) \ 247 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 248 npc_mcam_read_entry_req, \ 249 npc_mcam_read_entry_rsp) \ 250 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 251 npc_set_pkind, msg_rsp) \ 252 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 253 msg_req, npc_mcam_read_base_rule_rsp) \ 254 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 255 npc_mcam_get_stats_req, \ 256 npc_mcam_get_stats_rsp) \ 257 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 258 npc_get_field_hash_info_req, \ 259 npc_get_field_hash_info_rsp) \ 260 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 261 npc_get_field_status_req, \ 262 npc_get_field_status_rsp) \ 263 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 264 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 265 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 266 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 267 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 268 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 269 hwctx_disable_req, msg_rsp) \ 270 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 271 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 272 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 273 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 274 nix_txschq_config) \ 275 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 276 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 277 nix_vtag_config_rsp) \ 278 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 279 nix_rss_flowkey_cfg, \ 280 nix_rss_flowkey_cfg_rsp) \ 281 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 282 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 283 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 284 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 285 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 286 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 287 nix_mark_format_cfg, \ 288 nix_mark_format_cfg_rsp) \ 289 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 290 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 291 nix_lso_format_cfg, \ 292 nix_lso_format_cfg_rsp) \ 293 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 294 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 295 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 296 nix_bp_cfg_rsp) \ 297 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 298 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 299 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 300 nix_inline_ipsec_cfg, msg_rsp) \ 301 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 302 nix_inline_ipsec_lf_cfg, msg_rsp) \ 303 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 304 nix_cn10k_aq_enq_rsp) \ 305 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 306 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 307 nix_bandprof_alloc_rsp) \ 308 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 309 msg_rsp) \ 310 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 311 nix_bandprof_get_hwinfo_rsp) \ 312 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 313 msg_req, nix_inline_ipsec_cfg) \ 314 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 315 nix_mcast_grp_create_rsp) \ 316 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 317 msg_rsp) \ 318 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 319 nix_mcast_grp_update_req, \ 320 nix_mcast_grp_update_rsp) \ 321 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 322 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 323 mcs_alloc_rsrc_rsp) \ 324 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 325 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 326 msg_rsp) \ 327 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 328 msg_rsp) \ 329 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 330 msg_rsp) \ 331 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 332 msg_rsp) \ 333 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 334 msg_rsp) \ 335 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 336 msg_rsp) \ 337 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 338 msg_rsp) \ 339 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 340 msg_rsp) \ 341 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 342 msg_rsp) \ 343 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 344 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 345 mcs_flowid_stats) \ 346 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 347 mcs_secy_stats) \ 348 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 349 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 350 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 351 mcs_port_stats) \ 352 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 353 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 354 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 355 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 356 msg_rsp) \ 357 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 358 mcs_alloc_ctrl_pkt_rule_req, \ 359 mcs_alloc_ctrl_pkt_rule_rsp) \ 360 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 361 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 362 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 363 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 364 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 365 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 366 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 367 mcs_port_cfg_get_rsp) \ 368 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 369 mcs_custom_tag_cfg_get_req, \ 370 mcs_custom_tag_cfg_get_rsp) 371 372 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 373 #define MBOX_UP_CGX_MESSAGES \ 374 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 375 376 #define MBOX_UP_CPT_MESSAGES \ 377 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 378 379 #define MBOX_UP_MCS_MESSAGES \ 380 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 381 382 enum { 383 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 384 MBOX_MESSAGES 385 MBOX_UP_CGX_MESSAGES 386 MBOX_UP_CPT_MESSAGES 387 MBOX_UP_MCS_MESSAGES 388 #undef M 389 }; 390 391 /* Mailbox message formats */ 392 393 #define RVU_DEFAULT_PF_FUNC 0xFFFF 394 395 /* Generic request msg used for those mbox messages which 396 * don't send any data in the request. 397 */ 398 struct msg_req { 399 struct mbox_msghdr hdr; 400 }; 401 402 /* Generic response msg used an ack or response for those mbox 403 * messages which don't have a specific rsp msg format. 404 */ 405 struct msg_rsp { 406 struct mbox_msghdr hdr; 407 }; 408 409 /* RVU mailbox error codes 410 * Range 256 - 300. 411 */ 412 enum rvu_af_status { 413 RVU_INVALID_VF_ID = -256, 414 }; 415 416 struct ready_msg_rsp { 417 struct mbox_msghdr hdr; 418 u16 sclk_freq; /* SCLK frequency (in MHz) */ 419 u16 rclk_freq; /* RCLK frequency (in MHz) */ 420 }; 421 422 /* Structure for requesting resource provisioning. 423 * 'modify' flag to be used when either requesting more 424 * or to detach partial of a certain resource type. 425 * Rest of the fields specify how many of what type to 426 * be attached. 427 * To request LFs from two blocks of same type this mailbox 428 * can be sent twice as below: 429 * struct rsrc_attach *attach; 430 * .. Allocate memory for message .. 431 * attach->cptlfs = 3; <3 LFs from CPT0> 432 * .. Send message .. 433 * .. Allocate memory for message .. 434 * attach->modify = 1; 435 * attach->cpt_blkaddr = BLKADDR_CPT1; 436 * attach->cptlfs = 2; <2 LFs from CPT1> 437 * .. Send message .. 438 */ 439 struct rsrc_attach { 440 struct mbox_msghdr hdr; 441 u8 modify:1; 442 u8 npalf:1; 443 u8 nixlf:1; 444 u16 sso; 445 u16 ssow; 446 u16 timlfs; 447 u16 cptlfs; 448 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 449 }; 450 451 /* Structure for relinquishing resources. 452 * 'partial' flag to be used when relinquishing all resources 453 * but only of a certain type. If not set, all resources of all 454 * types provisioned to the RVU function will be detached. 455 */ 456 struct rsrc_detach { 457 struct mbox_msghdr hdr; 458 u8 partial:1; 459 u8 npalf:1; 460 u8 nixlf:1; 461 u8 sso:1; 462 u8 ssow:1; 463 u8 timlfs:1; 464 u8 cptlfs:1; 465 }; 466 467 /* Number of resources available to the caller. 468 * In reply to MBOX_MSG_FREE_RSRC_CNT. 469 */ 470 struct free_rsrcs_rsp { 471 struct mbox_msghdr hdr; 472 u16 schq[NIX_TXSCH_LVL_CNT]; 473 u16 sso; 474 u16 tim; 475 u16 ssow; 476 u16 cpt; 477 u8 npa; 478 u8 nix; 479 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 480 u8 nix1; 481 u8 cpt1; 482 u8 ree0; 483 u8 ree1; 484 }; 485 486 #define MSIX_VECTOR_INVALID 0xFFFF 487 #define MAX_RVU_BLKLF_CNT 256 488 489 struct msix_offset_rsp { 490 struct mbox_msghdr hdr; 491 u16 npa_msixoff; 492 u16 nix_msixoff; 493 u16 sso; 494 u16 ssow; 495 u16 timlfs; 496 u16 cptlfs; 497 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 498 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 499 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 500 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 501 u16 cpt1_lfs; 502 u16 ree0_lfs; 503 u16 ree1_lfs; 504 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 505 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 506 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 507 }; 508 509 struct get_hw_cap_rsp { 510 struct mbox_msghdr hdr; 511 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 512 u8 nix_shaping; /* Is shaping and coloring supported */ 513 u8 npc_hash_extract; /* Is hash extract supported */ 514 }; 515 516 /* CGX mbox message formats */ 517 518 struct cgx_stats_rsp { 519 struct mbox_msghdr hdr; 520 #define CGX_RX_STATS_COUNT 9 521 #define CGX_TX_STATS_COUNT 18 522 u64 rx_stats[CGX_RX_STATS_COUNT]; 523 u64 tx_stats[CGX_TX_STATS_COUNT]; 524 }; 525 526 struct cgx_fec_stats_rsp { 527 struct mbox_msghdr hdr; 528 u64 fec_corr_blks; 529 u64 fec_uncorr_blks; 530 }; 531 /* Structure for requesting the operation for 532 * setting/getting mac address in the CGX interface 533 */ 534 struct cgx_mac_addr_set_or_get { 535 struct mbox_msghdr hdr; 536 u8 mac_addr[ETH_ALEN]; 537 u32 index; 538 }; 539 540 /* Structure for requesting the operation to 541 * add DMAC filter entry into CGX interface 542 */ 543 struct cgx_mac_addr_add_req { 544 struct mbox_msghdr hdr; 545 u8 mac_addr[ETH_ALEN]; 546 }; 547 548 /* Structure for response against the operation to 549 * add DMAC filter entry into CGX interface 550 */ 551 struct cgx_mac_addr_add_rsp { 552 struct mbox_msghdr hdr; 553 u32 index; 554 }; 555 556 /* Structure for requesting the operation to 557 * delete DMAC filter entry from CGX interface 558 */ 559 struct cgx_mac_addr_del_req { 560 struct mbox_msghdr hdr; 561 u32 index; 562 }; 563 564 /* Structure for response against the operation to 565 * get maximum supported DMAC filter entries 566 */ 567 struct cgx_max_dmac_entries_get_rsp { 568 struct mbox_msghdr hdr; 569 u32 max_dmac_filters; 570 }; 571 572 struct cgx_link_user_info { 573 uint64_t link_up:1; 574 uint64_t full_duplex:1; 575 uint64_t lmac_type_id:4; 576 uint64_t speed:20; /* speed in Mbps */ 577 uint64_t an:1; /* AN supported or not */ 578 uint64_t fec:2; /* FEC type if enabled else 0 */ 579 #define LMACTYPE_STR_LEN 16 580 char lmac_type[LMACTYPE_STR_LEN]; 581 }; 582 583 struct cgx_link_info_msg { 584 struct mbox_msghdr hdr; 585 struct cgx_link_user_info link_info; 586 }; 587 588 struct cgx_pause_frm_cfg { 589 struct mbox_msghdr hdr; 590 u8 set; 591 /* set = 1 if the request is to config pause frames */ 592 /* set = 0 if the request is to fetch pause frames config */ 593 u8 rx_pause; 594 u8 tx_pause; 595 }; 596 597 enum fec_type { 598 OTX2_FEC_NONE, 599 OTX2_FEC_BASER, 600 OTX2_FEC_RS, 601 OTX2_FEC_STATS_CNT = 2, 602 OTX2_FEC_OFF, 603 }; 604 605 struct fec_mode { 606 struct mbox_msghdr hdr; 607 int fec; 608 }; 609 610 struct sfp_eeprom_s { 611 #define SFP_EEPROM_SIZE 256 612 u16 sff_id; 613 u8 buf[SFP_EEPROM_SIZE]; 614 u64 reserved; 615 }; 616 617 struct phy_s { 618 struct { 619 u64 can_change_mod_type:1; 620 u64 mod_type:1; 621 u64 has_fec_stats:1; 622 } misc; 623 struct fec_stats_s { 624 u32 rsfec_corr_cws; 625 u32 rsfec_uncorr_cws; 626 u32 brfec_corr_blks; 627 u32 brfec_uncorr_blks; 628 } fec_stats; 629 }; 630 631 struct cgx_lmac_fwdata_s { 632 u16 rw_valid; 633 u64 supported_fec; 634 u64 supported_an; 635 u64 supported_link_modes; 636 /* only applicable if AN is supported */ 637 u64 advertised_fec; 638 u64 advertised_link_modes; 639 /* Only applicable if SFP/QSFP slot is present */ 640 struct sfp_eeprom_s sfp_eeprom; 641 struct phy_s phy; 642 #define LMAC_FWDATA_RESERVED_MEM 1021 643 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 644 }; 645 646 struct cgx_fw_data { 647 struct mbox_msghdr hdr; 648 struct cgx_lmac_fwdata_s fwdata; 649 }; 650 651 struct cgx_set_link_mode_args { 652 u32 speed; 653 u8 duplex; 654 u8 an; 655 u8 ports; 656 u64 mode; 657 }; 658 659 struct cgx_set_link_mode_req { 660 #define AUTONEG_UNKNOWN 0xff 661 struct mbox_msghdr hdr; 662 struct cgx_set_link_mode_args args; 663 }; 664 665 struct cgx_set_link_mode_rsp { 666 struct mbox_msghdr hdr; 667 int status; 668 }; 669 670 struct cgx_mac_addr_reset_req { 671 struct mbox_msghdr hdr; 672 u32 index; 673 }; 674 675 struct cgx_mac_addr_update_req { 676 struct mbox_msghdr hdr; 677 u8 mac_addr[ETH_ALEN]; 678 u32 index; 679 }; 680 681 struct cgx_mac_addr_update_rsp { 682 struct mbox_msghdr hdr; 683 u32 index; 684 }; 685 686 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 687 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 688 /* flow control from physical link higig2 messages */ 689 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 690 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 691 #define RVU_MAC_VERSION BIT_ULL(4) 692 #define RVU_MAC_CGX BIT_ULL(5) 693 #define RVU_MAC_RPM BIT_ULL(6) 694 695 struct cgx_features_info_msg { 696 struct mbox_msghdr hdr; 697 u64 lmac_features; 698 }; 699 700 struct rpm_stats_rsp { 701 struct mbox_msghdr hdr; 702 #define RPM_RX_STATS_COUNT 43 703 #define RPM_TX_STATS_COUNT 34 704 u64 rx_stats[RPM_RX_STATS_COUNT]; 705 u64 tx_stats[RPM_TX_STATS_COUNT]; 706 }; 707 708 struct cgx_pfc_cfg { 709 struct mbox_msghdr hdr; 710 u8 rx_pause; 711 u8 tx_pause; 712 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 713 }; 714 715 struct cgx_pfc_rsp { 716 struct mbox_msghdr hdr; 717 u8 rx_pause; 718 u8 tx_pause; 719 }; 720 721 /* NPA mbox message formats */ 722 723 struct npc_set_pkind { 724 struct mbox_msghdr hdr; 725 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 726 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 727 u64 mode; 728 #define PKIND_TX BIT_ULL(0) 729 #define PKIND_RX BIT_ULL(1) 730 u8 dir; 731 u8 pkind; /* valid only in case custom flag */ 732 u8 var_len_off; /* Offset of custom header length field. 733 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 734 */ 735 u8 var_len_off_mask; /* Mask for length with in offset */ 736 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 737 }; 738 739 /* NPA mbox message formats */ 740 741 /* NPA mailbox error codes 742 * Range 301 - 400. 743 */ 744 enum npa_af_status { 745 NPA_AF_ERR_PARAM = -301, 746 NPA_AF_ERR_AQ_FULL = -302, 747 NPA_AF_ERR_AQ_ENQUEUE = -303, 748 NPA_AF_ERR_AF_LF_INVALID = -304, 749 NPA_AF_ERR_AF_LF_ALLOC = -305, 750 NPA_AF_ERR_LF_RESET = -306, 751 }; 752 753 /* For NPA LF context alloc and init */ 754 struct npa_lf_alloc_req { 755 struct mbox_msghdr hdr; 756 int node; 757 int aura_sz; /* No of auras */ 758 u32 nr_pools; /* No of pools */ 759 u64 way_mask; 760 }; 761 762 struct npa_lf_alloc_rsp { 763 struct mbox_msghdr hdr; 764 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 765 u32 stack_pg_bytes; /* Size of stack page */ 766 u16 qints; /* NPA_AF_CONST::QINTS */ 767 u8 cache_lines; /*BATCH ALLOC DMA */ 768 }; 769 770 /* NPA AQ enqueue msg */ 771 struct npa_aq_enq_req { 772 struct mbox_msghdr hdr; 773 u32 aura_id; 774 u8 ctype; 775 u8 op; 776 union { 777 /* Valid when op == WRITE/INIT and ctype == AURA. 778 * LF fills the pool_id in aura.pool_addr. AF will translate 779 * the pool_id to pool context pointer. 780 */ 781 struct npa_aura_s aura; 782 /* Valid when op == WRITE/INIT and ctype == POOL */ 783 struct npa_pool_s pool; 784 }; 785 /* Mask data when op == WRITE (1=write, 0=don't write) */ 786 union { 787 /* Valid when op == WRITE and ctype == AURA */ 788 struct npa_aura_s aura_mask; 789 /* Valid when op == WRITE and ctype == POOL */ 790 struct npa_pool_s pool_mask; 791 }; 792 }; 793 794 struct npa_aq_enq_rsp { 795 struct mbox_msghdr hdr; 796 union { 797 /* Valid when op == READ and ctype == AURA */ 798 struct npa_aura_s aura; 799 /* Valid when op == READ and ctype == POOL */ 800 struct npa_pool_s pool; 801 }; 802 }; 803 804 /* Disable all contexts of type 'ctype' */ 805 struct hwctx_disable_req { 806 struct mbox_msghdr hdr; 807 u8 ctype; 808 }; 809 810 /* NIX mbox message formats */ 811 812 /* NIX mailbox error codes 813 * Range 401 - 500. 814 */ 815 enum nix_af_status { 816 NIX_AF_ERR_PARAM = -401, 817 NIX_AF_ERR_AQ_FULL = -402, 818 NIX_AF_ERR_AQ_ENQUEUE = -403, 819 NIX_AF_ERR_AF_LF_INVALID = -404, 820 NIX_AF_ERR_AF_LF_ALLOC = -405, 821 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 822 NIX_AF_ERR_TLX_INVALID = -407, 823 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 824 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 825 NIX_AF_ERR_FRS_INVALID = -410, 826 NIX_AF_ERR_RX_LINK_INVALID = -411, 827 NIX_AF_INVAL_TXSCHQ_CFG = -412, 828 NIX_AF_SMQ_FLUSH_FAILED = -413, 829 NIX_AF_ERR_LF_RESET = -414, 830 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 831 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 832 NIX_AF_ERR_MARK_CFG_FAIL = -417, 833 NIX_AF_ERR_LSO_CFG_FAIL = -418, 834 NIX_AF_INVAL_NPA_PF_FUNC = -419, 835 NIX_AF_INVAL_SSO_PF_FUNC = -420, 836 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 837 NIX_AF_ERR_RX_VTAG_INUSE = -422, 838 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 839 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 840 NIX_AF_ERR_INVALID_NIXBLK = -425, 841 NIX_AF_ERR_INVALID_BANDPROF = -426, 842 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 843 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 844 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 845 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 846 NIX_AF_ERR_LINK_CREDITS = -431, 847 NIX_AF_ERR_INVALID_BPID = -434, 848 NIX_AF_ERR_INVALID_BPID_REQ = -435, 849 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 850 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 851 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 852 }; 853 854 /* For NIX RX vtag action */ 855 enum nix_rx_vtag0_type { 856 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 857 NIX_AF_LFX_RX_VTAG_TYPE1, 858 NIX_AF_LFX_RX_VTAG_TYPE2, 859 NIX_AF_LFX_RX_VTAG_TYPE3, 860 NIX_AF_LFX_RX_VTAG_TYPE4, 861 NIX_AF_LFX_RX_VTAG_TYPE5, 862 NIX_AF_LFX_RX_VTAG_TYPE6, 863 NIX_AF_LFX_RX_VTAG_TYPE7, 864 }; 865 866 /* For NIX LF context alloc and init */ 867 struct nix_lf_alloc_req { 868 struct mbox_msghdr hdr; 869 int node; 870 u32 rq_cnt; /* No of receive queues */ 871 u32 sq_cnt; /* No of send queues */ 872 u32 cq_cnt; /* No of completion queues */ 873 u8 xqe_sz; 874 u16 rss_sz; 875 u8 rss_grps; 876 u16 npa_func; 877 u16 sso_func; 878 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 879 u64 way_mask; 880 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 881 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 882 u64 flags; 883 }; 884 885 struct nix_lf_alloc_rsp { 886 struct mbox_msghdr hdr; 887 u16 sqb_size; 888 u16 rx_chan_base; 889 u16 tx_chan_base; 890 u8 rx_chan_cnt; /* total number of RX channels */ 891 u8 tx_chan_cnt; /* total number of TX channels */ 892 u8 lso_tsov4_idx; 893 u8 lso_tsov6_idx; 894 u8 mac_addr[ETH_ALEN]; 895 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 896 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 897 u16 cints; /* NIX_AF_CONST2::CINTS */ 898 u16 qints; /* NIX_AF_CONST2::QINTS */ 899 u8 cgx_links; /* No. of CGX links present in HW */ 900 u8 lbk_links; /* No. of LBK links present in HW */ 901 u8 sdp_links; /* No. of SDP links present in HW */ 902 u8 tx_link; /* Transmit channel link number */ 903 }; 904 905 struct nix_lf_free_req { 906 struct mbox_msghdr hdr; 907 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 908 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 909 u64 flags; 910 }; 911 912 /* CN10K NIX AQ enqueue msg */ 913 struct nix_cn10k_aq_enq_req { 914 struct mbox_msghdr hdr; 915 u32 qidx; 916 u8 ctype; 917 u8 op; 918 union { 919 struct nix_cn10k_rq_ctx_s rq; 920 struct nix_cn10k_sq_ctx_s sq; 921 struct nix_cq_ctx_s cq; 922 struct nix_rsse_s rss; 923 struct nix_rx_mce_s mce; 924 struct nix_bandprof_s prof; 925 }; 926 union { 927 struct nix_cn10k_rq_ctx_s rq_mask; 928 struct nix_cn10k_sq_ctx_s sq_mask; 929 struct nix_cq_ctx_s cq_mask; 930 struct nix_rsse_s rss_mask; 931 struct nix_rx_mce_s mce_mask; 932 struct nix_bandprof_s prof_mask; 933 }; 934 }; 935 936 struct nix_cn10k_aq_enq_rsp { 937 struct mbox_msghdr hdr; 938 union { 939 struct nix_cn10k_rq_ctx_s rq; 940 struct nix_cn10k_sq_ctx_s sq; 941 struct nix_cq_ctx_s cq; 942 struct nix_rsse_s rss; 943 struct nix_rx_mce_s mce; 944 struct nix_bandprof_s prof; 945 }; 946 }; 947 948 /* NIX AQ enqueue msg */ 949 struct nix_aq_enq_req { 950 struct mbox_msghdr hdr; 951 u32 qidx; 952 u8 ctype; 953 u8 op; 954 union { 955 struct nix_rq_ctx_s rq; 956 struct nix_sq_ctx_s sq; 957 struct nix_cq_ctx_s cq; 958 struct nix_rsse_s rss; 959 struct nix_rx_mce_s mce; 960 struct nix_bandprof_s prof; 961 }; 962 union { 963 struct nix_rq_ctx_s rq_mask; 964 struct nix_sq_ctx_s sq_mask; 965 struct nix_cq_ctx_s cq_mask; 966 struct nix_rsse_s rss_mask; 967 struct nix_rx_mce_s mce_mask; 968 struct nix_bandprof_s prof_mask; 969 }; 970 }; 971 972 struct nix_aq_enq_rsp { 973 struct mbox_msghdr hdr; 974 union { 975 struct nix_rq_ctx_s rq; 976 struct nix_sq_ctx_s sq; 977 struct nix_cq_ctx_s cq; 978 struct nix_rsse_s rss; 979 struct nix_rx_mce_s mce; 980 struct nix_bandprof_s prof; 981 }; 982 }; 983 984 /* Tx scheduler/shaper mailbox messages */ 985 986 #define MAX_TXSCHQ_PER_FUNC 128 987 988 struct nix_txsch_alloc_req { 989 struct mbox_msghdr hdr; 990 /* Scheduler queue count request at each level */ 991 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 992 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 993 }; 994 995 struct nix_txsch_alloc_rsp { 996 struct mbox_msghdr hdr; 997 /* Scheduler queue count allocated at each level */ 998 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 999 u16 schq[NIX_TXSCH_LVL_CNT]; 1000 /* Scheduler queue list allocated at each level */ 1001 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1002 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1003 u8 aggr_level; /* Traffic aggregation scheduler level */ 1004 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 1005 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 1006 }; 1007 1008 struct nix_txsch_free_req { 1009 struct mbox_msghdr hdr; 1010 #define TXSCHQ_FREE_ALL BIT_ULL(0) 1011 u16 flags; 1012 /* Scheduler queue level to be freed */ 1013 u16 schq_lvl; 1014 /* List of scheduler queues to be freed */ 1015 u16 schq; 1016 }; 1017 1018 struct nix_txschq_config { 1019 struct mbox_msghdr hdr; 1020 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1021 u8 read; 1022 #define TXSCHQ_IDX_SHIFT 16 1023 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1024 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1025 u8 num_regs; 1026 #define MAX_REGS_PER_MBOX_MSG 20 1027 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1028 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1029 /* All 0's => overwrite with new value */ 1030 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1031 }; 1032 1033 struct nix_vtag_config { 1034 struct mbox_msghdr hdr; 1035 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1036 u8 vtag_size; 1037 /* cfg_type is '0' for tx vlan cfg 1038 * cfg_type is '1' for rx vlan cfg 1039 */ 1040 u8 cfg_type; 1041 union { 1042 /* valid when cfg_type is '0' */ 1043 struct { 1044 u64 vtag0; 1045 u64 vtag1; 1046 1047 /* cfg_vtag0 & cfg_vtag1 fields are valid 1048 * when free_vtag0 & free_vtag1 are '0's. 1049 */ 1050 /* cfg_vtag0 = 1 to configure vtag0 */ 1051 u8 cfg_vtag0 :1; 1052 /* cfg_vtag1 = 1 to configure vtag1 */ 1053 u8 cfg_vtag1 :1; 1054 1055 /* vtag0_idx & vtag1_idx are only valid when 1056 * both cfg_vtag0 & cfg_vtag1 are '0's, 1057 * these fields are used along with free_vtag0 1058 * & free_vtag1 to free the nix lf's tx_vlan 1059 * configuration. 1060 * 1061 * Denotes the indices of tx_vtag def registers 1062 * that needs to be cleared and freed. 1063 */ 1064 int vtag0_idx; 1065 int vtag1_idx; 1066 1067 /* free_vtag0 & free_vtag1 fields are valid 1068 * when cfg_vtag0 & cfg_vtag1 are '0's. 1069 */ 1070 /* free_vtag0 = 1 clears vtag0 configuration 1071 * vtag0_idx denotes the index to be cleared. 1072 */ 1073 u8 free_vtag0 :1; 1074 /* free_vtag1 = 1 clears vtag1 configuration 1075 * vtag1_idx denotes the index to be cleared. 1076 */ 1077 u8 free_vtag1 :1; 1078 } tx; 1079 1080 /* valid when cfg_type is '1' */ 1081 struct { 1082 /* rx vtag type index, valid values are in 0..7 range */ 1083 u8 vtag_type; 1084 /* rx vtag strip */ 1085 u8 strip_vtag :1; 1086 /* rx vtag capture */ 1087 u8 capture_vtag :1; 1088 } rx; 1089 }; 1090 }; 1091 1092 struct nix_vtag_config_rsp { 1093 struct mbox_msghdr hdr; 1094 int vtag0_idx; 1095 int vtag1_idx; 1096 /* Indices of tx_vtag def registers used to configure 1097 * tx vtag0 & vtag1 headers, these indices are valid 1098 * when nix_vtag_config mbox requested for vtag0 and/ 1099 * or vtag1 configuration. 1100 */ 1101 }; 1102 1103 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1104 1105 struct nix_rss_flowkey_cfg { 1106 struct mbox_msghdr hdr; 1107 int mcam_index; /* MCAM entry index to modify */ 1108 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1109 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1110 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1111 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1112 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1113 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1114 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1115 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1116 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1117 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1118 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1119 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1120 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1121 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1122 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1123 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1124 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1125 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1126 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1127 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1128 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1129 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1130 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1131 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1132 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1133 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1134 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1135 u32 flowkey_cfg; /* Flowkey types selected */ 1136 u8 group; /* RSS context or group */ 1137 }; 1138 1139 struct nix_rss_flowkey_cfg_rsp { 1140 struct mbox_msghdr hdr; 1141 u8 alg_idx; /* Selected algo index */ 1142 }; 1143 1144 struct nix_set_mac_addr { 1145 struct mbox_msghdr hdr; 1146 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1147 }; 1148 1149 struct nix_get_mac_addr_rsp { 1150 struct mbox_msghdr hdr; 1151 u8 mac_addr[ETH_ALEN]; 1152 }; 1153 1154 struct nix_mark_format_cfg { 1155 struct mbox_msghdr hdr; 1156 u8 offset; 1157 u8 y_mask; 1158 u8 y_val; 1159 u8 r_mask; 1160 u8 r_val; 1161 }; 1162 1163 struct nix_mark_format_cfg_rsp { 1164 struct mbox_msghdr hdr; 1165 u8 mark_format_idx; 1166 }; 1167 1168 struct nix_rx_mode { 1169 struct mbox_msghdr hdr; 1170 #define NIX_RX_MODE_UCAST BIT(0) 1171 #define NIX_RX_MODE_PROMISC BIT(1) 1172 #define NIX_RX_MODE_ALLMULTI BIT(2) 1173 #define NIX_RX_MODE_USE_MCE BIT(3) 1174 u16 mode; 1175 }; 1176 1177 struct nix_rx_cfg { 1178 struct mbox_msghdr hdr; 1179 #define NIX_RX_OL3_VERIFY BIT(0) 1180 #define NIX_RX_OL4_VERIFY BIT(1) 1181 #define NIX_RX_DROP_RE BIT(2) 1182 u8 len_verify; /* Outer L3/L4 len check */ 1183 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1184 u8 csum_verify; /* Outer L4 checksum verification */ 1185 }; 1186 1187 struct nix_frs_cfg { 1188 struct mbox_msghdr hdr; 1189 u8 update_smq; /* Update SMQ's min/max lens */ 1190 u8 update_minlen; /* Set minlen also */ 1191 u8 sdp_link; /* Set SDP RX link */ 1192 u16 maxlen; 1193 u16 minlen; 1194 }; 1195 1196 struct nix_lso_format_cfg { 1197 struct mbox_msghdr hdr; 1198 u64 field_mask; 1199 #define NIX_LSO_FIELD_MAX 8 1200 u64 fields[NIX_LSO_FIELD_MAX]; 1201 }; 1202 1203 struct nix_lso_format_cfg_rsp { 1204 struct mbox_msghdr hdr; 1205 u8 lso_format_idx; 1206 }; 1207 1208 struct nix_bp_cfg_req { 1209 struct mbox_msghdr hdr; 1210 u16 chan_base; /* Starting channel number */ 1211 u8 chan_cnt; /* Number of channels */ 1212 u8 bpid_per_chan; 1213 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1214 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1215 }; 1216 1217 /* Maximum channels any single NIX interface can have */ 1218 #define NIX_MAX_BPID_CHAN 256 1219 struct nix_bp_cfg_rsp { 1220 struct mbox_msghdr hdr; 1221 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1222 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1223 }; 1224 1225 struct nix_mcast_grp_create_req { 1226 struct mbox_msghdr hdr; 1227 #define NIX_MCAST_INGRESS 0 1228 #define NIX_MCAST_EGRESS 1 1229 u8 dir; 1230 u8 reserved[11]; 1231 /* Reserving few bytes for future requirement */ 1232 }; 1233 1234 struct nix_mcast_grp_create_rsp { 1235 struct mbox_msghdr hdr; 1236 /* This mcast_grp_idx should be passed during MCAM 1237 * write entry for multicast. AF will identify the 1238 * corresponding multicast table index associated 1239 * with the group id and program the same to MCAM entry. 1240 * This group id is also needed during group delete 1241 * and update request. 1242 */ 1243 u32 mcast_grp_idx; 1244 }; 1245 1246 struct nix_mcast_grp_destroy_req { 1247 struct mbox_msghdr hdr; 1248 /* Group id returned by nix_mcast_grp_create_rsp */ 1249 u32 mcast_grp_idx; 1250 /* If AF is requesting for destroy, then set 1251 * it to '1'. Otherwise keep it to '0' 1252 */ 1253 u8 is_af; 1254 }; 1255 1256 struct nix_mcast_grp_update_req { 1257 struct mbox_msghdr hdr; 1258 /* Group id returned by nix_mcast_grp_create_rsp */ 1259 u32 mcast_grp_idx; 1260 /* Number of multicast/mirror entries requested */ 1261 u32 num_mce_entry; 1262 #define NIX_MCE_ENTRY_MAX 64 1263 #define NIX_RX_RQ 0 1264 #define NIX_RX_RSS 1 1265 /* Receive queue or RSS index within pf_func */ 1266 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1267 /* pcifunc is required for both ingress and egress multicast */ 1268 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1269 /* channel is required for egress multicast */ 1270 u16 channel[NIX_MCE_ENTRY_MAX]; 1271 #define NIX_MCAST_OP_ADD_ENTRY 0 1272 #define NIX_MCAST_OP_DEL_ENTRY 1 1273 /* Destination type. 0:Receive queue, 1:RSS*/ 1274 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1275 u8 op; 1276 /* If AF is requesting for update, then set 1277 * it to '1'. Otherwise keep it to '0' 1278 */ 1279 u8 is_af; 1280 }; 1281 1282 struct nix_mcast_grp_update_rsp { 1283 struct mbox_msghdr hdr; 1284 u32 mce_start_index; 1285 }; 1286 1287 /* Global NIX inline IPSec configuration */ 1288 struct nix_inline_ipsec_cfg { 1289 struct mbox_msghdr hdr; 1290 u32 cpt_credit; 1291 struct { 1292 u8 egrp; 1293 u16 opcode; 1294 u16 param1; 1295 u16 param2; 1296 } gen_cfg; 1297 struct { 1298 u16 cpt_pf_func; 1299 u8 cpt_slot; 1300 } inst_qsel; 1301 u8 enable; 1302 u16 bpid; 1303 u32 credit_th; 1304 }; 1305 1306 /* Per NIX LF inline IPSec configuration */ 1307 struct nix_inline_ipsec_lf_cfg { 1308 struct mbox_msghdr hdr; 1309 u64 sa_base_addr; 1310 struct { 1311 u32 tag_const; 1312 u16 lenm1_max; 1313 u8 sa_pow2_size; 1314 u8 tt; 1315 } ipsec_cfg0; 1316 struct { 1317 u32 sa_idx_max; 1318 u8 sa_idx_w; 1319 } ipsec_cfg1; 1320 u8 enable; 1321 }; 1322 1323 struct nix_hw_info { 1324 struct mbox_msghdr hdr; 1325 u16 rsvs16; 1326 u16 max_mtu; 1327 u16 min_mtu; 1328 u32 rpm_dwrr_mtu; 1329 u32 sdp_dwrr_mtu; 1330 u32 lbk_dwrr_mtu; 1331 u32 rsvd32[1]; 1332 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1333 }; 1334 1335 struct nix_bandprof_alloc_req { 1336 struct mbox_msghdr hdr; 1337 /* Count of profiles needed per layer */ 1338 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1339 }; 1340 1341 struct nix_bandprof_alloc_rsp { 1342 struct mbox_msghdr hdr; 1343 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1344 1345 /* There is no need to allocate morethan 1 bandwidth profile 1346 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1347 * profiles to 64 per PF_FUNC. 1348 */ 1349 #define MAX_BANDPROF_PER_PFFUNC 64 1350 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1351 }; 1352 1353 struct nix_bandprof_free_req { 1354 struct mbox_msghdr hdr; 1355 u8 free_all; 1356 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1357 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1358 }; 1359 1360 struct nix_bandprof_get_hwinfo_rsp { 1361 struct mbox_msghdr hdr; 1362 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1363 u32 policer_timeunit; 1364 }; 1365 1366 /* NPC mbox message structs */ 1367 1368 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1369 #define NPC_MCAM_INVALID_MAP 0xFFFF 1370 1371 /* NPC mailbox error codes 1372 * Range 701 - 800. 1373 */ 1374 enum npc_af_status { 1375 NPC_MCAM_INVALID_REQ = -701, 1376 NPC_MCAM_ALLOC_DENIED = -702, 1377 NPC_MCAM_ALLOC_FAILED = -703, 1378 NPC_MCAM_PERM_DENIED = -704, 1379 NPC_FLOW_INTF_INVALID = -707, 1380 NPC_FLOW_CHAN_INVALID = -708, 1381 NPC_FLOW_NO_NIXLF = -709, 1382 NPC_FLOW_NOT_SUPPORTED = -710, 1383 NPC_FLOW_VF_PERM_DENIED = -711, 1384 NPC_FLOW_VF_NOT_INIT = -712, 1385 NPC_FLOW_VF_OVERLAP = -713, 1386 }; 1387 1388 struct npc_mcam_alloc_entry_req { 1389 struct mbox_msghdr hdr; 1390 #define NPC_MAX_NONCONTIG_ENTRIES 256 1391 u8 contig; /* Contiguous entries ? */ 1392 #define NPC_MCAM_ANY_PRIO 0 1393 #define NPC_MCAM_LOWER_PRIO 1 1394 #define NPC_MCAM_HIGHER_PRIO 2 1395 u8 priority; /* Lower or higher w.r.t ref_entry */ 1396 u16 ref_entry; 1397 u16 count; /* Number of entries requested */ 1398 }; 1399 1400 struct npc_mcam_alloc_entry_rsp { 1401 struct mbox_msghdr hdr; 1402 u16 entry; /* Entry allocated or start index if contiguous. 1403 * Invalid incase of non-contiguous. 1404 */ 1405 u16 count; /* Number of entries allocated */ 1406 u16 free_count; /* Number of entries available */ 1407 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1408 }; 1409 1410 struct npc_mcam_free_entry_req { 1411 struct mbox_msghdr hdr; 1412 u16 entry; /* Entry index to be freed */ 1413 u8 all; /* If all entries allocated to this PFVF to be freed */ 1414 }; 1415 1416 struct mcam_entry { 1417 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1418 u64 kw[NPC_MAX_KWS_IN_KEY]; 1419 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1420 u64 action; 1421 u64 vtag_action; 1422 }; 1423 1424 struct npc_mcam_write_entry_req { 1425 struct mbox_msghdr hdr; 1426 struct mcam_entry entry_data; 1427 u16 entry; /* MCAM entry to write this match key */ 1428 u16 cntr; /* Counter for this MCAM entry */ 1429 u8 intf; /* Rx or Tx interface */ 1430 u8 enable_entry;/* Enable this MCAM entry ? */ 1431 u8 set_cntr; /* Set counter for this entry ? */ 1432 }; 1433 1434 /* Enable/Disable a given entry */ 1435 struct npc_mcam_ena_dis_entry_req { 1436 struct mbox_msghdr hdr; 1437 u16 entry; 1438 }; 1439 1440 struct npc_mcam_shift_entry_req { 1441 struct mbox_msghdr hdr; 1442 #define NPC_MCAM_MAX_SHIFTS 64 1443 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1444 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1445 u16 shift_count; /* Number of entries to shift */ 1446 }; 1447 1448 struct npc_mcam_shift_entry_rsp { 1449 struct mbox_msghdr hdr; 1450 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1451 }; 1452 1453 struct npc_mcam_alloc_counter_req { 1454 struct mbox_msghdr hdr; 1455 u8 contig; /* Contiguous counters ? */ 1456 #define NPC_MAX_NONCONTIG_COUNTERS 64 1457 u16 count; /* Number of counters requested */ 1458 }; 1459 1460 struct npc_mcam_alloc_counter_rsp { 1461 struct mbox_msghdr hdr; 1462 u16 cntr; /* Counter allocated or start index if contiguous. 1463 * Invalid incase of non-contiguous. 1464 */ 1465 u16 count; /* Number of counters allocated */ 1466 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1467 }; 1468 1469 struct npc_mcam_oper_counter_req { 1470 struct mbox_msghdr hdr; 1471 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1472 }; 1473 1474 struct npc_mcam_oper_counter_rsp { 1475 struct mbox_msghdr hdr; 1476 u64 stat; /* valid only while fetching counter's stats */ 1477 }; 1478 1479 struct npc_mcam_unmap_counter_req { 1480 struct mbox_msghdr hdr; 1481 u16 cntr; 1482 u16 entry; /* Entry and counter to be unmapped */ 1483 u8 all; /* Unmap all entries using this counter ? */ 1484 }; 1485 1486 struct npc_mcam_alloc_and_write_entry_req { 1487 struct mbox_msghdr hdr; 1488 struct mcam_entry entry_data; 1489 u16 ref_entry; 1490 u8 priority; /* Lower or higher w.r.t ref_entry */ 1491 u8 intf; /* Rx or Tx interface */ 1492 u8 enable_entry;/* Enable this MCAM entry ? */ 1493 u8 alloc_cntr; /* Allocate counter and map ? */ 1494 }; 1495 1496 struct npc_mcam_alloc_and_write_entry_rsp { 1497 struct mbox_msghdr hdr; 1498 u16 entry; 1499 u16 cntr; 1500 }; 1501 1502 struct npc_get_kex_cfg_rsp { 1503 struct mbox_msghdr hdr; 1504 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1505 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1506 #define NPC_MAX_INTF 2 1507 #define NPC_MAX_LID 8 1508 #define NPC_MAX_LT 16 1509 #define NPC_MAX_LD 2 1510 #define NPC_MAX_LFL 16 1511 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1512 u64 kex_ld_flags[NPC_MAX_LD]; 1513 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1514 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1515 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1516 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1517 #define MKEX_NAME_LEN 128 1518 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1519 }; 1520 1521 struct ptp_get_cap_rsp { 1522 struct mbox_msghdr hdr; 1523 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1524 u64 cap; 1525 }; 1526 1527 struct flow_msg { 1528 unsigned char dmac[6]; 1529 unsigned char smac[6]; 1530 __be16 etype; 1531 __be16 vlan_etype; 1532 __be16 vlan_tci; 1533 union { 1534 __be32 ip4src; 1535 __be32 ip6src[4]; 1536 }; 1537 union { 1538 __be32 ip4dst; 1539 __be32 ip6dst[4]; 1540 }; 1541 union { 1542 __be32 spi; 1543 }; 1544 1545 u8 tos; 1546 u8 ip_ver; 1547 u8 ip_proto; 1548 u8 tc; 1549 __be16 sport; 1550 __be16 dport; 1551 union { 1552 u8 ip_flag; 1553 u8 next_header; 1554 }; 1555 __be16 vlan_itci; 1556 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1557 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1558 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1559 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1560 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1561 u32 mpls_lse[4]; 1562 u8 icmp_type; 1563 u8 icmp_code; 1564 __be16 tcp_flags; 1565 }; 1566 1567 struct npc_install_flow_req { 1568 struct mbox_msghdr hdr; 1569 struct flow_msg packet; 1570 struct flow_msg mask; 1571 u64 features; 1572 u16 entry; 1573 u16 channel; 1574 u16 chan_mask; 1575 u8 intf; 1576 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1577 u8 default_rule; 1578 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1579 u16 vf; 1580 /* action */ 1581 u32 index; 1582 u16 match_id; 1583 u8 flow_key_alg; 1584 u8 op; 1585 /* vtag rx action */ 1586 u8 vtag0_type; 1587 u8 vtag0_valid; 1588 u8 vtag1_type; 1589 u8 vtag1_valid; 1590 /* vtag tx action */ 1591 u16 vtag0_def; 1592 u8 vtag0_op; 1593 u16 vtag1_def; 1594 u8 vtag1_op; 1595 /* old counter value */ 1596 u16 cntr_val; 1597 }; 1598 1599 struct npc_install_flow_rsp { 1600 struct mbox_msghdr hdr; 1601 int counter; /* negative if no counter else counter number */ 1602 }; 1603 1604 struct npc_delete_flow_req { 1605 struct mbox_msghdr hdr; 1606 u16 entry; 1607 u16 start;/*Disable range of entries */ 1608 u16 end; 1609 u8 all; /* PF + VFs */ 1610 }; 1611 1612 struct npc_delete_flow_rsp { 1613 struct mbox_msghdr hdr; 1614 u16 cntr_val; 1615 }; 1616 1617 struct npc_mcam_read_entry_req { 1618 struct mbox_msghdr hdr; 1619 u16 entry; /* MCAM entry to read */ 1620 }; 1621 1622 struct npc_mcam_read_entry_rsp { 1623 struct mbox_msghdr hdr; 1624 struct mcam_entry entry_data; 1625 u8 intf; 1626 u8 enable; 1627 }; 1628 1629 struct npc_mcam_read_base_rule_rsp { 1630 struct mbox_msghdr hdr; 1631 struct mcam_entry entry; 1632 }; 1633 1634 struct npc_mcam_get_stats_req { 1635 struct mbox_msghdr hdr; 1636 u16 entry; /* mcam entry */ 1637 }; 1638 1639 struct npc_mcam_get_stats_rsp { 1640 struct mbox_msghdr hdr; 1641 u64 stat; /* counter stats */ 1642 u8 stat_ena; /* enabled */ 1643 }; 1644 1645 struct npc_get_field_hash_info_req { 1646 struct mbox_msghdr hdr; 1647 u8 intf; 1648 }; 1649 1650 struct npc_get_field_hash_info_rsp { 1651 struct mbox_msghdr hdr; 1652 u64 secret_key[3]; 1653 #define NPC_MAX_HASH 2 1654 #define NPC_MAX_HASH_MASK 2 1655 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1656 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1657 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1658 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1659 }; 1660 1661 enum ptp_op { 1662 PTP_OP_ADJFINE = 0, 1663 PTP_OP_GET_CLOCK = 1, 1664 PTP_OP_GET_TSTMP = 2, 1665 PTP_OP_SET_THRESH = 3, 1666 PTP_OP_PPS_ON = 4, 1667 PTP_OP_ADJTIME = 5, 1668 PTP_OP_SET_CLOCK = 6, 1669 }; 1670 1671 struct ptp_req { 1672 struct mbox_msghdr hdr; 1673 u8 op; 1674 s64 scaled_ppm; 1675 u64 thresh; 1676 u64 period; 1677 int pps_on; 1678 s64 delta; 1679 u64 clk; 1680 }; 1681 1682 struct ptp_rsp { 1683 struct mbox_msghdr hdr; 1684 u64 clk; 1685 u64 tsc; 1686 }; 1687 1688 struct npc_get_field_status_req { 1689 struct mbox_msghdr hdr; 1690 u8 intf; 1691 u8 field; 1692 }; 1693 1694 struct npc_get_field_status_rsp { 1695 struct mbox_msghdr hdr; 1696 u8 enable; 1697 }; 1698 1699 struct set_vf_perm { 1700 struct mbox_msghdr hdr; 1701 u16 vf; 1702 #define RESET_VF_PERM BIT_ULL(0) 1703 #define VF_TRUSTED BIT_ULL(1) 1704 u64 flags; 1705 }; 1706 1707 struct lmtst_tbl_setup_req { 1708 struct mbox_msghdr hdr; 1709 u64 dis_sched_early_comp :1; 1710 u64 sch_ena :1; 1711 u64 dis_line_pref :1; 1712 u64 ssow_pf_func :13; 1713 u16 base_pcifunc; 1714 u8 use_local_lmt_region; 1715 u64 lmt_iova; 1716 u64 rsvd[4]; 1717 }; 1718 1719 /* CPT mailbox error codes 1720 * Range 901 - 1000. 1721 */ 1722 enum cpt_af_status { 1723 CPT_AF_ERR_PARAM = -901, 1724 CPT_AF_ERR_GRP_INVALID = -902, 1725 CPT_AF_ERR_LF_INVALID = -903, 1726 CPT_AF_ERR_ACCESS_DENIED = -904, 1727 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1728 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1729 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1730 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1731 }; 1732 1733 /* CPT mbox message formats */ 1734 struct cpt_rd_wr_reg_msg { 1735 struct mbox_msghdr hdr; 1736 u64 reg_offset; 1737 u64 *ret_val; 1738 u64 val; 1739 u8 is_write; 1740 int blkaddr; 1741 }; 1742 1743 struct cpt_lf_alloc_req_msg { 1744 struct mbox_msghdr hdr; 1745 u16 nix_pf_func; 1746 u16 sso_pf_func; 1747 u16 eng_grpmsk; 1748 int blkaddr; 1749 u8 ctx_ilen_valid : 1; 1750 u8 ctx_ilen : 7; 1751 }; 1752 1753 #define CPT_INLINE_INBOUND 0 1754 #define CPT_INLINE_OUTBOUND 1 1755 1756 /* Mailbox message request format for CPT IPsec 1757 * inline inbound and outbound configuration. 1758 */ 1759 struct cpt_inline_ipsec_cfg_msg { 1760 struct mbox_msghdr hdr; 1761 u8 enable; 1762 u8 slot; 1763 u8 dir; 1764 u8 sso_pf_func_ovrd; 1765 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1766 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1767 }; 1768 1769 /* Mailbox message request and response format for CPT stats. */ 1770 struct cpt_sts_req { 1771 struct mbox_msghdr hdr; 1772 u8 blkaddr; 1773 }; 1774 1775 struct cpt_sts_rsp { 1776 struct mbox_msghdr hdr; 1777 u64 inst_req_pc; 1778 u64 inst_lat_pc; 1779 u64 rd_req_pc; 1780 u64 rd_lat_pc; 1781 u64 rd_uc_pc; 1782 u64 active_cycles_pc; 1783 u64 ctx_mis_pc; 1784 u64 ctx_hit_pc; 1785 u64 ctx_aop_pc; 1786 u64 ctx_aop_lat_pc; 1787 u64 ctx_ifetch_pc; 1788 u64 ctx_ifetch_lat_pc; 1789 u64 ctx_ffetch_pc; 1790 u64 ctx_ffetch_lat_pc; 1791 u64 ctx_wback_pc; 1792 u64 ctx_wback_lat_pc; 1793 u64 ctx_psh_pc; 1794 u64 ctx_psh_lat_pc; 1795 u64 ctx_err; 1796 u64 ctx_enc_id; 1797 u64 ctx_flush_timer; 1798 u64 rxc_time; 1799 u64 rxc_time_cfg; 1800 u64 rxc_active_sts; 1801 u64 rxc_zombie_sts; 1802 u64 busy_sts_ae; 1803 u64 free_sts_ae; 1804 u64 busy_sts_se; 1805 u64 free_sts_se; 1806 u64 busy_sts_ie; 1807 u64 free_sts_ie; 1808 u64 exe_err_info; 1809 u64 cptclk_cnt; 1810 u64 diag; 1811 u64 rxc_dfrg; 1812 u64 x2p_link_cfg0; 1813 u64 x2p_link_cfg1; 1814 }; 1815 1816 /* Mailbox message request format to configure reassembly timeout. */ 1817 struct cpt_rxc_time_cfg_req { 1818 struct mbox_msghdr hdr; 1819 int blkaddr; 1820 u32 step; 1821 u16 zombie_thres; 1822 u16 zombie_limit; 1823 u16 active_thres; 1824 u16 active_limit; 1825 }; 1826 1827 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1828 struct cpt_inst_lmtst_req { 1829 struct mbox_msghdr hdr; 1830 u64 inst[8]; 1831 u64 rsvd; 1832 }; 1833 1834 /* Mailbox message format to request for CPT LF reset */ 1835 struct cpt_lf_rst_req { 1836 struct mbox_msghdr hdr; 1837 u32 slot; 1838 u32 rsvd; 1839 }; 1840 1841 /* Mailbox message format to request for CPT faulted engines */ 1842 struct cpt_flt_eng_info_req { 1843 struct mbox_msghdr hdr; 1844 int blkaddr; 1845 bool reset; 1846 u32 rsvd; 1847 }; 1848 1849 struct cpt_flt_eng_info_rsp { 1850 struct mbox_msghdr hdr; 1851 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1852 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1853 u64 rsvd; 1854 }; 1855 1856 struct sdp_node_info { 1857 /* Node to which this PF belons to */ 1858 u8 node_id; 1859 u8 max_vfs; 1860 u8 num_pf_rings; 1861 u8 pf_srn; 1862 #define SDP_MAX_VFS 128 1863 u8 vf_rings[SDP_MAX_VFS]; 1864 }; 1865 1866 struct sdp_chan_info_msg { 1867 struct mbox_msghdr hdr; 1868 struct sdp_node_info info; 1869 }; 1870 1871 struct sdp_get_chan_info_msg { 1872 struct mbox_msghdr hdr; 1873 u16 chan_base; 1874 u16 num_chan; 1875 }; 1876 1877 /* CGX mailbox error codes 1878 * Range 1101 - 1200. 1879 */ 1880 enum cgx_af_status { 1881 LMAC_AF_ERR_INVALID_PARAM = -1101, 1882 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1883 LMAC_AF_ERR_PERM_DENIED = -1103, 1884 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1885 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1886 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1887 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1888 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1889 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1890 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1891 }; 1892 1893 enum mcs_direction { 1894 MCS_RX, 1895 MCS_TX, 1896 }; 1897 1898 enum mcs_rsrc_type { 1899 MCS_RSRC_TYPE_FLOWID, 1900 MCS_RSRC_TYPE_SECY, 1901 MCS_RSRC_TYPE_SC, 1902 MCS_RSRC_TYPE_SA, 1903 }; 1904 1905 struct mcs_alloc_rsrc_req { 1906 struct mbox_msghdr hdr; 1907 u8 rsrc_type; 1908 u8 rsrc_cnt; /* Resources count */ 1909 u8 mcs_id; /* MCS block ID */ 1910 u8 dir; /* Macsec ingress or egress side */ 1911 u8 all; /* Allocate all resource type one each */ 1912 u64 rsvd; 1913 }; 1914 1915 struct mcs_alloc_rsrc_rsp { 1916 struct mbox_msghdr hdr; 1917 u8 flow_ids[128]; /* Index of reserved entries */ 1918 u8 secy_ids[128]; 1919 u8 sc_ids[128]; 1920 u8 sa_ids[256]; 1921 u8 rsrc_type; 1922 u8 rsrc_cnt; /* No of entries reserved */ 1923 u8 mcs_id; 1924 u8 dir; 1925 u8 all; 1926 u8 rsvd[256]; /* reserved fields for future expansion */ 1927 }; 1928 1929 struct mcs_free_rsrc_req { 1930 struct mbox_msghdr hdr; 1931 u8 rsrc_id; /* Index of the entry to be freed */ 1932 u8 rsrc_type; 1933 u8 mcs_id; 1934 u8 dir; 1935 u8 all; /* Free all the cam resources */ 1936 u64 rsvd; 1937 }; 1938 1939 struct mcs_flowid_entry_write_req { 1940 struct mbox_msghdr hdr; 1941 u64 data[4]; 1942 u64 mask[4]; 1943 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1944 u8 flow_id; 1945 u8 secy_id; /* secyid for which flowid is mapped */ 1946 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1947 u8 ena; /* Enable tcam entry */ 1948 u8 ctrl_pkt; 1949 u8 mcs_id; 1950 u8 dir; 1951 u64 rsvd; 1952 }; 1953 1954 struct mcs_secy_plcy_write_req { 1955 struct mbox_msghdr hdr; 1956 u64 plcy; 1957 u8 secy_id; 1958 u8 mcs_id; 1959 u8 dir; 1960 u64 rsvd; 1961 }; 1962 1963 /* RX SC_CAM mapping */ 1964 struct mcs_rx_sc_cam_write_req { 1965 struct mbox_msghdr hdr; 1966 u64 sci; /* SCI */ 1967 u64 secy_id; /* secy index mapped to SC */ 1968 u8 sc_id; /* SC CAM entry index */ 1969 u8 mcs_id; 1970 u64 rsvd; 1971 }; 1972 1973 struct mcs_sa_plcy_write_req { 1974 struct mbox_msghdr hdr; 1975 u64 plcy[2][9]; /* Support 2 SA policy */ 1976 u8 sa_index[2]; 1977 u8 sa_cnt; 1978 u8 mcs_id; 1979 u8 dir; 1980 u64 rsvd; 1981 }; 1982 1983 struct mcs_tx_sc_sa_map { 1984 struct mbox_msghdr hdr; 1985 u8 sa_index0; 1986 u8 sa_index1; 1987 u8 rekey_ena; 1988 u8 sa_index0_vld; 1989 u8 sa_index1_vld; 1990 u8 tx_sa_active; 1991 u64 sectag_sci; 1992 u8 sc_id; /* used as index for SA_MEM_MAP */ 1993 u8 mcs_id; 1994 u64 rsvd; 1995 }; 1996 1997 struct mcs_rx_sc_sa_map { 1998 struct mbox_msghdr hdr; 1999 u8 sa_index; 2000 u8 sa_in_use; 2001 u8 sc_id; 2002 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 2003 u8 mcs_id; 2004 u64 rsvd; 2005 }; 2006 2007 struct mcs_flowid_ena_dis_entry { 2008 struct mbox_msghdr hdr; 2009 u8 flow_id; 2010 u8 ena; 2011 u8 mcs_id; 2012 u8 dir; 2013 u64 rsvd; 2014 }; 2015 2016 struct mcs_pn_table_write_req { 2017 struct mbox_msghdr hdr; 2018 u64 next_pn; 2019 u8 pn_id; 2020 u8 mcs_id; 2021 u8 dir; 2022 u64 rsvd; 2023 }; 2024 2025 struct mcs_hw_info { 2026 struct mbox_msghdr hdr; 2027 u8 num_mcs_blks; /* Number of MCS blocks */ 2028 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2029 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2030 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2031 u16 sa_entries; /* PN table entries = SA entries */ 2032 u64 rsvd[16]; 2033 }; 2034 2035 struct mcs_set_active_lmac { 2036 struct mbox_msghdr hdr; 2037 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2038 u8 mcs_id; 2039 u16 chan_base; /* MCS channel base */ 2040 u64 rsvd; 2041 }; 2042 2043 struct mcs_set_lmac_mode { 2044 struct mbox_msghdr hdr; 2045 u8 mode; /* 1:Bypass 0:Operational */ 2046 u8 lmac_id; 2047 u8 mcs_id; 2048 u64 rsvd; 2049 }; 2050 2051 struct mcs_port_reset_req { 2052 struct mbox_msghdr hdr; 2053 u8 reset; 2054 u8 mcs_id; 2055 u8 port_id; 2056 u64 rsvd; 2057 }; 2058 2059 struct mcs_port_cfg_set_req { 2060 struct mbox_msghdr hdr; 2061 u8 cstm_tag_rel_mode_sel; 2062 u8 custom_hdr_enb; 2063 u8 fifo_skid; 2064 u8 port_mode; 2065 u8 port_id; 2066 u8 mcs_id; 2067 u64 rsvd; 2068 }; 2069 2070 struct mcs_port_cfg_get_req { 2071 struct mbox_msghdr hdr; 2072 u8 port_id; 2073 u8 mcs_id; 2074 u64 rsvd; 2075 }; 2076 2077 struct mcs_port_cfg_get_rsp { 2078 struct mbox_msghdr hdr; 2079 u8 cstm_tag_rel_mode_sel; 2080 u8 custom_hdr_enb; 2081 u8 fifo_skid; 2082 u8 port_mode; 2083 u8 port_id; 2084 u8 mcs_id; 2085 u64 rsvd; 2086 }; 2087 2088 struct mcs_custom_tag_cfg_get_req { 2089 struct mbox_msghdr hdr; 2090 u8 mcs_id; 2091 u8 dir; 2092 u64 rsvd; 2093 }; 2094 2095 struct mcs_custom_tag_cfg_get_rsp { 2096 struct mbox_msghdr hdr; 2097 u16 cstm_etype[8]; 2098 u8 cstm_indx[8]; 2099 u8 cstm_etype_en; 2100 u8 mcs_id; 2101 u8 dir; 2102 u64 rsvd; 2103 }; 2104 2105 /* MCS mailbox error codes 2106 * Range 1201 - 1300. 2107 */ 2108 enum mcs_af_status { 2109 MCS_AF_ERR_INVALID_MCSID = -1201, 2110 MCS_AF_ERR_NOT_MAPPED = -1202, 2111 }; 2112 2113 struct mcs_set_pn_threshold { 2114 struct mbox_msghdr hdr; 2115 u64 threshold; 2116 u8 xpn; /* '1' for setting xpn threshold */ 2117 u8 mcs_id; 2118 u8 dir; 2119 u64 rsvd; 2120 }; 2121 2122 enum mcs_ctrl_pkt_rulew_type { 2123 MCS_CTRL_PKT_RULE_TYPE_ETH, 2124 MCS_CTRL_PKT_RULE_TYPE_DA, 2125 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2126 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2127 MCS_CTRL_PKT_RULE_TYPE_MAC, 2128 }; 2129 2130 struct mcs_alloc_ctrl_pkt_rule_req { 2131 struct mbox_msghdr hdr; 2132 u8 rule_type; 2133 u8 mcs_id; /* MCS block ID */ 2134 u8 dir; /* Macsec ingress or egress side */ 2135 u64 rsvd; 2136 }; 2137 2138 struct mcs_alloc_ctrl_pkt_rule_rsp { 2139 struct mbox_msghdr hdr; 2140 u8 rule_idx; 2141 u8 rule_type; 2142 u8 mcs_id; 2143 u8 dir; 2144 u64 rsvd; 2145 }; 2146 2147 struct mcs_free_ctrl_pkt_rule_req { 2148 struct mbox_msghdr hdr; 2149 u8 rule_idx; 2150 u8 rule_type; 2151 u8 mcs_id; 2152 u8 dir; 2153 u8 all; 2154 u64 rsvd; 2155 }; 2156 2157 struct mcs_ctrl_pkt_rule_write_req { 2158 struct mbox_msghdr hdr; 2159 u64 data0; 2160 u64 data1; 2161 u64 data2; 2162 u8 rule_idx; 2163 u8 rule_type; 2164 u8 mcs_id; 2165 u8 dir; 2166 u64 rsvd; 2167 }; 2168 2169 struct mcs_stats_req { 2170 struct mbox_msghdr hdr; 2171 u8 id; 2172 u8 mcs_id; 2173 u8 dir; 2174 u64 rsvd; 2175 }; 2176 2177 struct mcs_flowid_stats { 2178 struct mbox_msghdr hdr; 2179 u64 tcam_hit_cnt; 2180 u64 rsvd; 2181 }; 2182 2183 struct mcs_secy_stats { 2184 struct mbox_msghdr hdr; 2185 u64 ctl_pkt_bcast_cnt; 2186 u64 ctl_pkt_mcast_cnt; 2187 u64 ctl_pkt_ucast_cnt; 2188 u64 ctl_octet_cnt; 2189 u64 unctl_pkt_bcast_cnt; 2190 u64 unctl_pkt_mcast_cnt; 2191 u64 unctl_pkt_ucast_cnt; 2192 u64 unctl_octet_cnt; 2193 /* Valid only for RX */ 2194 u64 octet_decrypted_cnt; 2195 u64 octet_validated_cnt; 2196 u64 pkt_port_disabled_cnt; 2197 u64 pkt_badtag_cnt; 2198 u64 pkt_nosa_cnt; 2199 u64 pkt_nosaerror_cnt; 2200 u64 pkt_tagged_ctl_cnt; 2201 u64 pkt_untaged_cnt; 2202 u64 pkt_ctl_cnt; /* CN10K-B */ 2203 u64 pkt_notag_cnt; /* CNF10K-B */ 2204 /* Valid only for TX */ 2205 u64 octet_encrypted_cnt; 2206 u64 octet_protected_cnt; 2207 u64 pkt_noactivesa_cnt; 2208 u64 pkt_toolong_cnt; 2209 u64 pkt_untagged_cnt; 2210 u64 rsvd[4]; 2211 }; 2212 2213 struct mcs_port_stats { 2214 struct mbox_msghdr hdr; 2215 u64 tcam_miss_cnt; 2216 u64 parser_err_cnt; 2217 u64 preempt_err_cnt; /* CNF10K-B */ 2218 u64 sectag_insert_err_cnt; 2219 u64 rsvd[4]; 2220 }; 2221 2222 /* Only for CN10K-B */ 2223 struct mcs_sa_stats { 2224 struct mbox_msghdr hdr; 2225 /* RX */ 2226 u64 pkt_invalid_cnt; 2227 u64 pkt_nosaerror_cnt; 2228 u64 pkt_notvalid_cnt; 2229 u64 pkt_ok_cnt; 2230 u64 pkt_nosa_cnt; 2231 /* TX */ 2232 u64 pkt_encrypt_cnt; 2233 u64 pkt_protected_cnt; 2234 u64 rsvd[4]; 2235 }; 2236 2237 struct mcs_sc_stats { 2238 struct mbox_msghdr hdr; 2239 /* RX */ 2240 u64 hit_cnt; 2241 u64 pkt_invalid_cnt; 2242 u64 pkt_late_cnt; 2243 u64 pkt_notvalid_cnt; 2244 u64 pkt_unchecked_cnt; 2245 u64 pkt_delay_cnt; /* CNF10K-B */ 2246 u64 pkt_ok_cnt; /* CNF10K-B */ 2247 u64 octet_decrypt_cnt; /* CN10K-B */ 2248 u64 octet_validate_cnt; /* CN10K-B */ 2249 /* TX */ 2250 u64 pkt_encrypt_cnt; 2251 u64 pkt_protected_cnt; 2252 u64 octet_encrypt_cnt; /* CN10K-B */ 2253 u64 octet_protected_cnt; /* CN10K-B */ 2254 u64 rsvd[4]; 2255 }; 2256 2257 struct mcs_clear_stats { 2258 struct mbox_msghdr hdr; 2259 #define MCS_FLOWID_STATS 0 2260 #define MCS_SECY_STATS 1 2261 #define MCS_SC_STATS 2 2262 #define MCS_SA_STATS 3 2263 #define MCS_PORT_STATS 4 2264 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2265 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2266 u8 mcs_id; 2267 u8 dir; 2268 u8 all; /* All resources stats mapped to PF are cleared */ 2269 }; 2270 2271 struct mcs_intr_cfg { 2272 struct mbox_msghdr hdr; 2273 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2274 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2275 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2276 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2277 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2278 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2279 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2280 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2281 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2282 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2283 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2284 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2285 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2286 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2287 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2288 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2289 u64 intr_mask; /* Interrupt enable mask */ 2290 u8 mcs_id; 2291 u8 lmac_id; 2292 u64 rsvd; 2293 }; 2294 2295 struct mcs_intr_info { 2296 struct mbox_msghdr hdr; 2297 u64 intr_mask; 2298 int sa_id; 2299 u8 mcs_id; 2300 u8 lmac_id; 2301 u64 rsvd; 2302 }; 2303 2304 #endif /* MBOX_H */ 2305