1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 #include "cn20k/struct.h" 17 18 #define MBOX_SIZE SZ_64K 19 20 #define MBOX_DOWN_MSG 1 21 #define MBOX_UP_MSG 2 22 23 /* AF/PF: PF initiated, PF/VF VF initiated */ 24 #define MBOX_DOWN_RX_START 0 25 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 26 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 27 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 28 /* AF/PF: AF initiated, PF/VF PF initiated */ 29 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 30 #define MBOX_UP_RX_SIZE SZ_1K 31 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 32 #define MBOX_UP_TX_SIZE SZ_1K 33 34 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 35 # error "incorrect mailbox area sizes" 36 #endif 37 38 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 39 40 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 41 42 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 43 44 /* Mailbox directions */ 45 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 46 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 47 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 48 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 49 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 50 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 51 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 52 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 53 54 enum { 55 TYPE_AFVF, 56 TYPE_AFPF, 57 }; 58 59 struct otx2_mbox_dev { 60 void *mbase; /* This dev's mbox region */ 61 void *hwbase; 62 spinlock_t mbox_lock; 63 u16 msg_size; /* Total msg size to be sent */ 64 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 65 u16 num_msgs; /* No of msgs sent or waiting for response */ 66 u16 msgs_acked; /* No of msgs for which response is received */ 67 }; 68 69 struct otx2_mbox { 70 struct pci_dev *pdev; 71 void *hwbase; /* Mbox region advertised by HW */ 72 void *reg_base;/* CSR base for this dev */ 73 u64 trigger; /* Trigger mbox notification */ 74 u16 tr_shift; /* Mbox trigger shift */ 75 u64 rx_start; /* Offset of Rx region in mbox memory */ 76 u64 tx_start; /* Offset of Tx region in mbox memory */ 77 u16 rx_size; /* Size of Rx region */ 78 u16 tx_size; /* Size of Tx region */ 79 u16 ndevs; /* The number of peers */ 80 struct otx2_mbox_dev *dev; 81 }; 82 83 /* Header which precedes all mbox messages */ 84 struct mbox_hdr { 85 u64 msg_size; /* Total msgs size embedded */ 86 u16 num_msgs; /* No of msgs embedded */ 87 u16 opt_msg; 88 u8 sig; 89 }; 90 91 /* Header which precedes every msg and is also part of it */ 92 struct mbox_msghdr { 93 u16 pcifunc; /* Who's sending this msg */ 94 u16 id; /* Mbox message ID */ 95 #define OTX2_MBOX_REQ_SIG (0xdead) 96 #define OTX2_MBOX_RSP_SIG (0xbeef) 97 u16 sig; /* Signature, for validating corrupted msgs */ 98 #define OTX2_MBOX_VERSION (0x000a) 99 u16 ver; /* Version of msg's structure for this ID */ 100 u16 next_msgoff; /* Offset of next msg within mailbox region */ 101 int rc; /* Msg process'ed response code */ 102 }; 103 104 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 105 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 106 void otx2_mbox_destroy(struct otx2_mbox *mbox); 107 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 108 struct pci_dev *pdev, void __force *reg_base, 109 int direction, int ndevs); 110 111 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 112 struct pci_dev *pdev, void __force *reg_base, 113 int direction, int ndevs, unsigned long *bmap); 114 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 115 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 116 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 117 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 118 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 119 int size, int size_rsp); 120 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 121 struct mbox_msghdr *msg); 122 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 123 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 124 u16 pcifunc, u16 id); 125 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 126 const char *otx2_mbox_id2name(u16 id); 127 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 128 int devid, int size) 129 { 130 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 131 } 132 133 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 134 135 /* Mailbox message types */ 136 #define MBOX_MSG_MASK 0xFFFF 137 #define MBOX_MSG_INVALID 0xFFFE 138 #define MBOX_MSG_MAX 0xFFFF 139 140 #define MBOX_MESSAGES \ 141 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 142 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 143 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 144 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 145 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 146 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 147 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 148 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 149 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 150 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \ 151 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 152 msg_rsp) \ 153 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 154 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 155 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ 156 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ 157 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ 158 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 159 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 160 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 161 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 162 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 163 cgx_mac_addr_set_or_get) \ 164 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 165 cgx_mac_addr_set_or_get) \ 166 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 167 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 168 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 169 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 170 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 171 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 172 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 173 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 174 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 175 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 176 cgx_pause_frm_cfg) \ 177 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 178 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 179 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 180 cgx_mac_addr_add_rsp) \ 181 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 182 msg_rsp) \ 183 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 184 cgx_max_dmac_entries_get_rsp) \ 185 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 186 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 187 cgx_set_link_mode_rsp) \ 188 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 189 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 190 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 191 cgx_features_info_msg) \ 192 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 193 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 194 msg_rsp) \ 195 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 196 cgx_mac_addr_update_rsp) \ 197 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 198 cgx_pfc_rsp) \ 199 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 200 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 201 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 202 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 203 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 204 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 205 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 206 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 207 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 208 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 209 msg_rsp) \ 210 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 211 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 212 cpt_rd_wr_reg_msg) \ 213 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 214 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 215 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 216 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 217 msg_rsp) \ 218 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 219 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 220 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 221 cpt_flt_eng_info_rsp) \ 222 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 223 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 224 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 225 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 226 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 227 npc_mcam_alloc_entry_rsp) \ 228 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 229 npc_mcam_free_entry_req, msg_rsp) \ 230 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 231 npc_mcam_write_entry_req, msg_rsp) \ 232 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 233 npc_mcam_ena_dis_entry_req, msg_rsp) \ 234 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 235 npc_mcam_ena_dis_entry_req, msg_rsp) \ 236 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 237 npc_mcam_shift_entry_rsp) \ 238 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 239 npc_mcam_alloc_counter_req, \ 240 npc_mcam_alloc_counter_rsp) \ 241 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 242 npc_mcam_oper_counter_req, msg_rsp) \ 243 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 244 npc_mcam_unmap_counter_req, msg_rsp) \ 245 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 246 npc_mcam_oper_counter_req, msg_rsp) \ 247 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 248 npc_mcam_oper_counter_req, \ 249 npc_mcam_oper_counter_rsp) \ 250 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 251 npc_mcam_alloc_and_write_entry_req, \ 252 npc_mcam_alloc_and_write_entry_rsp) \ 253 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 254 msg_req, npc_get_kex_cfg_rsp) \ 255 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 256 npc_install_flow_req, npc_install_flow_rsp) \ 257 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 258 npc_delete_flow_req, npc_delete_flow_rsp) \ 259 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 260 npc_mcam_read_entry_req, \ 261 npc_mcam_read_entry_rsp) \ 262 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 263 npc_set_pkind, msg_rsp) \ 264 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 265 msg_req, npc_mcam_read_base_rule_rsp) \ 266 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 267 npc_mcam_get_stats_req, \ 268 npc_mcam_get_stats_rsp) \ 269 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 270 npc_get_field_hash_info_req, \ 271 npc_get_field_hash_info_rsp) \ 272 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 273 npc_get_field_status_req, \ 274 npc_get_field_status_rsp) \ 275 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 276 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 277 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 278 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 279 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 280 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 281 hwctx_disable_req, msg_rsp) \ 282 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 283 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 284 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 285 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 286 nix_txschq_config) \ 287 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 288 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 289 nix_vtag_config_rsp) \ 290 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 291 nix_rss_flowkey_cfg, \ 292 nix_rss_flowkey_cfg_rsp) \ 293 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 294 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 295 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 296 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 297 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 298 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 299 nix_mark_format_cfg, \ 300 nix_mark_format_cfg_rsp) \ 301 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 302 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 303 nix_lso_format_cfg, \ 304 nix_lso_format_cfg_rsp) \ 305 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 306 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 307 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 308 nix_bp_cfg_rsp) \ 309 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 310 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 311 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 312 nix_inline_ipsec_cfg, msg_rsp) \ 313 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 314 nix_inline_ipsec_lf_cfg, msg_rsp) \ 315 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 316 nix_cn10k_aq_enq_rsp) \ 317 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 318 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 319 nix_bandprof_alloc_rsp) \ 320 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 321 msg_rsp) \ 322 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 323 nix_bandprof_get_hwinfo_rsp) \ 324 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ 325 nix_bp_cfg_rsp) \ 326 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ 327 msg_rsp) \ 328 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 329 msg_req, nix_inline_ipsec_cfg) \ 330 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 331 nix_mcast_grp_create_rsp) \ 332 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 333 msg_rsp) \ 334 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 335 nix_mcast_grp_update_req, \ 336 nix_mcast_grp_update_rsp) \ 337 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \ 338 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 339 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 340 mcs_alloc_rsrc_rsp) \ 341 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 342 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 343 msg_rsp) \ 344 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 345 msg_rsp) \ 346 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 347 msg_rsp) \ 348 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 349 msg_rsp) \ 350 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 351 msg_rsp) \ 352 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 353 msg_rsp) \ 354 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 355 msg_rsp) \ 356 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 357 msg_rsp) \ 358 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 359 msg_rsp) \ 360 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 361 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 362 mcs_flowid_stats) \ 363 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 364 mcs_secy_stats) \ 365 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 366 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 367 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 368 mcs_port_stats) \ 369 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 370 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 371 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 372 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 373 msg_rsp) \ 374 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 375 mcs_alloc_ctrl_pkt_rule_req, \ 376 mcs_alloc_ctrl_pkt_rule_rsp) \ 377 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 378 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 379 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 380 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 381 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 382 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 383 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 384 mcs_port_cfg_get_rsp) \ 385 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 386 mcs_custom_tag_cfg_get_req, \ 387 mcs_custom_tag_cfg_get_rsp) 388 389 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 390 #define MBOX_UP_CGX_MESSAGES \ 391 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 392 393 #define MBOX_UP_CPT_MESSAGES \ 394 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 395 396 #define MBOX_UP_MCS_MESSAGES \ 397 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 398 399 #define MBOX_UP_REP_MESSAGES \ 400 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \ 401 402 enum { 403 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 404 MBOX_MESSAGES 405 MBOX_UP_CGX_MESSAGES 406 MBOX_UP_CPT_MESSAGES 407 MBOX_UP_MCS_MESSAGES 408 MBOX_UP_REP_MESSAGES 409 #undef M 410 }; 411 412 /* Mailbox message formats */ 413 414 #define RVU_DEFAULT_PF_FUNC 0xFFFF 415 416 /* Generic request msg used for those mbox messages which 417 * don't send any data in the request. 418 */ 419 struct msg_req { 420 struct mbox_msghdr hdr; 421 }; 422 423 /* Generic response msg used an ack or response for those mbox 424 * messages which don't have a specific rsp msg format. 425 */ 426 struct msg_rsp { 427 struct mbox_msghdr hdr; 428 }; 429 430 /* RVU mailbox error codes 431 * Range 256 - 300. 432 */ 433 enum rvu_af_status { 434 RVU_INVALID_VF_ID = -256, 435 }; 436 437 struct ready_msg_rsp { 438 struct mbox_msghdr hdr; 439 u16 sclk_freq; /* SCLK frequency (in MHz) */ 440 u16 rclk_freq; /* RCLK frequency (in MHz) */ 441 }; 442 443 /* Structure for requesting resource provisioning. 444 * 'modify' flag to be used when either requesting more 445 * or to detach partial of a certain resource type. 446 * Rest of the fields specify how many of what type to 447 * be attached. 448 * To request LFs from two blocks of same type this mailbox 449 * can be sent twice as below: 450 * struct rsrc_attach *attach; 451 * .. Allocate memory for message .. 452 * attach->cptlfs = 3; <3 LFs from CPT0> 453 * .. Send message .. 454 * .. Allocate memory for message .. 455 * attach->modify = 1; 456 * attach->cpt_blkaddr = BLKADDR_CPT1; 457 * attach->cptlfs = 2; <2 LFs from CPT1> 458 * .. Send message .. 459 */ 460 struct rsrc_attach { 461 struct mbox_msghdr hdr; 462 u8 modify:1; 463 u8 npalf:1; 464 u8 nixlf:1; 465 u16 sso; 466 u16 ssow; 467 u16 timlfs; 468 u16 cptlfs; 469 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 470 }; 471 472 /* Structure for relinquishing resources. 473 * 'partial' flag to be used when relinquishing all resources 474 * but only of a certain type. If not set, all resources of all 475 * types provisioned to the RVU function will be detached. 476 */ 477 struct rsrc_detach { 478 struct mbox_msghdr hdr; 479 u8 partial:1; 480 u8 npalf:1; 481 u8 nixlf:1; 482 u8 sso:1; 483 u8 ssow:1; 484 u8 timlfs:1; 485 u8 cptlfs:1; 486 }; 487 488 /* Number of resources available to the caller. 489 * In reply to MBOX_MSG_FREE_RSRC_CNT. 490 */ 491 struct free_rsrcs_rsp { 492 struct mbox_msghdr hdr; 493 u16 schq[NIX_TXSCH_LVL_CNT]; 494 u16 sso; 495 u16 tim; 496 u16 ssow; 497 u16 cpt; 498 u8 npa; 499 u8 nix; 500 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 501 u8 nix1; 502 u8 cpt1; 503 u8 ree0; 504 u8 ree1; 505 }; 506 507 #define MSIX_VECTOR_INVALID 0xFFFF 508 #define MAX_RVU_BLKLF_CNT 256 509 510 struct msix_offset_rsp { 511 struct mbox_msghdr hdr; 512 u16 npa_msixoff; 513 u16 nix_msixoff; 514 u16 sso; 515 u16 ssow; 516 u16 timlfs; 517 u16 cptlfs; 518 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 519 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 520 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 521 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 522 u16 cpt1_lfs; 523 u16 ree0_lfs; 524 u16 ree1_lfs; 525 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 526 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 527 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 528 }; 529 530 struct get_hw_cap_rsp { 531 struct mbox_msghdr hdr; 532 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 533 u8 nix_shaping; /* Is shaping and coloring supported */ 534 u8 npc_hash_extract; /* Is hash extract supported */ 535 #define HW_CAP_MACSEC BIT_ULL(1) 536 u64 hw_caps; 537 }; 538 539 /* CGX mbox message formats */ 540 541 struct cgx_stats_rsp { 542 struct mbox_msghdr hdr; 543 #define CGX_RX_STATS_COUNT 9 544 #define CGX_TX_STATS_COUNT 18 545 u64 rx_stats[CGX_RX_STATS_COUNT]; 546 u64 tx_stats[CGX_TX_STATS_COUNT]; 547 }; 548 549 struct cgx_fec_stats_rsp { 550 struct mbox_msghdr hdr; 551 u64 fec_corr_blks; 552 u64 fec_uncorr_blks; 553 }; 554 /* Structure for requesting the operation for 555 * setting/getting mac address in the CGX interface 556 */ 557 struct cgx_mac_addr_set_or_get { 558 struct mbox_msghdr hdr; 559 u8 mac_addr[ETH_ALEN]; 560 u32 index; 561 }; 562 563 /* Structure for requesting the operation to 564 * add DMAC filter entry into CGX interface 565 */ 566 struct cgx_mac_addr_add_req { 567 struct mbox_msghdr hdr; 568 u8 mac_addr[ETH_ALEN]; 569 }; 570 571 /* Structure for response against the operation to 572 * add DMAC filter entry into CGX interface 573 */ 574 struct cgx_mac_addr_add_rsp { 575 struct mbox_msghdr hdr; 576 u32 index; 577 }; 578 579 /* Structure for requesting the operation to 580 * delete DMAC filter entry from CGX interface 581 */ 582 struct cgx_mac_addr_del_req { 583 struct mbox_msghdr hdr; 584 u32 index; 585 }; 586 587 /* Structure for response against the operation to 588 * get maximum supported DMAC filter entries 589 */ 590 struct cgx_max_dmac_entries_get_rsp { 591 struct mbox_msghdr hdr; 592 u32 max_dmac_filters; 593 }; 594 595 struct cgx_link_user_info { 596 uint64_t link_up:1; 597 uint64_t full_duplex:1; 598 uint64_t lmac_type_id:4; 599 uint64_t speed:20; /* speed in Mbps */ 600 uint64_t an:1; /* AN supported or not */ 601 uint64_t fec:2; /* FEC type if enabled else 0 */ 602 #define LMACTYPE_STR_LEN 16 603 char lmac_type[LMACTYPE_STR_LEN]; 604 }; 605 606 struct cgx_link_info_msg { 607 struct mbox_msghdr hdr; 608 struct cgx_link_user_info link_info; 609 }; 610 611 struct cgx_pause_frm_cfg { 612 struct mbox_msghdr hdr; 613 u8 set; 614 /* set = 1 if the request is to config pause frames */ 615 /* set = 0 if the request is to fetch pause frames config */ 616 u8 rx_pause; 617 u8 tx_pause; 618 }; 619 620 enum fec_type { 621 OTX2_FEC_NONE, 622 OTX2_FEC_BASER, 623 OTX2_FEC_RS, 624 OTX2_FEC_STATS_CNT = 2, 625 OTX2_FEC_OFF, 626 }; 627 628 struct fec_mode { 629 struct mbox_msghdr hdr; 630 int fec; 631 }; 632 633 struct sfp_eeprom_s { 634 #define SFP_EEPROM_SIZE 256 635 u16 sff_id; 636 u8 buf[SFP_EEPROM_SIZE]; 637 u64 reserved; 638 }; 639 640 struct phy_s { 641 struct { 642 u64 can_change_mod_type:1; 643 u64 mod_type:1; 644 u64 has_fec_stats:1; 645 } misc; 646 struct fec_stats_s { 647 u32 rsfec_corr_cws; 648 u32 rsfec_uncorr_cws; 649 u32 brfec_corr_blks; 650 u32 brfec_uncorr_blks; 651 } fec_stats; 652 }; 653 654 struct cgx_lmac_fwdata_s { 655 u16 rw_valid; 656 u64 supported_fec; 657 u64 supported_an; 658 u64 supported_link_modes; 659 /* only applicable if AN is supported */ 660 u64 advertised_fec; 661 u64 advertised_link_modes; 662 /* Only applicable if SFP/QSFP slot is present */ 663 struct sfp_eeprom_s sfp_eeprom; 664 struct phy_s phy; 665 #define LMAC_FWDATA_RESERVED_MEM 1021 666 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 667 }; 668 669 struct cgx_fw_data { 670 struct mbox_msghdr hdr; 671 struct cgx_lmac_fwdata_s fwdata; 672 }; 673 674 struct cgx_set_link_mode_args { 675 u32 speed; 676 u8 duplex; 677 u8 an; 678 u8 ports; 679 u64 mode; 680 }; 681 682 struct cgx_set_link_mode_req { 683 #define AUTONEG_UNKNOWN 0xff 684 struct mbox_msghdr hdr; 685 struct cgx_set_link_mode_args args; 686 }; 687 688 struct cgx_set_link_mode_rsp { 689 struct mbox_msghdr hdr; 690 int status; 691 }; 692 693 struct cgx_mac_addr_reset_req { 694 struct mbox_msghdr hdr; 695 u32 index; 696 }; 697 698 struct cgx_mac_addr_update_req { 699 struct mbox_msghdr hdr; 700 u8 mac_addr[ETH_ALEN]; 701 u32 index; 702 }; 703 704 struct cgx_mac_addr_update_rsp { 705 struct mbox_msghdr hdr; 706 u32 index; 707 }; 708 709 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 710 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 711 /* flow control from physical link higig2 messages */ 712 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 713 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 714 #define RVU_MAC_VERSION BIT_ULL(4) 715 #define RVU_MAC_CGX BIT_ULL(5) 716 #define RVU_MAC_RPM BIT_ULL(6) 717 718 struct cgx_features_info_msg { 719 struct mbox_msghdr hdr; 720 u64 lmac_features; 721 }; 722 723 struct rpm_stats_rsp { 724 struct mbox_msghdr hdr; 725 #define RPM_RX_STATS_COUNT 43 726 #define RPM_TX_STATS_COUNT 34 727 u64 rx_stats[RPM_RX_STATS_COUNT]; 728 u64 tx_stats[RPM_TX_STATS_COUNT]; 729 }; 730 731 struct cgx_pfc_cfg { 732 struct mbox_msghdr hdr; 733 u8 rx_pause; 734 u8 tx_pause; 735 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 736 }; 737 738 struct cgx_pfc_rsp { 739 struct mbox_msghdr hdr; 740 u8 rx_pause; 741 u8 tx_pause; 742 }; 743 744 /* NPA mbox message formats */ 745 746 struct npc_set_pkind { 747 struct mbox_msghdr hdr; 748 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 749 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 750 u64 mode; 751 #define PKIND_TX BIT_ULL(0) 752 #define PKIND_RX BIT_ULL(1) 753 u8 dir; 754 u8 pkind; /* valid only in case custom flag */ 755 u8 var_len_off; /* Offset of custom header length field. 756 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 757 */ 758 u8 var_len_off_mask; /* Mask for length with in offset */ 759 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 760 }; 761 762 /* NPA mbox message formats */ 763 764 /* NPA mailbox error codes 765 * Range 301 - 400. 766 */ 767 enum npa_af_status { 768 NPA_AF_ERR_PARAM = -301, 769 NPA_AF_ERR_AQ_FULL = -302, 770 NPA_AF_ERR_AQ_ENQUEUE = -303, 771 NPA_AF_ERR_AF_LF_INVALID = -304, 772 NPA_AF_ERR_AF_LF_ALLOC = -305, 773 NPA_AF_ERR_LF_RESET = -306, 774 }; 775 776 /* For NPA LF context alloc and init */ 777 struct npa_lf_alloc_req { 778 struct mbox_msghdr hdr; 779 int node; 780 int aura_sz; /* No of auras */ 781 u32 nr_pools; /* No of pools */ 782 u64 way_mask; 783 }; 784 785 struct npa_lf_alloc_rsp { 786 struct mbox_msghdr hdr; 787 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 788 u32 stack_pg_bytes; /* Size of stack page */ 789 u16 qints; /* NPA_AF_CONST::QINTS */ 790 u8 cache_lines; /*BATCH ALLOC DMA */ 791 }; 792 793 /* NPA AQ enqueue msg */ 794 struct npa_aq_enq_req { 795 struct mbox_msghdr hdr; 796 u32 aura_id; 797 u8 ctype; 798 u8 op; 799 union { 800 /* Valid when op == WRITE/INIT and ctype == AURA. 801 * LF fills the pool_id in aura.pool_addr. AF will translate 802 * the pool_id to pool context pointer. 803 */ 804 struct npa_aura_s aura; 805 /* Valid when op == WRITE/INIT and ctype == POOL */ 806 struct npa_pool_s pool; 807 }; 808 /* Mask data when op == WRITE (1=write, 0=don't write) */ 809 union { 810 /* Valid when op == WRITE and ctype == AURA */ 811 struct npa_aura_s aura_mask; 812 /* Valid when op == WRITE and ctype == POOL */ 813 struct npa_pool_s pool_mask; 814 }; 815 }; 816 817 struct npa_aq_enq_rsp { 818 struct mbox_msghdr hdr; 819 union { 820 /* Valid when op == READ and ctype == AURA */ 821 struct npa_aura_s aura; 822 /* Valid when op == READ and ctype == POOL */ 823 struct npa_pool_s pool; 824 }; 825 }; 826 827 /* Disable all contexts of type 'ctype' */ 828 struct hwctx_disable_req { 829 struct mbox_msghdr hdr; 830 u8 ctype; 831 }; 832 833 /* NIX mbox message formats */ 834 835 /* NIX mailbox error codes 836 * Range 401 - 500. 837 */ 838 enum nix_af_status { 839 NIX_AF_ERR_PARAM = -401, 840 NIX_AF_ERR_AQ_FULL = -402, 841 NIX_AF_ERR_AQ_ENQUEUE = -403, 842 NIX_AF_ERR_AF_LF_INVALID = -404, 843 NIX_AF_ERR_AF_LF_ALLOC = -405, 844 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 845 NIX_AF_ERR_TLX_INVALID = -407, 846 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 847 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 848 NIX_AF_ERR_FRS_INVALID = -410, 849 NIX_AF_ERR_RX_LINK_INVALID = -411, 850 NIX_AF_INVAL_TXSCHQ_CFG = -412, 851 NIX_AF_SMQ_FLUSH_FAILED = -413, 852 NIX_AF_ERR_LF_RESET = -414, 853 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 854 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 855 NIX_AF_ERR_MARK_CFG_FAIL = -417, 856 NIX_AF_ERR_LSO_CFG_FAIL = -418, 857 NIX_AF_INVAL_NPA_PF_FUNC = -419, 858 NIX_AF_INVAL_SSO_PF_FUNC = -420, 859 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 860 NIX_AF_ERR_RX_VTAG_INUSE = -422, 861 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 862 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 863 NIX_AF_ERR_INVALID_NIXBLK = -425, 864 NIX_AF_ERR_INVALID_BANDPROF = -426, 865 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 866 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 867 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 868 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 869 NIX_AF_ERR_LINK_CREDITS = -431, 870 NIX_AF_ERR_INVALID_BPID = -434, 871 NIX_AF_ERR_INVALID_BPID_REQ = -435, 872 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 873 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 874 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 875 }; 876 877 /* For NIX RX vtag action */ 878 enum nix_rx_vtag0_type { 879 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 880 NIX_AF_LFX_RX_VTAG_TYPE1, 881 NIX_AF_LFX_RX_VTAG_TYPE2, 882 NIX_AF_LFX_RX_VTAG_TYPE3, 883 NIX_AF_LFX_RX_VTAG_TYPE4, 884 NIX_AF_LFX_RX_VTAG_TYPE5, 885 NIX_AF_LFX_RX_VTAG_TYPE6, 886 NIX_AF_LFX_RX_VTAG_TYPE7, 887 }; 888 889 /* For NIX LF context alloc and init */ 890 struct nix_lf_alloc_req { 891 struct mbox_msghdr hdr; 892 int node; 893 u32 rq_cnt; /* No of receive queues */ 894 u32 sq_cnt; /* No of send queues */ 895 u32 cq_cnt; /* No of completion queues */ 896 u8 xqe_sz; 897 u16 rss_sz; 898 u8 rss_grps; 899 u16 npa_func; 900 u16 sso_func; 901 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 902 u64 way_mask; 903 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 904 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 905 u64 flags; 906 }; 907 908 struct nix_lf_alloc_rsp { 909 struct mbox_msghdr hdr; 910 u16 sqb_size; 911 u16 rx_chan_base; 912 u16 tx_chan_base; 913 u8 rx_chan_cnt; /* total number of RX channels */ 914 u8 tx_chan_cnt; /* total number of TX channels */ 915 u8 lso_tsov4_idx; 916 u8 lso_tsov6_idx; 917 u8 mac_addr[ETH_ALEN]; 918 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 919 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 920 u16 cints; /* NIX_AF_CONST2::CINTS */ 921 u16 qints; /* NIX_AF_CONST2::QINTS */ 922 u8 cgx_links; /* No. of CGX links present in HW */ 923 u8 lbk_links; /* No. of LBK links present in HW */ 924 u8 sdp_links; /* No. of SDP links present in HW */ 925 u8 tx_link; /* Transmit channel link number */ 926 }; 927 928 struct nix_lf_free_req { 929 struct mbox_msghdr hdr; 930 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 931 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 932 u64 flags; 933 }; 934 935 /* CN10K NIX AQ enqueue msg */ 936 struct nix_cn10k_aq_enq_req { 937 struct mbox_msghdr hdr; 938 u32 qidx; 939 u8 ctype; 940 u8 op; 941 union { 942 struct nix_cn10k_rq_ctx_s rq; 943 struct nix_cn10k_sq_ctx_s sq; 944 struct nix_cq_ctx_s cq; 945 struct nix_rsse_s rss; 946 struct nix_rx_mce_s mce; 947 struct nix_bandprof_s prof; 948 }; 949 union { 950 struct nix_cn10k_rq_ctx_s rq_mask; 951 struct nix_cn10k_sq_ctx_s sq_mask; 952 struct nix_cq_ctx_s cq_mask; 953 struct nix_rsse_s rss_mask; 954 struct nix_rx_mce_s mce_mask; 955 struct nix_bandprof_s prof_mask; 956 }; 957 }; 958 959 struct nix_cn10k_aq_enq_rsp { 960 struct mbox_msghdr hdr; 961 union { 962 struct nix_cn10k_rq_ctx_s rq; 963 struct nix_cn10k_sq_ctx_s sq; 964 struct nix_cq_ctx_s cq; 965 struct nix_rsse_s rss; 966 struct nix_rx_mce_s mce; 967 struct nix_bandprof_s prof; 968 }; 969 }; 970 971 /* NIX AQ enqueue msg */ 972 struct nix_aq_enq_req { 973 struct mbox_msghdr hdr; 974 u32 qidx; 975 u8 ctype; 976 u8 op; 977 union { 978 struct nix_rq_ctx_s rq; 979 struct nix_sq_ctx_s sq; 980 struct nix_cq_ctx_s cq; 981 struct nix_rsse_s rss; 982 struct nix_rx_mce_s mce; 983 struct nix_bandprof_s prof; 984 }; 985 union { 986 struct nix_rq_ctx_s rq_mask; 987 struct nix_sq_ctx_s sq_mask; 988 struct nix_cq_ctx_s cq_mask; 989 struct nix_rsse_s rss_mask; 990 struct nix_rx_mce_s mce_mask; 991 struct nix_bandprof_s prof_mask; 992 }; 993 }; 994 995 struct nix_aq_enq_rsp { 996 struct mbox_msghdr hdr; 997 union { 998 struct nix_rq_ctx_s rq; 999 struct nix_sq_ctx_s sq; 1000 struct nix_cq_ctx_s cq; 1001 struct nix_rsse_s rss; 1002 struct nix_rx_mce_s mce; 1003 struct nix_bandprof_s prof; 1004 }; 1005 }; 1006 1007 /* Tx scheduler/shaper mailbox messages */ 1008 1009 #define MAX_TXSCHQ_PER_FUNC 128 1010 1011 struct nix_txsch_alloc_req { 1012 struct mbox_msghdr hdr; 1013 /* Scheduler queue count request at each level */ 1014 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 1015 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 1016 }; 1017 1018 struct nix_txsch_alloc_rsp { 1019 struct mbox_msghdr hdr; 1020 /* Scheduler queue count allocated at each level */ 1021 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 1022 u16 schq[NIX_TXSCH_LVL_CNT]; 1023 /* Scheduler queue list allocated at each level */ 1024 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1025 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1026 u8 aggr_level; /* Traffic aggregation scheduler level */ 1027 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 1028 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 1029 }; 1030 1031 struct nix_txsch_free_req { 1032 struct mbox_msghdr hdr; 1033 #define TXSCHQ_FREE_ALL BIT_ULL(0) 1034 u16 flags; 1035 /* Scheduler queue level to be freed */ 1036 u16 schq_lvl; 1037 /* List of scheduler queues to be freed */ 1038 u16 schq; 1039 }; 1040 1041 struct nix_txschq_config { 1042 struct mbox_msghdr hdr; 1043 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1044 u8 read; 1045 #define TXSCHQ_IDX_SHIFT 16 1046 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1047 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1048 u8 num_regs; 1049 #define MAX_REGS_PER_MBOX_MSG 20 1050 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1051 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1052 /* All 0's => overwrite with new value */ 1053 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1054 }; 1055 1056 struct nix_vtag_config { 1057 struct mbox_msghdr hdr; 1058 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1059 u8 vtag_size; 1060 /* cfg_type is '0' for tx vlan cfg 1061 * cfg_type is '1' for rx vlan cfg 1062 */ 1063 u8 cfg_type; 1064 union { 1065 /* valid when cfg_type is '0' */ 1066 struct { 1067 u64 vtag0; 1068 u64 vtag1; 1069 1070 /* cfg_vtag0 & cfg_vtag1 fields are valid 1071 * when free_vtag0 & free_vtag1 are '0's. 1072 */ 1073 /* cfg_vtag0 = 1 to configure vtag0 */ 1074 u8 cfg_vtag0 :1; 1075 /* cfg_vtag1 = 1 to configure vtag1 */ 1076 u8 cfg_vtag1 :1; 1077 1078 /* vtag0_idx & vtag1_idx are only valid when 1079 * both cfg_vtag0 & cfg_vtag1 are '0's, 1080 * these fields are used along with free_vtag0 1081 * & free_vtag1 to free the nix lf's tx_vlan 1082 * configuration. 1083 * 1084 * Denotes the indices of tx_vtag def registers 1085 * that needs to be cleared and freed. 1086 */ 1087 int vtag0_idx; 1088 int vtag1_idx; 1089 1090 /* free_vtag0 & free_vtag1 fields are valid 1091 * when cfg_vtag0 & cfg_vtag1 are '0's. 1092 */ 1093 /* free_vtag0 = 1 clears vtag0 configuration 1094 * vtag0_idx denotes the index to be cleared. 1095 */ 1096 u8 free_vtag0 :1; 1097 /* free_vtag1 = 1 clears vtag1 configuration 1098 * vtag1_idx denotes the index to be cleared. 1099 */ 1100 u8 free_vtag1 :1; 1101 } tx; 1102 1103 /* valid when cfg_type is '1' */ 1104 struct { 1105 /* rx vtag type index, valid values are in 0..7 range */ 1106 u8 vtag_type; 1107 /* rx vtag strip */ 1108 u8 strip_vtag :1; 1109 /* rx vtag capture */ 1110 u8 capture_vtag :1; 1111 } rx; 1112 }; 1113 }; 1114 1115 struct nix_vtag_config_rsp { 1116 struct mbox_msghdr hdr; 1117 int vtag0_idx; 1118 int vtag1_idx; 1119 /* Indices of tx_vtag def registers used to configure 1120 * tx vtag0 & vtag1 headers, these indices are valid 1121 * when nix_vtag_config mbox requested for vtag0 and/ 1122 * or vtag1 configuration. 1123 */ 1124 }; 1125 1126 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1127 1128 struct nix_rss_flowkey_cfg { 1129 struct mbox_msghdr hdr; 1130 int mcam_index; /* MCAM entry index to modify */ 1131 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1132 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1133 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1134 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1135 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1136 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1137 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1138 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1139 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1140 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1141 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1142 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1143 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1144 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1145 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1146 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1147 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1148 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1149 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1150 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1151 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1152 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1153 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1154 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1155 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1156 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1157 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1158 u32 flowkey_cfg; /* Flowkey types selected */ 1159 u8 group; /* RSS context or group */ 1160 }; 1161 1162 struct nix_rss_flowkey_cfg_rsp { 1163 struct mbox_msghdr hdr; 1164 u8 alg_idx; /* Selected algo index */ 1165 }; 1166 1167 struct nix_set_mac_addr { 1168 struct mbox_msghdr hdr; 1169 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1170 }; 1171 1172 struct nix_get_mac_addr_rsp { 1173 struct mbox_msghdr hdr; 1174 u8 mac_addr[ETH_ALEN]; 1175 }; 1176 1177 struct nix_mark_format_cfg { 1178 struct mbox_msghdr hdr; 1179 u8 offset; 1180 u8 y_mask; 1181 u8 y_val; 1182 u8 r_mask; 1183 u8 r_val; 1184 }; 1185 1186 struct nix_mark_format_cfg_rsp { 1187 struct mbox_msghdr hdr; 1188 u8 mark_format_idx; 1189 }; 1190 1191 struct nix_rx_mode { 1192 struct mbox_msghdr hdr; 1193 #define NIX_RX_MODE_UCAST BIT(0) 1194 #define NIX_RX_MODE_PROMISC BIT(1) 1195 #define NIX_RX_MODE_ALLMULTI BIT(2) 1196 #define NIX_RX_MODE_USE_MCE BIT(3) 1197 u16 mode; 1198 }; 1199 1200 struct nix_rx_cfg { 1201 struct mbox_msghdr hdr; 1202 #define NIX_RX_OL3_VERIFY BIT(0) 1203 #define NIX_RX_OL4_VERIFY BIT(1) 1204 #define NIX_RX_DROP_RE BIT(2) 1205 u8 len_verify; /* Outer L3/L4 len check */ 1206 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1207 u8 csum_verify; /* Outer L4 checksum verification */ 1208 }; 1209 1210 struct nix_frs_cfg { 1211 struct mbox_msghdr hdr; 1212 u8 update_smq; /* Update SMQ's min/max lens */ 1213 u8 update_minlen; /* Set minlen also */ 1214 u8 sdp_link; /* Set SDP RX link */ 1215 u16 maxlen; 1216 u16 minlen; 1217 }; 1218 1219 struct nix_lso_format_cfg { 1220 struct mbox_msghdr hdr; 1221 u64 field_mask; 1222 #define NIX_LSO_FIELD_MAX 8 1223 u64 fields[NIX_LSO_FIELD_MAX]; 1224 }; 1225 1226 struct nix_lso_format_cfg_rsp { 1227 struct mbox_msghdr hdr; 1228 u8 lso_format_idx; 1229 }; 1230 1231 struct nix_bp_cfg_req { 1232 struct mbox_msghdr hdr; 1233 u16 chan_base; /* Starting channel number */ 1234 u8 chan_cnt; /* Number of channels */ 1235 u8 bpid_per_chan; 1236 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1237 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1238 }; 1239 1240 /* Maximum channels any single NIX interface can have */ 1241 #define NIX_MAX_BPID_CHAN 256 1242 struct nix_bp_cfg_rsp { 1243 struct mbox_msghdr hdr; 1244 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1245 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1246 }; 1247 1248 struct nix_mcast_grp_create_req { 1249 struct mbox_msghdr hdr; 1250 #define NIX_MCAST_INGRESS 0 1251 #define NIX_MCAST_EGRESS 1 1252 u8 dir; 1253 u8 reserved[11]; 1254 /* Reserving few bytes for future requirement */ 1255 }; 1256 1257 struct nix_mcast_grp_create_rsp { 1258 struct mbox_msghdr hdr; 1259 /* This mcast_grp_idx should be passed during MCAM 1260 * write entry for multicast. AF will identify the 1261 * corresponding multicast table index associated 1262 * with the group id and program the same to MCAM entry. 1263 * This group id is also needed during group delete 1264 * and update request. 1265 */ 1266 u32 mcast_grp_idx; 1267 }; 1268 1269 struct nix_mcast_grp_destroy_req { 1270 struct mbox_msghdr hdr; 1271 /* Group id returned by nix_mcast_grp_create_rsp */ 1272 u32 mcast_grp_idx; 1273 /* If AF is requesting for destroy, then set 1274 * it to '1'. Otherwise keep it to '0' 1275 */ 1276 u8 is_af; 1277 }; 1278 1279 struct nix_mcast_grp_update_req { 1280 struct mbox_msghdr hdr; 1281 /* Group id returned by nix_mcast_grp_create_rsp */ 1282 u32 mcast_grp_idx; 1283 /* Number of multicast/mirror entries requested */ 1284 u32 num_mce_entry; 1285 #define NIX_MCE_ENTRY_MAX 64 1286 #define NIX_RX_RQ 0 1287 #define NIX_RX_RSS 1 1288 /* Receive queue or RSS index within pf_func */ 1289 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1290 /* pcifunc is required for both ingress and egress multicast */ 1291 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1292 /* channel is required for egress multicast */ 1293 u16 channel[NIX_MCE_ENTRY_MAX]; 1294 #define NIX_MCAST_OP_ADD_ENTRY 0 1295 #define NIX_MCAST_OP_DEL_ENTRY 1 1296 /* Destination type. 0:Receive queue, 1:RSS*/ 1297 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1298 u8 op; 1299 /* If AF is requesting for update, then set 1300 * it to '1'. Otherwise keep it to '0' 1301 */ 1302 u8 is_af; 1303 }; 1304 1305 struct nix_mcast_grp_update_rsp { 1306 struct mbox_msghdr hdr; 1307 u32 mce_start_index; 1308 }; 1309 1310 /* Global NIX inline IPSec configuration */ 1311 struct nix_inline_ipsec_cfg { 1312 struct mbox_msghdr hdr; 1313 u32 cpt_credit; 1314 struct { 1315 u8 egrp; 1316 u16 opcode; 1317 u16 param1; 1318 u16 param2; 1319 } gen_cfg; 1320 struct { 1321 u16 cpt_pf_func; 1322 u8 cpt_slot; 1323 } inst_qsel; 1324 u8 enable; 1325 u16 bpid; 1326 u32 credit_th; 1327 }; 1328 1329 /* Per NIX LF inline IPSec configuration */ 1330 struct nix_inline_ipsec_lf_cfg { 1331 struct mbox_msghdr hdr; 1332 u64 sa_base_addr; 1333 struct { 1334 u32 tag_const; 1335 u16 lenm1_max; 1336 u8 sa_pow2_size; 1337 u8 tt; 1338 } ipsec_cfg0; 1339 struct { 1340 u32 sa_idx_max; 1341 u8 sa_idx_w; 1342 } ipsec_cfg1; 1343 u8 enable; 1344 }; 1345 1346 struct nix_hw_info { 1347 struct mbox_msghdr hdr; 1348 u16 rsvs16; 1349 u16 max_mtu; 1350 u16 min_mtu; 1351 u32 rpm_dwrr_mtu; 1352 u32 sdp_dwrr_mtu; 1353 u32 lbk_dwrr_mtu; 1354 u32 rsvd32[1]; 1355 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1356 }; 1357 1358 struct nix_bandprof_alloc_req { 1359 struct mbox_msghdr hdr; 1360 /* Count of profiles needed per layer */ 1361 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1362 }; 1363 1364 struct nix_bandprof_alloc_rsp { 1365 struct mbox_msghdr hdr; 1366 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1367 1368 /* There is no need to allocate morethan 1 bandwidth profile 1369 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1370 * profiles to 64 per PF_FUNC. 1371 */ 1372 #define MAX_BANDPROF_PER_PFFUNC 64 1373 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1374 }; 1375 1376 struct nix_bandprof_free_req { 1377 struct mbox_msghdr hdr; 1378 u8 free_all; 1379 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1380 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1381 }; 1382 1383 struct nix_bandprof_get_hwinfo_rsp { 1384 struct mbox_msghdr hdr; 1385 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1386 u32 policer_timeunit; 1387 }; 1388 1389 struct nix_stats_req { 1390 struct mbox_msghdr hdr; 1391 u8 reset; 1392 u16 pcifunc; 1393 u64 rsvd; 1394 }; 1395 1396 struct nix_stats_rsp { 1397 struct mbox_msghdr hdr; 1398 u16 pcifunc; 1399 struct { 1400 u64 octs; 1401 u64 ucast; 1402 u64 bcast; 1403 u64 mcast; 1404 u64 drop; 1405 u64 drop_octs; 1406 u64 drop_mcast; 1407 u64 drop_bcast; 1408 u64 err; 1409 u64 rsvd[5]; 1410 } rx; 1411 struct { 1412 u64 ucast; 1413 u64 bcast; 1414 u64 mcast; 1415 u64 drop; 1416 u64 octs; 1417 } tx; 1418 }; 1419 1420 /* NPC mbox message structs */ 1421 1422 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1423 #define NPC_MCAM_INVALID_MAP 0xFFFF 1424 1425 /* NPC mailbox error codes 1426 * Range 701 - 800. 1427 */ 1428 enum npc_af_status { 1429 NPC_MCAM_INVALID_REQ = -701, 1430 NPC_MCAM_ALLOC_DENIED = -702, 1431 NPC_MCAM_ALLOC_FAILED = -703, 1432 NPC_MCAM_PERM_DENIED = -704, 1433 NPC_FLOW_INTF_INVALID = -707, 1434 NPC_FLOW_CHAN_INVALID = -708, 1435 NPC_FLOW_NO_NIXLF = -709, 1436 NPC_FLOW_NOT_SUPPORTED = -710, 1437 NPC_FLOW_VF_PERM_DENIED = -711, 1438 NPC_FLOW_VF_NOT_INIT = -712, 1439 NPC_FLOW_VF_OVERLAP = -713, 1440 }; 1441 1442 struct npc_mcam_alloc_entry_req { 1443 struct mbox_msghdr hdr; 1444 #define NPC_MAX_NONCONTIG_ENTRIES 256 1445 u8 contig; /* Contiguous entries ? */ 1446 #define NPC_MCAM_ANY_PRIO 0 1447 #define NPC_MCAM_LOWER_PRIO 1 1448 #define NPC_MCAM_HIGHER_PRIO 2 1449 u8 priority; /* Lower or higher w.r.t ref_entry */ 1450 u16 ref_entry; 1451 u16 count; /* Number of entries requested */ 1452 }; 1453 1454 struct npc_mcam_alloc_entry_rsp { 1455 struct mbox_msghdr hdr; 1456 u16 entry; /* Entry allocated or start index if contiguous. 1457 * Invalid incase of non-contiguous. 1458 */ 1459 u16 count; /* Number of entries allocated */ 1460 u16 free_count; /* Number of entries available */ 1461 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1462 }; 1463 1464 struct npc_mcam_free_entry_req { 1465 struct mbox_msghdr hdr; 1466 u16 entry; /* Entry index to be freed */ 1467 u8 all; /* If all entries allocated to this PFVF to be freed */ 1468 }; 1469 1470 struct mcam_entry { 1471 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1472 u64 kw[NPC_MAX_KWS_IN_KEY]; 1473 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1474 u64 action; 1475 u64 vtag_action; 1476 }; 1477 1478 struct npc_mcam_write_entry_req { 1479 struct mbox_msghdr hdr; 1480 struct mcam_entry entry_data; 1481 u16 entry; /* MCAM entry to write this match key */ 1482 u16 cntr; /* Counter for this MCAM entry */ 1483 u8 intf; /* Rx or Tx interface */ 1484 u8 enable_entry;/* Enable this MCAM entry ? */ 1485 u8 set_cntr; /* Set counter for this entry ? */ 1486 }; 1487 1488 /* Enable/Disable a given entry */ 1489 struct npc_mcam_ena_dis_entry_req { 1490 struct mbox_msghdr hdr; 1491 u16 entry; 1492 }; 1493 1494 struct npc_mcam_shift_entry_req { 1495 struct mbox_msghdr hdr; 1496 #define NPC_MCAM_MAX_SHIFTS 64 1497 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1498 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1499 u16 shift_count; /* Number of entries to shift */ 1500 }; 1501 1502 struct npc_mcam_shift_entry_rsp { 1503 struct mbox_msghdr hdr; 1504 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1505 }; 1506 1507 struct npc_mcam_alloc_counter_req { 1508 struct mbox_msghdr hdr; 1509 u8 contig; /* Contiguous counters ? */ 1510 #define NPC_MAX_NONCONTIG_COUNTERS 64 1511 u16 count; /* Number of counters requested */ 1512 }; 1513 1514 struct npc_mcam_alloc_counter_rsp { 1515 struct mbox_msghdr hdr; 1516 u16 cntr; /* Counter allocated or start index if contiguous. 1517 * Invalid incase of non-contiguous. 1518 */ 1519 u16 count; /* Number of counters allocated */ 1520 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1521 }; 1522 1523 struct npc_mcam_oper_counter_req { 1524 struct mbox_msghdr hdr; 1525 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1526 }; 1527 1528 struct npc_mcam_oper_counter_rsp { 1529 struct mbox_msghdr hdr; 1530 u64 stat; /* valid only while fetching counter's stats */ 1531 }; 1532 1533 struct npc_mcam_unmap_counter_req { 1534 struct mbox_msghdr hdr; 1535 u16 cntr; 1536 u16 entry; /* Entry and counter to be unmapped */ 1537 u8 all; /* Unmap all entries using this counter ? */ 1538 }; 1539 1540 struct npc_mcam_alloc_and_write_entry_req { 1541 struct mbox_msghdr hdr; 1542 struct mcam_entry entry_data; 1543 u16 ref_entry; 1544 u8 priority; /* Lower or higher w.r.t ref_entry */ 1545 u8 intf; /* Rx or Tx interface */ 1546 u8 enable_entry;/* Enable this MCAM entry ? */ 1547 u8 alloc_cntr; /* Allocate counter and map ? */ 1548 }; 1549 1550 struct npc_mcam_alloc_and_write_entry_rsp { 1551 struct mbox_msghdr hdr; 1552 u16 entry; 1553 u16 cntr; 1554 }; 1555 1556 struct npc_get_kex_cfg_rsp { 1557 struct mbox_msghdr hdr; 1558 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1559 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1560 #define NPC_MAX_INTF 2 1561 #define NPC_MAX_LID 8 1562 #define NPC_MAX_LT 16 1563 #define NPC_MAX_LD 2 1564 #define NPC_MAX_LFL 16 1565 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1566 u64 kex_ld_flags[NPC_MAX_LD]; 1567 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1568 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1569 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1570 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1571 #define MKEX_NAME_LEN 128 1572 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1573 }; 1574 1575 struct ptp_get_cap_rsp { 1576 struct mbox_msghdr hdr; 1577 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1578 u64 cap; 1579 }; 1580 1581 struct get_rep_cnt_rsp { 1582 struct mbox_msghdr hdr; 1583 u16 rep_cnt; 1584 u16 rep_pf_map[64]; 1585 u64 rsvd; 1586 }; 1587 1588 struct esw_cfg_req { 1589 struct mbox_msghdr hdr; 1590 u8 ena; 1591 u64 rsvd; 1592 }; 1593 1594 struct rep_evt_data { 1595 u8 port_state; 1596 u8 vf_state; 1597 u16 rx_mode; 1598 u16 rx_flags; 1599 u16 mtu; 1600 u8 mac[ETH_ALEN]; 1601 u64 rsvd[5]; 1602 }; 1603 1604 struct rep_event { 1605 struct mbox_msghdr hdr; 1606 u16 pcifunc; 1607 #define RVU_EVENT_PORT_STATE BIT_ULL(0) 1608 #define RVU_EVENT_PFVF_STATE BIT_ULL(1) 1609 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2) 1610 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3) 1611 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4) 1612 u16 event; 1613 struct rep_evt_data evt_data; 1614 }; 1615 1616 struct flow_msg { 1617 unsigned char dmac[6]; 1618 unsigned char smac[6]; 1619 __be16 etype; 1620 __be16 vlan_etype; 1621 __be16 vlan_tci; 1622 union { 1623 __be32 ip4src; 1624 __be32 ip6src[4]; 1625 }; 1626 union { 1627 __be32 ip4dst; 1628 __be32 ip6dst[4]; 1629 }; 1630 union { 1631 __be32 spi; 1632 }; 1633 1634 u8 tos; 1635 u8 ip_ver; 1636 u8 ip_proto; 1637 u8 tc; 1638 __be16 sport; 1639 __be16 dport; 1640 union { 1641 u8 ip_flag; 1642 u8 next_header; 1643 }; 1644 __be16 vlan_itci; 1645 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1646 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1647 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1648 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1649 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1650 u32 mpls_lse[4]; 1651 u8 icmp_type; 1652 u8 icmp_code; 1653 __be16 tcp_flags; 1654 u16 sq_id; 1655 }; 1656 1657 struct npc_install_flow_req { 1658 struct mbox_msghdr hdr; 1659 struct flow_msg packet; 1660 struct flow_msg mask; 1661 u64 features; 1662 u16 entry; 1663 u16 channel; 1664 u16 chan_mask; 1665 u8 intf; 1666 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1667 u8 default_rule; 1668 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1669 u16 vf; 1670 /* action */ 1671 u32 index; 1672 u16 match_id; 1673 u8 flow_key_alg; 1674 u8 op; 1675 /* vtag rx action */ 1676 u8 vtag0_type; 1677 u8 vtag0_valid; 1678 u8 vtag1_type; 1679 u8 vtag1_valid; 1680 /* vtag tx action */ 1681 u16 vtag0_def; 1682 u8 vtag0_op; 1683 u16 vtag1_def; 1684 u8 vtag1_op; 1685 /* old counter value */ 1686 u16 cntr_val; 1687 }; 1688 1689 struct npc_install_flow_rsp { 1690 struct mbox_msghdr hdr; 1691 int counter; /* negative if no counter else counter number */ 1692 }; 1693 1694 struct npc_delete_flow_req { 1695 struct mbox_msghdr hdr; 1696 u16 entry; 1697 u16 start;/*Disable range of entries */ 1698 u16 end; 1699 u8 all; /* PF + VFs */ 1700 }; 1701 1702 struct npc_delete_flow_rsp { 1703 struct mbox_msghdr hdr; 1704 u16 cntr_val; 1705 }; 1706 1707 struct npc_mcam_read_entry_req { 1708 struct mbox_msghdr hdr; 1709 u16 entry; /* MCAM entry to read */ 1710 }; 1711 1712 struct npc_mcam_read_entry_rsp { 1713 struct mbox_msghdr hdr; 1714 struct mcam_entry entry_data; 1715 u8 intf; 1716 u8 enable; 1717 }; 1718 1719 struct npc_mcam_read_base_rule_rsp { 1720 struct mbox_msghdr hdr; 1721 struct mcam_entry entry; 1722 }; 1723 1724 struct npc_mcam_get_stats_req { 1725 struct mbox_msghdr hdr; 1726 u16 entry; /* mcam entry */ 1727 }; 1728 1729 struct npc_mcam_get_stats_rsp { 1730 struct mbox_msghdr hdr; 1731 u64 stat; /* counter stats */ 1732 u8 stat_ena; /* enabled */ 1733 }; 1734 1735 struct npc_get_field_hash_info_req { 1736 struct mbox_msghdr hdr; 1737 u8 intf; 1738 }; 1739 1740 struct npc_get_field_hash_info_rsp { 1741 struct mbox_msghdr hdr; 1742 u64 secret_key[3]; 1743 #define NPC_MAX_HASH 2 1744 #define NPC_MAX_HASH_MASK 2 1745 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1746 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1747 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1748 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1749 }; 1750 1751 enum ptp_op { 1752 PTP_OP_ADJFINE = 0, 1753 PTP_OP_GET_CLOCK = 1, 1754 PTP_OP_GET_TSTMP = 2, 1755 PTP_OP_SET_THRESH = 3, 1756 PTP_OP_PPS_ON = 4, 1757 PTP_OP_ADJTIME = 5, 1758 PTP_OP_SET_CLOCK = 6, 1759 }; 1760 1761 struct ptp_req { 1762 struct mbox_msghdr hdr; 1763 u8 op; 1764 s64 scaled_ppm; 1765 u64 thresh; 1766 u64 period; 1767 int pps_on; 1768 s64 delta; 1769 u64 clk; 1770 }; 1771 1772 struct ptp_rsp { 1773 struct mbox_msghdr hdr; 1774 u64 clk; 1775 u64 tsc; 1776 }; 1777 1778 struct npc_get_field_status_req { 1779 struct mbox_msghdr hdr; 1780 u8 intf; 1781 u8 field; 1782 }; 1783 1784 struct npc_get_field_status_rsp { 1785 struct mbox_msghdr hdr; 1786 u8 enable; 1787 }; 1788 1789 struct set_vf_perm { 1790 struct mbox_msghdr hdr; 1791 u16 vf; 1792 #define RESET_VF_PERM BIT_ULL(0) 1793 #define VF_TRUSTED BIT_ULL(1) 1794 u64 flags; 1795 }; 1796 1797 struct lmtst_tbl_setup_req { 1798 struct mbox_msghdr hdr; 1799 u64 dis_sched_early_comp :1; 1800 u64 sch_ena :1; 1801 u64 dis_line_pref :1; 1802 u64 ssow_pf_func :13; 1803 u16 base_pcifunc; 1804 u8 use_local_lmt_region; 1805 u64 lmt_iova; 1806 u64 rsvd[4]; 1807 }; 1808 1809 struct ndc_sync_op { 1810 struct mbox_msghdr hdr; 1811 u8 nix_lf_tx_sync; 1812 u8 nix_lf_rx_sync; 1813 u8 npa_lf_sync; 1814 }; 1815 1816 /* CPT mailbox error codes 1817 * Range 901 - 1000. 1818 */ 1819 enum cpt_af_status { 1820 CPT_AF_ERR_PARAM = -901, 1821 CPT_AF_ERR_GRP_INVALID = -902, 1822 CPT_AF_ERR_LF_INVALID = -903, 1823 CPT_AF_ERR_ACCESS_DENIED = -904, 1824 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1825 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1826 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1827 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1828 }; 1829 1830 /* CPT mbox message formats */ 1831 struct cpt_rd_wr_reg_msg { 1832 struct mbox_msghdr hdr; 1833 u64 reg_offset; 1834 u64 *ret_val; 1835 u64 val; 1836 u8 is_write; 1837 int blkaddr; 1838 }; 1839 1840 struct cpt_lf_alloc_req_msg { 1841 struct mbox_msghdr hdr; 1842 u16 nix_pf_func; 1843 u16 sso_pf_func; 1844 u16 eng_grpmsk; 1845 u8 blkaddr; 1846 u8 ctx_ilen_valid : 1; 1847 u8 ctx_ilen : 7; 1848 }; 1849 1850 #define CPT_INLINE_INBOUND 0 1851 #define CPT_INLINE_OUTBOUND 1 1852 1853 /* Mailbox message request format for CPT IPsec 1854 * inline inbound and outbound configuration. 1855 */ 1856 struct cpt_inline_ipsec_cfg_msg { 1857 struct mbox_msghdr hdr; 1858 u8 enable; 1859 u8 slot; 1860 u8 dir; 1861 u8 sso_pf_func_ovrd; 1862 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1863 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1864 }; 1865 1866 /* Mailbox message request and response format for CPT stats. */ 1867 struct cpt_sts_req { 1868 struct mbox_msghdr hdr; 1869 u8 blkaddr; 1870 }; 1871 1872 struct cpt_sts_rsp { 1873 struct mbox_msghdr hdr; 1874 u64 inst_req_pc; 1875 u64 inst_lat_pc; 1876 u64 rd_req_pc; 1877 u64 rd_lat_pc; 1878 u64 rd_uc_pc; 1879 u64 active_cycles_pc; 1880 u64 ctx_mis_pc; 1881 u64 ctx_hit_pc; 1882 u64 ctx_aop_pc; 1883 u64 ctx_aop_lat_pc; 1884 u64 ctx_ifetch_pc; 1885 u64 ctx_ifetch_lat_pc; 1886 u64 ctx_ffetch_pc; 1887 u64 ctx_ffetch_lat_pc; 1888 u64 ctx_wback_pc; 1889 u64 ctx_wback_lat_pc; 1890 u64 ctx_psh_pc; 1891 u64 ctx_psh_lat_pc; 1892 u64 ctx_err; 1893 u64 ctx_enc_id; 1894 u64 ctx_flush_timer; 1895 u64 rxc_time; 1896 u64 rxc_time_cfg; 1897 u64 rxc_active_sts; 1898 u64 rxc_zombie_sts; 1899 u64 busy_sts_ae; 1900 u64 free_sts_ae; 1901 u64 busy_sts_se; 1902 u64 free_sts_se; 1903 u64 busy_sts_ie; 1904 u64 free_sts_ie; 1905 u64 exe_err_info; 1906 u64 cptclk_cnt; 1907 u64 diag; 1908 u64 rxc_dfrg; 1909 u64 x2p_link_cfg0; 1910 u64 x2p_link_cfg1; 1911 }; 1912 1913 /* Mailbox message request format to configure reassembly timeout. */ 1914 struct cpt_rxc_time_cfg_req { 1915 struct mbox_msghdr hdr; 1916 int blkaddr; 1917 u32 step; 1918 u16 zombie_thres; 1919 u16 zombie_limit; 1920 u16 active_thres; 1921 u16 active_limit; 1922 }; 1923 1924 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1925 struct cpt_inst_lmtst_req { 1926 struct mbox_msghdr hdr; 1927 u64 inst[8]; 1928 u64 rsvd; 1929 }; 1930 1931 /* Mailbox message format to request for CPT LF reset */ 1932 struct cpt_lf_rst_req { 1933 struct mbox_msghdr hdr; 1934 u32 slot; 1935 u32 rsvd; 1936 }; 1937 1938 /* Mailbox message format to request for CPT faulted engines */ 1939 struct cpt_flt_eng_info_req { 1940 struct mbox_msghdr hdr; 1941 int blkaddr; 1942 bool reset; 1943 u32 rsvd; 1944 }; 1945 1946 struct cpt_flt_eng_info_rsp { 1947 struct mbox_msghdr hdr; 1948 #define CPT_AF_MAX_FLT_INT_VECS 3 1949 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1950 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 1951 u64 rsvd; 1952 }; 1953 1954 struct sdp_node_info { 1955 /* Node to which this PF belons to */ 1956 u8 node_id; 1957 u8 max_vfs; 1958 u8 num_pf_rings; 1959 u8 pf_srn; 1960 #define SDP_MAX_VFS 128 1961 u8 vf_rings[SDP_MAX_VFS]; 1962 }; 1963 1964 struct sdp_chan_info_msg { 1965 struct mbox_msghdr hdr; 1966 struct sdp_node_info info; 1967 }; 1968 1969 struct sdp_get_chan_info_msg { 1970 struct mbox_msghdr hdr; 1971 u16 chan_base; 1972 u16 num_chan; 1973 }; 1974 1975 /* CGX mailbox error codes 1976 * Range 1101 - 1200. 1977 */ 1978 enum cgx_af_status { 1979 LMAC_AF_ERR_INVALID_PARAM = -1101, 1980 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1981 LMAC_AF_ERR_PERM_DENIED = -1103, 1982 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1983 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1984 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1985 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1986 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1987 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1988 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1989 }; 1990 1991 enum mcs_direction { 1992 MCS_RX, 1993 MCS_TX, 1994 }; 1995 1996 enum mcs_rsrc_type { 1997 MCS_RSRC_TYPE_FLOWID, 1998 MCS_RSRC_TYPE_SECY, 1999 MCS_RSRC_TYPE_SC, 2000 MCS_RSRC_TYPE_SA, 2001 }; 2002 2003 struct mcs_alloc_rsrc_req { 2004 struct mbox_msghdr hdr; 2005 u8 rsrc_type; 2006 u8 rsrc_cnt; /* Resources count */ 2007 u8 mcs_id; /* MCS block ID */ 2008 u8 dir; /* Macsec ingress or egress side */ 2009 u8 all; /* Allocate all resource type one each */ 2010 u64 rsvd; 2011 }; 2012 2013 struct mcs_alloc_rsrc_rsp { 2014 struct mbox_msghdr hdr; 2015 u8 flow_ids[128]; /* Index of reserved entries */ 2016 u8 secy_ids[128]; 2017 u8 sc_ids[128]; 2018 u8 sa_ids[256]; 2019 u8 rsrc_type; 2020 u8 rsrc_cnt; /* No of entries reserved */ 2021 u8 mcs_id; 2022 u8 dir; 2023 u8 all; 2024 u8 rsvd[256]; /* reserved fields for future expansion */ 2025 }; 2026 2027 struct mcs_free_rsrc_req { 2028 struct mbox_msghdr hdr; 2029 u8 rsrc_id; /* Index of the entry to be freed */ 2030 u8 rsrc_type; 2031 u8 mcs_id; 2032 u8 dir; 2033 u8 all; /* Free all the cam resources */ 2034 u64 rsvd; 2035 }; 2036 2037 struct mcs_flowid_entry_write_req { 2038 struct mbox_msghdr hdr; 2039 u64 data[4]; 2040 u64 mask[4]; 2041 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 2042 u8 flow_id; 2043 u8 secy_id; /* secyid for which flowid is mapped */ 2044 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 2045 u8 ena; /* Enable tcam entry */ 2046 u8 ctrl_pkt; 2047 u8 mcs_id; 2048 u8 dir; 2049 u64 rsvd; 2050 }; 2051 2052 struct mcs_secy_plcy_write_req { 2053 struct mbox_msghdr hdr; 2054 u64 plcy; 2055 u8 secy_id; 2056 u8 mcs_id; 2057 u8 dir; 2058 u64 rsvd; 2059 }; 2060 2061 /* RX SC_CAM mapping */ 2062 struct mcs_rx_sc_cam_write_req { 2063 struct mbox_msghdr hdr; 2064 u64 sci; /* SCI */ 2065 u64 secy_id; /* secy index mapped to SC */ 2066 u8 sc_id; /* SC CAM entry index */ 2067 u8 mcs_id; 2068 u64 rsvd; 2069 }; 2070 2071 struct mcs_sa_plcy_write_req { 2072 struct mbox_msghdr hdr; 2073 u64 plcy[2][9]; /* Support 2 SA policy */ 2074 u8 sa_index[2]; 2075 u8 sa_cnt; 2076 u8 mcs_id; 2077 u8 dir; 2078 u64 rsvd; 2079 }; 2080 2081 struct mcs_tx_sc_sa_map { 2082 struct mbox_msghdr hdr; 2083 u8 sa_index0; 2084 u8 sa_index1; 2085 u8 rekey_ena; 2086 u8 sa_index0_vld; 2087 u8 sa_index1_vld; 2088 u8 tx_sa_active; 2089 u64 sectag_sci; 2090 u8 sc_id; /* used as index for SA_MEM_MAP */ 2091 u8 mcs_id; 2092 u64 rsvd; 2093 }; 2094 2095 struct mcs_rx_sc_sa_map { 2096 struct mbox_msghdr hdr; 2097 u8 sa_index; 2098 u8 sa_in_use; 2099 u8 sc_id; 2100 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 2101 u8 mcs_id; 2102 u64 rsvd; 2103 }; 2104 2105 struct mcs_flowid_ena_dis_entry { 2106 struct mbox_msghdr hdr; 2107 u8 flow_id; 2108 u8 ena; 2109 u8 mcs_id; 2110 u8 dir; 2111 u64 rsvd; 2112 }; 2113 2114 struct mcs_pn_table_write_req { 2115 struct mbox_msghdr hdr; 2116 u64 next_pn; 2117 u8 pn_id; 2118 u8 mcs_id; 2119 u8 dir; 2120 u64 rsvd; 2121 }; 2122 2123 struct mcs_hw_info { 2124 struct mbox_msghdr hdr; 2125 u8 num_mcs_blks; /* Number of MCS blocks */ 2126 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2127 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2128 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2129 u16 sa_entries; /* PN table entries = SA entries */ 2130 u64 rsvd[16]; 2131 }; 2132 2133 struct mcs_set_active_lmac { 2134 struct mbox_msghdr hdr; 2135 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2136 u8 mcs_id; 2137 u16 chan_base; /* MCS channel base */ 2138 u64 rsvd; 2139 }; 2140 2141 struct mcs_set_lmac_mode { 2142 struct mbox_msghdr hdr; 2143 u8 mode; /* 1:Bypass 0:Operational */ 2144 u8 lmac_id; 2145 u8 mcs_id; 2146 u64 rsvd; 2147 }; 2148 2149 struct mcs_port_reset_req { 2150 struct mbox_msghdr hdr; 2151 u8 reset; 2152 u8 mcs_id; 2153 u8 port_id; 2154 u64 rsvd; 2155 }; 2156 2157 struct mcs_port_cfg_set_req { 2158 struct mbox_msghdr hdr; 2159 u8 cstm_tag_rel_mode_sel; 2160 u8 custom_hdr_enb; 2161 u8 fifo_skid; 2162 u8 port_mode; 2163 u8 port_id; 2164 u8 mcs_id; 2165 u64 rsvd; 2166 }; 2167 2168 struct mcs_port_cfg_get_req { 2169 struct mbox_msghdr hdr; 2170 u8 port_id; 2171 u8 mcs_id; 2172 u64 rsvd; 2173 }; 2174 2175 struct mcs_port_cfg_get_rsp { 2176 struct mbox_msghdr hdr; 2177 u8 cstm_tag_rel_mode_sel; 2178 u8 custom_hdr_enb; 2179 u8 fifo_skid; 2180 u8 port_mode; 2181 u8 port_id; 2182 u8 mcs_id; 2183 u64 rsvd; 2184 }; 2185 2186 struct mcs_custom_tag_cfg_get_req { 2187 struct mbox_msghdr hdr; 2188 u8 mcs_id; 2189 u8 dir; 2190 u64 rsvd; 2191 }; 2192 2193 struct mcs_custom_tag_cfg_get_rsp { 2194 struct mbox_msghdr hdr; 2195 u16 cstm_etype[8]; 2196 u8 cstm_indx[8]; 2197 u8 cstm_etype_en; 2198 u8 mcs_id; 2199 u8 dir; 2200 u64 rsvd; 2201 }; 2202 2203 /* MCS mailbox error codes 2204 * Range 1201 - 1300. 2205 */ 2206 enum mcs_af_status { 2207 MCS_AF_ERR_INVALID_MCSID = -1201, 2208 MCS_AF_ERR_NOT_MAPPED = -1202, 2209 }; 2210 2211 struct mcs_set_pn_threshold { 2212 struct mbox_msghdr hdr; 2213 u64 threshold; 2214 u8 xpn; /* '1' for setting xpn threshold */ 2215 u8 mcs_id; 2216 u8 dir; 2217 u64 rsvd; 2218 }; 2219 2220 enum mcs_ctrl_pkt_rulew_type { 2221 MCS_CTRL_PKT_RULE_TYPE_ETH, 2222 MCS_CTRL_PKT_RULE_TYPE_DA, 2223 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2224 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2225 MCS_CTRL_PKT_RULE_TYPE_MAC, 2226 }; 2227 2228 struct mcs_alloc_ctrl_pkt_rule_req { 2229 struct mbox_msghdr hdr; 2230 u8 rule_type; 2231 u8 mcs_id; /* MCS block ID */ 2232 u8 dir; /* Macsec ingress or egress side */ 2233 u64 rsvd; 2234 }; 2235 2236 struct mcs_alloc_ctrl_pkt_rule_rsp { 2237 struct mbox_msghdr hdr; 2238 u8 rule_idx; 2239 u8 rule_type; 2240 u8 mcs_id; 2241 u8 dir; 2242 u64 rsvd; 2243 }; 2244 2245 struct mcs_free_ctrl_pkt_rule_req { 2246 struct mbox_msghdr hdr; 2247 u8 rule_idx; 2248 u8 rule_type; 2249 u8 mcs_id; 2250 u8 dir; 2251 u8 all; 2252 u64 rsvd; 2253 }; 2254 2255 struct mcs_ctrl_pkt_rule_write_req { 2256 struct mbox_msghdr hdr; 2257 u64 data0; 2258 u64 data1; 2259 u64 data2; 2260 u8 rule_idx; 2261 u8 rule_type; 2262 u8 mcs_id; 2263 u8 dir; 2264 u64 rsvd; 2265 }; 2266 2267 struct mcs_stats_req { 2268 struct mbox_msghdr hdr; 2269 u8 id; 2270 u8 mcs_id; 2271 u8 dir; 2272 u64 rsvd; 2273 }; 2274 2275 struct mcs_flowid_stats { 2276 struct mbox_msghdr hdr; 2277 u64 tcam_hit_cnt; 2278 u64 rsvd; 2279 }; 2280 2281 struct mcs_secy_stats { 2282 struct mbox_msghdr hdr; 2283 u64 ctl_pkt_bcast_cnt; 2284 u64 ctl_pkt_mcast_cnt; 2285 u64 ctl_pkt_ucast_cnt; 2286 u64 ctl_octet_cnt; 2287 u64 unctl_pkt_bcast_cnt; 2288 u64 unctl_pkt_mcast_cnt; 2289 u64 unctl_pkt_ucast_cnt; 2290 u64 unctl_octet_cnt; 2291 /* Valid only for RX */ 2292 u64 octet_decrypted_cnt; 2293 u64 octet_validated_cnt; 2294 u64 pkt_port_disabled_cnt; 2295 u64 pkt_badtag_cnt; 2296 u64 pkt_nosa_cnt; 2297 u64 pkt_nosaerror_cnt; 2298 u64 pkt_tagged_ctl_cnt; 2299 u64 pkt_untaged_cnt; 2300 u64 pkt_ctl_cnt; /* CN10K-B */ 2301 u64 pkt_notag_cnt; /* CNF10K-B */ 2302 /* Valid only for TX */ 2303 u64 octet_encrypted_cnt; 2304 u64 octet_protected_cnt; 2305 u64 pkt_noactivesa_cnt; 2306 u64 pkt_toolong_cnt; 2307 u64 pkt_untagged_cnt; 2308 u64 rsvd[4]; 2309 }; 2310 2311 struct mcs_port_stats { 2312 struct mbox_msghdr hdr; 2313 u64 tcam_miss_cnt; 2314 u64 parser_err_cnt; 2315 u64 preempt_err_cnt; /* CNF10K-B */ 2316 u64 sectag_insert_err_cnt; 2317 u64 rsvd[4]; 2318 }; 2319 2320 /* Only for CN10K-B */ 2321 struct mcs_sa_stats { 2322 struct mbox_msghdr hdr; 2323 /* RX */ 2324 u64 pkt_invalid_cnt; 2325 u64 pkt_nosaerror_cnt; 2326 u64 pkt_notvalid_cnt; 2327 u64 pkt_ok_cnt; 2328 u64 pkt_nosa_cnt; 2329 /* TX */ 2330 u64 pkt_encrypt_cnt; 2331 u64 pkt_protected_cnt; 2332 u64 rsvd[4]; 2333 }; 2334 2335 struct mcs_sc_stats { 2336 struct mbox_msghdr hdr; 2337 /* RX */ 2338 u64 hit_cnt; 2339 u64 pkt_invalid_cnt; 2340 u64 pkt_late_cnt; 2341 u64 pkt_notvalid_cnt; 2342 u64 pkt_unchecked_cnt; 2343 u64 pkt_delay_cnt; /* CNF10K-B */ 2344 u64 pkt_ok_cnt; /* CNF10K-B */ 2345 u64 octet_decrypt_cnt; /* CN10K-B */ 2346 u64 octet_validate_cnt; /* CN10K-B */ 2347 /* TX */ 2348 u64 pkt_encrypt_cnt; 2349 u64 pkt_protected_cnt; 2350 u64 octet_encrypt_cnt; /* CN10K-B */ 2351 u64 octet_protected_cnt; /* CN10K-B */ 2352 u64 rsvd[4]; 2353 }; 2354 2355 struct mcs_clear_stats { 2356 struct mbox_msghdr hdr; 2357 #define MCS_FLOWID_STATS 0 2358 #define MCS_SECY_STATS 1 2359 #define MCS_SC_STATS 2 2360 #define MCS_SA_STATS 3 2361 #define MCS_PORT_STATS 4 2362 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2363 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2364 u8 mcs_id; 2365 u8 dir; 2366 u8 all; /* All resources stats mapped to PF are cleared */ 2367 }; 2368 2369 struct mcs_intr_cfg { 2370 struct mbox_msghdr hdr; 2371 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2372 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2373 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2374 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2375 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2376 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2377 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2378 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2379 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2380 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2381 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2382 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2383 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2384 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2385 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2386 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2387 u64 intr_mask; /* Interrupt enable mask */ 2388 u8 mcs_id; 2389 u8 lmac_id; 2390 u64 rsvd; 2391 }; 2392 2393 struct mcs_intr_info { 2394 struct mbox_msghdr hdr; 2395 u64 intr_mask; 2396 int sa_id; 2397 u8 mcs_id; 2398 u8 lmac_id; 2399 u64 rsvd; 2400 }; 2401 2402 #endif /* MBOX_H */ 2403