1f326d5d8SSai Krishna /* SPDX-License-Identifier: GPL-2.0 */ 2f326d5d8SSai Krishna /* Marvell RVU Admin Function driver 3f326d5d8SSai Krishna * 4f326d5d8SSai Krishna * Copyright (C) 2024 Marvell. 5f326d5d8SSai Krishna * 6f326d5d8SSai Krishna */ 7f326d5d8SSai Krishna 8f326d5d8SSai Krishna #ifndef STRUCT_H 9f326d5d8SSai Krishna #define STRUCT_H 10f326d5d8SSai Krishna 11*370c2374SSai Krishna /* 12*370c2374SSai Krishna * CN20k RVU PF MBOX Interrupt Vector Enumeration 13*370c2374SSai Krishna * 14*370c2374SSai Krishna * Vectors 0 - 3 are compatible with pre cn20k and hence 15*370c2374SSai Krishna * existing macros are being reused. 16*370c2374SSai Krishna */ 17*370c2374SSai Krishna enum rvu_mbox_pf_int_vec_e { 18*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_VFPF_MBOX0 = 0x4, 19*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_VFPF_MBOX1 = 0x5, 20*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0 = 0x6, 21*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1 = 0x7, 22*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_AFPF_MBOX = 0x8, 23*370c2374SSai Krishna RVU_MBOX_PF_INT_VEC_CNT = 0x9, 24*370c2374SSai Krishna }; 25*370c2374SSai Krishna 26f326d5d8SSai Krishna /* RVU Admin function Interrupt Vector Enumeration */ 27f326d5d8SSai Krishna enum rvu_af_cn20k_int_vec_e { 28f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_POISON = 0x0, 29f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFFLR0 = 0x1, 30f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFFLR1 = 0x2, 31f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFME0 = 0x3, 32f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFME1 = 0x4, 33f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_GEN = 0x5, 34f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFAF_MBOX0 = 0x6, 35f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFAF_MBOX1 = 0x7, 36f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFAF1_MBOX0 = 0x8, 37f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_PFAF1_MBOX1 = 0x9, 38f326d5d8SSai Krishna RVU_AF_CN20K_INT_VEC_CNT = 0xa, 39f326d5d8SSai Krishna }; 40f326d5d8SSai Krishna #endif 41