1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __CGX_FW_INTF_H__ 12 #define __CGX_FW_INTF_H__ 13 14 #include <linux/bitops.h> 15 #include <linux/bitfield.h> 16 17 #define CGX_FIRMWARE_MAJOR_VER 1 18 #define CGX_FIRMWARE_MINOR_VER 0 19 20 #define CGX_EVENT_ACK 1UL 21 22 /* CGX error types. set for cmd response status as CGX_STAT_FAIL */ 23 enum cgx_error_type { 24 CGX_ERR_NONE, 25 CGX_ERR_LMAC_NOT_ENABLED, 26 CGX_ERR_LMAC_MODE_INVALID, 27 CGX_ERR_REQUEST_ID_INVALID, 28 CGX_ERR_PREV_ACK_NOT_CLEAR, 29 CGX_ERR_PHY_LINK_DOWN, 30 CGX_ERR_PCS_RESET_FAIL, 31 CGX_ERR_AN_CPT_FAIL, 32 CGX_ERR_TX_NOT_IDLE, 33 CGX_ERR_RX_NOT_IDLE, 34 CGX_ERR_SPUX_BR_BLKLOCK_FAIL, 35 CGX_ERR_SPUX_RX_ALIGN_FAIL, 36 CGX_ERR_SPUX_TX_FAULT, 37 CGX_ERR_SPUX_RX_FAULT, 38 CGX_ERR_SPUX_RESET_FAIL, 39 CGX_ERR_SPUX_AN_RESET_FAIL, 40 CGX_ERR_SPUX_USX_AN_RESET_FAIL, 41 CGX_ERR_SMUX_RX_LINK_NOT_OK, 42 CGX_ERR_PCS_RECV_LINK_FAIL, 43 CGX_ERR_TRAINING_FAIL, 44 CGX_ERR_RX_EQU_FAIL, 45 CGX_ERR_SPUX_BER_FAIL, 46 CGX_ERR_SPUX_RSFEC_ALGN_FAIL, 47 CGX_ERR_SPUX_MARKER_LOCK_FAIL, 48 CGX_ERR_SET_FEC_INVALID, 49 CGX_ERR_SET_FEC_FAIL, 50 CGX_ERR_MODULE_INVALID, 51 CGX_ERR_MODULE_NOT_PRESENT, 52 CGX_ERR_SPEED_CHANGE_INVALID, 53 }; 54 55 /* LINK speed types */ 56 enum cgx_link_speed { 57 CGX_LINK_NONE, 58 CGX_LINK_10M, 59 CGX_LINK_100M, 60 CGX_LINK_1G, 61 CGX_LINK_2HG, 62 CGX_LINK_5G, 63 CGX_LINK_10G, 64 CGX_LINK_20G, 65 CGX_LINK_25G, 66 CGX_LINK_40G, 67 CGX_LINK_50G, 68 CGX_LINK_80G, 69 CGX_LINK_100G, 70 CGX_LINK_SPEED_MAX, 71 }; 72 73 enum CGX_MODE_ { 74 CGX_MODE_SGMII, 75 CGX_MODE_1000_BASEX, 76 CGX_MODE_QSGMII, 77 CGX_MODE_10G_C2C, 78 CGX_MODE_10G_C2M, 79 CGX_MODE_10G_KR, 80 CGX_MODE_20G_C2C, 81 CGX_MODE_25G_C2C, 82 CGX_MODE_25G_C2M, 83 CGX_MODE_25G_2_C2C, 84 CGX_MODE_25G_CR, 85 CGX_MODE_25G_KR, 86 CGX_MODE_40G_C2C, 87 CGX_MODE_40G_C2M, 88 CGX_MODE_40G_CR4, 89 CGX_MODE_40G_KR4, 90 CGX_MODE_40GAUI_C2C, 91 CGX_MODE_50G_C2C, 92 CGX_MODE_50G_C2M, 93 CGX_MODE_50G_4_C2C, 94 CGX_MODE_50G_CR, 95 CGX_MODE_50G_KR, 96 CGX_MODE_80GAUI_C2C, 97 CGX_MODE_100G_C2C, 98 CGX_MODE_100G_C2M, 99 CGX_MODE_100G_CR4, 100 CGX_MODE_100G_KR4, 101 CGX_MODE_MAX /* = 29 */ 102 }; 103 /* REQUEST ID types. Input to firmware */ 104 enum cgx_cmd_id { 105 CGX_CMD_NONE, 106 CGX_CMD_GET_FW_VER, 107 CGX_CMD_GET_MAC_ADDR, 108 CGX_CMD_SET_MTU, 109 CGX_CMD_GET_LINK_STS, /* optional to user */ 110 CGX_CMD_LINK_BRING_UP, 111 CGX_CMD_LINK_BRING_DOWN, 112 CGX_CMD_INTERNAL_LBK, 113 CGX_CMD_EXTERNAL_LBK, 114 CGX_CMD_HIGIG, 115 CGX_CMD_LINK_STAT_CHANGE, 116 CGX_CMD_MODE_CHANGE, /* hot plug support */ 117 CGX_CMD_INTF_SHUTDOWN, 118 CGX_CMD_GET_MKEX_PRFL_SIZE, 119 CGX_CMD_GET_MKEX_PRFL_ADDR, 120 CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */ 121 CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */ 122 CGX_CMD_SET_LINK_MODE, 123 CGX_CMD_GET_SUPPORTED_FEC, 124 CGX_CMD_SET_FEC, 125 CGX_CMD_GET_AN, 126 CGX_CMD_SET_AN, 127 CGX_CMD_GET_ADV_LINK_MODES, 128 CGX_CMD_GET_ADV_FEC, 129 CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */ 130 CGX_CMD_SET_PHY_MOD_TYPE, 131 CGX_CMD_PRBS, 132 CGX_CMD_DISPLAY_EYE, 133 CGX_CMD_GET_PHY_FEC_STATS, 134 }; 135 136 /* async event ids */ 137 enum cgx_evt_id { 138 CGX_EVT_NONE, 139 CGX_EVT_LINK_CHANGE, 140 }; 141 142 /* event types - cause of interrupt */ 143 enum cgx_evt_type { 144 CGX_EVT_ASYNC, 145 CGX_EVT_CMD_RESP 146 }; 147 148 enum cgx_stat { 149 CGX_STAT_SUCCESS, 150 CGX_STAT_FAIL 151 }; 152 153 enum cgx_cmd_own { 154 CGX_CMD_OWN_NS, 155 CGX_CMD_OWN_FIRMWARE, 156 }; 157 158 /* m - bit mask 159 * y - value to be written in the bitrange 160 * x - input value whose bitrange to be modified 161 */ 162 #define FIELD_SET(m, y, x) \ 163 (((x) & ~(m)) | \ 164 FIELD_PREP((m), (y))) 165 166 /* scratchx(0) CSR used for ATF->non-secure SW communication. 167 * This acts as the status register 168 * Provides details on command ack/status, command response, error details 169 */ 170 #define EVTREG_ACK BIT_ULL(0) 171 #define EVTREG_EVT_TYPE BIT_ULL(1) 172 #define EVTREG_STAT BIT_ULL(2) 173 #define EVTREG_ID GENMASK_ULL(8, 3) 174 175 /* Response to command IDs with command status as CGX_STAT_FAIL 176 * 177 * Not applicable for commands : 178 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE 179 */ 180 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9) 181 182 /* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as 183 * CGX_STAT_SUCCESS 184 */ 185 #define RESP_MAJOR_VER GENMASK_ULL(12, 9) 186 #define RESP_MINOR_VER GENMASK_ULL(16, 13) 187 188 /* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as 189 * CGX_STAT_SUCCESS 190 */ 191 #define RESP_MAC_ADDR GENMASK_ULL(56, 9) 192 193 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as 194 * CGX_STAT_SUCCESS 195 */ 196 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9) 197 198 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as 199 * CGX_STAT_SUCCESS 200 */ 201 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9) 202 203 /* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as 204 * CGX_STAT_SUCCESS 205 */ 206 #define RESP_FWD_BASE GENMASK_ULL(56, 9) 207 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28) 208 209 /* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE 210 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS 211 * 212 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed 213 * when processing link up/down/change command. 214 * Both err_type and current link status will be updated 215 * 216 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current 217 * link status will be updated 218 */ 219 struct cgx_lnk_sts { 220 uint64_t reserved1:9; 221 uint64_t link_up:1; 222 uint64_t full_duplex:1; 223 uint64_t speed:4; /* cgx_link_speed */ 224 uint64_t err_type:10; 225 uint64_t an:1; /* AN supported or not */ 226 uint64_t fec:2; /* FEC type if enabled, if not 0 */ 227 uint64_t port:8; 228 uint64_t reserved2:28; 229 }; 230 231 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9) 232 #define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10) 233 #define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11) 234 #define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15) 235 #define RESP_LINKSTAT_AN GENMASK_ULL(25, 25) 236 #define RESP_LINKSTAT_FEC GENMASK_ULL(27, 26) 237 #define RESP_LINKSTAT_PORT GENMASK_ULL(35, 28) 238 239 /* scratchx(1) CSR used for non-secure SW->ATF communication 240 * This CSR acts as a command register 241 */ 242 #define CMDREG_OWN BIT_ULL(0) 243 #define CMDREG_ID GENMASK_ULL(7, 2) 244 245 /* Any command using enable/disable as an argument need 246 * to set this bitfield. 247 * Ex: Loopback, HiGig... 248 */ 249 #define CMDREG_ENABLE BIT_ULL(8) 250 251 /* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */ 252 #define CMDMTU_SIZE GENMASK_ULL(23, 8) 253 254 /* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */ 255 #define CMDLINKCHANGE_LINKUP BIT_ULL(8) 256 #define CMDLINKCHANGE_FULLDPLX BIT_ULL(9) 257 #define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10) 258 259 #define CMDSETFEC GENMASK_ULL(9, 8) 260 /* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */ 261 #define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8) 262 #define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12) 263 #define CMDMODECHANGE_AN GENMASK_ULL(13, 13) 264 #define CMDMODECHANGE_PORT GENMASK_ULL(21, 14) 265 #define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22) 266 267 #endif /* __CGX_FW_INTF_H__ */ 268