xref: /linux/drivers/net/ethernet/marvell/octeontx2/af/cgx.h (revision 4ab5a5d2a4a2289c2af07accbec7170ca5671f41)
1 /* SPDX-License-Identifier: GPL-2.0
2  * Marvell OcteonTx2 CGX driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef CGX_H
12 #define CGX_H
13 
14 #include "mbox.h"
15 #include "cgx_fw_if.h"
16 
17  /* PCI device IDs */
18 #define	PCI_DEVID_OCTEONTX2_CGX		0xA059
19 
20 /* PCI BAR nos */
21 #define PCI_CFG_REG_BAR_NUM		0
22 
23 #define MAX_CGX				3
24 #define MAX_LMAC_PER_CGX		4
25 #define CGX_OFFSET(x)			((x) * MAX_LMAC_PER_CGX)
26 
27 /* Registers */
28 #define CGXX_CMRX_CFG			0x00
29 #define  CMR_EN					BIT_ULL(55)
30 #define  DATA_PKT_TX_EN				BIT_ULL(53)
31 #define  DATA_PKT_RX_EN				BIT_ULL(54)
32 #define  CGX_LMAC_TYPE_SHIFT			40
33 #define  CGX_LMAC_TYPE_MASK			0xF
34 #define CGXX_CMRX_INT			0x040
35 #define  FW_CGX_INT				BIT_ULL(1)
36 #define CGXX_CMRX_INT_ENA_W1S		0x058
37 #define CGXX_CMRX_RX_ID_MAP		0x060
38 #define CGXX_CMRX_RX_STAT0		0x070
39 #define CGXX_CMRX_RX_LMACS		0x128
40 #define CGXX_CMRX_RX_DMAC_CTL0		0x1F8
41 #define  CGX_DMAC_CTL0_CAM_ENABLE		BIT_ULL(3)
42 #define  CGX_DMAC_CAM_ACCEPT			BIT_ULL(3)
43 #define  CGX_DMAC_MCAST_MODE			BIT_ULL(1)
44 #define  CGX_DMAC_BCAST_MODE			BIT_ULL(0)
45 #define CGXX_CMRX_RX_DMAC_CAM0		0x200
46 #define  CGX_DMAC_CAM_ADDR_ENABLE		BIT_ULL(48)
47 #define CGXX_CMRX_RX_DMAC_CAM1		0x400
48 #define CGX_RX_DMAC_ADR_MASK			GENMASK_ULL(47, 0)
49 #define CGXX_CMRX_TX_STAT0		0x700
50 #define CGXX_SCRATCH0_REG		0x1050
51 #define CGXX_SCRATCH1_REG		0x1058
52 #define CGX_CONST			0x2000
53 #define CGXX_SPUX_CONTROL1		0x10000
54 #define  CGXX_SPUX_CONTROL1_LBK			BIT_ULL(14)
55 #define CGXX_GMP_PCS_MRX_CTL		0x30000
56 #define  CGXX_GMP_PCS_MRX_CTL_LBK		BIT_ULL(14)
57 
58 #define CGX_COMMAND_REG			CGXX_SCRATCH1_REG
59 #define CGX_EVENT_REG			CGXX_SCRATCH0_REG
60 #define CGX_CMD_TIMEOUT			2200 /* msecs */
61 
62 #define CGX_NVEC			37
63 #define CGX_LMAC_FWI			0
64 
65 enum LMAC_TYPE {
66 	LMAC_MODE_SGMII		= 0,
67 	LMAC_MODE_XAUI		= 1,
68 	LMAC_MODE_RXAUI		= 2,
69 	LMAC_MODE_10G_R		= 3,
70 	LMAC_MODE_40G_R		= 4,
71 	LMAC_MODE_QSGMII	= 6,
72 	LMAC_MODE_25G_R		= 7,
73 	LMAC_MODE_50G_R		= 8,
74 	LMAC_MODE_100G_R	= 9,
75 	LMAC_MODE_USXGMII	= 10,
76 	LMAC_MODE_MAX,
77 };
78 
79 struct cgx_link_event {
80 	struct cgx_link_user_info link_uinfo;
81 	u8 cgx_id;
82 	u8 lmac_id;
83 };
84 
85 /**
86  * struct cgx_event_cb
87  * @notify_link_chg:	callback for link change notification
88  * @data:	data passed to callback function
89  */
90 struct cgx_event_cb {
91 	int (*notify_link_chg)(struct cgx_link_event *event, void *data);
92 	void *data;
93 };
94 
95 extern struct pci_driver cgx_driver;
96 
97 int cgx_get_cgx_cnt(void);
98 int cgx_get_lmac_cnt(void *cgxd);
99 void *cgx_get_pdata(int cgx_id);
100 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
101 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
102 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
103 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
104 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
105 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
106 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
107 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
108 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
109 int cgx_get_link_info(void *cgxd, int lmac_id,
110 		      struct cgx_link_user_info *linfo);
111 #endif /* CGX_H */
112