1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "cgx.h" 21 #include "rvu.h" 22 #include "lmac_common.h" 23 24 #define DRV_NAME "Marvell-CGX/RPM" 25 #define DRV_STRING "Marvell CGX/RPM Driver" 26 27 #define CGX_RX_STAT_GLOBAL_INDEX 9 28 29 static LIST_HEAD(cgx_list); 30 31 /* Convert firmware speed encoding to user format(Mbps) */ 32 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = { 33 [CGX_LINK_NONE] = 0, 34 [CGX_LINK_10M] = 10, 35 [CGX_LINK_100M] = 100, 36 [CGX_LINK_1G] = 1000, 37 [CGX_LINK_2HG] = 2500, 38 [CGX_LINK_5G] = 5000, 39 [CGX_LINK_10G] = 10000, 40 [CGX_LINK_20G] = 20000, 41 [CGX_LINK_25G] = 25000, 42 [CGX_LINK_40G] = 40000, 43 [CGX_LINK_50G] = 50000, 44 [CGX_LINK_80G] = 80000, 45 [CGX_LINK_100G] = 100000, 46 }; 47 48 /* Convert firmware lmac type encoding to string */ 49 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = { 50 [LMAC_MODE_SGMII] = "SGMII", 51 [LMAC_MODE_XAUI] = "XAUI", 52 [LMAC_MODE_RXAUI] = "RXAUI", 53 [LMAC_MODE_10G_R] = "10G_R", 54 [LMAC_MODE_40G_R] = "40G_R", 55 [LMAC_MODE_QSGMII] = "QSGMII", 56 [LMAC_MODE_25G_R] = "25G_R", 57 [LMAC_MODE_50G_R] = "50G_R", 58 [LMAC_MODE_100G_R] = "100G_R", 59 [LMAC_MODE_USXGMII] = "USXGMII", 60 [LMAC_MODE_USGMII] = "USGMII", 61 }; 62 63 /* CGX PHY management internal APIs */ 64 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 65 66 /* Supported devices */ 67 static const struct pci_device_id cgx_id_table[] = { 68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 70 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) }, 71 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 72 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) }, 73 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 74 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) }, 75 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 76 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) }, 77 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 78 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) }, 79 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 80 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) }, 81 { 0, } /* end of table */ 82 }; 83 84 MODULE_DEVICE_TABLE(pci, cgx_id_table); 85 86 static bool is_dev_rpm(void *cgxd) 87 { 88 struct cgx *cgx = cgxd; 89 90 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || 91 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); 92 } 93 94 bool is_lmac_valid(struct cgx *cgx, int lmac_id) 95 { 96 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) 97 return false; 98 return test_bit(lmac_id, &cgx->lmac_bmap); 99 } 100 101 /* Helper function to get sequential index 102 * given the enabled LMAC of a CGX 103 */ 104 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id) 105 { 106 int tmp, id = 0; 107 108 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 109 if (tmp == lmac_id) 110 break; 111 id++; 112 } 113 114 return id; 115 } 116 117 struct mac_ops *get_mac_ops(void *cgxd) 118 { 119 if (!cgxd) 120 return cgxd; 121 122 return ((struct cgx *)cgxd)->mac_ops; 123 } 124 125 u32 cgx_get_fifo_len(void *cgxd) 126 { 127 return ((struct cgx *)cgxd)->fifo_len; 128 } 129 130 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 131 { 132 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 133 offset); 134 } 135 136 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 137 { 138 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 139 offset); 140 } 141 142 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 143 { 144 if (!cgx || lmac_id >= cgx->max_lmac_per_mac) 145 return NULL; 146 147 return cgx->lmac_idmap[lmac_id]; 148 } 149 150 int cgx_get_cgxcnt_max(void) 151 { 152 struct cgx *cgx_dev; 153 int idmax = -ENODEV; 154 155 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 156 if (cgx_dev->cgx_id > idmax) 157 idmax = cgx_dev->cgx_id; 158 159 if (idmax < 0) 160 return 0; 161 162 return idmax + 1; 163 } 164 165 int cgx_get_lmac_cnt(void *cgxd) 166 { 167 struct cgx *cgx = cgxd; 168 169 if (!cgx) 170 return -ENODEV; 171 172 return cgx->lmac_count; 173 } 174 175 void *cgx_get_pdata(int cgx_id) 176 { 177 struct cgx *cgx_dev; 178 179 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 180 if (cgx_dev->cgx_id == cgx_id) 181 return cgx_dev; 182 } 183 return NULL; 184 } 185 186 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) 187 { 188 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 189 190 /* Software must not access disabled LMAC registers */ 191 if (!is_lmac_valid(cgx_dev, lmac_id)) 192 return; 193 cgx_write(cgx_dev, lmac_id, offset, val); 194 } 195 196 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) 197 { 198 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 199 200 /* Software must not access disabled LMAC registers */ 201 if (!is_lmac_valid(cgx_dev, lmac_id)) 202 return 0; 203 204 return cgx_read(cgx_dev, lmac_id, offset); 205 } 206 207 int cgx_get_cgxid(void *cgxd) 208 { 209 struct cgx *cgx = cgxd; 210 211 if (!cgx) 212 return -EINVAL; 213 214 return cgx->cgx_id; 215 } 216 217 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id) 218 { 219 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 220 u64 cfg; 221 222 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); 223 224 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; 225 } 226 227 static u8 cgx_get_nix_resetbit(struct cgx *cgx) 228 { 229 int first_lmac; 230 u8 p2x; 231 232 /* non 98XX silicons supports only NIX0 block */ 233 if (cgx->pdev->subsystem_device != PCI_SUBSYS_DEVID_98XX) 234 return CGX_NIX0_RESET; 235 236 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 237 p2x = cgx_lmac_get_p2x(cgx->cgx_id, first_lmac); 238 239 if (p2x == CMR_P2X_SEL_NIX1) 240 return CGX_NIX1_RESET; 241 else 242 return CGX_NIX0_RESET; 243 } 244 245 /* Ensure the required lock for event queue(where asynchronous events are 246 * posted) is acquired before calling this API. Else an asynchronous event(with 247 * latest link status) can reach the destination before this function returns 248 * and could make the link status appear wrong. 249 */ 250 int cgx_get_link_info(void *cgxd, int lmac_id, 251 struct cgx_link_user_info *linfo) 252 { 253 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 254 255 if (!lmac) 256 return -ENODEV; 257 258 *linfo = lmac->link_info; 259 return 0; 260 } 261 262 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 263 { 264 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 265 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 266 struct mac_ops *mac_ops; 267 int index, id; 268 u64 cfg; 269 270 if (!lmac) 271 return -ENODEV; 272 273 /* access mac_ops to know csr_offset */ 274 mac_ops = cgx_dev->mac_ops; 275 276 /* copy 6bytes from macaddr */ 277 /* memcpy(&cfg, mac_addr, 6); */ 278 279 cfg = ether_addr_to_u64(mac_addr); 280 281 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 282 283 index = id * lmac->mac_to_index_bmap.max; 284 285 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 286 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 287 288 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 289 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | 290 CGX_DMAC_MCAST_MODE); 291 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 292 293 return 0; 294 } 295 296 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id) 297 { 298 struct mac_ops *mac_ops; 299 struct cgx *cgx = cgxd; 300 301 if (!cgxd || !is_lmac_valid(cgxd, lmac_id)) 302 return 0; 303 304 cgx = cgxd; 305 /* Get mac_ops to know csr offset */ 306 mac_ops = cgx->mac_ops; 307 308 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 309 } 310 311 u64 cgx_read_dmac_entry(void *cgxd, int index) 312 { 313 struct mac_ops *mac_ops; 314 struct cgx *cgx; 315 316 if (!cgxd) 317 return 0; 318 319 cgx = cgxd; 320 mac_ops = cgx->mac_ops; 321 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8))); 322 } 323 324 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 325 { 326 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 327 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 328 struct mac_ops *mac_ops; 329 int index, idx; 330 u64 cfg = 0; 331 int id; 332 333 if (!lmac) 334 return -ENODEV; 335 336 mac_ops = cgx_dev->mac_ops; 337 /* Get available index where entry is to be installed */ 338 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap); 339 if (idx < 0) 340 return idx; 341 342 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 343 344 index = id * lmac->mac_to_index_bmap.max + idx; 345 346 cfg = ether_addr_to_u64(mac_addr); 347 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 348 cfg |= ((u64)lmac_id << 49); 349 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 350 351 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 352 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT); 353 354 if (is_multicast_ether_addr(mac_addr)) { 355 cfg &= ~GENMASK_ULL(2, 1); 356 cfg |= CGX_DMAC_MCAST_MODE_CAM; 357 lmac->mcast_filters_count++; 358 } else if (!lmac->mcast_filters_count) { 359 cfg |= CGX_DMAC_MCAST_MODE; 360 } 361 362 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 363 364 return idx; 365 } 366 367 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id) 368 { 369 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 370 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 371 struct mac_ops *mac_ops; 372 u8 index = 0, id; 373 u64 cfg; 374 375 if (!lmac) 376 return -ENODEV; 377 378 mac_ops = cgx_dev->mac_ops; 379 /* Restore index 0 to its default init value as done during 380 * cgx_lmac_init 381 */ 382 set_bit(0, lmac->mac_to_index_bmap.bmap); 383 384 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 385 386 index = id * lmac->mac_to_index_bmap.max + index; 387 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 388 389 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */ 390 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 391 cfg &= ~CGX_DMAC_CAM_ACCEPT; 392 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 393 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 394 395 return 0; 396 } 397 398 /* Allows caller to change macaddress associated with index 399 * in dmac filter table including index 0 reserved for 400 * interface mac address 401 */ 402 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index) 403 { 404 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 405 struct mac_ops *mac_ops; 406 struct lmac *lmac; 407 u64 cfg; 408 int id; 409 410 lmac = lmac_pdata(lmac_id, cgx_dev); 411 if (!lmac) 412 return -ENODEV; 413 414 mac_ops = cgx_dev->mac_ops; 415 /* Validate the index */ 416 if (index >= lmac->mac_to_index_bmap.max) 417 return -EINVAL; 418 419 /* ensure index is already set */ 420 if (!test_bit(index, lmac->mac_to_index_bmap.bmap)) 421 return -EINVAL; 422 423 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 424 425 index = id * lmac->mac_to_index_bmap.max + index; 426 427 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 428 cfg &= ~CGX_RX_DMAC_ADR_MASK; 429 cfg |= ether_addr_to_u64(mac_addr); 430 431 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 432 return 0; 433 } 434 435 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index) 436 { 437 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 438 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 439 struct mac_ops *mac_ops; 440 u8 mac[ETH_ALEN]; 441 u64 cfg; 442 int id; 443 444 if (!lmac) 445 return -ENODEV; 446 447 mac_ops = cgx_dev->mac_ops; 448 /* Validate the index */ 449 if (index >= lmac->mac_to_index_bmap.max) 450 return -EINVAL; 451 452 /* Skip deletion for reserved index i.e. index 0 */ 453 if (index == 0) 454 return 0; 455 456 rvu_free_rsrc(&lmac->mac_to_index_bmap, index); 457 458 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 459 460 index = id * lmac->mac_to_index_bmap.max + index; 461 462 /* Read MAC address to check whether it is ucast or mcast */ 463 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 464 465 u64_to_ether_addr(cfg, mac); 466 if (is_multicast_ether_addr(mac)) 467 lmac->mcast_filters_count--; 468 469 if (!lmac->mcast_filters_count) { 470 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 471 cfg &= ~GENMASK_ULL(2, 1); 472 cfg |= CGX_DMAC_MCAST_MODE; 473 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 474 } 475 476 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 477 478 return 0; 479 } 480 481 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id) 482 { 483 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 484 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 485 486 if (lmac) 487 return lmac->mac_to_index_bmap.max; 488 489 return 0; 490 } 491 492 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 493 { 494 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 495 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 496 struct mac_ops *mac_ops; 497 int index; 498 u64 cfg; 499 int id; 500 501 mac_ops = cgx_dev->mac_ops; 502 503 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 504 505 index = id * lmac->mac_to_index_bmap.max; 506 507 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8); 508 return cfg & CGX_RX_DMAC_ADR_MASK; 509 } 510 511 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 512 { 513 struct cgx *cgx = cgxd; 514 515 if (!is_lmac_valid(cgx, lmac_id)) 516 return -ENODEV; 517 518 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F)); 519 return 0; 520 } 521 522 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) 523 { 524 struct cgx *cgx = cgxd; 525 u64 cfg; 526 527 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 528 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 529 } 530 531 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id) 532 { 533 struct cgx *cgx = cgxd; 534 u8 num_lmacs; 535 u32 fifo_len; 536 537 fifo_len = cgx->fifo_len; 538 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx); 539 540 switch (num_lmacs) { 541 case 1: 542 return fifo_len; 543 case 2: 544 return fifo_len / 2; 545 case 3: 546 /* LMAC0 gets half of the FIFO, reset 1/4th */ 547 if (lmac_id == 0) 548 return fifo_len / 2; 549 return fifo_len / 4; 550 case 4: 551 default: 552 return fifo_len / 4; 553 } 554 return 0; 555 } 556 557 /* Configure CGX LMAC in internal loopback mode */ 558 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 559 { 560 struct cgx *cgx = cgxd; 561 struct lmac *lmac; 562 u64 cfg; 563 564 if (!is_lmac_valid(cgx, lmac_id)) 565 return -ENODEV; 566 567 lmac = lmac_pdata(lmac_id, cgx); 568 if (lmac->lmac_type == LMAC_MODE_SGMII || 569 lmac->lmac_type == LMAC_MODE_QSGMII) { 570 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 571 if (enable) 572 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 573 else 574 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 575 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 576 } else { 577 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 578 if (enable) 579 cfg |= CGXX_SPUX_CONTROL1_LBK; 580 else 581 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 582 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 583 } 584 return 0; 585 } 586 587 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 588 { 589 struct cgx *cgx = cgx_get_pdata(cgx_id); 590 struct lmac *lmac = lmac_pdata(lmac_id, cgx); 591 struct mac_ops *mac_ops; 592 u16 max_dmac; 593 int index, i; 594 u64 cfg = 0; 595 int id; 596 597 if (!cgx || !lmac) 598 return; 599 600 max_dmac = lmac->mac_to_index_bmap.max; 601 id = get_sequence_id_of_lmac(cgx, lmac_id); 602 603 mac_ops = cgx->mac_ops; 604 if (enable) { 605 /* Enable promiscuous mode on LMAC */ 606 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 607 cfg &= ~CGX_DMAC_CAM_ACCEPT; 608 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 609 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 610 611 for (i = 0; i < max_dmac; i++) { 612 index = id * max_dmac + i; 613 cfg = cgx_read(cgx, 0, 614 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 615 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 616 cgx_write(cgx, 0, 617 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg); 618 } 619 } else { 620 /* Disable promiscuous mode */ 621 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 622 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 623 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 624 for (i = 0; i < max_dmac; i++) { 625 index = id * max_dmac + i; 626 cfg = cgx_read(cgx, 0, 627 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 628 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) { 629 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 630 cgx_write(cgx, 0, 631 (CGXX_CMRX_RX_DMAC_CAM0 + 632 index * 0x8), 633 cfg); 634 } 635 } 636 } 637 } 638 639 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, 640 u8 *tx_pause, u8 *rx_pause) 641 { 642 struct cgx *cgx = cgxd; 643 u64 cfg; 644 645 if (is_dev_rpm(cgx)) 646 return 0; 647 648 if (!is_lmac_valid(cgx, lmac_id)) 649 return -ENODEV; 650 651 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 652 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK); 653 654 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 655 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV); 656 return 0; 657 } 658 659 /* Enable or disable forwarding received pause frames to Tx block */ 660 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 661 { 662 struct cgx *cgx = cgxd; 663 u8 rx_pause, tx_pause; 664 bool is_pfc_enabled; 665 struct lmac *lmac; 666 u64 cfg; 667 668 if (!cgx) 669 return; 670 671 lmac = lmac_pdata(lmac_id, cgx); 672 if (!lmac) 673 return; 674 675 /* Pause frames are not enabled just return */ 676 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 677 return; 678 679 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause); 680 is_pfc_enabled = rx_pause ? false : true; 681 682 if (enable) { 683 if (!is_pfc_enabled) { 684 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 685 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 686 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 687 688 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 689 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 690 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 691 } else { 692 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 693 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN; 694 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 695 } 696 } else { 697 698 if (!is_pfc_enabled) { 699 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 700 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 701 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 702 703 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 704 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 705 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 706 } else { 707 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 708 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN; 709 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 710 } 711 } 712 } 713 714 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 715 { 716 struct cgx *cgx = cgxd; 717 718 if (!is_lmac_valid(cgx, lmac_id)) 719 return -ENODEV; 720 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 721 return 0; 722 } 723 724 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 725 { 726 struct cgx *cgx = cgxd; 727 728 if (!is_lmac_valid(cgx, lmac_id)) 729 return -ENODEV; 730 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 731 return 0; 732 } 733 734 u64 cgx_features_get(void *cgxd) 735 { 736 return ((struct cgx *)cgxd)->hw_features; 737 } 738 739 int cgx_stats_reset(void *cgxd, int lmac_id) 740 { 741 struct cgx *cgx = cgxd; 742 int stat_id; 743 744 if (!is_lmac_valid(cgx, lmac_id)) 745 return -ENODEV; 746 747 for (stat_id = 0 ; stat_id < CGX_RX_STATS_COUNT; stat_id++) { 748 if (stat_id >= CGX_RX_STAT_GLOBAL_INDEX) 749 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */ 750 cgx_write(cgx, 0, 751 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0); 752 else 753 cgx_write(cgx, lmac_id, 754 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0); 755 } 756 757 for (stat_id = 0 ; stat_id < CGX_TX_STATS_COUNT; stat_id++) 758 cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0); 759 760 return 0; 761 } 762 763 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) 764 { 765 if (!linfo->fec) 766 return 0; 767 768 switch (linfo->lmac_type_id) { 769 case LMAC_MODE_SGMII: 770 case LMAC_MODE_XAUI: 771 case LMAC_MODE_RXAUI: 772 case LMAC_MODE_QSGMII: 773 return 0; 774 case LMAC_MODE_10G_R: 775 case LMAC_MODE_25G_R: 776 case LMAC_MODE_100G_R: 777 case LMAC_MODE_USXGMII: 778 return 1; 779 case LMAC_MODE_40G_R: 780 return 4; 781 case LMAC_MODE_50G_R: 782 if (linfo->fec == OTX2_FEC_BASER) 783 return 2; 784 else 785 return 1; 786 default: 787 return 0; 788 } 789 } 790 791 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 792 { 793 int stats, fec_stats_count = 0; 794 int corr_reg, uncorr_reg; 795 struct cgx *cgx = cgxd; 796 797 if (!is_lmac_valid(cgx, lmac_id)) 798 return -ENODEV; 799 800 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE) 801 return 0; 802 803 fec_stats_count = 804 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); 805 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 806 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS; 807 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS; 808 } else { 809 corr_reg = CGXX_SPUX_RSFEC_CORR; 810 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR; 811 } 812 for (stats = 0; stats < fec_stats_count; stats++) { 813 rsp->fec_corr_blks += 814 cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); 815 rsp->fec_uncorr_blks += 816 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); 817 } 818 return 0; 819 } 820 821 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 822 { 823 struct cgx *cgx = cgxd; 824 u64 cfg; 825 826 if (!is_lmac_valid(cgx, lmac_id)) 827 return -ENODEV; 828 829 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 830 if (enable) 831 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN; 832 else 833 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN); 834 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 835 return 0; 836 } 837 838 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 839 { 840 struct cgx *cgx = cgxd; 841 u64 cfg, last; 842 843 if (!is_lmac_valid(cgx, lmac_id)) 844 return -ENODEV; 845 846 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 847 last = cfg; 848 if (enable) 849 cfg |= DATA_PKT_TX_EN; 850 else 851 cfg &= ~DATA_PKT_TX_EN; 852 853 if (cfg != last) 854 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 855 return !!(last & DATA_PKT_TX_EN); 856 } 857 858 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, 859 u8 tx_pause, u8 rx_pause) 860 { 861 struct cgx *cgx = cgxd; 862 u64 cfg; 863 864 if (is_dev_rpm(cgx)) 865 return 0; 866 867 if (!is_lmac_valid(cgx, lmac_id)) 868 return -ENODEV; 869 870 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 871 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 872 cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0; 873 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 874 875 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 876 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 877 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0; 878 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 879 880 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 881 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 882 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0; 883 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 884 885 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 886 if (tx_pause) { 887 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id); 888 } else { 889 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 890 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 891 } 892 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 893 return 0; 894 } 895 896 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 897 { 898 struct cgx *cgx = cgxd; 899 u64 cfg; 900 901 if (!is_lmac_valid(cgx, lmac_id)) 902 return; 903 904 if (enable) { 905 /* Set pause time and interval */ 906 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME, 907 DEFAULT_PAUSE_TIME); 908 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); 909 cfg &= ~0xFFFFULL; 910 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, 911 cfg | (DEFAULT_PAUSE_TIME / 2)); 912 913 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, 914 DEFAULT_PAUSE_TIME); 915 916 cfg = cgx_read(cgx, lmac_id, 917 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); 918 cfg &= ~0xFFFFULL; 919 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, 920 cfg | (DEFAULT_PAUSE_TIME / 2)); 921 } 922 923 /* ALL pause frames received are completely ignored */ 924 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 925 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 926 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 927 928 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 929 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 930 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 931 932 /* Disable pause frames transmission */ 933 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 934 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 935 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 936 937 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 938 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 939 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 940 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 941 942 /* Disable all PFC classes by default */ 943 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 944 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 945 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 946 } 947 948 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 949 int pfvf_idx) 950 { 951 struct cgx *cgx = cgxd; 952 struct lmac *lmac; 953 954 lmac = lmac_pdata(lmac_id, cgx); 955 if (!lmac) 956 return -ENODEV; 957 958 if (!rx_pause) 959 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 960 else 961 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 962 963 if (!tx_pause) 964 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 965 else 966 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 967 968 /* check if other pfvfs are using flow control */ 969 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) { 970 dev_warn(&cgx->pdev->dev, 971 "Receive Flow control disable not permitted as its used by other PFVFs\n"); 972 return -EPERM; 973 } 974 975 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) { 976 dev_warn(&cgx->pdev->dev, 977 "Transmit Flow control disable not permitted as its used by other PFVFs\n"); 978 return -EPERM; 979 } 980 981 return 0; 982 } 983 984 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, 985 u8 rx_pause, u16 pfc_en) 986 { 987 struct cgx *cgx = cgxd; 988 u64 cfg; 989 990 if (!is_lmac_valid(cgx, lmac_id)) 991 return -ENODEV; 992 993 /* Return as no traffic classes are requested */ 994 if (tx_pause && !pfc_en) 995 return 0; 996 997 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 998 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg); 999 1000 if (rx_pause) { 1001 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN | 1002 CGXX_SMUX_CBFC_CTL_BCK_EN | 1003 CGXX_SMUX_CBFC_CTL_DRP_EN); 1004 } else { 1005 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN | 1006 CGXX_SMUX_CBFC_CTL_BCK_EN | 1007 CGXX_SMUX_CBFC_CTL_DRP_EN); 1008 } 1009 1010 if (tx_pause) { 1011 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN; 1012 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); 1013 } else { 1014 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN; 1015 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 1016 } 1017 1018 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 1019 1020 /* Write source MAC address which will be filled into PFC packet */ 1021 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id); 1022 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg); 1023 1024 return 0; 1025 } 1026 1027 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, 1028 u8 *rx_pause) 1029 { 1030 struct cgx *cgx = cgxd; 1031 u64 cfg; 1032 1033 if (!is_lmac_valid(cgx, lmac_id)) 1034 return -ENODEV; 1035 1036 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 1037 1038 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN); 1039 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN); 1040 1041 return 0; 1042 } 1043 1044 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 1045 { 1046 struct cgx *cgx = cgxd; 1047 u64 cfg; 1048 1049 if (!cgx) 1050 return; 1051 1052 if (enable) { 1053 /* Enable inbound PTP timestamping */ 1054 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 1055 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 1056 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 1057 1058 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1059 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1060 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1061 } else { 1062 /* Disable inbound PTP stamping */ 1063 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 1064 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 1065 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 1066 1067 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1068 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1069 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1070 } 1071 } 1072 1073 /* CGX Firmware interface low level support */ 1074 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 1075 { 1076 struct cgx *cgx = lmac->cgx; 1077 struct device *dev; 1078 int err = 0; 1079 u64 cmd; 1080 1081 /* Ensure no other command is in progress */ 1082 err = mutex_lock_interruptible(&lmac->cmd_lock); 1083 if (err) 1084 return err; 1085 1086 /* Ensure command register is free */ 1087 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 1088 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 1089 err = -EBUSY; 1090 goto unlock; 1091 } 1092 1093 /* Update ownership in command request */ 1094 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 1095 1096 /* Mark this lmac as pending, before we start */ 1097 lmac->cmd_pend = true; 1098 1099 /* Start command in hardware */ 1100 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 1101 1102 /* Ensure command is completed without errors */ 1103 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 1104 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 1105 dev = &cgx->pdev->dev; 1106 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n", 1107 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req)); 1108 err = LMAC_AF_ERR_CMD_TIMEOUT; 1109 goto unlock; 1110 } 1111 1112 /* we have a valid command response */ 1113 smp_rmb(); /* Ensure the latest updates are visible */ 1114 *resp = lmac->resp; 1115 1116 unlock: 1117 mutex_unlock(&lmac->cmd_lock); 1118 1119 return err; 1120 } 1121 1122 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) 1123 { 1124 struct lmac *lmac; 1125 int err; 1126 1127 lmac = lmac_pdata(lmac_id, cgx); 1128 if (!lmac) 1129 return -ENODEV; 1130 1131 err = cgx_fwi_cmd_send(req, resp, lmac); 1132 1133 /* Check for valid response */ 1134 if (!err) { 1135 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 1136 return -EIO; 1137 else 1138 return 0; 1139 } 1140 1141 return err; 1142 } 1143 1144 static int cgx_link_usertable_index_map(int speed) 1145 { 1146 switch (speed) { 1147 case SPEED_10: 1148 return CGX_LINK_10M; 1149 case SPEED_100: 1150 return CGX_LINK_100M; 1151 case SPEED_1000: 1152 return CGX_LINK_1G; 1153 case SPEED_2500: 1154 return CGX_LINK_2HG; 1155 case SPEED_5000: 1156 return CGX_LINK_5G; 1157 case SPEED_10000: 1158 return CGX_LINK_10G; 1159 case SPEED_20000: 1160 return CGX_LINK_20G; 1161 case SPEED_25000: 1162 return CGX_LINK_25G; 1163 case SPEED_40000: 1164 return CGX_LINK_40G; 1165 case SPEED_50000: 1166 return CGX_LINK_50G; 1167 case 80000: 1168 return CGX_LINK_80G; 1169 case SPEED_100000: 1170 return CGX_LINK_100G; 1171 case SPEED_UNKNOWN: 1172 return CGX_LINK_NONE; 1173 } 1174 return CGX_LINK_NONE; 1175 } 1176 1177 static void set_mod_args(struct cgx_set_link_mode_args *args, 1178 u32 speed, u8 duplex, u8 autoneg, u64 mode) 1179 { 1180 /* Fill default values incase of user did not pass 1181 * valid parameters 1182 */ 1183 if (args->duplex == DUPLEX_UNKNOWN) 1184 args->duplex = duplex; 1185 if (args->speed == SPEED_UNKNOWN) 1186 args->speed = speed; 1187 if (args->an == AUTONEG_UNKNOWN) 1188 args->an = autoneg; 1189 args->mode = mode; 1190 args->ports = 0; 1191 } 1192 1193 static void otx2_map_ethtool_link_modes(u64 bitmask, 1194 struct cgx_set_link_mode_args *args) 1195 { 1196 switch (bitmask) { 1197 case ETHTOOL_LINK_MODE_10baseT_Half_BIT: 1198 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1199 break; 1200 case ETHTOOL_LINK_MODE_10baseT_Full_BIT: 1201 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1202 break; 1203 case ETHTOOL_LINK_MODE_100baseT_Half_BIT: 1204 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1205 break; 1206 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1207 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1208 break; 1209 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: 1210 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1211 break; 1212 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1213 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1214 break; 1215 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT: 1216 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX)); 1217 break; 1218 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT: 1219 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII)); 1220 break; 1221 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT: 1222 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C)); 1223 break; 1224 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT: 1225 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M)); 1226 break; 1227 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT: 1228 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR)); 1229 break; 1230 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 1231 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C)); 1232 break; 1233 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 1234 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR)); 1235 break; 1236 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 1237 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR)); 1238 break; 1239 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 1240 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C)); 1241 break; 1242 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 1243 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M)); 1244 break; 1245 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 1246 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4)); 1247 break; 1248 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 1249 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4)); 1250 break; 1251 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 1252 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C)); 1253 break; 1254 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 1255 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M)); 1256 break; 1257 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 1258 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR)); 1259 break; 1260 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 1261 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR)); 1262 break; 1263 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 1264 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C)); 1265 break; 1266 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 1267 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M)); 1268 break; 1269 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 1270 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4)); 1271 break; 1272 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 1273 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4)); 1274 break; 1275 default: 1276 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX)); 1277 break; 1278 } 1279 } 1280 1281 static inline void link_status_user_format(u64 lstat, 1282 struct cgx_link_user_info *linfo, 1283 struct cgx *cgx, u8 lmac_id) 1284 { 1285 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 1286 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 1287 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 1288 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat); 1289 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat); 1290 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat); 1291 1292 if (linfo->lmac_type_id >= LMAC_MODE_MAX) { 1293 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d", 1294 linfo->lmac_type_id, cgx->cgx_id, lmac_id); 1295 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type)); 1296 return; 1297 } 1298 1299 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id], 1300 sizeof(linfo->lmac_type)); 1301 } 1302 1303 /* Hardware event handlers */ 1304 static inline void cgx_link_change_handler(u64 lstat, 1305 struct lmac *lmac) 1306 { 1307 struct cgx_link_user_info *linfo; 1308 struct cgx *cgx = lmac->cgx; 1309 struct cgx_link_event event; 1310 struct device *dev; 1311 int err_type; 1312 1313 dev = &cgx->pdev->dev; 1314 1315 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 1316 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 1317 1318 event.cgx_id = cgx->cgx_id; 1319 event.lmac_id = lmac->lmac_id; 1320 1321 /* update the local copy of link status */ 1322 lmac->link_info = event.link_uinfo; 1323 linfo = &lmac->link_info; 1324 1325 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID) 1326 return; 1327 1328 /* Ensure callback doesn't get unregistered until we finish it */ 1329 spin_lock(&lmac->event_cb_lock); 1330 1331 if (!lmac->event_cb.notify_link_chg) { 1332 dev_dbg(dev, "cgx port %d:%d Link change handler null", 1333 cgx->cgx_id, lmac->lmac_id); 1334 if (err_type != CGX_ERR_NONE) { 1335 dev_err(dev, "cgx port %d:%d Link error %d\n", 1336 cgx->cgx_id, lmac->lmac_id, err_type); 1337 } 1338 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 1339 cgx->cgx_id, lmac->lmac_id, 1340 linfo->link_up ? "UP" : "DOWN", linfo->speed); 1341 goto err; 1342 } 1343 1344 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 1345 dev_err(dev, "event notification failure\n"); 1346 err: 1347 spin_unlock(&lmac->event_cb_lock); 1348 } 1349 1350 static inline bool cgx_cmdresp_is_linkevent(u64 event) 1351 { 1352 u8 id; 1353 1354 id = FIELD_GET(EVTREG_ID, event); 1355 if (id == CGX_CMD_LINK_BRING_UP || 1356 id == CGX_CMD_LINK_BRING_DOWN || 1357 id == CGX_CMD_MODE_CHANGE) 1358 return true; 1359 else 1360 return false; 1361 } 1362 1363 static inline bool cgx_event_is_linkevent(u64 event) 1364 { 1365 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 1366 return true; 1367 else 1368 return false; 1369 } 1370 1371 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 1372 { 1373 u64 event, offset, clear_bit; 1374 struct lmac *lmac = data; 1375 struct cgx *cgx; 1376 1377 cgx = lmac->cgx; 1378 1379 /* Clear SW_INT for RPM and CMR_INT for CGX */ 1380 offset = cgx->mac_ops->int_register; 1381 clear_bit = cgx->mac_ops->int_ena_bit; 1382 1383 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 1384 1385 if (!FIELD_GET(EVTREG_ACK, event)) 1386 return IRQ_NONE; 1387 1388 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 1389 case CGX_EVT_CMD_RESP: 1390 /* Copy the response. Since only one command is active at a 1391 * time, there is no way a response can get overwritten 1392 */ 1393 lmac->resp = event; 1394 /* Ensure response is updated before thread context starts */ 1395 smp_wmb(); 1396 1397 /* There wont be separate events for link change initiated from 1398 * software; Hence report the command responses as events 1399 */ 1400 if (cgx_cmdresp_is_linkevent(event)) 1401 cgx_link_change_handler(event, lmac); 1402 1403 /* Release thread waiting for completion */ 1404 lmac->cmd_pend = false; 1405 wake_up(&lmac->wq_cmd_cmplt); 1406 break; 1407 case CGX_EVT_ASYNC: 1408 if (cgx_event_is_linkevent(event)) 1409 cgx_link_change_handler(event, lmac); 1410 break; 1411 } 1412 1413 /* Any new event or command response will be posted by firmware 1414 * only after the current status is acked. 1415 * Ack the interrupt register as well. 1416 */ 1417 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 1418 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); 1419 1420 return IRQ_HANDLED; 1421 } 1422 1423 /* APIs for PHY management using CGX firmware interface */ 1424 1425 /* callback registration for hardware events like link change */ 1426 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 1427 { 1428 struct cgx *cgx = cgxd; 1429 struct lmac *lmac; 1430 1431 lmac = lmac_pdata(lmac_id, cgx); 1432 if (!lmac) 1433 return -ENODEV; 1434 1435 lmac->event_cb = *cb; 1436 1437 return 0; 1438 } 1439 1440 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 1441 { 1442 struct lmac *lmac; 1443 unsigned long flags; 1444 struct cgx *cgx = cgxd; 1445 1446 lmac = lmac_pdata(lmac_id, cgx); 1447 if (!lmac) 1448 return -ENODEV; 1449 1450 spin_lock_irqsave(&lmac->event_cb_lock, flags); 1451 lmac->event_cb.notify_link_chg = NULL; 1452 lmac->event_cb.data = NULL; 1453 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 1454 1455 return 0; 1456 } 1457 1458 int cgx_get_fwdata_base(u64 *base) 1459 { 1460 u64 req = 0, resp; 1461 struct cgx *cgx; 1462 int first_lmac; 1463 int err; 1464 1465 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list); 1466 if (!cgx) 1467 return -ENXIO; 1468 1469 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1470 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); 1471 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); 1472 if (!err) 1473 *base = FIELD_GET(RESP_FWD_BASE, resp); 1474 1475 return err; 1476 } 1477 1478 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 1479 int cgx_id, int lmac_id) 1480 { 1481 struct cgx *cgx = cgxd; 1482 u64 req = 0, resp; 1483 1484 if (!cgx) 1485 return -ENODEV; 1486 1487 if (args.mode) 1488 otx2_map_ethtool_link_modes(args.mode, &args); 1489 if (!args.speed && args.duplex && !args.an) 1490 return -EINVAL; 1491 1492 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); 1493 req = FIELD_SET(CMDMODECHANGE_SPEED, 1494 cgx_link_usertable_index_map(args.speed), req); 1495 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); 1496 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); 1497 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); 1498 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); 1499 1500 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1501 } 1502 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) 1503 { 1504 u64 req = 0, resp; 1505 struct cgx *cgx; 1506 int err = 0; 1507 1508 cgx = cgx_get_pdata(cgx_id); 1509 if (!cgx) 1510 return -ENXIO; 1511 1512 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); 1513 req = FIELD_SET(CMDSETFEC, fec, req); 1514 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1515 if (err) 1516 return err; 1517 1518 cgx->lmac_idmap[lmac_id]->link_info.fec = 1519 FIELD_GET(RESP_LINKSTAT_FEC, resp); 1520 return cgx->lmac_idmap[lmac_id]->link_info.fec; 1521 } 1522 1523 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) 1524 { 1525 struct cgx *cgx = cgxd; 1526 u64 req = 0, resp; 1527 1528 if (!cgx) 1529 return -ENODEV; 1530 1531 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); 1532 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1533 } 1534 1535 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 1536 { 1537 u64 req = 0; 1538 u64 resp; 1539 1540 if (enable) { 1541 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 1542 /* On CN10K firmware offloads link bring up/down operations to ECP 1543 * On Octeontx2 link operations are handled by firmware itself 1544 * which can cause mbox errors so configure maximum time firmware 1545 * poll for Link as 1000 ms 1546 */ 1547 if (!is_dev_rpm(cgx)) 1548 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req); 1549 1550 } else { 1551 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 1552 } 1553 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1554 } 1555 1556 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 1557 { 1558 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1559 u64 req = 0; 1560 1561 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 1562 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); 1563 } 1564 1565 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 1566 { 1567 struct device *dev = &cgx->pdev->dev; 1568 int major_ver, minor_ver; 1569 u64 resp; 1570 int err; 1571 1572 if (!cgx->lmac_count) 1573 return 0; 1574 1575 err = cgx_fwi_read_version(&resp, cgx); 1576 if (err) 1577 return err; 1578 1579 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 1580 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 1581 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 1582 major_ver, minor_ver); 1583 if (major_ver != CGX_FIRMWARE_MAJOR_VER) 1584 return -EIO; 1585 else 1586 return 0; 1587 } 1588 1589 static void cgx_lmac_linkup_work(struct work_struct *work) 1590 { 1591 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 1592 struct device *dev = &cgx->pdev->dev; 1593 int i, err; 1594 1595 /* Do Link up for all the enabled lmacs */ 1596 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1597 err = cgx_fwi_link_change(cgx, i, true); 1598 if (err) 1599 dev_info(dev, "cgx port %d:%d Link up command failed\n", 1600 cgx->cgx_id, i); 1601 } 1602 } 1603 1604 int cgx_lmac_linkup_start(void *cgxd) 1605 { 1606 struct cgx *cgx = cgxd; 1607 1608 if (!cgx) 1609 return -ENODEV; 1610 1611 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 1612 1613 return 0; 1614 } 1615 1616 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr) 1617 { 1618 struct cgx *cgx = cgxd; 1619 u64 cfg; 1620 1621 if (!is_lmac_valid(cgx, lmac_id)) 1622 return -ENODEV; 1623 1624 /* Resetting PFC related CSRs */ 1625 cfg = 0xff; 1626 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg); 1627 1628 if (pf_req_flr) 1629 cgx_lmac_internal_loopback(cgxd, lmac_id, false); 1630 return 0; 1631 } 1632 1633 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, 1634 int cnt, bool req_free) 1635 { 1636 struct mac_ops *mac_ops = cgx->mac_ops; 1637 u64 offset, ena_bit; 1638 unsigned int irq; 1639 int err; 1640 1641 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + 1642 cnt * mac_ops->irq_offset); 1643 offset = mac_ops->int_set_reg; 1644 ena_bit = mac_ops->int_ena_bit; 1645 1646 if (req_free) { 1647 free_irq(irq, lmac); 1648 return 0; 1649 } 1650 1651 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); 1652 if (err) 1653 return err; 1654 1655 /* Enable interrupt */ 1656 cgx_write(cgx, lmac->lmac_id, offset, ena_bit); 1657 return 0; 1658 } 1659 1660 int cgx_get_nr_lmacs(void *cgxd) 1661 { 1662 struct cgx *cgx = cgxd; 1663 1664 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL; 1665 } 1666 1667 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) 1668 { 1669 struct cgx *cgx = cgxd; 1670 1671 return cgx->lmac_idmap[lmac_index]->lmac_id; 1672 } 1673 1674 unsigned long cgx_get_lmac_bmap(void *cgxd) 1675 { 1676 struct cgx *cgx = cgxd; 1677 1678 return cgx->lmac_bmap; 1679 } 1680 1681 static int cgx_lmac_init(struct cgx *cgx) 1682 { 1683 struct lmac *lmac; 1684 u64 lmac_list; 1685 int i, err; 1686 1687 /* lmac_list specifies which lmacs are enabled 1688 * when bit n is set to 1, LMAC[n] is enabled 1689 */ 1690 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1691 if (is_dev_rpm2(cgx)) 1692 lmac_list = 1693 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL; 1694 else 1695 lmac_list = 1696 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL; 1697 } 1698 1699 if (cgx->lmac_count > cgx->max_lmac_per_mac) 1700 cgx->lmac_count = cgx->max_lmac_per_mac; 1701 1702 for (i = 0; i < cgx->lmac_count; i++) { 1703 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL); 1704 if (!lmac) 1705 return -ENOMEM; 1706 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 1707 if (!lmac->name) { 1708 err = -ENOMEM; 1709 goto err_lmac_free; 1710 } 1711 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i); 1712 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1713 lmac->lmac_id = __ffs64(lmac_list); 1714 lmac_list &= ~BIT_ULL(lmac->lmac_id); 1715 } else { 1716 lmac->lmac_id = i; 1717 } 1718 1719 lmac->cgx = cgx; 1720 lmac->mac_to_index_bmap.max = 1721 cgx->mac_ops->dmac_filter_count / 1722 cgx->lmac_count; 1723 1724 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap); 1725 if (err) 1726 goto err_name_free; 1727 1728 /* Reserve first entry for default MAC address */ 1729 set_bit(0, lmac->mac_to_index_bmap.bmap); 1730 1731 lmac->rx_fc_pfvf_bmap.max = 128; 1732 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap); 1733 if (err) 1734 goto err_dmac_bmap_free; 1735 1736 lmac->tx_fc_pfvf_bmap.max = 128; 1737 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap); 1738 if (err) 1739 goto err_rx_fc_bmap_free; 1740 1741 init_waitqueue_head(&lmac->wq_cmd_cmplt); 1742 mutex_init(&lmac->cmd_lock); 1743 spin_lock_init(&lmac->event_cb_lock); 1744 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); 1745 if (err) 1746 goto err_bitmap_free; 1747 1748 /* Add reference */ 1749 cgx->lmac_idmap[lmac->lmac_id] = lmac; 1750 set_bit(lmac->lmac_id, &cgx->lmac_bmap); 1751 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); 1752 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id); 1753 } 1754 1755 /* Start X2P reset on given MAC block */ 1756 cgx->mac_ops->mac_x2p_reset(cgx, true); 1757 return cgx_lmac_verify_fwi_version(cgx); 1758 1759 err_bitmap_free: 1760 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap); 1761 err_rx_fc_bmap_free: 1762 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap); 1763 err_dmac_bmap_free: 1764 rvu_free_bitmap(&lmac->mac_to_index_bmap); 1765 err_name_free: 1766 kfree(lmac->name); 1767 err_lmac_free: 1768 kfree(lmac); 1769 return err; 1770 } 1771 1772 static int cgx_lmac_exit(struct cgx *cgx) 1773 { 1774 struct lmac *lmac; 1775 int i; 1776 1777 if (cgx->cgx_cmd_workq) { 1778 destroy_workqueue(cgx->cgx_cmd_workq); 1779 cgx->cgx_cmd_workq = NULL; 1780 } 1781 1782 /* Free all lmac related resources */ 1783 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1784 lmac = cgx->lmac_idmap[i]; 1785 if (!lmac) 1786 continue; 1787 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); 1788 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); 1789 kfree(lmac->mac_to_index_bmap.bmap); 1790 kfree(lmac->name); 1791 kfree(lmac); 1792 } 1793 1794 return 0; 1795 } 1796 1797 static void cgx_populate_features(struct cgx *cgx) 1798 { 1799 u64 cfg; 1800 1801 cfg = cgx_read(cgx, 0, CGX_CONST); 1802 cgx->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg); 1803 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg); 1804 1805 if (is_dev_rpm(cgx)) 1806 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM | 1807 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP); 1808 else 1809 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 | 1810 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF); 1811 } 1812 1813 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx) 1814 { 1815 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM || 1816 is_dev_rpm2(cgx)) 1817 return 0x80; 1818 else 1819 return 0x60; 1820 } 1821 1822 static void cgx_x2p_reset(void *cgxd, bool enable) 1823 { 1824 struct cgx *cgx = cgxd; 1825 int lmac_id; 1826 u64 cfg; 1827 1828 if (enable) { 1829 for_each_set_bit(lmac_id, &cgx->lmac_bmap, cgx->max_lmac_per_mac) 1830 cgx->mac_ops->mac_enadis_rx(cgx, lmac_id, false); 1831 1832 usleep_range(1000, 2000); 1833 1834 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG); 1835 cfg |= cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP; 1836 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg); 1837 } else { 1838 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG); 1839 cfg &= ~(cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP); 1840 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg); 1841 } 1842 } 1843 1844 static int cgx_enadis_rx(void *cgxd, int lmac_id, bool enable) 1845 { 1846 struct cgx *cgx = cgxd; 1847 u64 cfg; 1848 1849 if (!is_lmac_valid(cgx, lmac_id)) 1850 return -ENODEV; 1851 1852 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 1853 if (enable) 1854 cfg |= DATA_PKT_RX_EN; 1855 else 1856 cfg &= ~DATA_PKT_RX_EN; 1857 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 1858 return 0; 1859 } 1860 1861 static struct mac_ops cgx_mac_ops = { 1862 .name = "cgx", 1863 .csr_offset = 0, 1864 .lmac_offset = 18, 1865 .int_register = CGXX_CMRX_INT, 1866 .int_set_reg = CGXX_CMRX_INT_ENA_W1S, 1867 .irq_offset = 9, 1868 .int_ena_bit = FW_CGX_INT, 1869 .lmac_fwi = CGX_LMAC_FWI, 1870 .non_contiguous_serdes_lane = false, 1871 .rx_stats_cnt = 9, 1872 .tx_stats_cnt = 18, 1873 .dmac_filter_count = 32, 1874 .get_nr_lmacs = cgx_get_nr_lmacs, 1875 .get_lmac_type = cgx_get_lmac_type, 1876 .lmac_fifo_len = cgx_get_lmac_fifo_len, 1877 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, 1878 .mac_get_rx_stats = cgx_get_rx_stats, 1879 .mac_get_tx_stats = cgx_get_tx_stats, 1880 .get_fec_stats = cgx_get_fec_stats, 1881 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, 1882 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, 1883 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, 1884 .mac_pause_frm_config = cgx_lmac_pause_frm_config, 1885 .mac_enadis_ptp_config = cgx_lmac_ptp_config, 1886 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable, 1887 .mac_tx_enable = cgx_lmac_tx_enable, 1888 .pfc_config = cgx_lmac_pfc_config, 1889 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg, 1890 .mac_reset = cgx_lmac_reset, 1891 .mac_stats_reset = cgx_stats_reset, 1892 .mac_x2p_reset = cgx_x2p_reset, 1893 .mac_enadis_rx = cgx_enadis_rx, 1894 }; 1895 1896 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1897 { 1898 struct device *dev = &pdev->dev; 1899 struct cgx *cgx; 1900 int err, nvec; 1901 1902 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 1903 if (!cgx) 1904 return -ENOMEM; 1905 cgx->pdev = pdev; 1906 1907 pci_set_drvdata(pdev, cgx); 1908 1909 /* Use mac_ops to get MAC specific features */ 1910 if (is_dev_rpm(cgx)) 1911 cgx->mac_ops = rpm_get_mac_ops(cgx); 1912 else 1913 cgx->mac_ops = &cgx_mac_ops; 1914 1915 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx); 1916 1917 err = pci_enable_device(pdev); 1918 if (err) { 1919 dev_err(dev, "Failed to enable PCI device\n"); 1920 pci_set_drvdata(pdev, NULL); 1921 return err; 1922 } 1923 1924 err = pci_request_regions(pdev, DRV_NAME); 1925 if (err) { 1926 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1927 goto err_disable_device; 1928 } 1929 1930 /* MAP configuration registers */ 1931 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1932 if (!cgx->reg_base) { 1933 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 1934 err = -ENOMEM; 1935 goto err_release_regions; 1936 } 1937 1938 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); 1939 if (!cgx->lmac_count) { 1940 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id); 1941 err = -EOPNOTSUPP; 1942 goto err_release_regions; 1943 } 1944 1945 nvec = pci_msix_vec_count(cgx->pdev); 1946 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1947 if (err < 0 || err != nvec) { 1948 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 1949 nvec, err); 1950 goto err_release_regions; 1951 } 1952 1953 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 1954 & CGX_ID_MASK; 1955 1956 /* init wq for processing linkup requests */ 1957 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 1958 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 1959 if (!cgx->cgx_cmd_workq) { 1960 dev_err(dev, "alloc workqueue failed for cgx cmd"); 1961 err = -ENOMEM; 1962 goto err_free_irq_vectors; 1963 } 1964 1965 list_add(&cgx->cgx_list, &cgx_list); 1966 1967 1968 cgx_populate_features(cgx); 1969 1970 mutex_init(&cgx->lock); 1971 1972 err = cgx_lmac_init(cgx); 1973 if (err) 1974 goto err_release_lmac; 1975 1976 return 0; 1977 1978 err_release_lmac: 1979 cgx_lmac_exit(cgx); 1980 list_del(&cgx->cgx_list); 1981 err_free_irq_vectors: 1982 pci_free_irq_vectors(pdev); 1983 err_release_regions: 1984 pci_release_regions(pdev); 1985 err_disable_device: 1986 pci_disable_device(pdev); 1987 pci_set_drvdata(pdev, NULL); 1988 return err; 1989 } 1990 1991 static void cgx_remove(struct pci_dev *pdev) 1992 { 1993 struct cgx *cgx = pci_get_drvdata(pdev); 1994 1995 if (cgx) { 1996 cgx_lmac_exit(cgx); 1997 list_del(&cgx->cgx_list); 1998 } 1999 pci_free_irq_vectors(pdev); 2000 pci_release_regions(pdev); 2001 pci_disable_device(pdev); 2002 pci_set_drvdata(pdev, NULL); 2003 } 2004 2005 struct pci_driver cgx_driver = { 2006 .name = DRV_NAME, 2007 .id_table = cgx_id_table, 2008 .probe = cgx_probe, 2009 .remove = cgx_remove, 2010 }; 2011