1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/phy.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 22 #include "cgx.h" 23 24 #define DRV_NAME "octeontx2-cgx" 25 #define DRV_STRING "Marvell OcteonTX2 CGX/MAC Driver" 26 27 /** 28 * struct lmac 29 * @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion 30 * @cmd_lock: Lock to serialize the command interface 31 * @resp: command response 32 * @link_info: link related information 33 * @event_cb: callback for linkchange events 34 * @event_cb_lock: lock for serializing callback with unregister 35 * @cmd_pend: flag set before new command is started 36 * flag cleared after command response is received 37 * @cgx: parent cgx port 38 * @lmac_id: lmac port id 39 * @name: lmac port name 40 */ 41 struct lmac { 42 wait_queue_head_t wq_cmd_cmplt; 43 struct mutex cmd_lock; 44 u64 resp; 45 struct cgx_link_user_info link_info; 46 struct cgx_event_cb event_cb; 47 spinlock_t event_cb_lock; 48 bool cmd_pend; 49 struct cgx *cgx; 50 u8 lmac_id; 51 char *name; 52 }; 53 54 struct cgx { 55 void __iomem *reg_base; 56 struct pci_dev *pdev; 57 u8 cgx_id; 58 u8 lmac_count; 59 struct lmac *lmac_idmap[MAX_LMAC_PER_CGX]; 60 struct work_struct cgx_cmd_work; 61 struct workqueue_struct *cgx_cmd_workq; 62 struct list_head cgx_list; 63 }; 64 65 static LIST_HEAD(cgx_list); 66 67 /* Convert firmware speed encoding to user format(Mbps) */ 68 static u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX]; 69 70 /* Convert firmware lmac type encoding to string */ 71 static char *cgx_lmactype_string[LMAC_MODE_MAX]; 72 73 /* CGX PHY management internal APIs */ 74 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 75 76 /* Supported devices */ 77 static const struct pci_device_id cgx_id_table[] = { 78 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 79 { 0, } /* end of table */ 80 }; 81 82 MODULE_DEVICE_TABLE(pci, cgx_id_table); 83 84 static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 85 { 86 writeq(val, cgx->reg_base + (lmac << 18) + offset); 87 } 88 89 static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 90 { 91 return readq(cgx->reg_base + (lmac << 18) + offset); 92 } 93 94 static inline struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 95 { 96 if (!cgx || lmac_id >= MAX_LMAC_PER_CGX) 97 return NULL; 98 99 return cgx->lmac_idmap[lmac_id]; 100 } 101 102 int cgx_get_cgxcnt_max(void) 103 { 104 struct cgx *cgx_dev; 105 int idmax = -ENODEV; 106 107 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 108 if (cgx_dev->cgx_id > idmax) 109 idmax = cgx_dev->cgx_id; 110 111 if (idmax < 0) 112 return 0; 113 114 return idmax + 1; 115 } 116 117 int cgx_get_lmac_cnt(void *cgxd) 118 { 119 struct cgx *cgx = cgxd; 120 121 if (!cgx) 122 return -ENODEV; 123 124 return cgx->lmac_count; 125 } 126 127 void *cgx_get_pdata(int cgx_id) 128 { 129 struct cgx *cgx_dev; 130 131 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 132 if (cgx_dev->cgx_id == cgx_id) 133 return cgx_dev; 134 } 135 return NULL; 136 } 137 138 int cgx_get_cgxid(void *cgxd) 139 { 140 struct cgx *cgx = cgxd; 141 142 if (!cgx) 143 return -EINVAL; 144 145 return cgx->cgx_id; 146 } 147 148 /* Ensure the required lock for event queue(where asynchronous events are 149 * posted) is acquired before calling this API. Else an asynchronous event(with 150 * latest link status) can reach the destination before this function returns 151 * and could make the link status appear wrong. 152 */ 153 int cgx_get_link_info(void *cgxd, int lmac_id, 154 struct cgx_link_user_info *linfo) 155 { 156 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 157 158 if (!lmac) 159 return -ENODEV; 160 161 *linfo = lmac->link_info; 162 return 0; 163 } 164 165 static u64 mac2u64 (u8 *mac_addr) 166 { 167 u64 mac = 0; 168 int index; 169 170 for (index = ETH_ALEN - 1; index >= 0; index--) 171 mac |= ((u64)*mac_addr++) << (8 * index); 172 return mac; 173 } 174 175 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 176 { 177 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 178 u64 cfg; 179 180 /* copy 6bytes from macaddr */ 181 /* memcpy(&cfg, mac_addr, 6); */ 182 183 cfg = mac2u64 (mac_addr); 184 185 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (lmac_id * 0x8)), 186 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 187 188 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 189 cfg |= CGX_DMAC_CTL0_CAM_ENABLE; 190 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 191 192 return 0; 193 } 194 195 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 196 { 197 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 198 u64 cfg; 199 200 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8); 201 return cfg & CGX_RX_DMAC_ADR_MASK; 202 } 203 204 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 205 { 206 struct cgx *cgx = cgxd; 207 208 if (!cgx || lmac_id >= cgx->lmac_count) 209 return -ENODEV; 210 211 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F)); 212 return 0; 213 } 214 215 static inline u8 cgx_get_lmac_type(struct cgx *cgx, int lmac_id) 216 { 217 u64 cfg; 218 219 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 220 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 221 } 222 223 /* Configure CGX LMAC in internal loopback mode */ 224 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 225 { 226 struct cgx *cgx = cgxd; 227 u8 lmac_type; 228 u64 cfg; 229 230 if (!cgx || lmac_id >= cgx->lmac_count) 231 return -ENODEV; 232 233 lmac_type = cgx_get_lmac_type(cgx, lmac_id); 234 if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) { 235 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 236 if (enable) 237 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 238 else 239 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 240 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 241 } else { 242 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 243 if (enable) 244 cfg |= CGXX_SPUX_CONTROL1_LBK; 245 else 246 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 247 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 248 } 249 return 0; 250 } 251 252 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 253 { 254 struct cgx *cgx = cgx_get_pdata(cgx_id); 255 u64 cfg = 0; 256 257 if (!cgx) 258 return; 259 260 if (enable) { 261 /* Enable promiscuous mode on LMAC */ 262 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 263 cfg &= ~(CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE); 264 cfg |= CGX_DMAC_BCAST_MODE; 265 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 266 267 cfg = cgx_read(cgx, 0, 268 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8)); 269 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 270 cgx_write(cgx, 0, 271 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg); 272 } else { 273 /* Disable promiscuous mode */ 274 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 275 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 276 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 277 cfg = cgx_read(cgx, 0, 278 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8)); 279 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 280 cgx_write(cgx, 0, 281 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg); 282 } 283 } 284 285 /* Enable or disable forwarding received pause frames to Tx block */ 286 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 287 { 288 struct cgx *cgx = cgxd; 289 u64 cfg; 290 291 if (!cgx) 292 return; 293 294 if (enable) { 295 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 296 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 297 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 298 299 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 300 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 301 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 302 } else { 303 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 304 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 305 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 306 307 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 308 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 309 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 310 } 311 } 312 313 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 314 { 315 struct cgx *cgx = cgxd; 316 317 if (!cgx || lmac_id >= cgx->lmac_count) 318 return -ENODEV; 319 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 320 return 0; 321 } 322 323 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 324 { 325 struct cgx *cgx = cgxd; 326 327 if (!cgx || lmac_id >= cgx->lmac_count) 328 return -ENODEV; 329 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 330 return 0; 331 } 332 333 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 334 { 335 struct cgx *cgx = cgxd; 336 u64 cfg; 337 338 if (!cgx || lmac_id >= cgx->lmac_count) 339 return -ENODEV; 340 341 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 342 if (enable) 343 cfg |= CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN; 344 else 345 cfg &= ~(CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN); 346 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 347 return 0; 348 } 349 350 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 351 { 352 struct cgx *cgx = cgxd; 353 u64 cfg, last; 354 355 if (!cgx || lmac_id >= cgx->lmac_count) 356 return -ENODEV; 357 358 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 359 last = cfg; 360 if (enable) 361 cfg |= DATA_PKT_TX_EN; 362 else 363 cfg &= ~DATA_PKT_TX_EN; 364 365 if (cfg != last) 366 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 367 return !!(last & DATA_PKT_TX_EN); 368 } 369 370 /* CGX Firmware interface low level support */ 371 static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 372 { 373 struct cgx *cgx = lmac->cgx; 374 struct device *dev; 375 int err = 0; 376 u64 cmd; 377 378 /* Ensure no other command is in progress */ 379 err = mutex_lock_interruptible(&lmac->cmd_lock); 380 if (err) 381 return err; 382 383 /* Ensure command register is free */ 384 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 385 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 386 err = -EBUSY; 387 goto unlock; 388 } 389 390 /* Update ownership in command request */ 391 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 392 393 /* Mark this lmac as pending, before we start */ 394 lmac->cmd_pend = true; 395 396 /* Start command in hardware */ 397 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 398 399 /* Ensure command is completed without errors */ 400 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 401 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 402 dev = &cgx->pdev->dev; 403 dev_err(dev, "cgx port %d:%d cmd timeout\n", 404 cgx->cgx_id, lmac->lmac_id); 405 err = -EIO; 406 goto unlock; 407 } 408 409 /* we have a valid command response */ 410 smp_rmb(); /* Ensure the latest updates are visible */ 411 *resp = lmac->resp; 412 413 unlock: 414 mutex_unlock(&lmac->cmd_lock); 415 416 return err; 417 } 418 419 static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp, 420 struct cgx *cgx, int lmac_id) 421 { 422 struct lmac *lmac; 423 int err; 424 425 lmac = lmac_pdata(lmac_id, cgx); 426 if (!lmac) 427 return -ENODEV; 428 429 err = cgx_fwi_cmd_send(req, resp, lmac); 430 431 /* Check for valid response */ 432 if (!err) { 433 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 434 return -EIO; 435 else 436 return 0; 437 } 438 439 return err; 440 } 441 442 static inline void cgx_link_usertable_init(void) 443 { 444 cgx_speed_mbps[CGX_LINK_NONE] = 0; 445 cgx_speed_mbps[CGX_LINK_10M] = 10; 446 cgx_speed_mbps[CGX_LINK_100M] = 100; 447 cgx_speed_mbps[CGX_LINK_1G] = 1000; 448 cgx_speed_mbps[CGX_LINK_2HG] = 2500; 449 cgx_speed_mbps[CGX_LINK_5G] = 5000; 450 cgx_speed_mbps[CGX_LINK_10G] = 10000; 451 cgx_speed_mbps[CGX_LINK_20G] = 20000; 452 cgx_speed_mbps[CGX_LINK_25G] = 25000; 453 cgx_speed_mbps[CGX_LINK_40G] = 40000; 454 cgx_speed_mbps[CGX_LINK_50G] = 50000; 455 cgx_speed_mbps[CGX_LINK_100G] = 100000; 456 457 cgx_lmactype_string[LMAC_MODE_SGMII] = "SGMII"; 458 cgx_lmactype_string[LMAC_MODE_XAUI] = "XAUI"; 459 cgx_lmactype_string[LMAC_MODE_RXAUI] = "RXAUI"; 460 cgx_lmactype_string[LMAC_MODE_10G_R] = "10G_R"; 461 cgx_lmactype_string[LMAC_MODE_40G_R] = "40G_R"; 462 cgx_lmactype_string[LMAC_MODE_QSGMII] = "QSGMII"; 463 cgx_lmactype_string[LMAC_MODE_25G_R] = "25G_R"; 464 cgx_lmactype_string[LMAC_MODE_50G_R] = "50G_R"; 465 cgx_lmactype_string[LMAC_MODE_100G_R] = "100G_R"; 466 cgx_lmactype_string[LMAC_MODE_USXGMII] = "USXGMII"; 467 } 468 469 static inline void link_status_user_format(u64 lstat, 470 struct cgx_link_user_info *linfo, 471 struct cgx *cgx, u8 lmac_id) 472 { 473 char *lmac_string; 474 475 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 476 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 477 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 478 linfo->lmac_type_id = cgx_get_lmac_type(cgx, lmac_id); 479 lmac_string = cgx_lmactype_string[linfo->lmac_type_id]; 480 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1); 481 } 482 483 /* Hardware event handlers */ 484 static inline void cgx_link_change_handler(u64 lstat, 485 struct lmac *lmac) 486 { 487 struct cgx_link_user_info *linfo; 488 struct cgx *cgx = lmac->cgx; 489 struct cgx_link_event event; 490 struct device *dev; 491 int err_type; 492 493 dev = &cgx->pdev->dev; 494 495 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 496 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 497 498 event.cgx_id = cgx->cgx_id; 499 event.lmac_id = lmac->lmac_id; 500 501 /* update the local copy of link status */ 502 lmac->link_info = event.link_uinfo; 503 linfo = &lmac->link_info; 504 505 /* Ensure callback doesn't get unregistered until we finish it */ 506 spin_lock(&lmac->event_cb_lock); 507 508 if (!lmac->event_cb.notify_link_chg) { 509 dev_dbg(dev, "cgx port %d:%d Link change handler null", 510 cgx->cgx_id, lmac->lmac_id); 511 if (err_type != CGX_ERR_NONE) { 512 dev_err(dev, "cgx port %d:%d Link error %d\n", 513 cgx->cgx_id, lmac->lmac_id, err_type); 514 } 515 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 516 cgx->cgx_id, lmac->lmac_id, 517 linfo->link_up ? "UP" : "DOWN", linfo->speed); 518 goto err; 519 } 520 521 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 522 dev_err(dev, "event notification failure\n"); 523 err: 524 spin_unlock(&lmac->event_cb_lock); 525 } 526 527 static inline bool cgx_cmdresp_is_linkevent(u64 event) 528 { 529 u8 id; 530 531 id = FIELD_GET(EVTREG_ID, event); 532 if (id == CGX_CMD_LINK_BRING_UP || 533 id == CGX_CMD_LINK_BRING_DOWN) 534 return true; 535 else 536 return false; 537 } 538 539 static inline bool cgx_event_is_linkevent(u64 event) 540 { 541 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 542 return true; 543 else 544 return false; 545 } 546 547 static inline int cgx_fwi_get_mkex_prfl_sz(u64 *prfl_sz, 548 struct cgx *cgx) 549 { 550 u64 req = 0; 551 u64 resp; 552 int err; 553 554 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_MKEX_PRFL_SIZE, req); 555 err = cgx_fwi_cmd_generic(req, &resp, cgx, 0); 556 if (!err) 557 *prfl_sz = FIELD_GET(RESP_MKEX_PRFL_SIZE, resp); 558 559 return err; 560 } 561 562 static inline int cgx_fwi_get_mkex_prfl_addr(u64 *prfl_addr, 563 struct cgx *cgx) 564 { 565 u64 req = 0; 566 u64 resp; 567 int err; 568 569 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_MKEX_PRFL_ADDR, req); 570 err = cgx_fwi_cmd_generic(req, &resp, cgx, 0); 571 if (!err) 572 *prfl_addr = FIELD_GET(RESP_MKEX_PRFL_ADDR, resp); 573 574 return err; 575 } 576 577 int cgx_get_mkex_prfl_info(u64 *addr, u64 *size) 578 { 579 struct cgx *cgx_dev; 580 int err; 581 582 if (!addr || !size) 583 return -EINVAL; 584 585 cgx_dev = list_first_entry(&cgx_list, struct cgx, cgx_list); 586 if (!cgx_dev) 587 return -ENXIO; 588 589 err = cgx_fwi_get_mkex_prfl_sz(size, cgx_dev); 590 if (err) 591 return -EIO; 592 593 err = cgx_fwi_get_mkex_prfl_addr(addr, cgx_dev); 594 if (err) 595 return -EIO; 596 597 return 0; 598 } 599 600 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 601 { 602 struct lmac *lmac = data; 603 struct cgx *cgx; 604 u64 event; 605 606 cgx = lmac->cgx; 607 608 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 609 610 if (!FIELD_GET(EVTREG_ACK, event)) 611 return IRQ_NONE; 612 613 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 614 case CGX_EVT_CMD_RESP: 615 /* Copy the response. Since only one command is active at a 616 * time, there is no way a response can get overwritten 617 */ 618 lmac->resp = event; 619 /* Ensure response is updated before thread context starts */ 620 smp_wmb(); 621 622 /* There wont be separate events for link change initiated from 623 * software; Hence report the command responses as events 624 */ 625 if (cgx_cmdresp_is_linkevent(event)) 626 cgx_link_change_handler(event, lmac); 627 628 /* Release thread waiting for completion */ 629 lmac->cmd_pend = false; 630 wake_up_interruptible(&lmac->wq_cmd_cmplt); 631 break; 632 case CGX_EVT_ASYNC: 633 if (cgx_event_is_linkevent(event)) 634 cgx_link_change_handler(event, lmac); 635 break; 636 } 637 638 /* Any new event or command response will be posted by firmware 639 * only after the current status is acked. 640 * Ack the interrupt register as well. 641 */ 642 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 643 cgx_write(lmac->cgx, lmac->lmac_id, CGXX_CMRX_INT, FW_CGX_INT); 644 645 return IRQ_HANDLED; 646 } 647 648 /* APIs for PHY management using CGX firmware interface */ 649 650 /* callback registration for hardware events like link change */ 651 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 652 { 653 struct cgx *cgx = cgxd; 654 struct lmac *lmac; 655 656 lmac = lmac_pdata(lmac_id, cgx); 657 if (!lmac) 658 return -ENODEV; 659 660 lmac->event_cb = *cb; 661 662 return 0; 663 } 664 665 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 666 { 667 struct lmac *lmac; 668 unsigned long flags; 669 struct cgx *cgx = cgxd; 670 671 lmac = lmac_pdata(lmac_id, cgx); 672 if (!lmac) 673 return -ENODEV; 674 675 spin_lock_irqsave(&lmac->event_cb_lock, flags); 676 lmac->event_cb.notify_link_chg = NULL; 677 lmac->event_cb.data = NULL; 678 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 679 680 return 0; 681 } 682 683 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 684 { 685 u64 req = 0; 686 u64 resp; 687 688 if (enable) 689 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 690 else 691 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 692 693 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 694 } 695 696 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 697 { 698 u64 req = 0; 699 700 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 701 return cgx_fwi_cmd_generic(req, resp, cgx, 0); 702 } 703 704 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 705 { 706 struct device *dev = &cgx->pdev->dev; 707 int major_ver, minor_ver; 708 u64 resp; 709 int err; 710 711 if (!cgx->lmac_count) 712 return 0; 713 714 err = cgx_fwi_read_version(&resp, cgx); 715 if (err) 716 return err; 717 718 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 719 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 720 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 721 major_ver, minor_ver); 722 if (major_ver != CGX_FIRMWARE_MAJOR_VER || 723 minor_ver != CGX_FIRMWARE_MINOR_VER) 724 return -EIO; 725 else 726 return 0; 727 } 728 729 static void cgx_lmac_linkup_work(struct work_struct *work) 730 { 731 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 732 struct device *dev = &cgx->pdev->dev; 733 int i, err; 734 735 /* Do Link up for all the lmacs */ 736 for (i = 0; i < cgx->lmac_count; i++) { 737 err = cgx_fwi_link_change(cgx, i, true); 738 if (err) 739 dev_info(dev, "cgx port %d:%d Link up command failed\n", 740 cgx->cgx_id, i); 741 } 742 } 743 744 int cgx_lmac_linkup_start(void *cgxd) 745 { 746 struct cgx *cgx = cgxd; 747 748 if (!cgx) 749 return -ENODEV; 750 751 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 752 753 return 0; 754 } 755 756 static int cgx_lmac_init(struct cgx *cgx) 757 { 758 struct lmac *lmac; 759 int i, err; 760 761 cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7; 762 if (cgx->lmac_count > MAX_LMAC_PER_CGX) 763 cgx->lmac_count = MAX_LMAC_PER_CGX; 764 765 for (i = 0; i < cgx->lmac_count; i++) { 766 lmac = kcalloc(1, sizeof(struct lmac), GFP_KERNEL); 767 if (!lmac) 768 return -ENOMEM; 769 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 770 if (!lmac->name) 771 return -ENOMEM; 772 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i); 773 lmac->lmac_id = i; 774 lmac->cgx = cgx; 775 init_waitqueue_head(&lmac->wq_cmd_cmplt); 776 mutex_init(&lmac->cmd_lock); 777 spin_lock_init(&lmac->event_cb_lock); 778 err = request_irq(pci_irq_vector(cgx->pdev, 779 CGX_LMAC_FWI + i * 9), 780 cgx_fwi_event_handler, 0, lmac->name, lmac); 781 if (err) 782 return err; 783 784 /* Enable interrupt */ 785 cgx_write(cgx, lmac->lmac_id, CGXX_CMRX_INT_ENA_W1S, 786 FW_CGX_INT); 787 788 /* Add reference */ 789 cgx->lmac_idmap[i] = lmac; 790 } 791 792 return cgx_lmac_verify_fwi_version(cgx); 793 } 794 795 static int cgx_lmac_exit(struct cgx *cgx) 796 { 797 struct lmac *lmac; 798 int i; 799 800 if (cgx->cgx_cmd_workq) { 801 flush_workqueue(cgx->cgx_cmd_workq); 802 destroy_workqueue(cgx->cgx_cmd_workq); 803 cgx->cgx_cmd_workq = NULL; 804 } 805 806 /* Free all lmac related resources */ 807 for (i = 0; i < cgx->lmac_count; i++) { 808 lmac = cgx->lmac_idmap[i]; 809 if (!lmac) 810 continue; 811 free_irq(pci_irq_vector(cgx->pdev, CGX_LMAC_FWI + i * 9), lmac); 812 kfree(lmac->name); 813 kfree(lmac); 814 } 815 816 return 0; 817 } 818 819 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 820 { 821 struct device *dev = &pdev->dev; 822 struct cgx *cgx; 823 int err, nvec; 824 825 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 826 if (!cgx) 827 return -ENOMEM; 828 cgx->pdev = pdev; 829 830 pci_set_drvdata(pdev, cgx); 831 832 err = pci_enable_device(pdev); 833 if (err) { 834 dev_err(dev, "Failed to enable PCI device\n"); 835 pci_set_drvdata(pdev, NULL); 836 return err; 837 } 838 839 err = pci_request_regions(pdev, DRV_NAME); 840 if (err) { 841 dev_err(dev, "PCI request regions failed 0x%x\n", err); 842 goto err_disable_device; 843 } 844 845 /* MAP configuration registers */ 846 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 847 if (!cgx->reg_base) { 848 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 849 err = -ENOMEM; 850 goto err_release_regions; 851 } 852 853 nvec = CGX_NVEC; 854 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 855 if (err < 0 || err != nvec) { 856 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 857 nvec, err); 858 goto err_release_regions; 859 } 860 861 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 862 & CGX_ID_MASK; 863 864 /* init wq for processing linkup requests */ 865 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 866 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 867 if (!cgx->cgx_cmd_workq) { 868 dev_err(dev, "alloc workqueue failed for cgx cmd"); 869 err = -ENOMEM; 870 goto err_free_irq_vectors; 871 } 872 873 list_add(&cgx->cgx_list, &cgx_list); 874 875 cgx_link_usertable_init(); 876 877 err = cgx_lmac_init(cgx); 878 if (err) 879 goto err_release_lmac; 880 881 return 0; 882 883 err_release_lmac: 884 cgx_lmac_exit(cgx); 885 list_del(&cgx->cgx_list); 886 err_free_irq_vectors: 887 pci_free_irq_vectors(pdev); 888 err_release_regions: 889 pci_release_regions(pdev); 890 err_disable_device: 891 pci_disable_device(pdev); 892 pci_set_drvdata(pdev, NULL); 893 return err; 894 } 895 896 static void cgx_remove(struct pci_dev *pdev) 897 { 898 struct cgx *cgx = pci_get_drvdata(pdev); 899 900 cgx_lmac_exit(cgx); 901 list_del(&cgx->cgx_list); 902 pci_free_irq_vectors(pdev); 903 pci_release_regions(pdev); 904 pci_disable_device(pdev); 905 pci_set_drvdata(pdev, NULL); 906 } 907 908 struct pci_driver cgx_driver = { 909 .name = DRV_NAME, 910 .id_table = cgx_id_table, 911 .probe = cgx_probe, 912 .remove = cgx_remove, 913 }; 914