1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "cgx.h" 21 #include "rvu.h" 22 #include "lmac_common.h" 23 24 #define DRV_NAME "Marvell-CGX/RPM" 25 #define DRV_STRING "Marvell CGX/RPM Driver" 26 27 #define CGX_RX_STAT_GLOBAL_INDEX 9 28 29 static LIST_HEAD(cgx_list); 30 31 /* Convert firmware speed encoding to user format(Mbps) */ 32 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = { 33 [CGX_LINK_NONE] = 0, 34 [CGX_LINK_10M] = 10, 35 [CGX_LINK_100M] = 100, 36 [CGX_LINK_1G] = 1000, 37 [CGX_LINK_2HG] = 2500, 38 [CGX_LINK_5G] = 5000, 39 [CGX_LINK_10G] = 10000, 40 [CGX_LINK_20G] = 20000, 41 [CGX_LINK_25G] = 25000, 42 [CGX_LINK_40G] = 40000, 43 [CGX_LINK_50G] = 50000, 44 [CGX_LINK_80G] = 80000, 45 [CGX_LINK_100G] = 100000, 46 }; 47 48 /* Convert firmware lmac type encoding to string */ 49 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = { 50 [LMAC_MODE_SGMII] = "SGMII", 51 [LMAC_MODE_XAUI] = "XAUI", 52 [LMAC_MODE_RXAUI] = "RXAUI", 53 [LMAC_MODE_10G_R] = "10G_R", 54 [LMAC_MODE_40G_R] = "40G_R", 55 [LMAC_MODE_QSGMII] = "QSGMII", 56 [LMAC_MODE_25G_R] = "25G_R", 57 [LMAC_MODE_50G_R] = "50G_R", 58 [LMAC_MODE_100G_R] = "100G_R", 59 [LMAC_MODE_USXGMII] = "USXGMII", 60 [LMAC_MODE_USGMII] = "USGMII", 61 }; 62 63 /* CGX PHY management internal APIs */ 64 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 65 66 /* Supported devices */ 67 static const struct pci_device_id cgx_id_table[] = { 68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 70 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) }, 71 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 72 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) }, 73 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM, 74 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) }, 75 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 76 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) }, 77 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 78 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) }, 79 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM, 80 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) }, 81 { 0, } /* end of table */ 82 }; 83 84 MODULE_DEVICE_TABLE(pci, cgx_id_table); 85 86 static bool is_dev_rpm(void *cgxd) 87 { 88 struct cgx *cgx = cgxd; 89 90 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || 91 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); 92 } 93 94 bool is_lmac_valid(struct cgx *cgx, int lmac_id) 95 { 96 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) 97 return false; 98 return test_bit(lmac_id, &cgx->lmac_bmap); 99 } 100 101 /* Helper function to get sequential index 102 * given the enabled LMAC of a CGX 103 */ 104 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id) 105 { 106 int tmp, id = 0; 107 108 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 109 if (tmp == lmac_id) 110 break; 111 id++; 112 } 113 114 return id; 115 } 116 117 struct mac_ops *get_mac_ops(void *cgxd) 118 { 119 if (!cgxd) 120 return cgxd; 121 122 return ((struct cgx *)cgxd)->mac_ops; 123 } 124 125 u32 cgx_get_fifo_len(void *cgxd) 126 { 127 return ((struct cgx *)cgxd)->fifo_len; 128 } 129 130 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 131 { 132 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 133 offset); 134 } 135 136 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 137 { 138 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 139 offset); 140 } 141 142 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 143 { 144 if (!cgx || lmac_id >= cgx->max_lmac_per_mac) 145 return NULL; 146 147 return cgx->lmac_idmap[lmac_id]; 148 } 149 150 int cgx_get_cgxcnt_max(void) 151 { 152 struct cgx *cgx_dev; 153 int idmax = -ENODEV; 154 155 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 156 if (cgx_dev->cgx_id > idmax) 157 idmax = cgx_dev->cgx_id; 158 159 if (idmax < 0) 160 return 0; 161 162 return idmax + 1; 163 } 164 165 int cgx_get_lmac_cnt(void *cgxd) 166 { 167 struct cgx *cgx = cgxd; 168 169 if (!cgx) 170 return -ENODEV; 171 172 return cgx->lmac_count; 173 } 174 175 void *cgx_get_pdata(int cgx_id) 176 { 177 struct cgx *cgx_dev; 178 179 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 180 if (cgx_dev->cgx_id == cgx_id) 181 return cgx_dev; 182 } 183 return NULL; 184 } 185 186 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) 187 { 188 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 189 190 /* Software must not access disabled LMAC registers */ 191 if (!is_lmac_valid(cgx_dev, lmac_id)) 192 return; 193 cgx_write(cgx_dev, lmac_id, offset, val); 194 } 195 196 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) 197 { 198 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 199 200 /* Software must not access disabled LMAC registers */ 201 if (!is_lmac_valid(cgx_dev, lmac_id)) 202 return 0; 203 204 return cgx_read(cgx_dev, lmac_id, offset); 205 } 206 207 int cgx_get_cgxid(void *cgxd) 208 { 209 struct cgx *cgx = cgxd; 210 211 if (!cgx) 212 return -EINVAL; 213 214 return cgx->cgx_id; 215 } 216 217 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id) 218 { 219 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 220 u64 cfg; 221 222 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); 223 224 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; 225 } 226 227 static u8 cgx_get_nix_resetbit(struct cgx *cgx) 228 { 229 int first_lmac; 230 u8 p2x; 231 232 /* non 98XX silicons supports only NIX0 block */ 233 if (cgx->pdev->subsystem_device != PCI_SUBSYS_DEVID_98XX) 234 return CGX_NIX0_RESET; 235 236 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 237 p2x = cgx_lmac_get_p2x(cgx->cgx_id, first_lmac); 238 239 if (p2x == CMR_P2X_SEL_NIX1) 240 return CGX_NIX1_RESET; 241 else 242 return CGX_NIX0_RESET; 243 } 244 245 /* Ensure the required lock for event queue(where asynchronous events are 246 * posted) is acquired before calling this API. Else an asynchronous event(with 247 * latest link status) can reach the destination before this function returns 248 * and could make the link status appear wrong. 249 */ 250 int cgx_get_link_info(void *cgxd, int lmac_id, 251 struct cgx_link_user_info *linfo) 252 { 253 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 254 255 if (!lmac) 256 return -ENODEV; 257 258 *linfo = lmac->link_info; 259 return 0; 260 } 261 262 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 263 { 264 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 265 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 266 struct mac_ops *mac_ops; 267 int index, id; 268 u64 cfg; 269 270 if (!lmac) 271 return -ENODEV; 272 273 /* access mac_ops to know csr_offset */ 274 mac_ops = cgx_dev->mac_ops; 275 276 /* copy 6bytes from macaddr */ 277 /* memcpy(&cfg, mac_addr, 6); */ 278 279 cfg = ether_addr_to_u64(mac_addr); 280 281 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 282 283 index = id * lmac->mac_to_index_bmap.max; 284 285 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 286 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 287 288 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 289 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | 290 CGX_DMAC_MCAST_MODE); 291 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 292 293 return 0; 294 } 295 296 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id) 297 { 298 struct mac_ops *mac_ops; 299 struct cgx *cgx = cgxd; 300 301 if (!cgxd || !is_lmac_valid(cgxd, lmac_id)) 302 return 0; 303 304 cgx = cgxd; 305 /* Get mac_ops to know csr offset */ 306 mac_ops = cgx->mac_ops; 307 308 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 309 } 310 311 u64 cgx_read_dmac_entry(void *cgxd, int index) 312 { 313 struct mac_ops *mac_ops; 314 struct cgx *cgx; 315 316 if (!cgxd) 317 return 0; 318 319 cgx = cgxd; 320 mac_ops = cgx->mac_ops; 321 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8))); 322 } 323 324 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 325 { 326 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 327 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 328 struct mac_ops *mac_ops; 329 int index, idx; 330 u64 cfg = 0; 331 int id; 332 333 if (!lmac) 334 return -ENODEV; 335 336 mac_ops = cgx_dev->mac_ops; 337 /* Get available index where entry is to be installed */ 338 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap); 339 if (idx < 0) 340 return idx; 341 342 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 343 344 index = id * lmac->mac_to_index_bmap.max + idx; 345 346 cfg = ether_addr_to_u64(mac_addr); 347 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 348 cfg |= ((u64)lmac_id << 49); 349 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 350 351 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 352 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT); 353 354 if (is_multicast_ether_addr(mac_addr)) { 355 cfg &= ~GENMASK_ULL(2, 1); 356 cfg |= CGX_DMAC_MCAST_MODE_CAM; 357 lmac->mcast_filters_count++; 358 } else if (!lmac->mcast_filters_count) { 359 cfg |= CGX_DMAC_MCAST_MODE; 360 } 361 362 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 363 364 return idx; 365 } 366 367 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id) 368 { 369 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 370 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 371 struct mac_ops *mac_ops; 372 u8 index = 0, id; 373 u64 cfg; 374 375 if (!lmac) 376 return -ENODEV; 377 378 mac_ops = cgx_dev->mac_ops; 379 /* Restore index 0 to its default init value as done during 380 * cgx_lmac_init 381 */ 382 set_bit(0, lmac->mac_to_index_bmap.bmap); 383 384 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 385 386 index = id * lmac->mac_to_index_bmap.max + index; 387 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 388 389 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */ 390 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 391 cfg &= ~CGX_DMAC_CAM_ACCEPT; 392 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 393 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 394 395 return 0; 396 } 397 398 /* Allows caller to change macaddress associated with index 399 * in dmac filter table including index 0 reserved for 400 * interface mac address 401 */ 402 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index) 403 { 404 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 405 struct mac_ops *mac_ops; 406 struct lmac *lmac; 407 u64 cfg; 408 int id; 409 410 lmac = lmac_pdata(lmac_id, cgx_dev); 411 if (!lmac) 412 return -ENODEV; 413 414 mac_ops = cgx_dev->mac_ops; 415 /* Validate the index */ 416 if (index >= lmac->mac_to_index_bmap.max) 417 return -EINVAL; 418 419 /* ensure index is already set */ 420 if (!test_bit(index, lmac->mac_to_index_bmap.bmap)) 421 return -EINVAL; 422 423 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 424 425 index = id * lmac->mac_to_index_bmap.max + index; 426 427 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 428 cfg &= ~CGX_RX_DMAC_ADR_MASK; 429 cfg |= ether_addr_to_u64(mac_addr); 430 431 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 432 return 0; 433 } 434 435 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index) 436 { 437 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 438 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 439 struct mac_ops *mac_ops; 440 u8 mac[ETH_ALEN]; 441 u64 cfg; 442 int id; 443 444 if (!lmac) 445 return -ENODEV; 446 447 mac_ops = cgx_dev->mac_ops; 448 /* Validate the index */ 449 if (index >= lmac->mac_to_index_bmap.max) 450 return -EINVAL; 451 452 /* Skip deletion for reserved index i.e. index 0 */ 453 if (index == 0) 454 return 0; 455 456 rvu_free_rsrc(&lmac->mac_to_index_bmap, index); 457 458 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 459 460 index = id * lmac->mac_to_index_bmap.max + index; 461 462 /* Read MAC address to check whether it is ucast or mcast */ 463 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 464 465 u64_to_ether_addr(cfg, mac); 466 if (is_multicast_ether_addr(mac)) 467 lmac->mcast_filters_count--; 468 469 if (!lmac->mcast_filters_count) { 470 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 471 cfg &= ~GENMASK_ULL(2, 1); 472 cfg |= CGX_DMAC_MCAST_MODE; 473 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 474 } 475 476 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 477 478 return 0; 479 } 480 481 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id) 482 { 483 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 484 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 485 486 if (lmac) 487 return lmac->mac_to_index_bmap.max; 488 489 return 0; 490 } 491 492 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 493 { 494 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 495 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 496 struct mac_ops *mac_ops; 497 int index; 498 u64 cfg; 499 int id; 500 501 mac_ops = cgx_dev->mac_ops; 502 503 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 504 505 index = id * lmac->mac_to_index_bmap.max; 506 507 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8); 508 return cfg & CGX_RX_DMAC_ADR_MASK; 509 } 510 511 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 512 { 513 struct cgx *cgx = cgxd; 514 515 if (!is_lmac_valid(cgx, lmac_id)) 516 return -ENODEV; 517 518 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F)); 519 return 0; 520 } 521 522 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) 523 { 524 struct cgx *cgx = cgxd; 525 u64 cfg; 526 527 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 528 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 529 } 530 531 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id) 532 { 533 struct cgx *cgx = cgxd; 534 u8 num_lmacs; 535 u32 fifo_len; 536 537 fifo_len = cgx->fifo_len; 538 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx); 539 540 switch (num_lmacs) { 541 case 1: 542 return fifo_len; 543 case 2: 544 return fifo_len / 2; 545 case 3: 546 /* LMAC0 gets half of the FIFO, reset 1/4th */ 547 if (lmac_id == 0) 548 return fifo_len / 2; 549 return fifo_len / 4; 550 case 4: 551 default: 552 return fifo_len / 4; 553 } 554 return 0; 555 } 556 557 /* Configure CGX LMAC in internal loopback mode */ 558 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 559 { 560 struct cgx *cgx = cgxd; 561 struct lmac *lmac; 562 u64 cfg; 563 564 if (!is_lmac_valid(cgx, lmac_id)) 565 return -ENODEV; 566 567 lmac = lmac_pdata(lmac_id, cgx); 568 if (lmac->lmac_type == LMAC_MODE_SGMII || 569 lmac->lmac_type == LMAC_MODE_QSGMII) { 570 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 571 if (enable) 572 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 573 else 574 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 575 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 576 } else { 577 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 578 if (enable) 579 cfg |= CGXX_SPUX_CONTROL1_LBK; 580 else 581 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 582 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 583 } 584 return 0; 585 } 586 587 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 588 { 589 struct cgx *cgx = cgx_get_pdata(cgx_id); 590 struct lmac *lmac = lmac_pdata(lmac_id, cgx); 591 struct mac_ops *mac_ops; 592 u16 max_dmac; 593 int index, i; 594 u64 cfg = 0; 595 int id; 596 597 if (!cgx || !lmac) 598 return; 599 600 max_dmac = lmac->mac_to_index_bmap.max; 601 id = get_sequence_id_of_lmac(cgx, lmac_id); 602 603 mac_ops = cgx->mac_ops; 604 if (enable) { 605 /* Enable promiscuous mode on LMAC */ 606 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 607 cfg &= ~CGX_DMAC_CAM_ACCEPT; 608 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 609 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 610 611 for (i = 0; i < max_dmac; i++) { 612 index = id * max_dmac + i; 613 cfg = cgx_read(cgx, 0, 614 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 615 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 616 cgx_write(cgx, 0, 617 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg); 618 } 619 } else { 620 /* Disable promiscuous mode */ 621 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 622 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 623 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 624 for (i = 0; i < max_dmac; i++) { 625 index = id * max_dmac + i; 626 cfg = cgx_read(cgx, 0, 627 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 628 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) { 629 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 630 cgx_write(cgx, 0, 631 (CGXX_CMRX_RX_DMAC_CAM0 + 632 index * 0x8), 633 cfg); 634 } 635 } 636 } 637 } 638 639 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, 640 u8 *tx_pause, u8 *rx_pause) 641 { 642 struct cgx *cgx = cgxd; 643 u64 cfg; 644 645 if (is_dev_rpm(cgx)) 646 return 0; 647 648 if (!is_lmac_valid(cgx, lmac_id)) 649 return -ENODEV; 650 651 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 652 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK); 653 654 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 655 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV); 656 return 0; 657 } 658 659 /* Enable or disable forwarding received pause frames to Tx block */ 660 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 661 { 662 struct cgx *cgx = cgxd; 663 u8 rx_pause, tx_pause; 664 bool is_pfc_enabled; 665 struct lmac *lmac; 666 u64 cfg; 667 668 if (!cgx) 669 return; 670 671 lmac = lmac_pdata(lmac_id, cgx); 672 if (!lmac) 673 return; 674 675 /* Pause frames are not enabled just return */ 676 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 677 return; 678 679 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause); 680 is_pfc_enabled = rx_pause ? false : true; 681 682 if (enable) { 683 if (!is_pfc_enabled) { 684 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 685 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 686 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 687 688 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 689 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 690 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 691 } else { 692 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 693 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN; 694 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 695 } 696 } else { 697 698 if (!is_pfc_enabled) { 699 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 700 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 701 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 702 703 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 704 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 705 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 706 } else { 707 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 708 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN; 709 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 710 } 711 } 712 } 713 714 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 715 { 716 struct cgx *cgx = cgxd; 717 718 if (!is_lmac_valid(cgx, lmac_id)) 719 return -ENODEV; 720 721 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */ 722 if (idx >= CGX_RX_STAT_GLOBAL_INDEX) 723 lmac_id = 0; 724 725 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 726 return 0; 727 } 728 729 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 730 { 731 struct cgx *cgx = cgxd; 732 733 if (!is_lmac_valid(cgx, lmac_id)) 734 return -ENODEV; 735 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 736 return 0; 737 } 738 739 u64 cgx_features_get(void *cgxd) 740 { 741 return ((struct cgx *)cgxd)->hw_features; 742 } 743 744 int cgx_stats_reset(void *cgxd, int lmac_id) 745 { 746 struct cgx *cgx = cgxd; 747 int stat_id; 748 749 if (!is_lmac_valid(cgx, lmac_id)) 750 return -ENODEV; 751 752 for (stat_id = 0 ; stat_id < CGX_RX_STATS_COUNT; stat_id++) { 753 if (stat_id >= CGX_RX_STAT_GLOBAL_INDEX) 754 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */ 755 cgx_write(cgx, 0, 756 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0); 757 else 758 cgx_write(cgx, lmac_id, 759 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0); 760 } 761 762 for (stat_id = 0 ; stat_id < CGX_TX_STATS_COUNT; stat_id++) 763 cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0); 764 765 return 0; 766 } 767 768 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) 769 { 770 if (!linfo->fec) 771 return 0; 772 773 switch (linfo->lmac_type_id) { 774 case LMAC_MODE_SGMII: 775 case LMAC_MODE_XAUI: 776 case LMAC_MODE_RXAUI: 777 case LMAC_MODE_QSGMII: 778 return 0; 779 case LMAC_MODE_10G_R: 780 case LMAC_MODE_25G_R: 781 case LMAC_MODE_100G_R: 782 case LMAC_MODE_USXGMII: 783 return 1; 784 case LMAC_MODE_40G_R: 785 return 4; 786 case LMAC_MODE_50G_R: 787 if (linfo->fec == OTX2_FEC_BASER) 788 return 2; 789 else 790 return 1; 791 default: 792 return 0; 793 } 794 } 795 796 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 797 { 798 int stats, fec_stats_count = 0; 799 int corr_reg, uncorr_reg; 800 struct cgx *cgx = cgxd; 801 802 if (!is_lmac_valid(cgx, lmac_id)) 803 return -ENODEV; 804 805 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE) 806 return 0; 807 808 fec_stats_count = 809 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); 810 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 811 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS; 812 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS; 813 } else { 814 corr_reg = CGXX_SPUX_RSFEC_CORR; 815 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR; 816 } 817 for (stats = 0; stats < fec_stats_count; stats++) { 818 rsp->fec_corr_blks += 819 cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); 820 rsp->fec_uncorr_blks += 821 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); 822 } 823 return 0; 824 } 825 826 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 827 { 828 struct cgx *cgx = cgxd; 829 u64 cfg; 830 831 if (!is_lmac_valid(cgx, lmac_id)) 832 return -ENODEV; 833 834 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 835 if (enable) 836 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN; 837 else 838 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN); 839 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 840 return 0; 841 } 842 843 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 844 { 845 struct cgx *cgx = cgxd; 846 u64 cfg, last; 847 848 if (!is_lmac_valid(cgx, lmac_id)) 849 return -ENODEV; 850 851 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 852 last = cfg; 853 if (enable) 854 cfg |= DATA_PKT_TX_EN; 855 else 856 cfg &= ~DATA_PKT_TX_EN; 857 858 if (cfg != last) 859 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 860 return !!(last & DATA_PKT_TX_EN); 861 } 862 863 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, 864 u8 tx_pause, u8 rx_pause) 865 { 866 struct cgx *cgx = cgxd; 867 u64 cfg; 868 869 if (is_dev_rpm(cgx)) 870 return 0; 871 872 if (!is_lmac_valid(cgx, lmac_id)) 873 return -ENODEV; 874 875 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 876 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 877 cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0; 878 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 879 880 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 881 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 882 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0; 883 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 884 885 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 886 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 887 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0; 888 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 889 890 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 891 if (tx_pause) { 892 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id); 893 } else { 894 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 895 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 896 } 897 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 898 return 0; 899 } 900 901 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 902 { 903 struct cgx *cgx = cgxd; 904 u64 cfg; 905 906 if (!is_lmac_valid(cgx, lmac_id)) 907 return; 908 909 if (enable) { 910 /* Set pause time and interval */ 911 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME, 912 DEFAULT_PAUSE_TIME); 913 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); 914 cfg &= ~0xFFFFULL; 915 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, 916 cfg | (DEFAULT_PAUSE_TIME / 2)); 917 918 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, 919 DEFAULT_PAUSE_TIME); 920 921 cfg = cgx_read(cgx, lmac_id, 922 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); 923 cfg &= ~0xFFFFULL; 924 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, 925 cfg | (DEFAULT_PAUSE_TIME / 2)); 926 } 927 928 /* ALL pause frames received are completely ignored */ 929 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 930 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 931 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 932 933 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 934 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 935 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 936 937 /* Disable pause frames transmission */ 938 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 939 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 940 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 941 942 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 943 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 944 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 945 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 946 947 /* Disable all PFC classes by default */ 948 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 949 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 950 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 951 } 952 953 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 954 int pfvf_idx) 955 { 956 struct cgx *cgx = cgxd; 957 struct lmac *lmac; 958 959 lmac = lmac_pdata(lmac_id, cgx); 960 if (!lmac) 961 return -ENODEV; 962 963 if (!rx_pause) 964 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 965 else 966 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 967 968 if (!tx_pause) 969 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 970 else 971 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 972 973 /* check if other pfvfs are using flow control */ 974 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) { 975 dev_warn(&cgx->pdev->dev, 976 "Receive Flow control disable not permitted as its used by other PFVFs\n"); 977 return -EPERM; 978 } 979 980 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) { 981 dev_warn(&cgx->pdev->dev, 982 "Transmit Flow control disable not permitted as its used by other PFVFs\n"); 983 return -EPERM; 984 } 985 986 return 0; 987 } 988 989 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, 990 u8 rx_pause, u16 pfc_en) 991 { 992 struct cgx *cgx = cgxd; 993 u64 cfg; 994 995 if (!is_lmac_valid(cgx, lmac_id)) 996 return -ENODEV; 997 998 /* Return as no traffic classes are requested */ 999 if (tx_pause && !pfc_en) 1000 return 0; 1001 1002 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 1003 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg); 1004 1005 if (rx_pause) { 1006 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN | 1007 CGXX_SMUX_CBFC_CTL_BCK_EN | 1008 CGXX_SMUX_CBFC_CTL_DRP_EN); 1009 } else { 1010 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN | 1011 CGXX_SMUX_CBFC_CTL_BCK_EN | 1012 CGXX_SMUX_CBFC_CTL_DRP_EN); 1013 } 1014 1015 if (tx_pause) { 1016 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN; 1017 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); 1018 } else { 1019 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN; 1020 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 1021 } 1022 1023 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 1024 1025 /* Write source MAC address which will be filled into PFC packet */ 1026 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id); 1027 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg); 1028 1029 return 0; 1030 } 1031 1032 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, 1033 u8 *rx_pause) 1034 { 1035 struct cgx *cgx = cgxd; 1036 u64 cfg; 1037 1038 if (!is_lmac_valid(cgx, lmac_id)) 1039 return -ENODEV; 1040 1041 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 1042 1043 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN); 1044 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN); 1045 1046 return 0; 1047 } 1048 1049 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 1050 { 1051 struct cgx *cgx = cgxd; 1052 u64 cfg; 1053 1054 if (!cgx) 1055 return; 1056 1057 if (enable) { 1058 /* Enable inbound PTP timestamping */ 1059 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 1060 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 1061 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 1062 1063 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1064 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1065 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1066 } else { 1067 /* Disable inbound PTP stamping */ 1068 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 1069 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 1070 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 1071 1072 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1073 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1074 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1075 } 1076 } 1077 1078 /* CGX Firmware interface low level support */ 1079 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 1080 { 1081 struct cgx *cgx = lmac->cgx; 1082 struct device *dev; 1083 int err = 0; 1084 u64 cmd; 1085 1086 /* Ensure no other command is in progress */ 1087 err = mutex_lock_interruptible(&lmac->cmd_lock); 1088 if (err) 1089 return err; 1090 1091 /* Ensure command register is free */ 1092 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 1093 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 1094 err = -EBUSY; 1095 goto unlock; 1096 } 1097 1098 /* Update ownership in command request */ 1099 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 1100 1101 /* Mark this lmac as pending, before we start */ 1102 lmac->cmd_pend = true; 1103 1104 /* Start command in hardware */ 1105 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 1106 1107 /* Ensure command is completed without errors */ 1108 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 1109 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 1110 dev = &cgx->pdev->dev; 1111 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n", 1112 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req)); 1113 err = LMAC_AF_ERR_CMD_TIMEOUT; 1114 goto unlock; 1115 } 1116 1117 /* we have a valid command response */ 1118 smp_rmb(); /* Ensure the latest updates are visible */ 1119 *resp = lmac->resp; 1120 1121 unlock: 1122 mutex_unlock(&lmac->cmd_lock); 1123 1124 return err; 1125 } 1126 1127 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) 1128 { 1129 struct lmac *lmac; 1130 int err; 1131 1132 lmac = lmac_pdata(lmac_id, cgx); 1133 if (!lmac) 1134 return -ENODEV; 1135 1136 err = cgx_fwi_cmd_send(req, resp, lmac); 1137 1138 /* Check for valid response */ 1139 if (!err) { 1140 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 1141 return -EIO; 1142 else 1143 return 0; 1144 } 1145 1146 return err; 1147 } 1148 1149 static int cgx_link_usertable_index_map(int speed) 1150 { 1151 switch (speed) { 1152 case SPEED_10: 1153 return CGX_LINK_10M; 1154 case SPEED_100: 1155 return CGX_LINK_100M; 1156 case SPEED_1000: 1157 return CGX_LINK_1G; 1158 case SPEED_2500: 1159 return CGX_LINK_2HG; 1160 case SPEED_5000: 1161 return CGX_LINK_5G; 1162 case SPEED_10000: 1163 return CGX_LINK_10G; 1164 case SPEED_20000: 1165 return CGX_LINK_20G; 1166 case SPEED_25000: 1167 return CGX_LINK_25G; 1168 case SPEED_40000: 1169 return CGX_LINK_40G; 1170 case SPEED_50000: 1171 return CGX_LINK_50G; 1172 case 80000: 1173 return CGX_LINK_80G; 1174 case SPEED_100000: 1175 return CGX_LINK_100G; 1176 case SPEED_UNKNOWN: 1177 return CGX_LINK_NONE; 1178 } 1179 return CGX_LINK_NONE; 1180 } 1181 1182 static void set_mod_args(struct cgx_set_link_mode_args *args, 1183 u32 speed, u8 duplex, u8 autoneg, u64 mode) 1184 { 1185 int mode_baseidx; 1186 u8 cgx_mode; 1187 1188 if (args->multimode) { 1189 args->mode |= mode; 1190 return; 1191 } 1192 1193 /* Derive mode_base_idx and mode fields based 1194 * on cgx_mode value 1195 */ 1196 cgx_mode = find_first_bit((unsigned long *)&mode, 1197 CGX_MODE_MAX); 1198 args->mode = mode; 1199 mode_baseidx = cgx_mode - 41; 1200 if (mode_baseidx > 0) { 1201 args->mode_baseidx = 1; 1202 args->mode = BIT_ULL(mode_baseidx); 1203 } 1204 } 1205 1206 static void otx2_map_ethtool_link_modes(u64 bitmask, 1207 struct cgx_set_link_mode_args *args) 1208 { 1209 switch (bitmask) { 1210 case ETHTOOL_LINK_MODE_10baseT_Half_BIT: 1211 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); 1212 break; 1213 case ETHTOOL_LINK_MODE_10baseT_Full_BIT: 1214 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); 1215 break; 1216 case ETHTOOL_LINK_MODE_100baseT_Half_BIT: 1217 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); 1218 break; 1219 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1220 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); 1221 break; 1222 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: 1223 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1224 break; 1225 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1226 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1227 break; 1228 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT: 1229 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX)); 1230 break; 1231 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT: 1232 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII)); 1233 break; 1234 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT: 1235 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C)); 1236 break; 1237 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT: 1238 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M)); 1239 break; 1240 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT: 1241 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR)); 1242 break; 1243 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 1244 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C)); 1245 break; 1246 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 1247 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR)); 1248 break; 1249 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 1250 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR)); 1251 break; 1252 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 1253 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C)); 1254 break; 1255 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 1256 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M)); 1257 break; 1258 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 1259 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4)); 1260 break; 1261 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 1262 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4)); 1263 break; 1264 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 1265 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C)); 1266 break; 1267 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 1268 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M)); 1269 break; 1270 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 1271 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR)); 1272 break; 1273 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 1274 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR)); 1275 break; 1276 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 1277 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C)); 1278 break; 1279 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 1280 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M)); 1281 break; 1282 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 1283 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4)); 1284 break; 1285 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 1286 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4)); 1287 break; 1288 default: 1289 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX)); 1290 break; 1291 } 1292 } 1293 1294 static inline void link_status_user_format(u64 lstat, 1295 struct cgx_link_user_info *linfo, 1296 struct cgx *cgx, u8 lmac_id) 1297 { 1298 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 1299 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 1300 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 1301 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat); 1302 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat); 1303 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat); 1304 1305 if (linfo->lmac_type_id >= LMAC_MODE_MAX) { 1306 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d", 1307 linfo->lmac_type_id, cgx->cgx_id, lmac_id); 1308 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type)); 1309 return; 1310 } 1311 1312 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id], 1313 sizeof(linfo->lmac_type)); 1314 } 1315 1316 /* Hardware event handlers */ 1317 static inline void cgx_link_change_handler(u64 lstat, 1318 struct lmac *lmac) 1319 { 1320 struct cgx_link_user_info *linfo; 1321 struct cgx *cgx = lmac->cgx; 1322 struct cgx_link_event event; 1323 struct device *dev; 1324 int err_type; 1325 1326 dev = &cgx->pdev->dev; 1327 1328 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 1329 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 1330 1331 event.cgx_id = cgx->cgx_id; 1332 event.lmac_id = lmac->lmac_id; 1333 1334 /* update the local copy of link status */ 1335 lmac->link_info = event.link_uinfo; 1336 linfo = &lmac->link_info; 1337 1338 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID) 1339 return; 1340 1341 /* Ensure callback doesn't get unregistered until we finish it */ 1342 spin_lock(&lmac->event_cb_lock); 1343 1344 if (!lmac->event_cb.notify_link_chg) { 1345 dev_dbg(dev, "cgx port %d:%d Link change handler null", 1346 cgx->cgx_id, lmac->lmac_id); 1347 if (err_type != CGX_ERR_NONE) { 1348 dev_err(dev, "cgx port %d:%d Link error %d\n", 1349 cgx->cgx_id, lmac->lmac_id, err_type); 1350 } 1351 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 1352 cgx->cgx_id, lmac->lmac_id, 1353 linfo->link_up ? "UP" : "DOWN", linfo->speed); 1354 goto err; 1355 } 1356 1357 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 1358 dev_err(dev, "event notification failure\n"); 1359 err: 1360 spin_unlock(&lmac->event_cb_lock); 1361 } 1362 1363 static inline bool cgx_cmdresp_is_linkevent(u64 event) 1364 { 1365 u8 id; 1366 1367 id = FIELD_GET(EVTREG_ID, event); 1368 if (id == CGX_CMD_LINK_BRING_UP || 1369 id == CGX_CMD_LINK_BRING_DOWN || 1370 id == CGX_CMD_MODE_CHANGE) 1371 return true; 1372 else 1373 return false; 1374 } 1375 1376 static inline bool cgx_event_is_linkevent(u64 event) 1377 { 1378 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 1379 return true; 1380 else 1381 return false; 1382 } 1383 1384 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 1385 { 1386 u64 event, offset, clear_bit; 1387 struct lmac *lmac = data; 1388 struct cgx *cgx; 1389 1390 cgx = lmac->cgx; 1391 1392 /* Clear SW_INT for RPM and CMR_INT for CGX */ 1393 offset = cgx->mac_ops->int_register; 1394 clear_bit = cgx->mac_ops->int_ena_bit; 1395 1396 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 1397 1398 if (!FIELD_GET(EVTREG_ACK, event)) 1399 return IRQ_NONE; 1400 1401 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 1402 case CGX_EVT_CMD_RESP: 1403 /* Copy the response. Since only one command is active at a 1404 * time, there is no way a response can get overwritten 1405 */ 1406 lmac->resp = event; 1407 /* Ensure response is updated before thread context starts */ 1408 smp_wmb(); 1409 1410 /* There wont be separate events for link change initiated from 1411 * software; Hence report the command responses as events 1412 */ 1413 if (cgx_cmdresp_is_linkevent(event)) 1414 cgx_link_change_handler(event, lmac); 1415 1416 /* Release thread waiting for completion */ 1417 lmac->cmd_pend = false; 1418 wake_up(&lmac->wq_cmd_cmplt); 1419 break; 1420 case CGX_EVT_ASYNC: 1421 if (cgx_event_is_linkevent(event)) 1422 cgx_link_change_handler(event, lmac); 1423 break; 1424 } 1425 1426 /* Any new event or command response will be posted by firmware 1427 * only after the current status is acked. 1428 * Ack the interrupt register as well. 1429 */ 1430 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 1431 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); 1432 1433 return IRQ_HANDLED; 1434 } 1435 1436 /* APIs for PHY management using CGX firmware interface */ 1437 1438 /* callback registration for hardware events like link change */ 1439 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 1440 { 1441 struct cgx *cgx = cgxd; 1442 struct lmac *lmac; 1443 1444 lmac = lmac_pdata(lmac_id, cgx); 1445 if (!lmac) 1446 return -ENODEV; 1447 1448 lmac->event_cb = *cb; 1449 1450 return 0; 1451 } 1452 1453 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 1454 { 1455 struct lmac *lmac; 1456 unsigned long flags; 1457 struct cgx *cgx = cgxd; 1458 1459 lmac = lmac_pdata(lmac_id, cgx); 1460 if (!lmac) 1461 return -ENODEV; 1462 1463 spin_lock_irqsave(&lmac->event_cb_lock, flags); 1464 lmac->event_cb.notify_link_chg = NULL; 1465 lmac->event_cb.data = NULL; 1466 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 1467 1468 return 0; 1469 } 1470 1471 int cgx_get_fwdata_base(u64 *base) 1472 { 1473 u64 req = 0, resp; 1474 struct cgx *cgx; 1475 int first_lmac; 1476 int err; 1477 1478 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list); 1479 if (!cgx) 1480 return -ENXIO; 1481 1482 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1483 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); 1484 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); 1485 if (!err) 1486 *base = FIELD_GET(RESP_FWD_BASE, resp); 1487 1488 return err; 1489 } 1490 1491 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 1492 struct cgx_lmac_fwdata_s *linkmodes, 1493 int cgx_id, int lmac_id) 1494 { 1495 struct cgx *cgx = cgxd; 1496 u64 req = 0, resp; 1497 u8 bit; 1498 1499 if (!cgx) 1500 return -ENODEV; 1501 1502 for_each_set_bit(bit, args.advertising, 1503 __ETHTOOL_LINK_MODE_MASK_NBITS) 1504 otx2_map_ethtool_link_modes(bit, &args); 1505 1506 if (args.multimode) { 1507 if (linkmodes->advertised_link_modes_own != CGX_CMD_OWN_NS) 1508 return -EBUSY; 1509 1510 linkmodes->advertised_link_modes = args.mode; 1511 /* Update ownership */ 1512 linkmodes->advertised_link_modes_own = CGX_CMD_OWN_FIRMWARE; 1513 args.mode = GENMASK_ULL(41, 0); 1514 } 1515 1516 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); 1517 req = FIELD_SET(CMDMODECHANGE_SPEED, 1518 cgx_link_usertable_index_map(args.speed), req); 1519 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); 1520 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); 1521 req = FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req); 1522 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); 1523 1524 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1525 } 1526 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) 1527 { 1528 u64 req = 0, resp; 1529 struct cgx *cgx; 1530 int err = 0; 1531 1532 cgx = cgx_get_pdata(cgx_id); 1533 if (!cgx) 1534 return -ENXIO; 1535 1536 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); 1537 req = FIELD_SET(CMDSETFEC, fec, req); 1538 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1539 if (err) 1540 return err; 1541 1542 cgx->lmac_idmap[lmac_id]->link_info.fec = 1543 FIELD_GET(RESP_LINKSTAT_FEC, resp); 1544 return cgx->lmac_idmap[lmac_id]->link_info.fec; 1545 } 1546 1547 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) 1548 { 1549 struct cgx *cgx = cgxd; 1550 u64 req = 0, resp; 1551 1552 if (!cgx) 1553 return -ENODEV; 1554 1555 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); 1556 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1557 } 1558 1559 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 1560 { 1561 u64 req = 0; 1562 u64 resp; 1563 1564 if (enable) { 1565 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 1566 /* On CN10K firmware offloads link bring up/down operations to ECP 1567 * On Octeontx2 link operations are handled by firmware itself 1568 * which can cause mbox errors so configure maximum time firmware 1569 * poll for Link as 1000 ms 1570 */ 1571 if (!is_dev_rpm(cgx)) 1572 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req); 1573 1574 } else { 1575 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 1576 } 1577 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1578 } 1579 1580 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 1581 { 1582 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1583 u64 req = 0; 1584 1585 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 1586 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); 1587 } 1588 1589 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 1590 { 1591 struct device *dev = &cgx->pdev->dev; 1592 int major_ver, minor_ver; 1593 u64 resp; 1594 int err; 1595 1596 if (!cgx->lmac_count) 1597 return 0; 1598 1599 err = cgx_fwi_read_version(&resp, cgx); 1600 if (err) 1601 return err; 1602 1603 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 1604 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 1605 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 1606 major_ver, minor_ver); 1607 if (major_ver != CGX_FIRMWARE_MAJOR_VER) 1608 return -EIO; 1609 else 1610 return 0; 1611 } 1612 1613 static void cgx_lmac_linkup_work(struct work_struct *work) 1614 { 1615 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 1616 struct device *dev = &cgx->pdev->dev; 1617 int i, err; 1618 1619 /* Do Link up for all the enabled lmacs */ 1620 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1621 err = cgx_fwi_link_change(cgx, i, true); 1622 if (err) 1623 dev_info(dev, "cgx port %d:%d Link up command failed\n", 1624 cgx->cgx_id, i); 1625 } 1626 } 1627 1628 int cgx_lmac_linkup_start(void *cgxd) 1629 { 1630 struct cgx *cgx = cgxd; 1631 1632 if (!cgx) 1633 return -ENODEV; 1634 1635 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 1636 1637 return 0; 1638 } 1639 1640 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr) 1641 { 1642 struct cgx *cgx = cgxd; 1643 u64 cfg; 1644 1645 if (!is_lmac_valid(cgx, lmac_id)) 1646 return -ENODEV; 1647 1648 /* Resetting PFC related CSRs */ 1649 cfg = 0xff; 1650 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg); 1651 1652 if (pf_req_flr) 1653 cgx_lmac_internal_loopback(cgxd, lmac_id, false); 1654 return 0; 1655 } 1656 1657 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, 1658 int cnt, bool req_free) 1659 { 1660 struct mac_ops *mac_ops = cgx->mac_ops; 1661 u64 offset, ena_bit; 1662 unsigned int irq; 1663 int err; 1664 1665 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + 1666 cnt * mac_ops->irq_offset); 1667 offset = mac_ops->int_set_reg; 1668 ena_bit = mac_ops->int_ena_bit; 1669 1670 if (req_free) { 1671 free_irq(irq, lmac); 1672 return 0; 1673 } 1674 1675 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); 1676 if (err) 1677 return err; 1678 1679 /* Enable interrupt */ 1680 cgx_write(cgx, lmac->lmac_id, offset, ena_bit); 1681 return 0; 1682 } 1683 1684 int cgx_get_nr_lmacs(void *cgxd) 1685 { 1686 struct cgx *cgx = cgxd; 1687 1688 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL; 1689 } 1690 1691 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) 1692 { 1693 struct cgx *cgx = cgxd; 1694 1695 return cgx->lmac_idmap[lmac_index]->lmac_id; 1696 } 1697 1698 unsigned long cgx_get_lmac_bmap(void *cgxd) 1699 { 1700 struct cgx *cgx = cgxd; 1701 1702 return cgx->lmac_bmap; 1703 } 1704 1705 static int cgx_lmac_init(struct cgx *cgx) 1706 { 1707 u8 max_dmac_filters; 1708 struct lmac *lmac; 1709 int err, filter; 1710 unsigned int i; 1711 u64 lmac_list; 1712 1713 /* lmac_list specifies which lmacs are enabled 1714 * when bit n is set to 1, LMAC[n] is enabled 1715 */ 1716 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1717 if (is_dev_rpm2(cgx)) 1718 lmac_list = 1719 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL; 1720 else 1721 lmac_list = 1722 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL; 1723 } 1724 1725 if (cgx->lmac_count > cgx->max_lmac_per_mac) 1726 cgx->lmac_count = cgx->max_lmac_per_mac; 1727 1728 for (i = 0; i < cgx->lmac_count; i++) { 1729 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL); 1730 if (!lmac) 1731 return -ENOMEM; 1732 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 1733 if (!lmac->name) { 1734 err = -ENOMEM; 1735 goto err_lmac_free; 1736 } 1737 sprintf(lmac->name, "cgx_fwi_%u_%u", cgx->cgx_id, i); 1738 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1739 lmac->lmac_id = __ffs64(lmac_list); 1740 lmac_list &= ~BIT_ULL(lmac->lmac_id); 1741 } else { 1742 lmac->lmac_id = i; 1743 } 1744 1745 lmac->cgx = cgx; 1746 lmac->mac_to_index_bmap.max = 1747 cgx->mac_ops->dmac_filter_count / 1748 cgx->lmac_count; 1749 1750 max_dmac_filters = lmac->mac_to_index_bmap.max; 1751 1752 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap); 1753 if (err) 1754 goto err_name_free; 1755 1756 /* Reserve first entry for default MAC address */ 1757 set_bit(0, lmac->mac_to_index_bmap.bmap); 1758 1759 lmac->rx_fc_pfvf_bmap.max = 128; 1760 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap); 1761 if (err) 1762 goto err_dmac_bmap_free; 1763 1764 lmac->tx_fc_pfvf_bmap.max = 128; 1765 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap); 1766 if (err) 1767 goto err_rx_fc_bmap_free; 1768 1769 init_waitqueue_head(&lmac->wq_cmd_cmplt); 1770 mutex_init(&lmac->cmd_lock); 1771 spin_lock_init(&lmac->event_cb_lock); 1772 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); 1773 if (err) 1774 goto err_bitmap_free; 1775 1776 /* Add reference */ 1777 cgx->lmac_idmap[lmac->lmac_id] = lmac; 1778 set_bit(lmac->lmac_id, &cgx->lmac_bmap); 1779 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); 1780 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id); 1781 1782 /* Disable stale DMAC filters for sane state */ 1783 for (filter = 0; filter < max_dmac_filters; filter++) 1784 cgx_lmac_addr_del(cgx->cgx_id, lmac->lmac_id, filter); 1785 1786 /* As cgx_lmac_addr_del does not clear entry for index 0 1787 * so it needs to be done explicitly 1788 */ 1789 cgx_lmac_addr_reset(cgx->cgx_id, lmac->lmac_id); 1790 } 1791 1792 /* Start X2P reset on given MAC block */ 1793 cgx->mac_ops->mac_x2p_reset(cgx, true); 1794 return cgx_lmac_verify_fwi_version(cgx); 1795 1796 err_bitmap_free: 1797 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap); 1798 err_rx_fc_bmap_free: 1799 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap); 1800 err_dmac_bmap_free: 1801 rvu_free_bitmap(&lmac->mac_to_index_bmap); 1802 err_name_free: 1803 kfree(lmac->name); 1804 err_lmac_free: 1805 kfree(lmac); 1806 return err; 1807 } 1808 1809 static int cgx_lmac_exit(struct cgx *cgx) 1810 { 1811 struct lmac *lmac; 1812 int i; 1813 1814 if (cgx->cgx_cmd_workq) { 1815 destroy_workqueue(cgx->cgx_cmd_workq); 1816 cgx->cgx_cmd_workq = NULL; 1817 } 1818 1819 /* Free all lmac related resources */ 1820 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1821 lmac = cgx->lmac_idmap[i]; 1822 if (!lmac) 1823 continue; 1824 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); 1825 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); 1826 kfree(lmac->mac_to_index_bmap.bmap); 1827 kfree(lmac->name); 1828 kfree(lmac); 1829 } 1830 1831 return 0; 1832 } 1833 1834 static void cgx_populate_features(struct cgx *cgx) 1835 { 1836 u64 cfg; 1837 1838 cfg = cgx_read(cgx, 0, CGX_CONST); 1839 cgx->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg); 1840 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg); 1841 1842 if (is_dev_rpm(cgx)) 1843 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM | 1844 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP); 1845 else 1846 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 | 1847 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF); 1848 } 1849 1850 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx) 1851 { 1852 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM || 1853 is_dev_rpm2(cgx)) 1854 return 0x80; 1855 else 1856 return 0x60; 1857 } 1858 1859 static void cgx_x2p_reset(void *cgxd, bool enable) 1860 { 1861 struct cgx *cgx = cgxd; 1862 int lmac_id; 1863 u64 cfg; 1864 1865 if (enable) { 1866 for_each_set_bit(lmac_id, &cgx->lmac_bmap, cgx->max_lmac_per_mac) 1867 cgx->mac_ops->mac_enadis_rx(cgx, lmac_id, false); 1868 1869 usleep_range(1000, 2000); 1870 1871 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG); 1872 cfg |= cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP; 1873 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg); 1874 } else { 1875 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG); 1876 cfg &= ~(cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP); 1877 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg); 1878 } 1879 } 1880 1881 static int cgx_enadis_rx(void *cgxd, int lmac_id, bool enable) 1882 { 1883 struct cgx *cgx = cgxd; 1884 u64 cfg; 1885 1886 if (!is_lmac_valid(cgx, lmac_id)) 1887 return -ENODEV; 1888 1889 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 1890 if (enable) 1891 cfg |= DATA_PKT_RX_EN; 1892 else 1893 cfg &= ~DATA_PKT_RX_EN; 1894 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 1895 return 0; 1896 } 1897 1898 static struct mac_ops cgx_mac_ops = { 1899 .name = "cgx", 1900 .csr_offset = 0, 1901 .lmac_offset = 18, 1902 .int_register = CGXX_CMRX_INT, 1903 .int_set_reg = CGXX_CMRX_INT_ENA_W1S, 1904 .irq_offset = 9, 1905 .int_ena_bit = FW_CGX_INT, 1906 .lmac_fwi = CGX_LMAC_FWI, 1907 .non_contiguous_serdes_lane = false, 1908 .rx_stats_cnt = 9, 1909 .tx_stats_cnt = 18, 1910 .dmac_filter_count = 32, 1911 .get_nr_lmacs = cgx_get_nr_lmacs, 1912 .get_lmac_type = cgx_get_lmac_type, 1913 .lmac_fifo_len = cgx_get_lmac_fifo_len, 1914 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, 1915 .mac_get_rx_stats = cgx_get_rx_stats, 1916 .mac_get_tx_stats = cgx_get_tx_stats, 1917 .get_fec_stats = cgx_get_fec_stats, 1918 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, 1919 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, 1920 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, 1921 .mac_pause_frm_config = cgx_lmac_pause_frm_config, 1922 .mac_enadis_ptp_config = cgx_lmac_ptp_config, 1923 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable, 1924 .mac_tx_enable = cgx_lmac_tx_enable, 1925 .pfc_config = cgx_lmac_pfc_config, 1926 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg, 1927 .mac_reset = cgx_lmac_reset, 1928 .mac_stats_reset = cgx_stats_reset, 1929 .mac_x2p_reset = cgx_x2p_reset, 1930 .mac_enadis_rx = cgx_enadis_rx, 1931 }; 1932 1933 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1934 { 1935 struct device *dev = &pdev->dev; 1936 struct cgx *cgx; 1937 int err, nvec; 1938 1939 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 1940 if (!cgx) 1941 return -ENOMEM; 1942 cgx->pdev = pdev; 1943 1944 pci_set_drvdata(pdev, cgx); 1945 1946 /* Use mac_ops to get MAC specific features */ 1947 if (is_dev_rpm(cgx)) 1948 cgx->mac_ops = rpm_get_mac_ops(cgx); 1949 else 1950 cgx->mac_ops = &cgx_mac_ops; 1951 1952 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx); 1953 1954 err = pci_enable_device(pdev); 1955 if (err) { 1956 dev_err(dev, "Failed to enable PCI device\n"); 1957 pci_set_drvdata(pdev, NULL); 1958 return err; 1959 } 1960 1961 err = pci_request_regions(pdev, DRV_NAME); 1962 if (err) { 1963 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1964 goto err_disable_device; 1965 } 1966 1967 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 1968 if (err) { 1969 dev_err(dev, "DMA mask config failed, abort\n"); 1970 goto err_release_regions; 1971 } 1972 1973 /* MAP configuration registers */ 1974 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1975 if (!cgx->reg_base) { 1976 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 1977 err = -ENOMEM; 1978 goto err_release_regions; 1979 } 1980 1981 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); 1982 if (!cgx->lmac_count) { 1983 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id); 1984 err = -EOPNOTSUPP; 1985 goto err_release_regions; 1986 } 1987 1988 nvec = pci_msix_vec_count(cgx->pdev); 1989 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1990 if (err < 0 || err != nvec) { 1991 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 1992 nvec, err); 1993 goto err_release_regions; 1994 } 1995 1996 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 1997 & CGX_ID_MASK; 1998 1999 /* init wq for processing linkup requests */ 2000 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 2001 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 2002 if (!cgx->cgx_cmd_workq) { 2003 dev_err(dev, "alloc workqueue failed for cgx cmd"); 2004 err = -ENOMEM; 2005 goto err_free_irq_vectors; 2006 } 2007 2008 list_add(&cgx->cgx_list, &cgx_list); 2009 2010 2011 cgx_populate_features(cgx); 2012 2013 mutex_init(&cgx->lock); 2014 2015 err = cgx_lmac_init(cgx); 2016 if (err) 2017 goto err_release_lmac; 2018 2019 return 0; 2020 2021 err_release_lmac: 2022 cgx_lmac_exit(cgx); 2023 list_del(&cgx->cgx_list); 2024 err_free_irq_vectors: 2025 pci_free_irq_vectors(pdev); 2026 err_release_regions: 2027 pci_release_regions(pdev); 2028 err_disable_device: 2029 pci_disable_device(pdev); 2030 pci_set_drvdata(pdev, NULL); 2031 return err; 2032 } 2033 2034 static void cgx_remove(struct pci_dev *pdev) 2035 { 2036 struct cgx *cgx = pci_get_drvdata(pdev); 2037 2038 if (cgx) { 2039 cgx_lmac_exit(cgx); 2040 list_del(&cgx->cgx_list); 2041 } 2042 pci_free_irq_vectors(pdev); 2043 pci_release_regions(pdev); 2044 pci_disable_device(pdev); 2045 pci_set_drvdata(pdev, NULL); 2046 } 2047 2048 struct pci_driver cgx_driver = { 2049 .name = DRV_NAME, 2050 .id_table = cgx_id_table, 2051 .probe = cgx_probe, 2052 .remove = cgx_remove, 2053 }; 2054