1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_TX_H_ 9 #define _OCTEP_TX_H_ 10 11 #define IQ_SEND_OK 0 12 #define IQ_SEND_STOP 1 13 #define IQ_SEND_FAILED -1 14 15 #define TX_BUFTYPE_NONE 0 16 #define TX_BUFTYPE_NET 1 17 #define TX_BUFTYPE_NET_SG 2 18 #define NUM_TX_BUFTYPES 3 19 20 /* Hardware format for Scatter/Gather list */ 21 struct octep_tx_sglist_desc { 22 u16 len[4]; 23 dma_addr_t dma_ptr[4]; 24 }; 25 26 /* Each Scatter/Gather entry sent to hardwar hold four pointers. 27 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1' 28 * is for main skb which also goes as a gather buffer to Octeon hardware. 29 * To allocate sufficient SGLIST entries for a packet with max fragments, 30 * align by adding 3 before calcuating max SGLIST entries per packet. 31 */ 32 #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4) 33 #define OCTEP_SGLIST_SIZE_PER_PKT \ 34 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc)) 35 36 struct octep_tx_buffer { 37 struct sk_buff *skb; 38 dma_addr_t dma; 39 struct octep_tx_sglist_desc *sglist; 40 dma_addr_t sglist_dma; 41 u8 gather; 42 }; 43 44 #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer)) 45 46 /* Hardware interface Tx statistics */ 47 struct octep_iface_tx_stats { 48 /* Packets dropped due to excessive collisions */ 49 u64 xscol; 50 51 /* Packets dropped due to excessive deferral */ 52 u64 xsdef; 53 54 /* Packets sent that experienced multiple collisions before successful 55 * transmission 56 */ 57 u64 mcol; 58 59 /* Packets sent that experienced a single collision before successful 60 * transmission 61 */ 62 u64 scol; 63 64 /* Total octets sent on the interface */ 65 u64 octs; 66 67 /* Total frames sent on the interface */ 68 u64 pkts; 69 70 /* Packets sent with an octet count < 64 */ 71 u64 hist_lt64; 72 73 /* Packets sent with an octet count == 64 */ 74 u64 hist_eq64; 75 76 /* Packets sent with an octet count of 65–127 */ 77 u64 hist_65to127; 78 79 /* Packets sent with an octet count of 128–255 */ 80 u64 hist_128to255; 81 82 /* Packets sent with an octet count of 256–511 */ 83 u64 hist_256to511; 84 85 /* Packets sent with an octet count of 512–1023 */ 86 u64 hist_512to1023; 87 88 /* Packets sent with an octet count of 1024-1518 */ 89 u64 hist_1024to1518; 90 91 /* Packets sent with an octet count of > 1518 */ 92 u64 hist_gt1518; 93 94 /* Packets sent to a broadcast DMAC */ 95 u64 bcst; 96 97 /* Packets sent to the multicast DMAC */ 98 u64 mcst; 99 100 /* Packets sent that experienced a transmit underflow and were 101 * truncated 102 */ 103 u64 undflw; 104 105 /* Control/PAUSE packets sent */ 106 u64 ctl; 107 }; 108 109 /* Input Queue statistics. Each input queue has four stats fields. */ 110 struct octep_iq_stats { 111 /* Instructions posted to this queue. */ 112 u64 instr_posted; 113 114 /* Instructions copied by hardware for processing. */ 115 u64 instr_completed; 116 117 /* Instructions that could not be processed. */ 118 u64 instr_dropped; 119 120 /* Bytes sent through this queue. */ 121 u64 bytes_sent; 122 123 /* Gather entries sent through this queue. */ 124 u64 sgentry_sent; 125 126 /* Number of transmit failures due to TX_BUSY */ 127 u64 tx_busy; 128 129 /* Number of times the queue is restarted */ 130 u64 restart_cnt; 131 }; 132 133 /* The instruction (input) queue. 134 * The input queue is used to post raw (instruction) mode data or packet 135 * data to Octeon device from the host. Each input queue (up to 4) for 136 * a Octeon device has one such structure to represent it. 137 */ 138 struct octep_iq { 139 u32 q_no; 140 141 struct octep_device *octep_dev; 142 struct net_device *netdev; 143 struct device *dev; 144 struct netdev_queue *netdev_q; 145 146 /* Index in input ring where driver should write the next packet */ 147 u16 host_write_index; 148 149 /* Index in input ring where Octeon is expected to read next packet */ 150 u16 octep_read_index; 151 152 /* This index aids in finding the window in the queue where Octeon 153 * has read the commands. 154 */ 155 u16 flush_index; 156 157 /* Statistics for this input queue. */ 158 struct octep_iq_stats stats; 159 160 /* This field keeps track of the instructions pending in this queue. */ 161 atomic_t instr_pending; 162 163 /* Pointer to the Virtual Base addr of the input ring. */ 164 struct octep_tx_desc_hw *desc_ring; 165 166 /* DMA mapped base address of the input descriptor ring. */ 167 dma_addr_t desc_ring_dma; 168 169 /* Info of Tx buffers pending completion. */ 170 struct octep_tx_buffer *buff_info; 171 172 /* Base pointer to Scatter/Gather lists for all ring descriptors. */ 173 struct octep_tx_sglist_desc *sglist; 174 175 /* DMA mapped addr of Scatter Gather Lists */ 176 dma_addr_t sglist_dma; 177 178 /* Octeon doorbell register for the ring. */ 179 u8 __iomem *doorbell_reg; 180 181 /* Octeon instruction count register for this ring. */ 182 u8 __iomem *inst_cnt_reg; 183 184 /* interrupt level register for this ring */ 185 u8 __iomem *intr_lvl_reg; 186 187 /* Maximum no. of instructions in this queue. */ 188 u32 max_count; 189 u32 ring_size_mask; 190 191 u32 pkt_in_done; 192 u32 pkts_processed; 193 194 u32 status; 195 196 /* Number of instructions pending to be posted to Octeon. */ 197 u32 fill_cnt; 198 199 /* The max. number of instructions that can be held pending by the 200 * driver before ringing doorbell. 201 */ 202 u32 fill_threshold; 203 }; 204 205 /* Hardware Tx Instruction Header */ 206 struct octep_instr_hdr { 207 /* Data Len */ 208 u64 tlen:16; 209 210 /* Reserved */ 211 u64 rsvd:20; 212 213 /* PKIND for SDP */ 214 u64 pkind:6; 215 216 /* Front Data size */ 217 u64 fsz:6; 218 219 /* No. of entries in gather list */ 220 u64 gsz:14; 221 222 /* Gather indicator 1=gather*/ 223 u64 gather:1; 224 225 /* Reserved3 */ 226 u64 reserved3:1; 227 }; 228 229 /* Hardware Tx completion response header */ 230 struct octep_instr_resp_hdr { 231 /* Request ID */ 232 u64 rid:16; 233 234 /* PCIe port to use for response */ 235 u64 pcie_port:3; 236 237 /* Scatter indicator 1=scatter */ 238 u64 scatter:1; 239 240 /* Size of Expected result OR no. of entries in scatter list */ 241 u64 rlenssz:14; 242 243 /* Desired destination port for result */ 244 u64 dport:6; 245 246 /* Opcode Specific parameters */ 247 u64 param:8; 248 249 /* Opcode for the return packet */ 250 u64 opcode:16; 251 }; 252 253 /* 64-byte Tx instruction format. 254 * Format of instruction for a 64-byte mode input queue. 255 * 256 * only first 16-bytes (dptr and ih) are mandatory; rest are optional 257 * and filled by the driver based on firmware/hardware capabilities. 258 * These optional headers together called Front Data and its size is 259 * described by ih->fsz. 260 */ 261 struct octep_tx_desc_hw { 262 /* Pointer where the input data is available. */ 263 u64 dptr; 264 265 /* Instruction Header. */ 266 union { 267 struct octep_instr_hdr ih; 268 u64 ih64; 269 }; 270 271 /* Pointer where the response for a RAW mode packet will be written 272 * by Octeon. 273 */ 274 u64 rptr; 275 276 /* Input Instruction Response Header. */ 277 struct octep_instr_resp_hdr irh; 278 279 /* Additional headers available in a 64-byte instruction. */ 280 u64 exhdr[4]; 281 }; 282 283 #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw)) 284 #endif /* _OCTEP_TX_H_ */ 285