1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_RX_H_ 9 #define _OCTEP_RX_H_ 10 11 /* struct octep_oq_desc_hw - Octeon Hardware OQ descriptor format. 12 * 13 * The descriptor ring is made of descriptors which have 2 64-bit values: 14 * 15 * @buffer_ptr: DMA address of the skb->data 16 * @info_ptr: DMA address of host memory, used to update pkt count by hw. 17 * This is currently unused to save pci writes. 18 */ 19 struct octep_oq_desc_hw { 20 dma_addr_t buffer_ptr; 21 u64 info_ptr; 22 }; 23 static_assert(sizeof(struct octep_oq_desc_hw) == 16); 24 25 #define OCTEP_OQ_DESC_SIZE (sizeof(struct octep_oq_desc_hw)) 26 27 #define OCTEP_CSUM_L4_VERIFIED 0x1 28 #define OCTEP_CSUM_IP_VERIFIED 0x2 29 #define OCTEP_CSUM_VERIFIED (OCTEP_CSUM_L4_VERIFIED | OCTEP_CSUM_IP_VERIFIED) 30 31 /* Extended Response Header in packet data received from Hardware. 32 * Includes metadata like checksum status. 33 * this is valid only if hardware/firmware published support for this. 34 * This is at offset 0 of packet data (skb->data). 35 */ 36 struct octep_oq_resp_hw_ext { 37 /* Reserved. */ 38 u64 reserved:62; 39 40 /* checksum verified. */ 41 u64 csum_verified:2; 42 }; 43 static_assert(sizeof(struct octep_oq_resp_hw_ext) == 8); 44 45 #define OCTEP_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_oq_resp_hw_ext)) 46 47 /* Length of Rx packet DMA'ed by Octeon to Host. 48 * this is in bigendian; so need to be converted to cpu endian. 49 * Octeon writes this at the beginning of Rx buffer (skb->data). 50 */ 51 struct octep_oq_resp_hw { 52 /* The Length of the packet. */ 53 __be64 length; 54 }; 55 static_assert(sizeof(struct octep_oq_resp_hw) == 8); 56 57 #define OCTEP_OQ_RESP_HW_SIZE (sizeof(struct octep_oq_resp_hw)) 58 59 /* Pointer to data buffer. 60 * Driver keeps a pointer to the data buffer that it made available to 61 * the Octeon device. Since the descriptor ring keeps physical (bus) 62 * addresses, this field is required for the driver to keep track of 63 * the virtual address pointers. The fields are operated by 64 * OS-dependent routines. 65 */ 66 struct octep_rx_buffer { 67 struct page *page; 68 69 /* length from rx hardware descriptor after converting to cpu endian */ 70 u64 len; 71 }; 72 73 #define OCTEP_OQ_RECVBUF_SIZE (sizeof(struct octep_rx_buffer)) 74 75 /* Output Queue statistics. Each output queue has four stats fields. */ 76 struct octep_oq_stats { 77 /* Number of packets received from the Device. */ 78 u64 packets; 79 80 /* Number of bytes received from the Device. */ 81 u64 bytes; 82 83 /* Number of times failed to allocate buffers. */ 84 u64 alloc_failures; 85 }; 86 87 #define OCTEP_OQ_STATS_SIZE (sizeof(struct octep_oq_stats)) 88 89 /* Hardware interface Rx statistics */ 90 struct octep_iface_rx_stats { 91 /* Received packets */ 92 u64 pkts; 93 94 /* Octets of received packets */ 95 u64 octets; 96 97 /* Received PAUSE and Control packets */ 98 u64 pause_pkts; 99 100 /* Received PAUSE and Control octets */ 101 u64 pause_octets; 102 103 /* Filtered DMAC0 packets */ 104 u64 dmac0_pkts; 105 106 /* Filtered DMAC0 octets */ 107 u64 dmac0_octets; 108 109 /* Packets dropped due to RX FIFO full */ 110 u64 dropped_pkts_fifo_full; 111 112 /* Octets dropped due to RX FIFO full */ 113 u64 dropped_octets_fifo_full; 114 115 /* Error packets */ 116 u64 err_pkts; 117 118 /* Filtered DMAC1 packets */ 119 u64 dmac1_pkts; 120 121 /* Filtered DMAC1 octets */ 122 u64 dmac1_octets; 123 124 /* NCSI-bound packets dropped */ 125 u64 ncsi_dropped_pkts; 126 127 /* NCSI-bound octets dropped */ 128 u64 ncsi_dropped_octets; 129 130 /* Multicast packets received. */ 131 u64 mcast_pkts; 132 133 /* Broadcast packets received. */ 134 u64 bcast_pkts; 135 136 }; 137 138 /* The Descriptor Ring Output Queue structure. 139 * This structure has all the information required to implement a 140 * Octeon OQ. 141 */ 142 struct octep_oq { 143 u32 q_no; 144 145 struct octep_device *octep_dev; 146 struct net_device *netdev; 147 struct device *dev; 148 149 struct napi_struct *napi; 150 151 /* The receive buffer list. This list has the virtual addresses 152 * of the buffers. 153 */ 154 struct octep_rx_buffer *buff_info; 155 156 /* Pointer to the mapped packet credit register. 157 * Host writes number of info/buffer ptrs available to this register 158 */ 159 u8 __iomem *pkts_credit_reg; 160 161 /* Pointer to the mapped packet sent register. 162 * Octeon writes the number of packets DMA'ed to host memory 163 * in this register. 164 */ 165 u8 __iomem *pkts_sent_reg; 166 167 /* Statistics for this OQ. */ 168 struct octep_oq_stats stats; 169 170 /* Packets pending to be processed */ 171 u32 pkts_pending; 172 u32 last_pkt_count; 173 174 /* Index in the ring where the driver should read the next packet */ 175 u32 host_read_idx; 176 177 /* Number of descriptors in this ring. */ 178 u32 max_count; 179 u32 ring_size_mask; 180 181 /* The number of descriptors pending refill. */ 182 u32 refill_count; 183 184 /* Index in the ring where the driver will refill the 185 * descriptor's buffer 186 */ 187 u32 host_refill_idx; 188 u32 refill_threshold; 189 190 /* The size of each buffer pointed by the buffer pointer. */ 191 u32 buffer_size; 192 u32 max_single_buffer_size; 193 194 /* The 8B aligned descriptor ring starts at this address. */ 195 struct octep_oq_desc_hw *desc_ring; 196 197 /* DMA mapped address of the OQ descriptor ring. */ 198 dma_addr_t desc_ring_dma; 199 }; 200 201 #define OCTEP_OQ_SIZE (sizeof(struct octep_oq)) 202 #endif /* _OCTEP_RX_H_ */ 203