1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_MAIN_H_ 9 #define _OCTEP_MAIN_H_ 10 11 #include "octep_tx.h" 12 #include "octep_rx.h" 13 #include "octep_ctrl_mbox.h" 14 15 #define OCTEP_DRV_NAME "octeon_ep" 16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18 #define OCTEP_PCIID_CN93_PF 0xB200177d 19 #define OCTEP_PCIID_CN93_VF 0xB203177d 20 21 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 22 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 23 24 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF 25 26 #define OCTEP_MAX_QUEUES 63 27 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 28 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 29 #define OCTEP_MAX_VF 64 30 31 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 32 33 /* Flags to disable and enable Interrupts */ 34 #define OCTEP_INPUT_INTR (1) 35 #define OCTEP_OUTPUT_INTR (2) 36 #define OCTEP_MBOX_INTR (4) 37 #define OCTEP_ALL_INTR 0xff 38 39 #define OCTEP_IQ_INTR_RESEND_BIT 59 40 #define OCTEP_OQ_INTR_RESEND_BIT 59 41 42 #define OCTEP_MMIO_REGIONS 3 43 44 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 45 ((iq__)->host_write_index - (iq__)->flush_index) & \ 46 (iq__)->ring_size_mask; \ 47 }) 48 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 49 (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ 50 }) 51 52 /* PCI address space mapping information. 53 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 54 * Octeon gets mapped to different physical address spaces in 55 * the kernel. 56 */ 57 struct octep_mmio { 58 /* The physical address to which the PCI address space is mapped. */ 59 u8 __iomem *hw_addr; 60 61 /* Flag indicating the mapping was successful. */ 62 int mapped; 63 }; 64 65 struct octep_pci_win_regs { 66 u8 __iomem *pci_win_wr_addr; 67 u8 __iomem *pci_win_rd_addr; 68 u8 __iomem *pci_win_wr_data; 69 u8 __iomem *pci_win_rd_data; 70 }; 71 72 struct octep_hw_ops { 73 void (*setup_iq_regs)(struct octep_device *oct, int q); 74 void (*setup_oq_regs)(struct octep_device *oct, int q); 75 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 76 77 irqreturn_t (*oei_intr_handler)(void *ioq_vector); 78 irqreturn_t (*ire_intr_handler)(void *ioq_vector); 79 irqreturn_t (*ore_intr_handler)(void *ioq_vector); 80 irqreturn_t (*vfire_intr_handler)(void *ioq_vector); 81 irqreturn_t (*vfore_intr_handler)(void *ioq_vector); 82 irqreturn_t (*dma_intr_handler)(void *ioq_vector); 83 irqreturn_t (*dma_vf_intr_handler)(void *ioq_vector); 84 irqreturn_t (*pp_vf_intr_handler)(void *ioq_vector); 85 irqreturn_t (*misc_intr_handler)(void *ioq_vector); 86 irqreturn_t (*rsvd_intr_handler)(void *ioq_vector); 87 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 88 int (*soft_reset)(struct octep_device *oct); 89 void (*reinit_regs)(struct octep_device *oct); 90 u32 (*update_iq_read_idx)(struct octep_iq *iq); 91 92 void (*enable_interrupts)(struct octep_device *oct); 93 void (*disable_interrupts)(struct octep_device *oct); 94 void (*poll_non_ioq_interrupts)(struct octep_device *oct); 95 96 void (*enable_io_queues)(struct octep_device *oct); 97 void (*disable_io_queues)(struct octep_device *oct); 98 void (*enable_iq)(struct octep_device *oct, int q); 99 void (*disable_iq)(struct octep_device *oct, int q); 100 void (*enable_oq)(struct octep_device *oct, int q); 101 void (*disable_oq)(struct octep_device *oct, int q); 102 void (*reset_io_queues)(struct octep_device *oct); 103 void (*dump_registers)(struct octep_device *oct); 104 }; 105 106 /* Octeon mailbox data */ 107 struct octep_mbox_data { 108 u32 cmd; 109 u32 total_len; 110 u32 recv_len; 111 u32 rsvd; 112 u64 *data; 113 }; 114 115 /* Octeon device mailbox */ 116 struct octep_mbox { 117 /* A spinlock to protect access to this q_mbox. */ 118 spinlock_t lock; 119 120 u32 q_no; 121 u32 state; 122 123 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 124 u8 __iomem *mbox_int_reg; 125 126 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 127 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 128 */ 129 u8 __iomem *mbox_write_reg; 130 131 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 132 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 133 */ 134 u8 __iomem *mbox_read_reg; 135 136 struct octep_mbox_data mbox_data; 137 }; 138 139 /* Tx/Rx queue vector per interrupt. */ 140 struct octep_ioq_vector { 141 char name[OCTEP_MSIX_NAME_SIZE]; 142 struct napi_struct napi; 143 struct octep_device *octep_dev; 144 struct octep_iq *iq; 145 struct octep_oq *oq; 146 cpumask_t affinity_mask; 147 }; 148 149 /* Octeon hardware/firmware offload capability flags. */ 150 #define OCTEP_CAP_TX_CHECKSUM BIT(0) 151 #define OCTEP_CAP_RX_CHECKSUM BIT(1) 152 #define OCTEP_CAP_TSO BIT(2) 153 154 /* Link modes */ 155 enum octep_link_mode_bit_indices { 156 OCTEP_LINK_MODE_10GBASE_T = 0, 157 OCTEP_LINK_MODE_10GBASE_R, 158 OCTEP_LINK_MODE_10GBASE_CR, 159 OCTEP_LINK_MODE_10GBASE_KR, 160 OCTEP_LINK_MODE_10GBASE_LR, 161 OCTEP_LINK_MODE_10GBASE_SR, 162 OCTEP_LINK_MODE_25GBASE_CR, 163 OCTEP_LINK_MODE_25GBASE_KR, 164 OCTEP_LINK_MODE_25GBASE_SR, 165 OCTEP_LINK_MODE_40GBASE_CR4, 166 OCTEP_LINK_MODE_40GBASE_KR4, 167 OCTEP_LINK_MODE_40GBASE_LR4, 168 OCTEP_LINK_MODE_40GBASE_SR4, 169 OCTEP_LINK_MODE_50GBASE_CR2, 170 OCTEP_LINK_MODE_50GBASE_KR2, 171 OCTEP_LINK_MODE_50GBASE_SR2, 172 OCTEP_LINK_MODE_50GBASE_CR, 173 OCTEP_LINK_MODE_50GBASE_KR, 174 OCTEP_LINK_MODE_50GBASE_LR, 175 OCTEP_LINK_MODE_50GBASE_SR, 176 OCTEP_LINK_MODE_100GBASE_CR4, 177 OCTEP_LINK_MODE_100GBASE_KR4, 178 OCTEP_LINK_MODE_100GBASE_LR4, 179 OCTEP_LINK_MODE_100GBASE_SR4, 180 OCTEP_LINK_MODE_NBITS 181 }; 182 183 /* Hardware interface link state information. */ 184 struct octep_iface_link_info { 185 /* Bitmap of Supported link speeds/modes. */ 186 u64 supported_modes; 187 188 /* Bitmap of Advertised link speeds/modes. */ 189 u64 advertised_modes; 190 191 /* Negotiated link speed in Mbps. */ 192 u32 speed; 193 194 /* MTU */ 195 u16 mtu; 196 197 /* Autonegotation state. */ 198 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 199 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 200 u8 autoneg; 201 202 /* Pause frames setting. */ 203 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 204 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 205 u8 pause; 206 207 /* Admin state of the link (ifconfig <iface> up/down */ 208 u8 admin_up; 209 210 /* Operational state of the link: physical link is up down */ 211 u8 oper_up; 212 }; 213 214 /* The Octeon device specific private data structure. 215 * Each Octeon device has this structure to represent all its components. 216 */ 217 struct octep_device { 218 struct octep_config *conf; 219 220 /* Octeon Chip type. */ 221 u16 chip_id; 222 u16 rev_id; 223 224 /* Device capabilities enabled */ 225 u64 caps_enabled; 226 /* Device capabilities supported */ 227 u64 caps_supported; 228 229 /* Pointer to basic Linux device */ 230 struct device *dev; 231 /* Linux PCI device pointer */ 232 struct pci_dev *pdev; 233 /* Netdev corresponding to the Octeon device */ 234 struct net_device *netdev; 235 236 /* memory mapped io range */ 237 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 238 239 /* MAC address */ 240 u8 mac_addr[ETH_ALEN]; 241 242 /* Tx queues (IQ: Instruction Queue) */ 243 u16 num_iqs; 244 /* pkind value to be used in every Tx hardware descriptor */ 245 u8 pkind; 246 /* Pointers to Octeon Tx queues */ 247 struct octep_iq *iq[OCTEP_MAX_IQ]; 248 249 /* Rx queues (OQ: Output Queue) */ 250 u16 num_oqs; 251 /* Pointers to Octeon Rx queues */ 252 struct octep_oq *oq[OCTEP_MAX_OQ]; 253 254 /* Hardware port number of the PCIe interface */ 255 u16 pcie_port; 256 257 /* PCI Window registers to access some hardware CSRs */ 258 struct octep_pci_win_regs pci_win_regs; 259 /* Hardware operations */ 260 struct octep_hw_ops hw_ops; 261 262 /* IRQ info */ 263 u16 num_irqs; 264 u16 num_non_ioq_irqs; 265 char *non_ioq_irq_names; 266 struct msix_entry *msix_entries; 267 /* IOq information of it's corresponding MSI-X interrupt. */ 268 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 269 270 /* Hardware Interface Tx statistics */ 271 struct octep_iface_tx_stats iface_tx_stats; 272 /* Hardware Interface Rx statistics */ 273 struct octep_iface_rx_stats iface_rx_stats; 274 275 /* Hardware Interface Link info like supported modes, aneg support */ 276 struct octep_iface_link_info link_info; 277 278 /* Mailbox to talk to VFs */ 279 struct octep_mbox *mbox[OCTEP_MAX_VF]; 280 281 /* Work entry to handle Tx timeout */ 282 struct work_struct tx_timeout_task; 283 284 /* control mbox over pf */ 285 struct octep_ctrl_mbox ctrl_mbox; 286 287 /* offset for iface stats */ 288 u32 ctrl_mbox_ifstats_offset; 289 290 /* Work entry to handle ctrl mbox interrupt */ 291 struct work_struct ctrl_mbox_task; 292 /* Wait queue for host to firmware requests */ 293 wait_queue_head_t ctrl_req_wait_q; 294 /* List of objects waiting for h2f response */ 295 struct list_head ctrl_req_wait_list; 296 297 /* Enable non-ioq interrupt polling */ 298 bool poll_non_ioq_intr; 299 /* Work entry to poll non-ioq interrupts */ 300 struct delayed_work intr_poll_task; 301 302 /* Firmware heartbeat timer */ 303 struct timer_list hb_timer; 304 /* Firmware heartbeat miss count tracked by timer */ 305 atomic_t hb_miss_cnt; 306 /* Task to reset device on heartbeat miss */ 307 struct delayed_work hb_task; 308 }; 309 310 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 311 { 312 u16 rev = (oct->rev_id & 0xC) >> 2; 313 314 return (rev == 0) ? 1 : rev; 315 } 316 317 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 318 { 319 return (oct->rev_id & 0x3); 320 } 321 322 /* Octeon CSR read/write access APIs */ 323 #define octep_write_csr(octep_dev, reg_off, value) \ 324 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 325 326 #define octep_write_csr64(octep_dev, reg_off, val64) \ 327 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 328 329 #define octep_read_csr(octep_dev, reg_off) \ 330 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 331 332 #define octep_read_csr64(octep_dev, reg_off) \ 333 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 334 335 /* Read windowed register. 336 * @param oct - pointer to the Octeon device. 337 * @param addr - Address of the register to read. 338 * 339 * This routine is called to read from the indirectly accessed 340 * Octeon registers that are visible through a PCI BAR0 mapped window 341 * register. 342 * @return - 64 bit value read from the register. 343 */ 344 static inline u64 345 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 346 { 347 u64 val64; 348 349 addr |= 1ull << 53; /* read 8 bytes */ 350 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 351 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 352 353 dev_dbg(&oct->pdev->dev, 354 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 355 356 return val64; 357 } 358 359 /* Write windowed register. 360 * @param oct - pointer to the Octeon device. 361 * @param addr - Address of the register to write 362 * @param val - Value to write 363 * 364 * This routine is called to write to the indirectly accessed 365 * Octeon registers that are visible through a PCI BAR0 mapped window 366 * register. 367 * @return Nothing. 368 */ 369 static inline void 370 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 371 { 372 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 373 writeq(val, oct->pci_win_regs.pci_win_wr_data); 374 375 dev_dbg(&oct->pdev->dev, 376 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 377 } 378 379 extern struct workqueue_struct *octep_wq; 380 381 int octep_device_setup(struct octep_device *oct); 382 int octep_setup_iqs(struct octep_device *oct); 383 void octep_free_iqs(struct octep_device *oct); 384 void octep_clean_iqs(struct octep_device *oct); 385 int octep_setup_oqs(struct octep_device *oct); 386 void octep_free_oqs(struct octep_device *oct); 387 void octep_oq_dbell_init(struct octep_device *oct); 388 void octep_device_setup_cn93_pf(struct octep_device *oct); 389 int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 390 int octep_oq_process_rx(struct octep_oq *oq, int budget); 391 void octep_set_ethtool_ops(struct net_device *netdev); 392 393 #endif /* _OCTEP_MAIN_H_ */ 394