1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_MAIN_H_ 9 #define _OCTEP_MAIN_H_ 10 11 #include "octep_tx.h" 12 #include "octep_rx.h" 13 #include "octep_ctrl_mbox.h" 14 15 #define OCTEP_DRV_NAME "octeon_ep" 16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18 #define OCTEP_PCIID_CN93_PF 0xB200177d 19 #define OCTEP_PCIID_CN93_VF 0xB203177d 20 21 #define OCTEP_PCI_DEVICE_ID_CN98_PF 0xB100 22 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 23 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 24 25 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF 26 27 #define OCTEP_PCI_DEVICE_ID_CN10KA_PF 0xB900 //CN10KA PF 28 #define OCTEP_PCI_DEVICE_ID_CNF10KA_PF 0xBA00 //CNF10KA PF 29 #define OCTEP_PCI_DEVICE_ID_CNF10KB_PF 0xBC00 //CNF10KB PF 30 #define OCTEP_PCI_DEVICE_ID_CN10KB_PF 0xBD00 //CN10KB PF 31 32 #define OCTEP_MAX_QUEUES 63 33 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 34 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 35 #define OCTEP_MAX_VF 64 36 37 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 38 39 /* Flags to disable and enable Interrupts */ 40 #define OCTEP_INPUT_INTR (1) 41 #define OCTEP_OUTPUT_INTR (2) 42 #define OCTEP_MBOX_INTR (4) 43 #define OCTEP_ALL_INTR 0xff 44 45 #define OCTEP_IQ_INTR_RESEND_BIT 59 46 #define OCTEP_OQ_INTR_RESEND_BIT 59 47 48 #define OCTEP_MMIO_REGIONS 3 49 50 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 51 ((iq__)->host_write_index - (iq__)->flush_index) & \ 52 (iq__)->ring_size_mask; \ 53 }) 54 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 55 (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ 56 }) 57 58 /* PCI address space mapping information. 59 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 60 * Octeon gets mapped to different physical address spaces in 61 * the kernel. 62 */ 63 struct octep_mmio { 64 /* The physical address to which the PCI address space is mapped. */ 65 u8 __iomem *hw_addr; 66 67 /* Flag indicating the mapping was successful. */ 68 int mapped; 69 }; 70 71 struct octep_pci_win_regs { 72 u8 __iomem *pci_win_wr_addr; 73 u8 __iomem *pci_win_rd_addr; 74 u8 __iomem *pci_win_wr_data; 75 u8 __iomem *pci_win_rd_data; 76 }; 77 78 struct octep_hw_ops { 79 void (*setup_iq_regs)(struct octep_device *oct, int q); 80 void (*setup_oq_regs)(struct octep_device *oct, int q); 81 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 82 83 irqreturn_t (*mbox_intr_handler)(void *ioq_vector); 84 irqreturn_t (*oei_intr_handler)(void *ioq_vector); 85 irqreturn_t (*ire_intr_handler)(void *ioq_vector); 86 irqreturn_t (*ore_intr_handler)(void *ioq_vector); 87 irqreturn_t (*vfire_intr_handler)(void *ioq_vector); 88 irqreturn_t (*vfore_intr_handler)(void *ioq_vector); 89 irqreturn_t (*dma_intr_handler)(void *ioq_vector); 90 irqreturn_t (*dma_vf_intr_handler)(void *ioq_vector); 91 irqreturn_t (*pp_vf_intr_handler)(void *ioq_vector); 92 irqreturn_t (*misc_intr_handler)(void *ioq_vector); 93 irqreturn_t (*rsvd_intr_handler)(void *ioq_vector); 94 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 95 int (*soft_reset)(struct octep_device *oct); 96 void (*reinit_regs)(struct octep_device *oct); 97 u32 (*update_iq_read_idx)(struct octep_iq *iq); 98 99 void (*enable_interrupts)(struct octep_device *oct); 100 void (*disable_interrupts)(struct octep_device *oct); 101 void (*poll_non_ioq_interrupts)(struct octep_device *oct); 102 103 void (*enable_io_queues)(struct octep_device *oct); 104 void (*disable_io_queues)(struct octep_device *oct); 105 void (*enable_iq)(struct octep_device *oct, int q); 106 void (*disable_iq)(struct octep_device *oct, int q); 107 void (*enable_oq)(struct octep_device *oct, int q); 108 void (*disable_oq)(struct octep_device *oct, int q); 109 void (*reset_io_queues)(struct octep_device *oct); 110 void (*dump_registers)(struct octep_device *oct); 111 }; 112 113 /* Octeon mailbox data */ 114 struct octep_mbox_data { 115 u32 cmd; 116 u32 total_len; 117 u32 recv_len; 118 u32 rsvd; 119 u64 *data; 120 }; 121 122 #define MAX_VF_PF_MBOX_DATA_SIZE 384 123 /* wrappers around work structs */ 124 struct octep_pfvf_mbox_wk { 125 struct work_struct work; 126 void *ctxptr; 127 u64 ctxul; 128 }; 129 130 /* Octeon device mailbox */ 131 struct octep_mbox { 132 /* A mutex to protect access to this q_mbox. */ 133 struct mutex lock; 134 u32 vf_id; 135 u32 config_data_index; 136 u32 message_len; 137 u8 __iomem *pf_vf_data_reg; 138 u8 __iomem *vf_pf_data_reg; 139 struct octep_pfvf_mbox_wk wk; 140 struct octep_device *oct; 141 struct octep_mbox_data mbox_data; 142 u8 config_data[MAX_VF_PF_MBOX_DATA_SIZE]; 143 }; 144 145 /* Tx/Rx queue vector per interrupt. */ 146 struct octep_ioq_vector { 147 char name[OCTEP_MSIX_NAME_SIZE]; 148 struct napi_struct napi; 149 struct octep_device *octep_dev; 150 struct octep_iq *iq; 151 struct octep_oq *oq; 152 cpumask_t affinity_mask; 153 }; 154 155 /* Octeon hardware/firmware offload capability flags. */ 156 #define OCTEP_CAP_TX_CHECKSUM BIT(0) 157 #define OCTEP_CAP_RX_CHECKSUM BIT(1) 158 #define OCTEP_CAP_TSO BIT(2) 159 160 /* Link modes */ 161 enum octep_link_mode_bit_indices { 162 OCTEP_LINK_MODE_10GBASE_T = 0, 163 OCTEP_LINK_MODE_10GBASE_R, 164 OCTEP_LINK_MODE_10GBASE_CR, 165 OCTEP_LINK_MODE_10GBASE_KR, 166 OCTEP_LINK_MODE_10GBASE_LR, 167 OCTEP_LINK_MODE_10GBASE_SR, 168 OCTEP_LINK_MODE_25GBASE_CR, 169 OCTEP_LINK_MODE_25GBASE_KR, 170 OCTEP_LINK_MODE_25GBASE_SR, 171 OCTEP_LINK_MODE_40GBASE_CR4, 172 OCTEP_LINK_MODE_40GBASE_KR4, 173 OCTEP_LINK_MODE_40GBASE_LR4, 174 OCTEP_LINK_MODE_40GBASE_SR4, 175 OCTEP_LINK_MODE_50GBASE_CR2, 176 OCTEP_LINK_MODE_50GBASE_KR2, 177 OCTEP_LINK_MODE_50GBASE_SR2, 178 OCTEP_LINK_MODE_50GBASE_CR, 179 OCTEP_LINK_MODE_50GBASE_KR, 180 OCTEP_LINK_MODE_50GBASE_LR, 181 OCTEP_LINK_MODE_50GBASE_SR, 182 OCTEP_LINK_MODE_100GBASE_CR4, 183 OCTEP_LINK_MODE_100GBASE_KR4, 184 OCTEP_LINK_MODE_100GBASE_LR4, 185 OCTEP_LINK_MODE_100GBASE_SR4, 186 OCTEP_LINK_MODE_NBITS 187 }; 188 189 /* Hardware interface link state information. */ 190 struct octep_iface_link_info { 191 /* Bitmap of Supported link speeds/modes. */ 192 u64 supported_modes; 193 194 /* Bitmap of Advertised link speeds/modes. */ 195 u64 advertised_modes; 196 197 /* Negotiated link speed in Mbps. */ 198 u32 speed; 199 200 /* MTU */ 201 u16 mtu; 202 203 /* Autonegotation state. */ 204 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 205 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 206 u8 autoneg; 207 208 /* Pause frames setting. */ 209 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 210 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 211 u8 pause; 212 213 /* Admin state of the link (ifconfig <iface> up/down */ 214 u8 admin_up; 215 216 /* Operational state of the link: physical link is up down */ 217 u8 oper_up; 218 }; 219 220 /* The Octeon VF device specific info data structure.*/ 221 struct octep_pfvf_info { 222 u8 mac_addr[ETH_ALEN]; 223 u32 flags; 224 u32 mbox_version; 225 }; 226 227 /* The Octeon device specific private data structure. 228 * Each Octeon device has this structure to represent all its components. 229 */ 230 struct octep_device { 231 struct octep_config *conf; 232 233 /* Octeon Chip type. */ 234 u16 chip_id; 235 u16 rev_id; 236 237 /* Device capabilities enabled */ 238 u64 caps_enabled; 239 /* Device capabilities supported */ 240 u64 caps_supported; 241 242 /* Pointer to basic Linux device */ 243 struct device *dev; 244 /* Linux PCI device pointer */ 245 struct pci_dev *pdev; 246 /* Netdev corresponding to the Octeon device */ 247 struct net_device *netdev; 248 249 /* memory mapped io range */ 250 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 251 252 /* MAC address */ 253 u8 mac_addr[ETH_ALEN]; 254 255 /* Tx queues (IQ: Instruction Queue) */ 256 u16 num_iqs; 257 258 /* Pointers to Octeon Tx queues */ 259 struct octep_iq *iq[OCTEP_MAX_IQ]; 260 261 /* Rx queues (OQ: Output Queue) */ 262 u16 num_oqs; 263 /* Pointers to Octeon Rx queues */ 264 struct octep_oq *oq[OCTEP_MAX_OQ]; 265 266 /* Hardware port number of the PCIe interface */ 267 u16 pcie_port; 268 269 /* PCI Window registers to access some hardware CSRs */ 270 struct octep_pci_win_regs pci_win_regs; 271 /* Hardware operations */ 272 struct octep_hw_ops hw_ops; 273 274 /* IRQ info */ 275 u16 num_irqs; 276 u16 num_non_ioq_irqs; 277 char *non_ioq_irq_names; 278 struct msix_entry *msix_entries; 279 /* IOq information of it's corresponding MSI-X interrupt. */ 280 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 281 282 /* Hardware Interface Tx statistics */ 283 struct octep_iface_tx_stats iface_tx_stats; 284 /* Hardware Interface Rx statistics */ 285 struct octep_iface_rx_stats iface_rx_stats; 286 287 /* Hardware Interface Link info like supported modes, aneg support */ 288 struct octep_iface_link_info link_info; 289 290 /* Mailbox to talk to VFs */ 291 struct octep_mbox *mbox[OCTEP_MAX_VF]; 292 /* VFs info */ 293 struct octep_pfvf_info vf_info[OCTEP_MAX_VF]; 294 295 /* Work entry to handle Tx timeout */ 296 struct work_struct tx_timeout_task; 297 298 /* control mbox over pf */ 299 struct octep_ctrl_mbox ctrl_mbox; 300 301 /* offset for iface stats */ 302 u32 ctrl_mbox_ifstats_offset; 303 304 /* Work entry to handle ctrl mbox interrupt */ 305 struct work_struct ctrl_mbox_task; 306 /* Wait queue for host to firmware requests */ 307 wait_queue_head_t ctrl_req_wait_q; 308 /* List of objects waiting for h2f response */ 309 struct list_head ctrl_req_wait_list; 310 311 /* Enable non-ioq interrupt polling */ 312 bool poll_non_ioq_intr; 313 /* Work entry to poll non-ioq interrupts */ 314 struct delayed_work intr_poll_task; 315 316 /* Firmware heartbeat timer */ 317 struct timer_list hb_timer; 318 /* Firmware heartbeat miss count tracked by timer */ 319 atomic_t hb_miss_cnt; 320 /* Task to reset device on heartbeat miss */ 321 struct delayed_work hb_task; 322 }; 323 324 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 325 { 326 u16 rev = (oct->rev_id & 0xC) >> 2; 327 328 return (rev == 0) ? 1 : rev; 329 } 330 331 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 332 { 333 return (oct->rev_id & 0x3); 334 } 335 336 /* Octeon CSR read/write access APIs */ 337 #define octep_write_csr(octep_dev, reg_off, value) \ 338 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 339 340 #define octep_write_csr64(octep_dev, reg_off, val64) \ 341 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 342 343 #define octep_read_csr(octep_dev, reg_off) \ 344 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 345 346 #define octep_read_csr64(octep_dev, reg_off) \ 347 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 348 349 /* Read windowed register. 350 * @param oct - pointer to the Octeon device. 351 * @param addr - Address of the register to read. 352 * 353 * This routine is called to read from the indirectly accessed 354 * Octeon registers that are visible through a PCI BAR0 mapped window 355 * register. 356 * @return - 64 bit value read from the register. 357 */ 358 static inline u64 359 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 360 { 361 u64 val64; 362 363 addr |= 1ull << 53; /* read 8 bytes */ 364 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 365 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 366 367 dev_dbg(&oct->pdev->dev, 368 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 369 370 return val64; 371 } 372 373 /* Write windowed register. 374 * @param oct - pointer to the Octeon device. 375 * @param addr - Address of the register to write 376 * @param val - Value to write 377 * 378 * This routine is called to write to the indirectly accessed 379 * Octeon registers that are visible through a PCI BAR0 mapped window 380 * register. 381 * @return Nothing. 382 */ 383 static inline void 384 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 385 { 386 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 387 writeq(val, oct->pci_win_regs.pci_win_wr_data); 388 389 dev_dbg(&oct->pdev->dev, 390 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 391 } 392 393 extern struct workqueue_struct *octep_wq; 394 395 int octep_device_setup(struct octep_device *oct); 396 int octep_setup_iqs(struct octep_device *oct); 397 void octep_free_iqs(struct octep_device *oct); 398 void octep_clean_iqs(struct octep_device *oct); 399 int octep_setup_oqs(struct octep_device *oct); 400 void octep_free_oqs(struct octep_device *oct); 401 void octep_oq_dbell_init(struct octep_device *oct); 402 void octep_device_setup_cn93_pf(struct octep_device *oct); 403 void octep_device_setup_cnxk_pf(struct octep_device *oct); 404 int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 405 int octep_oq_process_rx(struct octep_oq *oq, int budget); 406 void octep_set_ethtool_ops(struct net_device *netdev); 407 408 #endif /* _OCTEP_MAIN_H_ */ 409