1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_MAIN_H_ 9 #define _OCTEP_MAIN_H_ 10 11 #include "octep_tx.h" 12 #include "octep_rx.h" 13 #include "octep_ctrl_mbox.h" 14 15 #define OCTEP_DRV_NAME "octeon_ep" 16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18 #define OCTEP_PCIID_CN93_PF 0xB200177d 19 #define OCTEP_PCIID_CN93_VF 0xB203177d 20 21 #define OCTEP_PCI_DEVICE_ID_CN98_PF 0xB100 22 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 23 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 24 25 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF 26 27 #define OCTEP_PCI_DEVICE_ID_CN10KA_PF 0xB900 //CN10KA PF 28 #define OCTEP_PCI_DEVICE_ID_CNF10KA_PF 0xBA00 //CNF10KA PF 29 #define OCTEP_PCI_DEVICE_ID_CNF10KB_PF 0xBC00 //CNF10KB PF 30 #define OCTEP_PCI_DEVICE_ID_CN10KB_PF 0xBD00 //CN10KB PF 31 32 #define OCTEP_MAX_QUEUES 63 33 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 34 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 35 #define OCTEP_MAX_VF 64 36 37 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 38 39 /* Flags to disable and enable Interrupts */ 40 #define OCTEP_INPUT_INTR (1) 41 #define OCTEP_OUTPUT_INTR (2) 42 #define OCTEP_MBOX_INTR (4) 43 #define OCTEP_ALL_INTR 0xff 44 45 #define OCTEP_IQ_INTR_RESEND_BIT 59 46 #define OCTEP_OQ_INTR_RESEND_BIT 59 47 48 #define OCTEP_MMIO_REGIONS 3 49 50 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 51 ((iq__)->host_write_index - (iq__)->flush_index) & \ 52 (iq__)->ring_size_mask; \ 53 }) 54 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 55 (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ 56 }) 57 58 /* PCI address space mapping information. 59 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 60 * Octeon gets mapped to different physical address spaces in 61 * the kernel. 62 */ 63 struct octep_mmio { 64 /* The physical address to which the PCI address space is mapped. */ 65 u8 __iomem *hw_addr; 66 67 /* Flag indicating the mapping was successful. */ 68 int mapped; 69 }; 70 71 struct octep_pci_win_regs { 72 u8 __iomem *pci_win_wr_addr; 73 u8 __iomem *pci_win_rd_addr; 74 u8 __iomem *pci_win_wr_data; 75 u8 __iomem *pci_win_rd_data; 76 }; 77 78 struct octep_hw_ops { 79 void (*setup_iq_regs)(struct octep_device *oct, int q); 80 void (*setup_oq_regs)(struct octep_device *oct, int q); 81 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 82 83 irqreturn_t (*oei_intr_handler)(void *ioq_vector); 84 irqreturn_t (*ire_intr_handler)(void *ioq_vector); 85 irqreturn_t (*ore_intr_handler)(void *ioq_vector); 86 irqreturn_t (*vfire_intr_handler)(void *ioq_vector); 87 irqreturn_t (*vfore_intr_handler)(void *ioq_vector); 88 irqreturn_t (*dma_intr_handler)(void *ioq_vector); 89 irqreturn_t (*dma_vf_intr_handler)(void *ioq_vector); 90 irqreturn_t (*pp_vf_intr_handler)(void *ioq_vector); 91 irqreturn_t (*misc_intr_handler)(void *ioq_vector); 92 irqreturn_t (*rsvd_intr_handler)(void *ioq_vector); 93 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 94 int (*soft_reset)(struct octep_device *oct); 95 void (*reinit_regs)(struct octep_device *oct); 96 u32 (*update_iq_read_idx)(struct octep_iq *iq); 97 98 void (*enable_interrupts)(struct octep_device *oct); 99 void (*disable_interrupts)(struct octep_device *oct); 100 void (*poll_non_ioq_interrupts)(struct octep_device *oct); 101 102 void (*enable_io_queues)(struct octep_device *oct); 103 void (*disable_io_queues)(struct octep_device *oct); 104 void (*enable_iq)(struct octep_device *oct, int q); 105 void (*disable_iq)(struct octep_device *oct, int q); 106 void (*enable_oq)(struct octep_device *oct, int q); 107 void (*disable_oq)(struct octep_device *oct, int q); 108 void (*reset_io_queues)(struct octep_device *oct); 109 void (*dump_registers)(struct octep_device *oct); 110 }; 111 112 /* Octeon mailbox data */ 113 struct octep_mbox_data { 114 u32 cmd; 115 u32 total_len; 116 u32 recv_len; 117 u32 rsvd; 118 u64 *data; 119 }; 120 121 /* Octeon device mailbox */ 122 struct octep_mbox { 123 /* A spinlock to protect access to this q_mbox. */ 124 spinlock_t lock; 125 126 u32 q_no; 127 u32 state; 128 129 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 130 u8 __iomem *mbox_int_reg; 131 132 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 133 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 134 */ 135 u8 __iomem *mbox_write_reg; 136 137 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 138 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 139 */ 140 u8 __iomem *mbox_read_reg; 141 142 struct octep_mbox_data mbox_data; 143 }; 144 145 /* Tx/Rx queue vector per interrupt. */ 146 struct octep_ioq_vector { 147 char name[OCTEP_MSIX_NAME_SIZE]; 148 struct napi_struct napi; 149 struct octep_device *octep_dev; 150 struct octep_iq *iq; 151 struct octep_oq *oq; 152 cpumask_t affinity_mask; 153 }; 154 155 /* Octeon hardware/firmware offload capability flags. */ 156 #define OCTEP_CAP_TX_CHECKSUM BIT(0) 157 #define OCTEP_CAP_RX_CHECKSUM BIT(1) 158 #define OCTEP_CAP_TSO BIT(2) 159 160 /* Link modes */ 161 enum octep_link_mode_bit_indices { 162 OCTEP_LINK_MODE_10GBASE_T = 0, 163 OCTEP_LINK_MODE_10GBASE_R, 164 OCTEP_LINK_MODE_10GBASE_CR, 165 OCTEP_LINK_MODE_10GBASE_KR, 166 OCTEP_LINK_MODE_10GBASE_LR, 167 OCTEP_LINK_MODE_10GBASE_SR, 168 OCTEP_LINK_MODE_25GBASE_CR, 169 OCTEP_LINK_MODE_25GBASE_KR, 170 OCTEP_LINK_MODE_25GBASE_SR, 171 OCTEP_LINK_MODE_40GBASE_CR4, 172 OCTEP_LINK_MODE_40GBASE_KR4, 173 OCTEP_LINK_MODE_40GBASE_LR4, 174 OCTEP_LINK_MODE_40GBASE_SR4, 175 OCTEP_LINK_MODE_50GBASE_CR2, 176 OCTEP_LINK_MODE_50GBASE_KR2, 177 OCTEP_LINK_MODE_50GBASE_SR2, 178 OCTEP_LINK_MODE_50GBASE_CR, 179 OCTEP_LINK_MODE_50GBASE_KR, 180 OCTEP_LINK_MODE_50GBASE_LR, 181 OCTEP_LINK_MODE_50GBASE_SR, 182 OCTEP_LINK_MODE_100GBASE_CR4, 183 OCTEP_LINK_MODE_100GBASE_KR4, 184 OCTEP_LINK_MODE_100GBASE_LR4, 185 OCTEP_LINK_MODE_100GBASE_SR4, 186 OCTEP_LINK_MODE_NBITS 187 }; 188 189 /* Hardware interface link state information. */ 190 struct octep_iface_link_info { 191 /* Bitmap of Supported link speeds/modes. */ 192 u64 supported_modes; 193 194 /* Bitmap of Advertised link speeds/modes. */ 195 u64 advertised_modes; 196 197 /* Negotiated link speed in Mbps. */ 198 u32 speed; 199 200 /* MTU */ 201 u16 mtu; 202 203 /* Autonegotation state. */ 204 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 205 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 206 u8 autoneg; 207 208 /* Pause frames setting. */ 209 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 210 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 211 u8 pause; 212 213 /* Admin state of the link (ifconfig <iface> up/down */ 214 u8 admin_up; 215 216 /* Operational state of the link: physical link is up down */ 217 u8 oper_up; 218 }; 219 220 /* The Octeon device specific private data structure. 221 * Each Octeon device has this structure to represent all its components. 222 */ 223 struct octep_device { 224 struct octep_config *conf; 225 226 /* Octeon Chip type. */ 227 u16 chip_id; 228 u16 rev_id; 229 230 /* Device capabilities enabled */ 231 u64 caps_enabled; 232 /* Device capabilities supported */ 233 u64 caps_supported; 234 235 /* Pointer to basic Linux device */ 236 struct device *dev; 237 /* Linux PCI device pointer */ 238 struct pci_dev *pdev; 239 /* Netdev corresponding to the Octeon device */ 240 struct net_device *netdev; 241 242 /* memory mapped io range */ 243 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 244 245 /* MAC address */ 246 u8 mac_addr[ETH_ALEN]; 247 248 /* Tx queues (IQ: Instruction Queue) */ 249 u16 num_iqs; 250 251 /* Pointers to Octeon Tx queues */ 252 struct octep_iq *iq[OCTEP_MAX_IQ]; 253 254 /* Rx queues (OQ: Output Queue) */ 255 u16 num_oqs; 256 /* Pointers to Octeon Rx queues */ 257 struct octep_oq *oq[OCTEP_MAX_OQ]; 258 259 /* Hardware port number of the PCIe interface */ 260 u16 pcie_port; 261 262 /* PCI Window registers to access some hardware CSRs */ 263 struct octep_pci_win_regs pci_win_regs; 264 /* Hardware operations */ 265 struct octep_hw_ops hw_ops; 266 267 /* IRQ info */ 268 u16 num_irqs; 269 u16 num_non_ioq_irqs; 270 char *non_ioq_irq_names; 271 struct msix_entry *msix_entries; 272 /* IOq information of it's corresponding MSI-X interrupt. */ 273 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 274 275 /* Hardware Interface Tx statistics */ 276 struct octep_iface_tx_stats iface_tx_stats; 277 /* Hardware Interface Rx statistics */ 278 struct octep_iface_rx_stats iface_rx_stats; 279 280 /* Hardware Interface Link info like supported modes, aneg support */ 281 struct octep_iface_link_info link_info; 282 283 /* Mailbox to talk to VFs */ 284 struct octep_mbox *mbox[OCTEP_MAX_VF]; 285 286 /* Work entry to handle Tx timeout */ 287 struct work_struct tx_timeout_task; 288 289 /* control mbox over pf */ 290 struct octep_ctrl_mbox ctrl_mbox; 291 292 /* offset for iface stats */ 293 u32 ctrl_mbox_ifstats_offset; 294 295 /* Work entry to handle ctrl mbox interrupt */ 296 struct work_struct ctrl_mbox_task; 297 /* Wait queue for host to firmware requests */ 298 wait_queue_head_t ctrl_req_wait_q; 299 /* List of objects waiting for h2f response */ 300 struct list_head ctrl_req_wait_list; 301 302 /* Enable non-ioq interrupt polling */ 303 bool poll_non_ioq_intr; 304 /* Work entry to poll non-ioq interrupts */ 305 struct delayed_work intr_poll_task; 306 307 /* Firmware heartbeat timer */ 308 struct timer_list hb_timer; 309 /* Firmware heartbeat miss count tracked by timer */ 310 atomic_t hb_miss_cnt; 311 /* Task to reset device on heartbeat miss */ 312 struct delayed_work hb_task; 313 }; 314 315 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 316 { 317 u16 rev = (oct->rev_id & 0xC) >> 2; 318 319 return (rev == 0) ? 1 : rev; 320 } 321 322 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 323 { 324 return (oct->rev_id & 0x3); 325 } 326 327 /* Octeon CSR read/write access APIs */ 328 #define octep_write_csr(octep_dev, reg_off, value) \ 329 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 330 331 #define octep_write_csr64(octep_dev, reg_off, val64) \ 332 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 333 334 #define octep_read_csr(octep_dev, reg_off) \ 335 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 336 337 #define octep_read_csr64(octep_dev, reg_off) \ 338 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 339 340 /* Read windowed register. 341 * @param oct - pointer to the Octeon device. 342 * @param addr - Address of the register to read. 343 * 344 * This routine is called to read from the indirectly accessed 345 * Octeon registers that are visible through a PCI BAR0 mapped window 346 * register. 347 * @return - 64 bit value read from the register. 348 */ 349 static inline u64 350 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 351 { 352 u64 val64; 353 354 addr |= 1ull << 53; /* read 8 bytes */ 355 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 356 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 357 358 dev_dbg(&oct->pdev->dev, 359 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 360 361 return val64; 362 } 363 364 /* Write windowed register. 365 * @param oct - pointer to the Octeon device. 366 * @param addr - Address of the register to write 367 * @param val - Value to write 368 * 369 * This routine is called to write to the indirectly accessed 370 * Octeon registers that are visible through a PCI BAR0 mapped window 371 * register. 372 * @return Nothing. 373 */ 374 static inline void 375 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 376 { 377 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 378 writeq(val, oct->pci_win_regs.pci_win_wr_data); 379 380 dev_dbg(&oct->pdev->dev, 381 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 382 } 383 384 extern struct workqueue_struct *octep_wq; 385 386 int octep_device_setup(struct octep_device *oct); 387 int octep_setup_iqs(struct octep_device *oct); 388 void octep_free_iqs(struct octep_device *oct); 389 void octep_clean_iqs(struct octep_device *oct); 390 int octep_setup_oqs(struct octep_device *oct); 391 void octep_free_oqs(struct octep_device *oct); 392 void octep_oq_dbell_init(struct octep_device *oct); 393 void octep_device_setup_cn93_pf(struct octep_device *oct); 394 void octep_device_setup_cnxk_pf(struct octep_device *oct); 395 int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 396 int octep_oq_process_rx(struct octep_oq *oq, int budget); 397 void octep_set_ethtool_ops(struct net_device *netdev); 398 399 #endif /* _OCTEP_MAIN_H_ */ 400