1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_MAIN_H_ 9 #define _OCTEP_MAIN_H_ 10 11 #include "octep_tx.h" 12 #include "octep_rx.h" 13 #include "octep_ctrl_mbox.h" 14 15 #define OCTEP_DRV_NAME "octeon_ep" 16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18 #define OCTEP_PCIID_CN93_PF 0xB200177d 19 #define OCTEP_PCIID_CN93_VF 0xB203177d 20 21 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 22 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 23 24 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF 25 26 #define OCTEP_MAX_QUEUES 63 27 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 28 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 29 #define OCTEP_MAX_VF 64 30 31 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 32 33 /* Flags to disable and enable Interrupts */ 34 #define OCTEP_INPUT_INTR (1) 35 #define OCTEP_OUTPUT_INTR (2) 36 #define OCTEP_MBOX_INTR (4) 37 #define OCTEP_ALL_INTR 0xff 38 39 #define OCTEP_IQ_INTR_RESEND_BIT 59 40 #define OCTEP_OQ_INTR_RESEND_BIT 59 41 42 #define OCTEP_MMIO_REGIONS 3 43 /* PCI address space mapping information. 44 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 45 * Octeon gets mapped to different physical address spaces in 46 * the kernel. 47 */ 48 struct octep_mmio { 49 /* The physical address to which the PCI address space is mapped. */ 50 u8 __iomem *hw_addr; 51 52 /* Flag indicating the mapping was successful. */ 53 int mapped; 54 }; 55 56 struct octep_pci_win_regs { 57 u8 __iomem *pci_win_wr_addr; 58 u8 __iomem *pci_win_rd_addr; 59 u8 __iomem *pci_win_wr_data; 60 u8 __iomem *pci_win_rd_data; 61 }; 62 63 struct octep_hw_ops { 64 void (*setup_iq_regs)(struct octep_device *oct, int q); 65 void (*setup_oq_regs)(struct octep_device *oct, int q); 66 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 67 68 irqreturn_t (*oei_intr_handler)(void *ioq_vector); 69 irqreturn_t (*ire_intr_handler)(void *ioq_vector); 70 irqreturn_t (*ore_intr_handler)(void *ioq_vector); 71 irqreturn_t (*vfire_intr_handler)(void *ioq_vector); 72 irqreturn_t (*vfore_intr_handler)(void *ioq_vector); 73 irqreturn_t (*dma_intr_handler)(void *ioq_vector); 74 irqreturn_t (*dma_vf_intr_handler)(void *ioq_vector); 75 irqreturn_t (*pp_vf_intr_handler)(void *ioq_vector); 76 irqreturn_t (*misc_intr_handler)(void *ioq_vector); 77 irqreturn_t (*rsvd_intr_handler)(void *ioq_vector); 78 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 79 int (*soft_reset)(struct octep_device *oct); 80 void (*reinit_regs)(struct octep_device *oct); 81 u32 (*update_iq_read_idx)(struct octep_iq *iq); 82 83 void (*enable_interrupts)(struct octep_device *oct); 84 void (*disable_interrupts)(struct octep_device *oct); 85 void (*poll_non_ioq_interrupts)(struct octep_device *oct); 86 87 void (*enable_io_queues)(struct octep_device *oct); 88 void (*disable_io_queues)(struct octep_device *oct); 89 void (*enable_iq)(struct octep_device *oct, int q); 90 void (*disable_iq)(struct octep_device *oct, int q); 91 void (*enable_oq)(struct octep_device *oct, int q); 92 void (*disable_oq)(struct octep_device *oct, int q); 93 void (*reset_io_queues)(struct octep_device *oct); 94 void (*dump_registers)(struct octep_device *oct); 95 }; 96 97 /* Octeon mailbox data */ 98 struct octep_mbox_data { 99 u32 cmd; 100 u32 total_len; 101 u32 recv_len; 102 u32 rsvd; 103 u64 *data; 104 }; 105 106 /* Octeon device mailbox */ 107 struct octep_mbox { 108 /* A spinlock to protect access to this q_mbox. */ 109 spinlock_t lock; 110 111 u32 q_no; 112 u32 state; 113 114 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 115 u8 __iomem *mbox_int_reg; 116 117 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 118 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 119 */ 120 u8 __iomem *mbox_write_reg; 121 122 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 123 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 124 */ 125 u8 __iomem *mbox_read_reg; 126 127 struct octep_mbox_data mbox_data; 128 }; 129 130 /* Tx/Rx queue vector per interrupt. */ 131 struct octep_ioq_vector { 132 char name[OCTEP_MSIX_NAME_SIZE]; 133 struct napi_struct napi; 134 struct octep_device *octep_dev; 135 struct octep_iq *iq; 136 struct octep_oq *oq; 137 cpumask_t affinity_mask; 138 }; 139 140 /* Octeon hardware/firmware offload capability flags. */ 141 #define OCTEP_CAP_TX_CHECKSUM BIT(0) 142 #define OCTEP_CAP_RX_CHECKSUM BIT(1) 143 #define OCTEP_CAP_TSO BIT(2) 144 145 /* Link modes */ 146 enum octep_link_mode_bit_indices { 147 OCTEP_LINK_MODE_10GBASE_T = 0, 148 OCTEP_LINK_MODE_10GBASE_R, 149 OCTEP_LINK_MODE_10GBASE_CR, 150 OCTEP_LINK_MODE_10GBASE_KR, 151 OCTEP_LINK_MODE_10GBASE_LR, 152 OCTEP_LINK_MODE_10GBASE_SR, 153 OCTEP_LINK_MODE_25GBASE_CR, 154 OCTEP_LINK_MODE_25GBASE_KR, 155 OCTEP_LINK_MODE_25GBASE_SR, 156 OCTEP_LINK_MODE_40GBASE_CR4, 157 OCTEP_LINK_MODE_40GBASE_KR4, 158 OCTEP_LINK_MODE_40GBASE_LR4, 159 OCTEP_LINK_MODE_40GBASE_SR4, 160 OCTEP_LINK_MODE_50GBASE_CR2, 161 OCTEP_LINK_MODE_50GBASE_KR2, 162 OCTEP_LINK_MODE_50GBASE_SR2, 163 OCTEP_LINK_MODE_50GBASE_CR, 164 OCTEP_LINK_MODE_50GBASE_KR, 165 OCTEP_LINK_MODE_50GBASE_LR, 166 OCTEP_LINK_MODE_50GBASE_SR, 167 OCTEP_LINK_MODE_100GBASE_CR4, 168 OCTEP_LINK_MODE_100GBASE_KR4, 169 OCTEP_LINK_MODE_100GBASE_LR4, 170 OCTEP_LINK_MODE_100GBASE_SR4, 171 OCTEP_LINK_MODE_NBITS 172 }; 173 174 /* Hardware interface link state information. */ 175 struct octep_iface_link_info { 176 /* Bitmap of Supported link speeds/modes. */ 177 u64 supported_modes; 178 179 /* Bitmap of Advertised link speeds/modes. */ 180 u64 advertised_modes; 181 182 /* Negotiated link speed in Mbps. */ 183 u32 speed; 184 185 /* MTU */ 186 u16 mtu; 187 188 /* Autonegotation state. */ 189 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 190 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 191 u8 autoneg; 192 193 /* Pause frames setting. */ 194 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 195 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 196 u8 pause; 197 198 /* Admin state of the link (ifconfig <iface> up/down */ 199 u8 admin_up; 200 201 /* Operational state of the link: physical link is up down */ 202 u8 oper_up; 203 }; 204 205 /* The Octeon device specific private data structure. 206 * Each Octeon device has this structure to represent all its components. 207 */ 208 struct octep_device { 209 struct octep_config *conf; 210 211 /* Octeon Chip type. */ 212 u16 chip_id; 213 u16 rev_id; 214 215 /* Device capabilities enabled */ 216 u64 caps_enabled; 217 /* Device capabilities supported */ 218 u64 caps_supported; 219 220 /* Pointer to basic Linux device */ 221 struct device *dev; 222 /* Linux PCI device pointer */ 223 struct pci_dev *pdev; 224 /* Netdev corresponding to the Octeon device */ 225 struct net_device *netdev; 226 227 /* memory mapped io range */ 228 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 229 230 /* MAC address */ 231 u8 mac_addr[ETH_ALEN]; 232 233 /* Tx queues (IQ: Instruction Queue) */ 234 u16 num_iqs; 235 /* pkind value to be used in every Tx hardware descriptor */ 236 u8 pkind; 237 /* Pointers to Octeon Tx queues */ 238 struct octep_iq *iq[OCTEP_MAX_IQ]; 239 240 /* Rx queues (OQ: Output Queue) */ 241 u16 num_oqs; 242 /* Pointers to Octeon Rx queues */ 243 struct octep_oq *oq[OCTEP_MAX_OQ]; 244 245 /* Hardware port number of the PCIe interface */ 246 u16 pcie_port; 247 248 /* PCI Window registers to access some hardware CSRs */ 249 struct octep_pci_win_regs pci_win_regs; 250 /* Hardware operations */ 251 struct octep_hw_ops hw_ops; 252 253 /* IRQ info */ 254 u16 num_irqs; 255 u16 num_non_ioq_irqs; 256 char *non_ioq_irq_names; 257 struct msix_entry *msix_entries; 258 /* IOq information of it's corresponding MSI-X interrupt. */ 259 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 260 261 /* Hardware Interface Tx statistics */ 262 struct octep_iface_tx_stats iface_tx_stats; 263 /* Hardware Interface Rx statistics */ 264 struct octep_iface_rx_stats iface_rx_stats; 265 266 /* Hardware Interface Link info like supported modes, aneg support */ 267 struct octep_iface_link_info link_info; 268 269 /* Mailbox to talk to VFs */ 270 struct octep_mbox *mbox[OCTEP_MAX_VF]; 271 272 /* Work entry to handle Tx timeout */ 273 struct work_struct tx_timeout_task; 274 275 /* control mbox over pf */ 276 struct octep_ctrl_mbox ctrl_mbox; 277 278 /* offset for iface stats */ 279 u32 ctrl_mbox_ifstats_offset; 280 281 /* Work entry to handle ctrl mbox interrupt */ 282 struct work_struct ctrl_mbox_task; 283 /* Wait queue for host to firmware requests */ 284 wait_queue_head_t ctrl_req_wait_q; 285 /* List of objects waiting for h2f response */ 286 struct list_head ctrl_req_wait_list; 287 288 /* Enable non-ioq interrupt polling */ 289 bool poll_non_ioq_intr; 290 /* Work entry to poll non-ioq interrupts */ 291 struct delayed_work intr_poll_task; 292 293 /* Firmware heartbeat timer */ 294 struct timer_list hb_timer; 295 /* Firmware heartbeat miss count tracked by timer */ 296 atomic_t hb_miss_cnt; 297 /* Task to reset device on heartbeat miss */ 298 struct delayed_work hb_task; 299 }; 300 301 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 302 { 303 u16 rev = (oct->rev_id & 0xC) >> 2; 304 305 return (rev == 0) ? 1 : rev; 306 } 307 308 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 309 { 310 return (oct->rev_id & 0x3); 311 } 312 313 /* Octeon CSR read/write access APIs */ 314 #define octep_write_csr(octep_dev, reg_off, value) \ 315 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 316 317 #define octep_write_csr64(octep_dev, reg_off, val64) \ 318 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 319 320 #define octep_read_csr(octep_dev, reg_off) \ 321 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 322 323 #define octep_read_csr64(octep_dev, reg_off) \ 324 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 325 326 /* Read windowed register. 327 * @param oct - pointer to the Octeon device. 328 * @param addr - Address of the register to read. 329 * 330 * This routine is called to read from the indirectly accessed 331 * Octeon registers that are visible through a PCI BAR0 mapped window 332 * register. 333 * @return - 64 bit value read from the register. 334 */ 335 static inline u64 336 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 337 { 338 u64 val64; 339 340 addr |= 1ull << 53; /* read 8 bytes */ 341 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 342 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 343 344 dev_dbg(&oct->pdev->dev, 345 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 346 347 return val64; 348 } 349 350 /* Write windowed register. 351 * @param oct - pointer to the Octeon device. 352 * @param addr - Address of the register to write 353 * @param val - Value to write 354 * 355 * This routine is called to write to the indirectly accessed 356 * Octeon registers that are visible through a PCI BAR0 mapped window 357 * register. 358 * @return Nothing. 359 */ 360 static inline void 361 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 362 { 363 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 364 writeq(val, oct->pci_win_regs.pci_win_wr_data); 365 366 dev_dbg(&oct->pdev->dev, 367 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 368 } 369 370 extern struct workqueue_struct *octep_wq; 371 372 int octep_device_setup(struct octep_device *oct); 373 int octep_setup_iqs(struct octep_device *oct); 374 void octep_free_iqs(struct octep_device *oct); 375 void octep_clean_iqs(struct octep_device *oct); 376 int octep_setup_oqs(struct octep_device *oct); 377 void octep_free_oqs(struct octep_device *oct); 378 void octep_oq_dbell_init(struct octep_device *oct); 379 void octep_device_setup_cn93_pf(struct octep_device *oct); 380 int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 381 int octep_oq_process_rx(struct octep_oq *oq, int budget); 382 void octep_set_ethtool_ops(struct net_device *netdev); 383 384 #endif /* _OCTEP_MAIN_H_ */ 385