1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_CONFIG_H_ 9 #define _OCTEP_CONFIG_H_ 10 11 /* Tx instruction types by length */ 12 #define OCTEP_32BYTE_INSTR 32 13 #define OCTEP_64BYTE_INSTR 64 14 15 /* Tx Queue: maximum descriptors per ring */ 16 /* This needs to be a power of 2 */ 17 #define OCTEP_IQ_MAX_DESCRIPTORS 1024 18 /* Minimum input (Tx) requests to be enqueued to ring doorbell */ 19 #define OCTEP_DB_MIN 8 20 /* Packet threshold for Tx queue interrupt */ 21 #define OCTEP_IQ_INTR_THRESHOLD 0x0 22 23 /* Rx Queue: maximum descriptors per ring */ 24 #define OCTEP_OQ_MAX_DESCRIPTORS 1024 25 26 /* Rx buffer size: Use page size buffers. 27 * Build skb from allocated page buffer once the packet is received. 28 * When a gathered packet is received, make head page as skb head and 29 * page buffers in consecutive Rx descriptors as fragments. 30 */ 31 #define OCTEP_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE)) 32 #define OCTEP_OQ_PKTS_PER_INTR 128 33 #define OCTEP_OQ_REFILL_THRESHOLD (OCTEP_OQ_MAX_DESCRIPTORS / 4) 34 35 #define OCTEP_OQ_INTR_PKT_THRESHOLD 1 36 #define OCTEP_OQ_INTR_TIME_THRESHOLD 10 37 38 #define OCTEP_MSIX_NAME_SIZE (IFNAMSIZ + 32) 39 40 /* Tx Queue wake threshold 41 * wakeup a stopped Tx queue if minimum 2 descriptors are available. 42 * Even a skb with fragments consume only one Tx queue descriptor entry. 43 */ 44 #define OCTEP_WAKE_QUEUE_THRESHOLD 2 45 46 /* Minimum MTU supported by Octeon network interface */ 47 #define OCTEP_MIN_MTU ETH_MIN_MTU 48 /* Maximum MTU supported by Octeon interface*/ 49 #define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN)) 50 /* Default MTU */ 51 #define OCTEP_DEFAULT_MTU 1500 52 53 /* pf heartbeat interval in milliseconds */ 54 #define OCTEP_DEFAULT_FW_HB_INTERVAL 1000 55 /* pf heartbeat miss count */ 56 #define OCTEP_DEFAULT_FW_HB_MISS_COUNT 20 57 58 /* Macros to get octeon config params */ 59 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 60 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) 61 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 62 #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind) 63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) 64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) 66 67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) 68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) 69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) 70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) 71 #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time) 72 73 #define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.max_io_rings) 74 #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings) 75 #define CFG_GET_PORTS_PF_SRN(cfg) ((cfg)->pf_ring_cfg.srn) 76 77 #define CFG_GET_DPI_PKIND(cfg) ((cfg)->core_cfg.dpi_pkind) 78 #define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us) 79 #define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us) 80 81 #define CFG_GET_MAX_VFS(cfg) ((cfg)->sriov_cfg.max_vfs) 82 #define CFG_GET_ACTIVE_VFS(cfg) ((cfg)->sriov_cfg.active_vfs) 83 #define CFG_GET_MAX_RPVF(cfg) ((cfg)->sriov_cfg.max_rings_per_vf) 84 #define CFG_GET_ACTIVE_RPVF(cfg) ((cfg)->sriov_cfg.active_rings_per_vf) 85 #define CFG_GET_VF_SRN(cfg) ((cfg)->sriov_cfg.vf_srn) 86 87 #define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix) 88 #define CFG_GET_NON_IOQ_MSIX(cfg) ((cfg)->msix_cfg.non_ioq_msix) 89 #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) ((cfg)->msix_cfg.non_ioq_msix_names) 90 91 #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) ((cfg)->ctrl_mbox_cfg.barmem_addr) 92 93 /* Hardware Tx Queue configuration. */ 94 struct octep_iq_config { 95 /* Size of the Input queue (number of commands) */ 96 u16 num_descs; 97 98 /* Command size - 32 or 64 bytes */ 99 u16 instr_type; 100 101 /* pkind for packets sent to Octeon */ 102 u16 pkind; 103 104 /* Minimum number of commands pending to be posted to Octeon before driver 105 * hits the Input queue doorbell. 106 */ 107 u16 db_min; 108 109 /* Trigger the IQ interrupt when processed cmd count reaches 110 * this level. 111 */ 112 u32 intr_threshold; 113 }; 114 115 /* Hardware Rx Queue configuration. */ 116 struct octep_oq_config { 117 /* Size of Output queue (number of descriptors) */ 118 u16 num_descs; 119 120 /* Size of buffer in this Output queue. */ 121 u16 buf_size; 122 123 /* The number of buffers that were consumed during packet processing 124 * by the driver on this Output queue before the driver attempts to 125 * replenish the descriptor ring with new buffers. 126 */ 127 u16 refill_threshold; 128 129 /* Interrupt Coalescing (Packet Count). Octeon will interrupt the host 130 * only if it sent as many packets as specified by this field. 131 * The driver usually does not use packet count interrupt coalescing. 132 */ 133 u32 oq_intr_pkt; 134 135 /* Interrupt Coalescing (Time Interval). Octeon will interrupt the host 136 * if at least one packet was sent in the time interval specified by 137 * this field. The driver uses time interval interrupt coalescing by 138 * default. The time is specified in microseconds. 139 */ 140 u32 oq_intr_time; 141 }; 142 143 /* Tx/Rx configuration */ 144 struct octep_pf_ring_config { 145 /* Max number of IOQs */ 146 u16 max_io_rings; 147 148 /* Number of active IOQs */ 149 u16 active_io_rings; 150 151 /* Starting IOQ number: this changes based on which PEM is used */ 152 u16 srn; 153 }; 154 155 /* Octeon Hardware SRIOV config */ 156 struct octep_sriov_config { 157 /* Max number of VF devices supported */ 158 u16 max_vfs; 159 160 /* Number of VF devices enabled */ 161 u16 active_vfs; 162 163 /* Max number of rings assigned to VF */ 164 u8 max_rings_per_vf; 165 166 /* Number of rings enabled per VF */ 167 u8 active_rings_per_vf; 168 169 /* starting ring number of VF's: ring-0 of VF-0 of the PF */ 170 u16 vf_srn; 171 }; 172 173 /* Octeon MSI-x config. */ 174 struct octep_msix_config { 175 /* Number of IOQ interrupts */ 176 u16 ioq_msix; 177 178 /* Number of Non IOQ interrupts */ 179 u16 non_ioq_msix; 180 181 /* Names of Non IOQ interrupts */ 182 char **non_ioq_msix_names; 183 }; 184 185 struct octep_ctrl_mbox_config { 186 /* Barmem address for control mbox */ 187 void __iomem *barmem_addr; 188 }; 189 190 /* Info from firmware */ 191 struct octep_fw_info { 192 /* interface pkind */ 193 u16 pkind; 194 /* heartbeat interval in milliseconds */ 195 u16 hb_interval; 196 /* heartbeat miss count */ 197 u16 hb_miss_count; 198 }; 199 200 /* Data Structure to hold configuration limits and active config */ 201 struct octep_config { 202 /* Input Queue attributes. */ 203 struct octep_iq_config iq; 204 205 /* Output Queue attributes. */ 206 struct octep_oq_config oq; 207 208 /* NIC Port Configuration */ 209 struct octep_pf_ring_config pf_ring_cfg; 210 211 /* SRIOV configuration of the PF */ 212 struct octep_sriov_config sriov_cfg; 213 214 /* MSI-X interrupt config */ 215 struct octep_msix_config msix_cfg; 216 217 /* ctrl mbox config */ 218 struct octep_ctrl_mbox_config ctrl_mbox_cfg; 219 220 /* fw info */ 221 struct octep_fw_info fw_info; 222 }; 223 #endif /* _OCTEP_CONFIG_H_ */ 224