1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 40 #include "mvpp2.h" 41 #include "mvpp2_prs.h" 42 #include "mvpp2_cls.h" 43 44 enum mvpp2_bm_pool_log_num { 45 MVPP2_BM_SHORT, 46 MVPP2_BM_LONG, 47 MVPP2_BM_JUMBO, 48 MVPP2_BM_POOLS_NUM 49 }; 50 51 static struct { 52 int pkt_size; 53 int buf_num; 54 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 55 56 /* The prototype is added here to be used in start_dev when using ACPI. This 57 * will be removed once phylink is used for all modes (dt+ACPI). 58 */ 59 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 60 const struct phylink_link_state *state); 61 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 62 phy_interface_t interface, struct phy_device *phy); 63 64 /* Queue modes */ 65 #define MVPP2_QDIST_SINGLE_MODE 0 66 #define MVPP2_QDIST_MULTI_MODE 1 67 68 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 69 70 module_param(queue_mode, int, 0444); 71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 72 73 /* Utility/helper methods */ 74 75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 76 { 77 writel(data, priv->swth_base[0] + offset); 78 } 79 80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 81 { 82 return readl(priv->swth_base[0] + offset); 83 } 84 85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 86 { 87 return readl_relaxed(priv->swth_base[0] + offset); 88 } 89 90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 91 { 92 return cpu % priv->nthreads; 93 } 94 95 /* These accessors should be used to access: 96 * 97 * - per-thread registers, where each thread has its own copy of the 98 * register. 99 * 100 * MVPP2_BM_VIRT_ALLOC_REG 101 * MVPP2_BM_ADDR_HIGH_ALLOC 102 * MVPP22_BM_ADDR_HIGH_RLS_REG 103 * MVPP2_BM_VIRT_RLS_REG 104 * MVPP2_ISR_RX_TX_CAUSE_REG 105 * MVPP2_ISR_RX_TX_MASK_REG 106 * MVPP2_TXQ_NUM_REG 107 * MVPP2_AGGR_TXQ_UPDATE_REG 108 * MVPP2_TXQ_RSVD_REQ_REG 109 * MVPP2_TXQ_RSVD_RSLT_REG 110 * MVPP2_TXQ_SENT_REG 111 * MVPP2_RXQ_NUM_REG 112 * 113 * - global registers that must be accessed through a specific thread 114 * window, because they are related to an access to a per-thread 115 * register 116 * 117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 130 */ 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 132 u32 offset, u32 data) 133 { 134 writel(data, priv->swth_base[thread] + offset); 135 } 136 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 138 u32 offset) 139 { 140 return readl(priv->swth_base[thread] + offset); 141 } 142 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 144 u32 offset, u32 data) 145 { 146 writel_relaxed(data, priv->swth_base[thread] + offset); 147 } 148 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 150 u32 offset) 151 { 152 return readl_relaxed(priv->swth_base[thread] + offset); 153 } 154 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 156 struct mvpp2_tx_desc *tx_desc) 157 { 158 if (port->priv->hw_version == MVPP21) 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 160 else 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 162 MVPP2_DESC_DMA_MASK; 163 } 164 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 166 struct mvpp2_tx_desc *tx_desc, 167 dma_addr_t dma_addr) 168 { 169 dma_addr_t addr, offset; 170 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 172 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 173 174 if (port->priv->hw_version == MVPP21) { 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 176 tx_desc->pp21.packet_offset = offset; 177 } else { 178 __le64 val = cpu_to_le64(addr); 179 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 181 tx_desc->pp22.buf_dma_addr_ptp |= val; 182 tx_desc->pp22.packet_offset = offset; 183 } 184 } 185 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 187 struct mvpp2_tx_desc *tx_desc) 188 { 189 if (port->priv->hw_version == MVPP21) 190 return le16_to_cpu(tx_desc->pp21.data_size); 191 else 192 return le16_to_cpu(tx_desc->pp22.data_size); 193 } 194 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 196 struct mvpp2_tx_desc *tx_desc, 197 size_t size) 198 { 199 if (port->priv->hw_version == MVPP21) 200 tx_desc->pp21.data_size = cpu_to_le16(size); 201 else 202 tx_desc->pp22.data_size = cpu_to_le16(size); 203 } 204 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 206 struct mvpp2_tx_desc *tx_desc, 207 unsigned int txq) 208 { 209 if (port->priv->hw_version == MVPP21) 210 tx_desc->pp21.phys_txq = txq; 211 else 212 tx_desc->pp22.phys_txq = txq; 213 } 214 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 216 struct mvpp2_tx_desc *tx_desc, 217 unsigned int command) 218 { 219 if (port->priv->hw_version == MVPP21) 220 tx_desc->pp21.command = cpu_to_le32(command); 221 else 222 tx_desc->pp22.command = cpu_to_le32(command); 223 } 224 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 226 struct mvpp2_tx_desc *tx_desc) 227 { 228 if (port->priv->hw_version == MVPP21) 229 return tx_desc->pp21.packet_offset; 230 else 231 return tx_desc->pp22.packet_offset; 232 } 233 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 235 struct mvpp2_rx_desc *rx_desc) 236 { 237 if (port->priv->hw_version == MVPP21) 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 239 else 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 241 MVPP2_DESC_DMA_MASK; 242 } 243 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 245 struct mvpp2_rx_desc *rx_desc) 246 { 247 if (port->priv->hw_version == MVPP21) 248 return le32_to_cpu(rx_desc->pp21.buf_cookie); 249 else 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 251 MVPP2_DESC_DMA_MASK; 252 } 253 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 255 struct mvpp2_rx_desc *rx_desc) 256 { 257 if (port->priv->hw_version == MVPP21) 258 return le16_to_cpu(rx_desc->pp21.data_size); 259 else 260 return le16_to_cpu(rx_desc->pp22.data_size); 261 } 262 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 264 struct mvpp2_rx_desc *rx_desc) 265 { 266 if (port->priv->hw_version == MVPP21) 267 return le32_to_cpu(rx_desc->pp21.status); 268 else 269 return le32_to_cpu(rx_desc->pp22.status); 270 } 271 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 273 { 274 txq_pcpu->txq_get_index++; 275 if (txq_pcpu->txq_get_index == txq_pcpu->size) 276 txq_pcpu->txq_get_index = 0; 277 } 278 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 280 struct mvpp2_txq_pcpu *txq_pcpu, 281 struct sk_buff *skb, 282 struct mvpp2_tx_desc *tx_desc) 283 { 284 struct mvpp2_txq_pcpu_buf *tx_buf = 285 txq_pcpu->buffs + txq_pcpu->txq_put_index; 286 tx_buf->skb = skb; 287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 289 mvpp2_txdesc_offset_get(port, tx_desc); 290 txq_pcpu->txq_put_index++; 291 if (txq_pcpu->txq_put_index == txq_pcpu->size) 292 txq_pcpu->txq_put_index = 0; 293 } 294 295 /* Get number of physical egress port */ 296 static inline int mvpp2_egress_port(struct mvpp2_port *port) 297 { 298 return MVPP2_MAX_TCONT + port->id; 299 } 300 301 /* Get number of physical TXQ */ 302 static inline int mvpp2_txq_phys(int port, int txq) 303 { 304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 305 } 306 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 return netdev_alloc_frag(pool->frag_size); 311 else 312 return kmalloc(pool->frag_size, GFP_ATOMIC); 313 } 314 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 316 { 317 if (likely(pool->frag_size <= PAGE_SIZE)) 318 skb_free_frag(data); 319 else 320 kfree(data); 321 } 322 323 /* Buffer Manager configuration routines */ 324 325 /* Create pool */ 326 static int mvpp2_bm_pool_create(struct platform_device *pdev, 327 struct mvpp2 *priv, 328 struct mvpp2_bm_pool *bm_pool, int size) 329 { 330 u32 val; 331 332 /* Number of buffer pointers must be a multiple of 16, as per 333 * hardware constraints 334 */ 335 if (!IS_ALIGNED(size, 16)) 336 return -EINVAL; 337 338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 339 * bytes per buffer pointer 340 */ 341 if (priv->hw_version == MVPP21) 342 bm_pool->size_bytes = 2 * sizeof(u32) * size; 343 else 344 bm_pool->size_bytes = 2 * sizeof(u64) * size; 345 346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 347 &bm_pool->dma_addr, 348 GFP_KERNEL); 349 if (!bm_pool->virt_addr) 350 return -ENOMEM; 351 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 353 MVPP2_BM_POOL_PTR_ALIGN)) { 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 355 bm_pool->virt_addr, bm_pool->dma_addr); 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 358 return -ENOMEM; 359 } 360 361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 362 lower_32_bits(bm_pool->dma_addr)); 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 364 365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 366 val |= MVPP2_BM_START_MASK; 367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 368 369 bm_pool->size = size; 370 bm_pool->pkt_size = 0; 371 bm_pool->buf_num = 0; 372 373 return 0; 374 } 375 376 /* Set pool buffer size */ 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 378 struct mvpp2_bm_pool *bm_pool, 379 int buf_size) 380 { 381 u32 val; 382 383 bm_pool->buf_size = buf_size; 384 385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 387 } 388 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 390 struct mvpp2_bm_pool *bm_pool, 391 dma_addr_t *dma_addr, 392 phys_addr_t *phys_addr) 393 { 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 395 396 *dma_addr = mvpp2_thread_read(priv, thread, 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 399 400 if (priv->hw_version == MVPP22) { 401 u32 val; 402 u32 dma_addr_highbits, phys_addr_highbits; 403 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 408 409 if (sizeof(dma_addr_t) == 8) 410 *dma_addr |= (u64)dma_addr_highbits << 32; 411 412 if (sizeof(phys_addr_t) == 8) 413 *phys_addr |= (u64)phys_addr_highbits << 32; 414 } 415 416 put_cpu(); 417 } 418 419 /* Free all buffers from the pool */ 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 421 struct mvpp2_bm_pool *bm_pool, int buf_num) 422 { 423 int i; 424 425 if (buf_num > bm_pool->buf_num) { 426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 427 bm_pool->id, buf_num); 428 buf_num = bm_pool->buf_num; 429 } 430 431 for (i = 0; i < buf_num; i++) { 432 dma_addr_t buf_dma_addr; 433 phys_addr_t buf_phys_addr; 434 void *data; 435 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 437 &buf_dma_addr, &buf_phys_addr); 438 439 dma_unmap_single(dev, buf_dma_addr, 440 bm_pool->buf_size, DMA_FROM_DEVICE); 441 442 data = (void *)phys_to_virt(buf_phys_addr); 443 if (!data) 444 break; 445 446 mvpp2_frag_free(bm_pool, data); 447 } 448 449 /* Update BM driver with number of buffers removed from pool */ 450 bm_pool->buf_num -= i; 451 } 452 453 /* Check number of buffers in BM pool */ 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 455 { 456 int buf_num = 0; 457 458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 459 MVPP22_BM_POOL_PTRS_NUM_MASK; 460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 461 MVPP2_BM_BPPI_PTR_NUM_MASK; 462 463 /* HW has one buffer ready which is not reflected in the counters */ 464 if (buf_num) 465 buf_num += 1; 466 467 return buf_num; 468 } 469 470 /* Cleanup pool */ 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 472 struct mvpp2 *priv, 473 struct mvpp2_bm_pool *bm_pool) 474 { 475 int buf_num; 476 u32 val; 477 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 480 481 /* Check buffer counters after free */ 482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 483 if (buf_num) { 484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 485 bm_pool->id, bm_pool->buf_num); 486 return 0; 487 } 488 489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 490 val |= MVPP2_BM_STOP_MASK; 491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 492 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 494 bm_pool->virt_addr, 495 bm_pool->dma_addr); 496 return 0; 497 } 498 499 static int mvpp2_bm_pools_init(struct platform_device *pdev, 500 struct mvpp2 *priv) 501 { 502 int i, err, size; 503 struct mvpp2_bm_pool *bm_pool; 504 505 /* Create all pools with maximum size */ 506 size = MVPP2_BM_POOL_SIZE_MAX; 507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 508 bm_pool = &priv->bm_pools[i]; 509 bm_pool->id = i; 510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 511 if (err) 512 goto err_unroll_pools; 513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 514 } 515 return 0; 516 517 err_unroll_pools: 518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 519 for (i = i - 1; i >= 0; i--) 520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 521 return err; 522 } 523 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 525 { 526 int i, err; 527 528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 529 /* Mask BM all interrupts */ 530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 531 /* Clear BM cause register */ 532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 533 } 534 535 /* Allocate and initialize BM pools */ 536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 537 sizeof(*priv->bm_pools), GFP_KERNEL); 538 if (!priv->bm_pools) 539 return -ENOMEM; 540 541 err = mvpp2_bm_pools_init(pdev, priv); 542 if (err < 0) 543 return err; 544 return 0; 545 } 546 547 static void mvpp2_setup_bm_pool(void) 548 { 549 /* Short pool */ 550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 552 553 /* Long pool */ 554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 556 557 /* Jumbo pool */ 558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 560 } 561 562 /* Attach long pool to rxq */ 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 564 int lrxq, int long_pool) 565 { 566 u32 val, mask; 567 int prxq; 568 569 /* Get queue physical ID */ 570 prxq = port->rxqs[lrxq]->id; 571 572 if (port->priv->hw_version == MVPP21) 573 mask = MVPP21_RXQ_POOL_LONG_MASK; 574 else 575 mask = MVPP22_RXQ_POOL_LONG_MASK; 576 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 578 val &= ~mask; 579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 581 } 582 583 /* Attach short pool to rxq */ 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 585 int lrxq, int short_pool) 586 { 587 u32 val, mask; 588 int prxq; 589 590 /* Get queue physical ID */ 591 prxq = port->rxqs[lrxq]->id; 592 593 if (port->priv->hw_version == MVPP21) 594 mask = MVPP21_RXQ_POOL_SHORT_MASK; 595 else 596 mask = MVPP22_RXQ_POOL_SHORT_MASK; 597 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 599 val &= ~mask; 600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 602 } 603 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 605 struct mvpp2_bm_pool *bm_pool, 606 dma_addr_t *buf_dma_addr, 607 phys_addr_t *buf_phys_addr, 608 gfp_t gfp_mask) 609 { 610 dma_addr_t dma_addr; 611 void *data; 612 613 data = mvpp2_frag_alloc(bm_pool); 614 if (!data) 615 return NULL; 616 617 dma_addr = dma_map_single(port->dev->dev.parent, data, 618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 619 DMA_FROM_DEVICE); 620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 621 mvpp2_frag_free(bm_pool, data); 622 return NULL; 623 } 624 *buf_dma_addr = dma_addr; 625 *buf_phys_addr = virt_to_phys(data); 626 627 return data; 628 } 629 630 /* Release buffer to BM */ 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 632 dma_addr_t buf_dma_addr, 633 phys_addr_t buf_phys_addr) 634 { 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 636 unsigned long flags = 0; 637 638 if (test_bit(thread, &port->priv->lock_map)) 639 spin_lock_irqsave(&port->bm_lock[thread], flags); 640 641 if (port->priv->hw_version == MVPP22) { 642 u32 val = 0; 643 644 if (sizeof(dma_addr_t) == 8) 645 val |= upper_32_bits(buf_dma_addr) & 646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 647 648 if (sizeof(phys_addr_t) == 8) 649 val |= (upper_32_bits(buf_phys_addr) 650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 652 653 mvpp2_thread_write_relaxed(port->priv, thread, 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 655 } 656 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 658 * returned in the "cookie" field of the RX 659 * descriptor. Instead of storing the virtual address, we 660 * store the physical address 661 */ 662 mvpp2_thread_write_relaxed(port->priv, thread, 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 664 mvpp2_thread_write_relaxed(port->priv, thread, 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 666 667 if (test_bit(thread, &port->priv->lock_map)) 668 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 669 670 put_cpu(); 671 } 672 673 /* Allocate buffers for the pool */ 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 675 struct mvpp2_bm_pool *bm_pool, int buf_num) 676 { 677 int i, buf_size, total_size; 678 dma_addr_t dma_addr; 679 phys_addr_t phys_addr; 680 void *buf; 681 682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 684 685 if (buf_num < 0 || 686 (buf_num + bm_pool->buf_num > bm_pool->size)) { 687 netdev_err(port->dev, 688 "cannot allocate %d buffers for pool %d\n", 689 buf_num, bm_pool->id); 690 return 0; 691 } 692 693 for (i = 0; i < buf_num; i++) { 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 695 &phys_addr, GFP_KERNEL); 696 if (!buf) 697 break; 698 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 700 phys_addr); 701 } 702 703 /* Update BM driver with number of buffers added to pool */ 704 bm_pool->buf_num += i; 705 706 netdev_dbg(port->dev, 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 709 710 netdev_dbg(port->dev, 711 "pool %d: %d of %d buffers added\n", 712 bm_pool->id, i, buf_num); 713 return i; 714 } 715 716 /* Notify the driver that BM pool is being used as specific type and return the 717 * pool pointer on success 718 */ 719 static struct mvpp2_bm_pool * 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 721 { 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 723 int num; 724 725 if (pool >= MVPP2_BM_POOLS_NUM) { 726 netdev_err(port->dev, "Invalid pool %d\n", pool); 727 return NULL; 728 } 729 730 /* Allocate buffers in case BM pool is used as long pool, but packet 731 * size doesn't match MTU or BM pool hasn't being used yet 732 */ 733 if (new_pool->pkt_size == 0) { 734 int pkts_num; 735 736 /* Set default buffer number or free all the buffers in case 737 * the pool is not empty 738 */ 739 pkts_num = new_pool->buf_num; 740 if (pkts_num == 0) 741 pkts_num = mvpp2_pools[pool].buf_num; 742 else 743 mvpp2_bm_bufs_free(port->dev->dev.parent, 744 port->priv, new_pool, pkts_num); 745 746 new_pool->pkt_size = pkt_size; 747 new_pool->frag_size = 748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 749 MVPP2_SKB_SHINFO_SIZE; 750 751 /* Allocate buffers for this pool */ 752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 753 if (num != pkts_num) { 754 WARN(1, "pool %d: %d of %d allocated\n", 755 new_pool->id, num, pkts_num); 756 return NULL; 757 } 758 } 759 760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 762 763 return new_pool; 764 } 765 766 /* Initialize pools for swf */ 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 768 { 769 int rxq; 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 771 772 /* If port pkt_size is higher than 1518B: 773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 775 */ 776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 777 long_log_pool = MVPP2_BM_JUMBO; 778 short_log_pool = MVPP2_BM_LONG; 779 } else { 780 long_log_pool = MVPP2_BM_LONG; 781 short_log_pool = MVPP2_BM_SHORT; 782 } 783 784 if (!port->pool_long) { 785 port->pool_long = 786 mvpp2_bm_pool_use(port, long_log_pool, 787 mvpp2_pools[long_log_pool].pkt_size); 788 if (!port->pool_long) 789 return -ENOMEM; 790 791 port->pool_long->port_map |= BIT(port->id); 792 793 for (rxq = 0; rxq < port->nrxqs; rxq++) 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 795 } 796 797 if (!port->pool_short) { 798 port->pool_short = 799 mvpp2_bm_pool_use(port, short_log_pool, 800 mvpp2_pools[short_log_pool].pkt_size); 801 if (!port->pool_short) 802 return -ENOMEM; 803 804 port->pool_short->port_map |= BIT(port->id); 805 806 for (rxq = 0; rxq < port->nrxqs; rxq++) 807 mvpp2_rxq_short_pool_set(port, rxq, 808 port->pool_short->id); 809 } 810 811 return 0; 812 } 813 814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 815 { 816 struct mvpp2_port *port = netdev_priv(dev); 817 enum mvpp2_bm_pool_log_num new_long_pool; 818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 819 820 /* If port MTU is higher than 1518B: 821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 823 */ 824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 825 new_long_pool = MVPP2_BM_JUMBO; 826 else 827 new_long_pool = MVPP2_BM_LONG; 828 829 if (new_long_pool != port->pool_long->id) { 830 /* Remove port from old short & long pool */ 831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 832 port->pool_long->pkt_size); 833 port->pool_long->port_map &= ~BIT(port->id); 834 port->pool_long = NULL; 835 836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 837 port->pool_short->pkt_size); 838 port->pool_short->port_map &= ~BIT(port->id); 839 port->pool_short = NULL; 840 841 port->pkt_size = pkt_size; 842 843 /* Add port to new short & long pool */ 844 mvpp2_swf_bm_pool_init(port); 845 846 /* Update L4 checksum when jumbo enable/disable on port */ 847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 849 dev->hw_features &= ~(NETIF_F_IP_CSUM | 850 NETIF_F_IPV6_CSUM); 851 } else { 852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 854 } 855 } 856 857 dev->mtu = mtu; 858 dev->wanted_features = dev->features; 859 860 netdev_update_features(dev); 861 return 0; 862 } 863 864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 865 { 866 int i, sw_thread_mask = 0; 867 868 for (i = 0; i < port->nqvecs; i++) 869 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 870 871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 873 } 874 875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 876 { 877 int i, sw_thread_mask = 0; 878 879 for (i = 0; i < port->nqvecs; i++) 880 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 881 882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 884 } 885 886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 887 { 888 struct mvpp2_port *port = qvec->port; 889 890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 892 } 893 894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 895 { 896 struct mvpp2_port *port = qvec->port; 897 898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 900 } 901 902 /* Mask the current thread's Rx/Tx interrupts 903 * Called by on_each_cpu(), guaranteed to run with migration disabled, 904 * using smp_processor_id() is OK. 905 */ 906 static void mvpp2_interrupts_mask(void *arg) 907 { 908 struct mvpp2_port *port = arg; 909 910 /* If the thread isn't used, don't do anything */ 911 if (smp_processor_id() > port->priv->nthreads) 912 return; 913 914 mvpp2_thread_write(port->priv, 915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 917 } 918 919 /* Unmask the current thread's Rx/Tx interrupts. 920 * Called by on_each_cpu(), guaranteed to run with migration disabled, 921 * using smp_processor_id() is OK. 922 */ 923 static void mvpp2_interrupts_unmask(void *arg) 924 { 925 struct mvpp2_port *port = arg; 926 u32 val; 927 928 /* If the thread isn't used, don't do anything */ 929 if (smp_processor_id() > port->priv->nthreads) 930 return; 931 932 val = MVPP2_CAUSE_MISC_SUM_MASK | 933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 934 if (port->has_tx_irqs) 935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 936 937 mvpp2_thread_write(port->priv, 938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 940 } 941 942 static void 943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 944 { 945 u32 val; 946 int i; 947 948 if (port->priv->hw_version != MVPP22) 949 return; 950 951 if (mask) 952 val = 0; 953 else 954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 955 956 for (i = 0; i < port->nqvecs; i++) { 957 struct mvpp2_queue_vector *v = port->qvecs + i; 958 959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 960 continue; 961 962 mvpp2_thread_write(port->priv, v->sw_thread_id, 963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 964 } 965 } 966 967 /* Port configuration routines */ 968 static bool mvpp2_is_xlg(phy_interface_t interface) 969 { 970 return interface == PHY_INTERFACE_MODE_10GKR || 971 interface == PHY_INTERFACE_MODE_XAUI; 972 } 973 974 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 975 { 976 struct mvpp2 *priv = port->priv; 977 u32 val; 978 979 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 980 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 981 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 982 983 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 984 if (port->gop_id == 2) 985 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 986 else if (port->gop_id == 3) 987 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 988 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 989 } 990 991 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 992 { 993 struct mvpp2 *priv = port->priv; 994 u32 val; 995 996 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 997 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 998 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 999 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1000 1001 if (port->gop_id > 1) { 1002 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1003 if (port->gop_id == 2) 1004 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1005 else if (port->gop_id == 3) 1006 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1007 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1008 } 1009 } 1010 1011 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1012 { 1013 struct mvpp2 *priv = port->priv; 1014 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1015 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1016 u32 val; 1017 1018 val = readl(xpcs + MVPP22_XPCS_CFG0); 1019 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1020 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1021 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1022 writel(val, xpcs + MVPP22_XPCS_CFG0); 1023 1024 val = readl(mpcs + MVPP22_MPCS_CTRL); 1025 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1026 writel(val, mpcs + MVPP22_MPCS_CTRL); 1027 1028 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1029 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1030 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1031 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1032 } 1033 1034 static int mvpp22_gop_init(struct mvpp2_port *port) 1035 { 1036 struct mvpp2 *priv = port->priv; 1037 u32 val; 1038 1039 if (!priv->sysctrl_base) 1040 return 0; 1041 1042 switch (port->phy_interface) { 1043 case PHY_INTERFACE_MODE_RGMII: 1044 case PHY_INTERFACE_MODE_RGMII_ID: 1045 case PHY_INTERFACE_MODE_RGMII_RXID: 1046 case PHY_INTERFACE_MODE_RGMII_TXID: 1047 if (port->gop_id == 0) 1048 goto invalid_conf; 1049 mvpp22_gop_init_rgmii(port); 1050 break; 1051 case PHY_INTERFACE_MODE_SGMII: 1052 case PHY_INTERFACE_MODE_1000BASEX: 1053 case PHY_INTERFACE_MODE_2500BASEX: 1054 mvpp22_gop_init_sgmii(port); 1055 break; 1056 case PHY_INTERFACE_MODE_10GKR: 1057 if (port->gop_id != 0) 1058 goto invalid_conf; 1059 mvpp22_gop_init_10gkr(port); 1060 break; 1061 default: 1062 goto unsupported_conf; 1063 } 1064 1065 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1066 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1067 GENCONF_PORT_CTRL1_EN(port->gop_id); 1068 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1069 1070 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1071 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1072 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1073 1074 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1075 val |= GENCONF_SOFT_RESET1_GOP; 1076 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1077 1078 unsupported_conf: 1079 return 0; 1080 1081 invalid_conf: 1082 netdev_err(port->dev, "Invalid port configuration\n"); 1083 return -EINVAL; 1084 } 1085 1086 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1087 { 1088 u32 val; 1089 1090 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1091 phy_interface_mode_is_8023z(port->phy_interface) || 1092 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1093 /* Enable the GMAC link status irq for this port */ 1094 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1095 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1096 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1097 } 1098 1099 if (port->gop_id == 0) { 1100 /* Enable the XLG/GIG irqs for this port */ 1101 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1102 if (mvpp2_is_xlg(port->phy_interface)) 1103 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1104 else 1105 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1106 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1107 } 1108 } 1109 1110 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1111 { 1112 u32 val; 1113 1114 if (port->gop_id == 0) { 1115 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1116 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1117 MVPP22_XLG_EXT_INT_MASK_GIG); 1118 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1119 } 1120 1121 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1122 phy_interface_mode_is_8023z(port->phy_interface) || 1123 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1124 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1125 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1126 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1127 } 1128 } 1129 1130 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1131 { 1132 u32 val; 1133 1134 if (port->phylink || 1135 phy_interface_mode_is_rgmii(port->phy_interface) || 1136 phy_interface_mode_is_8023z(port->phy_interface) || 1137 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1138 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1139 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1140 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1141 } 1142 1143 if (port->gop_id == 0) { 1144 val = readl(port->base + MVPP22_XLG_INT_MASK); 1145 val |= MVPP22_XLG_INT_MASK_LINK; 1146 writel(val, port->base + MVPP22_XLG_INT_MASK); 1147 } 1148 1149 mvpp22_gop_unmask_irq(port); 1150 } 1151 1152 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1153 * 1154 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1155 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1156 * differ. 1157 * 1158 * The COMPHY configures the serdes lanes regardless of the actual use of the 1159 * lanes by the physical layer. This is why configurations like 1160 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1161 */ 1162 static int mvpp22_comphy_init(struct mvpp2_port *port) 1163 { 1164 int ret; 1165 1166 if (!port->comphy) 1167 return 0; 1168 1169 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1170 port->phy_interface); 1171 if (ret) 1172 return ret; 1173 1174 return phy_power_on(port->comphy); 1175 } 1176 1177 static void mvpp2_port_enable(struct mvpp2_port *port) 1178 { 1179 u32 val; 1180 1181 /* Only GOP port 0 has an XLG MAC */ 1182 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1183 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1184 val |= MVPP22_XLG_CTRL0_PORT_EN; 1185 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1186 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1187 } else { 1188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1189 val |= MVPP2_GMAC_PORT_EN_MASK; 1190 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1192 } 1193 } 1194 1195 static void mvpp2_port_disable(struct mvpp2_port *port) 1196 { 1197 u32 val; 1198 1199 /* Only GOP port 0 has an XLG MAC */ 1200 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1201 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1202 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1203 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1204 } 1205 1206 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1207 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1208 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1209 } 1210 1211 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1212 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1213 { 1214 u32 val; 1215 1216 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1217 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1218 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1219 } 1220 1221 /* Configure loopback port */ 1222 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1223 const struct phylink_link_state *state) 1224 { 1225 u32 val; 1226 1227 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1228 1229 if (state->speed == 1000) 1230 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1231 else 1232 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1233 1234 if (phy_interface_mode_is_8023z(port->phy_interface) || 1235 port->phy_interface == PHY_INTERFACE_MODE_SGMII) 1236 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1237 else 1238 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1239 1240 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1241 } 1242 1243 struct mvpp2_ethtool_counter { 1244 unsigned int offset; 1245 const char string[ETH_GSTRING_LEN]; 1246 bool reg_is_64b; 1247 }; 1248 1249 static u64 mvpp2_read_count(struct mvpp2_port *port, 1250 const struct mvpp2_ethtool_counter *counter) 1251 { 1252 u64 val; 1253 1254 val = readl(port->stats_base + counter->offset); 1255 if (counter->reg_is_64b) 1256 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1257 1258 return val; 1259 } 1260 1261 /* Due to the fact that software statistics and hardware statistics are, by 1262 * design, incremented at different moments in the chain of packet processing, 1263 * it is very likely that incoming packets could have been dropped after being 1264 * counted by hardware but before reaching software statistics (most probably 1265 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1266 * are added in between as well as TSO skb will be split and header bytes added. 1267 * Hence, statistics gathered from userspace with ifconfig (software) and 1268 * ethtool (hardware) cannot be compared. 1269 */ 1270 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { 1271 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1272 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1273 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1274 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1275 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1276 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1277 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1278 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1279 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1280 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1281 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1282 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1283 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1284 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1285 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1286 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1287 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1288 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1289 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1290 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1291 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1292 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1293 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1294 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1295 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1296 { MVPP2_MIB_COLLISION, "collision" }, 1297 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1298 }; 1299 1300 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1301 u8 *data) 1302 { 1303 if (sset == ETH_SS_STATS) { 1304 int i; 1305 1306 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1307 strscpy(data + i * ETH_GSTRING_LEN, 1308 mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); 1309 } 1310 } 1311 1312 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1313 { 1314 struct delayed_work *del_work = to_delayed_work(work); 1315 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1316 stats_work); 1317 u64 *pstats; 1318 int i; 1319 1320 mutex_lock(&port->gather_stats_lock); 1321 1322 pstats = port->ethtool_stats; 1323 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1324 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1325 1326 /* No need to read again the counters right after this function if it 1327 * was called asynchronously by the user (ie. use of ethtool). 1328 */ 1329 cancel_delayed_work(&port->stats_work); 1330 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1331 MVPP2_MIB_COUNTERS_STATS_DELAY); 1332 1333 mutex_unlock(&port->gather_stats_lock); 1334 } 1335 1336 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1337 struct ethtool_stats *stats, u64 *data) 1338 { 1339 struct mvpp2_port *port = netdev_priv(dev); 1340 1341 /* Update statistics for the given port, then take the lock to avoid 1342 * concurrent accesses on the ethtool_stats structure during its copy. 1343 */ 1344 mvpp2_gather_hw_statistics(&port->stats_work.work); 1345 1346 mutex_lock(&port->gather_stats_lock); 1347 memcpy(data, port->ethtool_stats, 1348 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); 1349 mutex_unlock(&port->gather_stats_lock); 1350 } 1351 1352 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1353 { 1354 if (sset == ETH_SS_STATS) 1355 return ARRAY_SIZE(mvpp2_ethtool_regs); 1356 1357 return -EOPNOTSUPP; 1358 } 1359 1360 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 1361 { 1362 unsigned int i; 1363 u32 val; 1364 1365 /* Read the GOP statistics to reset the hardware counters */ 1366 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1367 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1368 1369 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1370 MVPP2_GMAC_PORT_RESET_MASK; 1371 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1372 1373 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 1374 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 1375 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1376 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1377 } 1378 } 1379 1380 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 1381 { 1382 struct mvpp2 *priv = port->priv; 1383 void __iomem *mpcs, *xpcs; 1384 u32 val; 1385 1386 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1387 return; 1388 1389 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1390 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1391 1392 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1393 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1394 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 1395 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1396 1397 val = readl(xpcs + MVPP22_XPCS_CFG0); 1398 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1399 } 1400 1401 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 1402 { 1403 struct mvpp2 *priv = port->priv; 1404 void __iomem *mpcs, *xpcs; 1405 u32 val; 1406 1407 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1408 return; 1409 1410 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1411 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1412 1413 switch (port->phy_interface) { 1414 case PHY_INTERFACE_MODE_10GKR: 1415 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1416 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 1417 MAC_CLK_RESET_SD_TX; 1418 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1419 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1420 break; 1421 case PHY_INTERFACE_MODE_XAUI: 1422 case PHY_INTERFACE_MODE_RXAUI: 1423 val = readl(xpcs + MVPP22_XPCS_CFG0); 1424 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1425 break; 1426 default: 1427 break; 1428 } 1429 } 1430 1431 /* Change maximum receive size of the port */ 1432 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1433 { 1434 u32 val; 1435 1436 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1437 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1438 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1439 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1440 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1441 } 1442 1443 /* Change maximum receive size of the port */ 1444 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1445 { 1446 u32 val; 1447 1448 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1449 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1450 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1451 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1452 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1453 } 1454 1455 /* Set defaults to the MVPP2 port */ 1456 static void mvpp2_defaults_set(struct mvpp2_port *port) 1457 { 1458 int tx_port_num, val, queue, lrxq; 1459 1460 if (port->priv->hw_version == MVPP21) { 1461 /* Update TX FIFO MIN Threshold */ 1462 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1463 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1464 /* Min. TX threshold must be less than minimal packet length */ 1465 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1466 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1467 } 1468 1469 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1470 tx_port_num = mvpp2_egress_port(port); 1471 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1472 tx_port_num); 1473 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1474 1475 /* Set TXQ scheduling to Round-Robin */ 1476 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1477 1478 /* Close bandwidth for all queues */ 1479 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 1480 mvpp2_write(port->priv, 1481 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 1482 1483 /* Set refill period to 1 usec, refill tokens 1484 * and bucket size to maximum 1485 */ 1486 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1487 port->priv->tclk / USEC_PER_SEC); 1488 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1489 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1490 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1491 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1492 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1493 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1494 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1495 1496 /* Set MaximumLowLatencyPacketSize value to 256 */ 1497 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1498 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1499 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1500 1501 /* Enable Rx cache snoop */ 1502 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1503 queue = port->rxqs[lrxq]->id; 1504 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1505 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1506 MVPP2_SNOOP_BUF_HDR_MASK; 1507 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1508 } 1509 1510 /* At default, mask all interrupts to all present cpus */ 1511 mvpp2_interrupts_disable(port); 1512 } 1513 1514 /* Enable/disable receiving packets */ 1515 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1516 { 1517 u32 val; 1518 int lrxq, queue; 1519 1520 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1521 queue = port->rxqs[lrxq]->id; 1522 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1523 val &= ~MVPP2_RXQ_DISABLE_MASK; 1524 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1525 } 1526 } 1527 1528 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1529 { 1530 u32 val; 1531 int lrxq, queue; 1532 1533 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1534 queue = port->rxqs[lrxq]->id; 1535 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1536 val |= MVPP2_RXQ_DISABLE_MASK; 1537 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1538 } 1539 } 1540 1541 /* Enable transmit via physical egress queue 1542 * - HW starts take descriptors from DRAM 1543 */ 1544 static void mvpp2_egress_enable(struct mvpp2_port *port) 1545 { 1546 u32 qmap; 1547 int queue; 1548 int tx_port_num = mvpp2_egress_port(port); 1549 1550 /* Enable all initialized TXs. */ 1551 qmap = 0; 1552 for (queue = 0; queue < port->ntxqs; queue++) { 1553 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1554 1555 if (txq->descs) 1556 qmap |= (1 << queue); 1557 } 1558 1559 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1560 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1561 } 1562 1563 /* Disable transmit via physical egress queue 1564 * - HW doesn't take descriptors from DRAM 1565 */ 1566 static void mvpp2_egress_disable(struct mvpp2_port *port) 1567 { 1568 u32 reg_data; 1569 int delay; 1570 int tx_port_num = mvpp2_egress_port(port); 1571 1572 /* Issue stop command for active channels only */ 1573 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1574 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1575 MVPP2_TXP_SCHED_ENQ_MASK; 1576 if (reg_data != 0) 1577 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1578 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1579 1580 /* Wait for all Tx activity to terminate. */ 1581 delay = 0; 1582 do { 1583 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1584 netdev_warn(port->dev, 1585 "Tx stop timed out, status=0x%08x\n", 1586 reg_data); 1587 break; 1588 } 1589 mdelay(1); 1590 delay++; 1591 1592 /* Check port TX Command register that all 1593 * Tx queues are stopped 1594 */ 1595 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1596 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1597 } 1598 1599 /* Rx descriptors helper methods */ 1600 1601 /* Get number of Rx descriptors occupied by received packets */ 1602 static inline int 1603 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1604 { 1605 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1606 1607 return val & MVPP2_RXQ_OCCUPIED_MASK; 1608 } 1609 1610 /* Update Rx queue status with the number of occupied and available 1611 * Rx descriptor slots. 1612 */ 1613 static inline void 1614 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1615 int used_count, int free_count) 1616 { 1617 /* Decrement the number of used descriptors and increment count 1618 * increment the number of free descriptors. 1619 */ 1620 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1621 1622 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1623 } 1624 1625 /* Get pointer to next RX descriptor to be processed by SW */ 1626 static inline struct mvpp2_rx_desc * 1627 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1628 { 1629 int rx_desc = rxq->next_desc_to_proc; 1630 1631 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1632 prefetch(rxq->descs + rxq->next_desc_to_proc); 1633 return rxq->descs + rx_desc; 1634 } 1635 1636 /* Set rx queue offset */ 1637 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1638 int prxq, int offset) 1639 { 1640 u32 val; 1641 1642 /* Convert offset from bytes to units of 32 bytes */ 1643 offset = offset >> 5; 1644 1645 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1646 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1647 1648 /* Offset is in */ 1649 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1650 MVPP2_RXQ_PACKET_OFFSET_MASK); 1651 1652 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1653 } 1654 1655 /* Tx descriptors helper methods */ 1656 1657 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1658 static struct mvpp2_tx_desc * 1659 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1660 { 1661 int tx_desc = txq->next_desc_to_proc; 1662 1663 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1664 return txq->descs + tx_desc; 1665 } 1666 1667 /* Update HW with number of aggregated Tx descriptors to be sent 1668 * 1669 * Called only from mvpp2_tx(), so migration is disabled, using 1670 * smp_processor_id() is OK. 1671 */ 1672 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1673 { 1674 /* aggregated access - relevant TXQ number is written in TX desc */ 1675 mvpp2_thread_write(port->priv, 1676 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1677 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1678 } 1679 1680 /* Check if there are enough free descriptors in aggregated txq. 1681 * If not, update the number of occupied descriptors and repeat the check. 1682 * 1683 * Called only from mvpp2_tx(), so migration is disabled, using 1684 * smp_processor_id() is OK. 1685 */ 1686 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 1687 struct mvpp2_tx_queue *aggr_txq, int num) 1688 { 1689 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1690 /* Update number of occupied aggregated Tx descriptors */ 1691 unsigned int thread = 1692 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1693 u32 val = mvpp2_read_relaxed(port->priv, 1694 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 1695 1696 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1697 1698 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1699 return -ENOMEM; 1700 } 1701 return 0; 1702 } 1703 1704 /* Reserved Tx descriptors allocation request 1705 * 1706 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1707 * only by mvpp2_tx(), so migration is disabled, using 1708 * smp_processor_id() is OK. 1709 */ 1710 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 1711 struct mvpp2_tx_queue *txq, int num) 1712 { 1713 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1714 struct mvpp2 *priv = port->priv; 1715 u32 val; 1716 1717 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1718 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 1719 1720 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 1721 1722 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1723 } 1724 1725 /* Check if there are enough reserved descriptors for transmission. 1726 * If not, request chunk of reserved descriptors and check again. 1727 */ 1728 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 1729 struct mvpp2_tx_queue *txq, 1730 struct mvpp2_txq_pcpu *txq_pcpu, 1731 int num) 1732 { 1733 int req, desc_count; 1734 unsigned int thread; 1735 1736 if (txq_pcpu->reserved_num >= num) 1737 return 0; 1738 1739 /* Not enough descriptors reserved! Update the reserved descriptor 1740 * count and check again. 1741 */ 1742 1743 desc_count = 0; 1744 /* Compute total of used descriptors */ 1745 for (thread = 0; thread < port->priv->nthreads; thread++) { 1746 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1747 1748 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 1749 desc_count += txq_pcpu_aux->count; 1750 desc_count += txq_pcpu_aux->reserved_num; 1751 } 1752 1753 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1754 desc_count += req; 1755 1756 if (desc_count > 1757 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 1758 return -ENOMEM; 1759 1760 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 1761 1762 /* OK, the descriptor could have been updated: check again. */ 1763 if (txq_pcpu->reserved_num < num) 1764 return -ENOMEM; 1765 return 0; 1766 } 1767 1768 /* Release the last allocated Tx descriptor. Useful to handle DMA 1769 * mapping failures in the Tx path. 1770 */ 1771 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1772 { 1773 if (txq->next_desc_to_proc == 0) 1774 txq->next_desc_to_proc = txq->last_desc - 1; 1775 else 1776 txq->next_desc_to_proc--; 1777 } 1778 1779 /* Set Tx descriptors fields relevant for CSUM calculation */ 1780 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 1781 int ip_hdr_len, int l4_proto) 1782 { 1783 u32 command; 1784 1785 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1786 * G_L4_chk, L4_type required only for checksum calculation 1787 */ 1788 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1789 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1790 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1791 1792 if (l3_proto == htons(ETH_P_IP)) { 1793 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1794 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1795 } else { 1796 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1797 } 1798 1799 if (l4_proto == IPPROTO_TCP) { 1800 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1801 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1802 } else if (l4_proto == IPPROTO_UDP) { 1803 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1804 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1805 } else { 1806 command |= MVPP2_TXD_L4_CSUM_NOT; 1807 } 1808 1809 return command; 1810 } 1811 1812 /* Get number of sent descriptors and decrement counter. 1813 * The number of sent descriptors is returned. 1814 * Per-thread access 1815 * 1816 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1817 * (migration disabled) and from the TX completion tasklet (migration 1818 * disabled) so using smp_processor_id() is OK. 1819 */ 1820 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1821 struct mvpp2_tx_queue *txq) 1822 { 1823 u32 val; 1824 1825 /* Reading status reg resets transmitted descriptor counter */ 1826 val = mvpp2_thread_read_relaxed(port->priv, 1827 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1828 MVPP2_TXQ_SENT_REG(txq->id)); 1829 1830 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1831 MVPP2_TRANSMITTED_COUNT_OFFSET; 1832 } 1833 1834 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1835 * disabled, therefore using smp_processor_id() is OK. 1836 */ 1837 static void mvpp2_txq_sent_counter_clear(void *arg) 1838 { 1839 struct mvpp2_port *port = arg; 1840 int queue; 1841 1842 /* If the thread isn't used, don't do anything */ 1843 if (smp_processor_id() > port->priv->nthreads) 1844 return; 1845 1846 for (queue = 0; queue < port->ntxqs; queue++) { 1847 int id = port->txqs[queue]->id; 1848 1849 mvpp2_thread_read(port->priv, 1850 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1851 MVPP2_TXQ_SENT_REG(id)); 1852 } 1853 } 1854 1855 /* Set max sizes for Tx queues */ 1856 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1857 { 1858 u32 val, size, mtu; 1859 int txq, tx_port_num; 1860 1861 mtu = port->pkt_size * 8; 1862 if (mtu > MVPP2_TXP_MTU_MAX) 1863 mtu = MVPP2_TXP_MTU_MAX; 1864 1865 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1866 mtu = 3 * mtu; 1867 1868 /* Indirect access to registers */ 1869 tx_port_num = mvpp2_egress_port(port); 1870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1871 1872 /* Set MTU */ 1873 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1874 val &= ~MVPP2_TXP_MTU_MAX; 1875 val |= mtu; 1876 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1877 1878 /* TXP token size and all TXQs token size must be larger that MTU */ 1879 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1880 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1881 if (size < mtu) { 1882 size = mtu; 1883 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1884 val |= size; 1885 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1886 } 1887 1888 for (txq = 0; txq < port->ntxqs; txq++) { 1889 val = mvpp2_read(port->priv, 1890 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1891 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1892 1893 if (size < mtu) { 1894 size = mtu; 1895 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1896 val |= size; 1897 mvpp2_write(port->priv, 1898 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1899 val); 1900 } 1901 } 1902 } 1903 1904 /* Set the number of packets that will be received before Rx interrupt 1905 * will be generated by HW. 1906 */ 1907 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1908 struct mvpp2_rx_queue *rxq) 1909 { 1910 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1911 1912 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 1913 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 1914 1915 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 1916 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 1917 rxq->pkts_coal); 1918 1919 put_cpu(); 1920 } 1921 1922 /* For some reason in the LSP this is done on each CPU. Why ? */ 1923 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 1924 struct mvpp2_tx_queue *txq) 1925 { 1926 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1927 u32 val; 1928 1929 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 1930 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 1931 1932 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 1933 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 1934 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 1935 1936 put_cpu(); 1937 } 1938 1939 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 1940 { 1941 u64 tmp = (u64)clk_hz * usec; 1942 1943 do_div(tmp, USEC_PER_SEC); 1944 1945 return tmp > U32_MAX ? U32_MAX : tmp; 1946 } 1947 1948 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 1949 { 1950 u64 tmp = (u64)cycles * USEC_PER_SEC; 1951 1952 do_div(tmp, clk_hz); 1953 1954 return tmp > U32_MAX ? U32_MAX : tmp; 1955 } 1956 1957 /* Set the time delay in usec before Rx interrupt */ 1958 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 1959 struct mvpp2_rx_queue *rxq) 1960 { 1961 unsigned long freq = port->priv->tclk; 1962 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1963 1964 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 1965 rxq->time_coal = 1966 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 1967 1968 /* re-evaluate to get actual register value */ 1969 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1970 } 1971 1972 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 1973 } 1974 1975 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 1976 { 1977 unsigned long freq = port->priv->tclk; 1978 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1979 1980 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 1981 port->tx_time_coal = 1982 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 1983 1984 /* re-evaluate to get actual register value */ 1985 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1986 } 1987 1988 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 1989 } 1990 1991 /* Free Tx queue skbuffs */ 1992 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 1993 struct mvpp2_tx_queue *txq, 1994 struct mvpp2_txq_pcpu *txq_pcpu, int num) 1995 { 1996 int i; 1997 1998 for (i = 0; i < num; i++) { 1999 struct mvpp2_txq_pcpu_buf *tx_buf = 2000 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2001 2002 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 2003 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2004 tx_buf->size, DMA_TO_DEVICE); 2005 if (tx_buf->skb) 2006 dev_kfree_skb_any(tx_buf->skb); 2007 2008 mvpp2_txq_inc_get(txq_pcpu); 2009 } 2010 } 2011 2012 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2013 u32 cause) 2014 { 2015 int queue = fls(cause) - 1; 2016 2017 return port->rxqs[queue]; 2018 } 2019 2020 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2021 u32 cause) 2022 { 2023 int queue = fls(cause) - 1; 2024 2025 return port->txqs[queue]; 2026 } 2027 2028 /* Handle end of transmission */ 2029 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2030 struct mvpp2_txq_pcpu *txq_pcpu) 2031 { 2032 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2033 int tx_done; 2034 2035 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2036 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2037 2038 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2039 if (!tx_done) 2040 return; 2041 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2042 2043 txq_pcpu->count -= tx_done; 2044 2045 if (netif_tx_queue_stopped(nq)) 2046 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2047 netif_tx_wake_queue(nq); 2048 } 2049 2050 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2051 unsigned int thread) 2052 { 2053 struct mvpp2_tx_queue *txq; 2054 struct mvpp2_txq_pcpu *txq_pcpu; 2055 unsigned int tx_todo = 0; 2056 2057 while (cause) { 2058 txq = mvpp2_get_tx_queue(port, cause); 2059 if (!txq) 2060 break; 2061 2062 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2063 2064 if (txq_pcpu->count) { 2065 mvpp2_txq_done(port, txq, txq_pcpu); 2066 tx_todo += txq_pcpu->count; 2067 } 2068 2069 cause &= ~(1 << txq->log_id); 2070 } 2071 return tx_todo; 2072 } 2073 2074 /* Rx/Tx queue initialization/cleanup methods */ 2075 2076 /* Allocate and initialize descriptors for aggr TXQ */ 2077 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2078 struct mvpp2_tx_queue *aggr_txq, 2079 unsigned int thread, struct mvpp2 *priv) 2080 { 2081 u32 txq_dma; 2082 2083 /* Allocate memory for TX descriptors */ 2084 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2085 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2086 &aggr_txq->descs_dma, GFP_KERNEL); 2087 if (!aggr_txq->descs) 2088 return -ENOMEM; 2089 2090 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2091 2092 /* Aggr TXQ no reset WA */ 2093 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2094 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2095 2096 /* Set Tx descriptors queue starting address indirect 2097 * access 2098 */ 2099 if (priv->hw_version == MVPP21) 2100 txq_dma = aggr_txq->descs_dma; 2101 else 2102 txq_dma = aggr_txq->descs_dma >> 2103 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2104 2105 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2106 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2107 MVPP2_AGGR_TXQ_SIZE); 2108 2109 return 0; 2110 } 2111 2112 /* Create a specified Rx queue */ 2113 static int mvpp2_rxq_init(struct mvpp2_port *port, 2114 struct mvpp2_rx_queue *rxq) 2115 2116 { 2117 unsigned int thread; 2118 u32 rxq_dma; 2119 2120 rxq->size = port->rx_ring_size; 2121 2122 /* Allocate memory for RX descriptors */ 2123 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2124 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2125 &rxq->descs_dma, GFP_KERNEL); 2126 if (!rxq->descs) 2127 return -ENOMEM; 2128 2129 rxq->last_desc = rxq->size - 1; 2130 2131 /* Zero occupied and non-occupied counters - direct access */ 2132 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2133 2134 /* Set Rx descriptors queue starting address - indirect access */ 2135 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2136 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2137 if (port->priv->hw_version == MVPP21) 2138 rxq_dma = rxq->descs_dma; 2139 else 2140 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2141 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2142 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2143 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2144 put_cpu(); 2145 2146 /* Set Offset */ 2147 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2148 2149 /* Set coalescing pkts and time */ 2150 mvpp2_rx_pkts_coal_set(port, rxq); 2151 mvpp2_rx_time_coal_set(port, rxq); 2152 2153 /* Add number of descriptors ready for receiving packets */ 2154 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2155 2156 return 0; 2157 } 2158 2159 /* Push packets received by the RXQ to BM pool */ 2160 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2161 struct mvpp2_rx_queue *rxq) 2162 { 2163 int rx_received, i; 2164 2165 rx_received = mvpp2_rxq_received(port, rxq->id); 2166 if (!rx_received) 2167 return; 2168 2169 for (i = 0; i < rx_received; i++) { 2170 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2171 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2172 int pool; 2173 2174 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2175 MVPP2_RXD_BM_POOL_ID_OFFS; 2176 2177 mvpp2_bm_pool_put(port, pool, 2178 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2179 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2180 } 2181 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2182 } 2183 2184 /* Cleanup Rx queue */ 2185 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2186 struct mvpp2_rx_queue *rxq) 2187 { 2188 unsigned int thread; 2189 2190 mvpp2_rxq_drop_pkts(port, rxq); 2191 2192 if (rxq->descs) 2193 dma_free_coherent(port->dev->dev.parent, 2194 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2195 rxq->descs, 2196 rxq->descs_dma); 2197 2198 rxq->descs = NULL; 2199 rxq->last_desc = 0; 2200 rxq->next_desc_to_proc = 0; 2201 rxq->descs_dma = 0; 2202 2203 /* Clear Rx descriptors queue starting address and size; 2204 * free descriptor number 2205 */ 2206 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2207 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2208 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2209 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2210 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2211 put_cpu(); 2212 } 2213 2214 /* Create and initialize a Tx queue */ 2215 static int mvpp2_txq_init(struct mvpp2_port *port, 2216 struct mvpp2_tx_queue *txq) 2217 { 2218 u32 val; 2219 unsigned int thread; 2220 int desc, desc_per_txq, tx_port_num; 2221 struct mvpp2_txq_pcpu *txq_pcpu; 2222 2223 txq->size = port->tx_ring_size; 2224 2225 /* Allocate memory for Tx descriptors */ 2226 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2227 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2228 &txq->descs_dma, GFP_KERNEL); 2229 if (!txq->descs) 2230 return -ENOMEM; 2231 2232 txq->last_desc = txq->size - 1; 2233 2234 /* Set Tx descriptors queue starting address - indirect access */ 2235 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2236 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2237 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2238 txq->descs_dma); 2239 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2240 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2241 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2242 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2243 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2244 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2245 val &= ~MVPP2_TXQ_PENDING_MASK; 2246 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2247 2248 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2249 * for each existing TXQ. 2250 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2251 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2252 */ 2253 desc_per_txq = 16; 2254 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2255 (txq->log_id * desc_per_txq); 2256 2257 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2258 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2259 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2260 put_cpu(); 2261 2262 /* WRR / EJP configuration - indirect access */ 2263 tx_port_num = mvpp2_egress_port(port); 2264 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2265 2266 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2267 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2268 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2269 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2270 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2271 2272 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2273 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2274 val); 2275 2276 for (thread = 0; thread < port->priv->nthreads; thread++) { 2277 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2278 txq_pcpu->size = txq->size; 2279 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2280 sizeof(*txq_pcpu->buffs), 2281 GFP_KERNEL); 2282 if (!txq_pcpu->buffs) 2283 return -ENOMEM; 2284 2285 txq_pcpu->count = 0; 2286 txq_pcpu->reserved_num = 0; 2287 txq_pcpu->txq_put_index = 0; 2288 txq_pcpu->txq_get_index = 0; 2289 txq_pcpu->tso_headers = NULL; 2290 2291 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2292 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2293 2294 txq_pcpu->tso_headers = 2295 dma_alloc_coherent(port->dev->dev.parent, 2296 txq_pcpu->size * TSO_HEADER_SIZE, 2297 &txq_pcpu->tso_headers_dma, 2298 GFP_KERNEL); 2299 if (!txq_pcpu->tso_headers) 2300 return -ENOMEM; 2301 } 2302 2303 return 0; 2304 } 2305 2306 /* Free allocated TXQ resources */ 2307 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2308 struct mvpp2_tx_queue *txq) 2309 { 2310 struct mvpp2_txq_pcpu *txq_pcpu; 2311 unsigned int thread; 2312 2313 for (thread = 0; thread < port->priv->nthreads; thread++) { 2314 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2315 kfree(txq_pcpu->buffs); 2316 2317 if (txq_pcpu->tso_headers) 2318 dma_free_coherent(port->dev->dev.parent, 2319 txq_pcpu->size * TSO_HEADER_SIZE, 2320 txq_pcpu->tso_headers, 2321 txq_pcpu->tso_headers_dma); 2322 2323 txq_pcpu->tso_headers = NULL; 2324 } 2325 2326 if (txq->descs) 2327 dma_free_coherent(port->dev->dev.parent, 2328 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2329 txq->descs, txq->descs_dma); 2330 2331 txq->descs = NULL; 2332 txq->last_desc = 0; 2333 txq->next_desc_to_proc = 0; 2334 txq->descs_dma = 0; 2335 2336 /* Set minimum bandwidth for disabled TXQs */ 2337 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 2338 2339 /* Set Tx descriptors queue starting address and size */ 2340 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2341 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2342 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2343 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2344 put_cpu(); 2345 } 2346 2347 /* Cleanup Tx ports */ 2348 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2349 { 2350 struct mvpp2_txq_pcpu *txq_pcpu; 2351 int delay, pending; 2352 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2353 u32 val; 2354 2355 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2356 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2357 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2358 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2359 2360 /* The napi queue has been stopped so wait for all packets 2361 * to be transmitted. 2362 */ 2363 delay = 0; 2364 do { 2365 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2366 netdev_warn(port->dev, 2367 "port %d: cleaning queue %d timed out\n", 2368 port->id, txq->log_id); 2369 break; 2370 } 2371 mdelay(1); 2372 delay++; 2373 2374 pending = mvpp2_thread_read(port->priv, thread, 2375 MVPP2_TXQ_PENDING_REG); 2376 pending &= MVPP2_TXQ_PENDING_MASK; 2377 } while (pending); 2378 2379 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2380 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2381 put_cpu(); 2382 2383 for (thread = 0; thread < port->priv->nthreads; thread++) { 2384 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2385 2386 /* Release all packets */ 2387 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2388 2389 /* Reset queue */ 2390 txq_pcpu->count = 0; 2391 txq_pcpu->txq_put_index = 0; 2392 txq_pcpu->txq_get_index = 0; 2393 } 2394 } 2395 2396 /* Cleanup all Tx queues */ 2397 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2398 { 2399 struct mvpp2_tx_queue *txq; 2400 int queue; 2401 u32 val; 2402 2403 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2404 2405 /* Reset Tx ports and delete Tx queues */ 2406 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2407 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2408 2409 for (queue = 0; queue < port->ntxqs; queue++) { 2410 txq = port->txqs[queue]; 2411 mvpp2_txq_clean(port, txq); 2412 mvpp2_txq_deinit(port, txq); 2413 } 2414 2415 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2416 2417 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2418 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2419 } 2420 2421 /* Cleanup all Rx queues */ 2422 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2423 { 2424 int queue; 2425 2426 for (queue = 0; queue < port->nrxqs; queue++) 2427 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2428 } 2429 2430 /* Init all Rx queues for port */ 2431 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2432 { 2433 int queue, err; 2434 2435 for (queue = 0; queue < port->nrxqs; queue++) { 2436 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2437 if (err) 2438 goto err_cleanup; 2439 } 2440 return 0; 2441 2442 err_cleanup: 2443 mvpp2_cleanup_rxqs(port); 2444 return err; 2445 } 2446 2447 /* Init all tx queues for port */ 2448 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2449 { 2450 struct mvpp2_tx_queue *txq; 2451 int queue, err, cpu; 2452 2453 for (queue = 0; queue < port->ntxqs; queue++) { 2454 txq = port->txqs[queue]; 2455 err = mvpp2_txq_init(port, txq); 2456 if (err) 2457 goto err_cleanup; 2458 2459 /* Assign this queue to a CPU */ 2460 cpu = queue % num_present_cpus(); 2461 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue); 2462 } 2463 2464 if (port->has_tx_irqs) { 2465 mvpp2_tx_time_coal_set(port); 2466 for (queue = 0; queue < port->ntxqs; queue++) { 2467 txq = port->txqs[queue]; 2468 mvpp2_tx_pkts_coal_set(port, txq); 2469 } 2470 } 2471 2472 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2473 return 0; 2474 2475 err_cleanup: 2476 mvpp2_cleanup_txqs(port); 2477 return err; 2478 } 2479 2480 /* The callback for per-port interrupt */ 2481 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2482 { 2483 struct mvpp2_queue_vector *qv = dev_id; 2484 2485 mvpp2_qvec_interrupt_disable(qv); 2486 2487 napi_schedule(&qv->napi); 2488 2489 return IRQ_HANDLED; 2490 } 2491 2492 /* Per-port interrupt for link status changes */ 2493 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2494 { 2495 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2496 struct net_device *dev = port->dev; 2497 bool event = false, link = false; 2498 u32 val; 2499 2500 mvpp22_gop_mask_irq(port); 2501 2502 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 2503 val = readl(port->base + MVPP22_XLG_INT_STAT); 2504 if (val & MVPP22_XLG_INT_STAT_LINK) { 2505 event = true; 2506 val = readl(port->base + MVPP22_XLG_STATUS); 2507 if (val & MVPP22_XLG_STATUS_LINK_UP) 2508 link = true; 2509 } 2510 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2511 phy_interface_mode_is_8023z(port->phy_interface) || 2512 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 2513 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2514 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2515 event = true; 2516 val = readl(port->base + MVPP2_GMAC_STATUS0); 2517 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2518 link = true; 2519 } 2520 } 2521 2522 if (port->phylink) { 2523 phylink_mac_change(port->phylink, link); 2524 goto handled; 2525 } 2526 2527 if (!netif_running(dev) || !event) 2528 goto handled; 2529 2530 if (link) { 2531 mvpp2_interrupts_enable(port); 2532 2533 mvpp2_egress_enable(port); 2534 mvpp2_ingress_enable(port); 2535 netif_carrier_on(dev); 2536 netif_tx_wake_all_queues(dev); 2537 } else { 2538 netif_tx_stop_all_queues(dev); 2539 netif_carrier_off(dev); 2540 mvpp2_ingress_disable(port); 2541 mvpp2_egress_disable(port); 2542 2543 mvpp2_interrupts_disable(port); 2544 } 2545 2546 handled: 2547 mvpp22_gop_unmask_irq(port); 2548 return IRQ_HANDLED; 2549 } 2550 2551 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2552 { 2553 ktime_t interval; 2554 2555 if (!port_pcpu->timer_scheduled) { 2556 port_pcpu->timer_scheduled = true; 2557 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2558 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2559 HRTIMER_MODE_REL_PINNED); 2560 } 2561 } 2562 2563 static void mvpp2_tx_proc_cb(unsigned long data) 2564 { 2565 struct net_device *dev = (struct net_device *)data; 2566 struct mvpp2_port *port = netdev_priv(dev); 2567 struct mvpp2_port_pcpu *port_pcpu; 2568 unsigned int tx_todo, cause; 2569 2570 port_pcpu = per_cpu_ptr(port->pcpu, 2571 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2572 2573 if (!netif_running(dev)) 2574 return; 2575 port_pcpu->timer_scheduled = false; 2576 2577 /* Process all the Tx queues */ 2578 cause = (1 << port->ntxqs) - 1; 2579 tx_todo = mvpp2_tx_done(port, cause, 2580 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2581 2582 /* Set the timer in case not all the packets were processed */ 2583 if (tx_todo) 2584 mvpp2_timer_set(port_pcpu); 2585 } 2586 2587 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2588 { 2589 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2590 struct mvpp2_port_pcpu, 2591 tx_done_timer); 2592 2593 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2594 2595 return HRTIMER_NORESTART; 2596 } 2597 2598 /* Main RX/TX processing routines */ 2599 2600 /* Display more error info */ 2601 static void mvpp2_rx_error(struct mvpp2_port *port, 2602 struct mvpp2_rx_desc *rx_desc) 2603 { 2604 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2605 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2606 char *err_str = NULL; 2607 2608 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2609 case MVPP2_RXD_ERR_CRC: 2610 err_str = "crc"; 2611 break; 2612 case MVPP2_RXD_ERR_OVERRUN: 2613 err_str = "overrun"; 2614 break; 2615 case MVPP2_RXD_ERR_RESOURCE: 2616 err_str = "resource"; 2617 break; 2618 } 2619 if (err_str && net_ratelimit()) 2620 netdev_err(port->dev, 2621 "bad rx status %08x (%s error), size=%zu\n", 2622 status, err_str, sz); 2623 } 2624 2625 /* Handle RX checksum offload */ 2626 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2627 struct sk_buff *skb) 2628 { 2629 if (((status & MVPP2_RXD_L3_IP4) && 2630 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2631 (status & MVPP2_RXD_L3_IP6)) 2632 if (((status & MVPP2_RXD_L4_UDP) || 2633 (status & MVPP2_RXD_L4_TCP)) && 2634 (status & MVPP2_RXD_L4_CSUM_OK)) { 2635 skb->csum = 0; 2636 skb->ip_summed = CHECKSUM_UNNECESSARY; 2637 return; 2638 } 2639 2640 skb->ip_summed = CHECKSUM_NONE; 2641 } 2642 2643 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2644 static int mvpp2_rx_refill(struct mvpp2_port *port, 2645 struct mvpp2_bm_pool *bm_pool, int pool) 2646 { 2647 dma_addr_t dma_addr; 2648 phys_addr_t phys_addr; 2649 void *buf; 2650 2651 /* No recycle or too many buffers are in use, so allocate a new skb */ 2652 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2653 GFP_ATOMIC); 2654 if (!buf) 2655 return -ENOMEM; 2656 2657 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2658 2659 return 0; 2660 } 2661 2662 /* Handle tx checksum */ 2663 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2664 { 2665 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2666 int ip_hdr_len = 0; 2667 u8 l4_proto; 2668 __be16 l3_proto = vlan_get_protocol(skb); 2669 2670 if (l3_proto == htons(ETH_P_IP)) { 2671 struct iphdr *ip4h = ip_hdr(skb); 2672 2673 /* Calculate IPv4 checksum and L4 checksum */ 2674 ip_hdr_len = ip4h->ihl; 2675 l4_proto = ip4h->protocol; 2676 } else if (l3_proto == htons(ETH_P_IPV6)) { 2677 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2678 2679 /* Read l4_protocol from one of IPv6 extra headers */ 2680 if (skb_network_header_len(skb) > 0) 2681 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2682 l4_proto = ip6h->nexthdr; 2683 } else { 2684 return MVPP2_TXD_L4_CSUM_NOT; 2685 } 2686 2687 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2688 l3_proto, ip_hdr_len, l4_proto); 2689 } 2690 2691 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2692 } 2693 2694 /* Main rx processing */ 2695 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2696 int rx_todo, struct mvpp2_rx_queue *rxq) 2697 { 2698 struct net_device *dev = port->dev; 2699 int rx_received; 2700 int rx_done = 0; 2701 u32 rcvd_pkts = 0; 2702 u32 rcvd_bytes = 0; 2703 2704 /* Get number of received packets and clamp the to-do */ 2705 rx_received = mvpp2_rxq_received(port, rxq->id); 2706 if (rx_todo > rx_received) 2707 rx_todo = rx_received; 2708 2709 while (rx_done < rx_todo) { 2710 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2711 struct mvpp2_bm_pool *bm_pool; 2712 struct sk_buff *skb; 2713 unsigned int frag_size; 2714 dma_addr_t dma_addr; 2715 phys_addr_t phys_addr; 2716 u32 rx_status; 2717 int pool, rx_bytes, err; 2718 void *data; 2719 2720 rx_done++; 2721 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2722 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2723 rx_bytes -= MVPP2_MH_SIZE; 2724 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2725 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2726 data = (void *)phys_to_virt(phys_addr); 2727 2728 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2729 MVPP2_RXD_BM_POOL_ID_OFFS; 2730 bm_pool = &port->priv->bm_pools[pool]; 2731 2732 /* In case of an error, release the requested buffer pointer 2733 * to the Buffer Manager. This request process is controlled 2734 * by the hardware, and the information about the buffer is 2735 * comprised by the RX descriptor. 2736 */ 2737 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2738 err_drop_frame: 2739 dev->stats.rx_errors++; 2740 mvpp2_rx_error(port, rx_desc); 2741 /* Return the buffer to the pool */ 2742 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2743 continue; 2744 } 2745 2746 if (bm_pool->frag_size > PAGE_SIZE) 2747 frag_size = 0; 2748 else 2749 frag_size = bm_pool->frag_size; 2750 2751 skb = build_skb(data, frag_size); 2752 if (!skb) { 2753 netdev_warn(port->dev, "skb build failed\n"); 2754 goto err_drop_frame; 2755 } 2756 2757 err = mvpp2_rx_refill(port, bm_pool, pool); 2758 if (err) { 2759 netdev_err(port->dev, "failed to refill BM pools\n"); 2760 goto err_drop_frame; 2761 } 2762 2763 dma_unmap_single(dev->dev.parent, dma_addr, 2764 bm_pool->buf_size, DMA_FROM_DEVICE); 2765 2766 rcvd_pkts++; 2767 rcvd_bytes += rx_bytes; 2768 2769 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2770 skb_put(skb, rx_bytes); 2771 skb->protocol = eth_type_trans(skb, dev); 2772 mvpp2_rx_csum(port, rx_status, skb); 2773 2774 napi_gro_receive(napi, skb); 2775 } 2776 2777 if (rcvd_pkts) { 2778 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2779 2780 u64_stats_update_begin(&stats->syncp); 2781 stats->rx_packets += rcvd_pkts; 2782 stats->rx_bytes += rcvd_bytes; 2783 u64_stats_update_end(&stats->syncp); 2784 } 2785 2786 /* Update Rx queue management counters */ 2787 wmb(); 2788 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2789 2790 return rx_todo; 2791 } 2792 2793 static inline void 2794 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2795 struct mvpp2_tx_desc *desc) 2796 { 2797 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2798 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2799 2800 dma_addr_t buf_dma_addr = 2801 mvpp2_txdesc_dma_addr_get(port, desc); 2802 size_t buf_sz = 2803 mvpp2_txdesc_size_get(port, desc); 2804 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2805 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2806 buf_sz, DMA_TO_DEVICE); 2807 mvpp2_txq_desc_put(txq); 2808 } 2809 2810 /* Handle tx fragmentation processing */ 2811 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2812 struct mvpp2_tx_queue *aggr_txq, 2813 struct mvpp2_tx_queue *txq) 2814 { 2815 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2816 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2817 struct mvpp2_tx_desc *tx_desc; 2818 int i; 2819 dma_addr_t buf_dma_addr; 2820 2821 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2822 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2823 void *addr = page_address(frag->page.p) + frag->page_offset; 2824 2825 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2826 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2827 mvpp2_txdesc_size_set(port, tx_desc, frag->size); 2828 2829 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2830 frag->size, DMA_TO_DEVICE); 2831 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2832 mvpp2_txq_desc_put(txq); 2833 goto cleanup; 2834 } 2835 2836 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2837 2838 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2839 /* Last descriptor */ 2840 mvpp2_txdesc_cmd_set(port, tx_desc, 2841 MVPP2_TXD_L_DESC); 2842 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2843 } else { 2844 /* Descriptor in the middle: Not First, Not Last */ 2845 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2846 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2847 } 2848 } 2849 2850 return 0; 2851 cleanup: 2852 /* Release all descriptors that were used to map fragments of 2853 * this packet, as well as the corresponding DMA mappings 2854 */ 2855 for (i = i - 1; i >= 0; i--) { 2856 tx_desc = txq->descs + i; 2857 tx_desc_unmap_put(port, txq, tx_desc); 2858 } 2859 2860 return -ENOMEM; 2861 } 2862 2863 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2864 struct net_device *dev, 2865 struct mvpp2_tx_queue *txq, 2866 struct mvpp2_tx_queue *aggr_txq, 2867 struct mvpp2_txq_pcpu *txq_pcpu, 2868 int hdr_sz) 2869 { 2870 struct mvpp2_port *port = netdev_priv(dev); 2871 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2872 dma_addr_t addr; 2873 2874 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2875 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2876 2877 addr = txq_pcpu->tso_headers_dma + 2878 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2879 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2880 2881 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2882 MVPP2_TXD_F_DESC | 2883 MVPP2_TXD_PADDING_DISABLE); 2884 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2885 } 2886 2887 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2888 struct net_device *dev, struct tso_t *tso, 2889 struct mvpp2_tx_queue *txq, 2890 struct mvpp2_tx_queue *aggr_txq, 2891 struct mvpp2_txq_pcpu *txq_pcpu, 2892 int sz, bool left, bool last) 2893 { 2894 struct mvpp2_port *port = netdev_priv(dev); 2895 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2896 dma_addr_t buf_dma_addr; 2897 2898 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2899 mvpp2_txdesc_size_set(port, tx_desc, sz); 2900 2901 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2902 DMA_TO_DEVICE); 2903 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2904 mvpp2_txq_desc_put(txq); 2905 return -ENOMEM; 2906 } 2907 2908 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2909 2910 if (!left) { 2911 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 2912 if (last) { 2913 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2914 return 0; 2915 } 2916 } else { 2917 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2918 } 2919 2920 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2921 return 0; 2922 } 2923 2924 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 2925 struct mvpp2_tx_queue *txq, 2926 struct mvpp2_tx_queue *aggr_txq, 2927 struct mvpp2_txq_pcpu *txq_pcpu) 2928 { 2929 struct mvpp2_port *port = netdev_priv(dev); 2930 struct tso_t tso; 2931 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 2932 int i, len, descs = 0; 2933 2934 /* Check number of available descriptors */ 2935 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 2936 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 2937 tso_count_descs(skb))) 2938 return 0; 2939 2940 tso_start(skb, &tso); 2941 len = skb->len - hdr_sz; 2942 while (len > 0) { 2943 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 2944 char *hdr = txq_pcpu->tso_headers + 2945 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2946 2947 len -= left; 2948 descs++; 2949 2950 tso_build_hdr(skb, hdr, &tso, left, len == 0); 2951 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 2952 2953 while (left > 0) { 2954 int sz = min_t(int, tso.size, left); 2955 left -= sz; 2956 descs++; 2957 2958 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 2959 txq_pcpu, sz, left, len == 0)) 2960 goto release; 2961 tso_build_data(skb, &tso, sz); 2962 } 2963 } 2964 2965 return descs; 2966 2967 release: 2968 for (i = descs - 1; i >= 0; i--) { 2969 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 2970 tx_desc_unmap_put(port, txq, tx_desc); 2971 } 2972 return 0; 2973 } 2974 2975 /* Main tx processing */ 2976 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 2977 { 2978 struct mvpp2_port *port = netdev_priv(dev); 2979 struct mvpp2_tx_queue *txq, *aggr_txq; 2980 struct mvpp2_txq_pcpu *txq_pcpu; 2981 struct mvpp2_tx_desc *tx_desc; 2982 dma_addr_t buf_dma_addr; 2983 unsigned long flags = 0; 2984 unsigned int thread; 2985 int frags = 0; 2986 u16 txq_id; 2987 u32 tx_cmd; 2988 2989 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2990 2991 txq_id = skb_get_queue_mapping(skb); 2992 txq = port->txqs[txq_id]; 2993 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2994 aggr_txq = &port->priv->aggr_txqs[thread]; 2995 2996 if (test_bit(thread, &port->priv->lock_map)) 2997 spin_lock_irqsave(&port->tx_lock[thread], flags); 2998 2999 if (skb_is_gso(skb)) { 3000 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 3001 goto out; 3002 } 3003 frags = skb_shinfo(skb)->nr_frags + 1; 3004 3005 /* Check number of available descriptors */ 3006 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 3007 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 3008 frags = 0; 3009 goto out; 3010 } 3011 3012 /* Get a descriptor for the first part of the packet */ 3013 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3014 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3015 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 3016 3017 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 3018 skb_headlen(skb), DMA_TO_DEVICE); 3019 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3020 mvpp2_txq_desc_put(txq); 3021 frags = 0; 3022 goto out; 3023 } 3024 3025 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3026 3027 tx_cmd = mvpp2_skb_tx_csum(port, skb); 3028 3029 if (frags == 1) { 3030 /* First and Last descriptor */ 3031 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3032 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3033 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3034 } else { 3035 /* First but not Last */ 3036 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 3037 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3038 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3039 3040 /* Continue with other skb fragments */ 3041 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 3042 tx_desc_unmap_put(port, txq, tx_desc); 3043 frags = 0; 3044 } 3045 } 3046 3047 out: 3048 if (frags > 0) { 3049 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 3050 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 3051 3052 txq_pcpu->reserved_num -= frags; 3053 txq_pcpu->count += frags; 3054 aggr_txq->count += frags; 3055 3056 /* Enable transmit */ 3057 wmb(); 3058 mvpp2_aggr_txq_pend_desc_add(port, frags); 3059 3060 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3061 netif_tx_stop_queue(nq); 3062 3063 u64_stats_update_begin(&stats->syncp); 3064 stats->tx_packets++; 3065 stats->tx_bytes += skb->len; 3066 u64_stats_update_end(&stats->syncp); 3067 } else { 3068 dev->stats.tx_dropped++; 3069 dev_kfree_skb_any(skb); 3070 } 3071 3072 /* Finalize TX processing */ 3073 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3074 mvpp2_txq_done(port, txq, txq_pcpu); 3075 3076 /* Set the timer in case not all frags were processed */ 3077 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3078 txq_pcpu->count > 0) { 3079 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 3080 3081 mvpp2_timer_set(port_pcpu); 3082 } 3083 3084 if (test_bit(thread, &port->priv->lock_map)) 3085 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 3086 3087 return NETDEV_TX_OK; 3088 } 3089 3090 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3091 { 3092 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3093 netdev_err(dev, "FCS error\n"); 3094 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3095 netdev_err(dev, "rx fifo overrun error\n"); 3096 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3097 netdev_err(dev, "tx fifo underrun error\n"); 3098 } 3099 3100 static int mvpp2_poll(struct napi_struct *napi, int budget) 3101 { 3102 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3103 int rx_done = 0; 3104 struct mvpp2_port *port = netdev_priv(napi->dev); 3105 struct mvpp2_queue_vector *qv; 3106 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3107 3108 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3109 3110 /* Rx/Tx cause register 3111 * 3112 * Bits 0-15: each bit indicates received packets on the Rx queue 3113 * (bit 0 is for Rx queue 0). 3114 * 3115 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3116 * (bit 16 is for Tx queue 0). 3117 * 3118 * Each CPU has its own Rx/Tx cause register 3119 */ 3120 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 3121 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3122 3123 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3124 if (cause_misc) { 3125 mvpp2_cause_error(port->dev, cause_misc); 3126 3127 /* Clear the cause register */ 3128 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3129 mvpp2_thread_write(port->priv, thread, 3130 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3131 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3132 } 3133 3134 if (port->has_tx_irqs) { 3135 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3136 if (cause_tx) { 3137 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3138 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3139 } 3140 } 3141 3142 /* Process RX packets */ 3143 cause_rx = cause_rx_tx & 3144 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 3145 cause_rx <<= qv->first_rxq; 3146 cause_rx |= qv->pending_cause_rx; 3147 while (cause_rx && budget > 0) { 3148 int count; 3149 struct mvpp2_rx_queue *rxq; 3150 3151 rxq = mvpp2_get_rx_queue(port, cause_rx); 3152 if (!rxq) 3153 break; 3154 3155 count = mvpp2_rx(port, napi, budget, rxq); 3156 rx_done += count; 3157 budget -= count; 3158 if (budget > 0) { 3159 /* Clear the bit associated to this Rx queue 3160 * so that next iteration will continue from 3161 * the next Rx queue. 3162 */ 3163 cause_rx &= ~(1 << rxq->logic_rxq); 3164 } 3165 } 3166 3167 if (budget > 0) { 3168 cause_rx = 0; 3169 napi_complete_done(napi, rx_done); 3170 3171 mvpp2_qvec_interrupt_enable(qv); 3172 } 3173 qv->pending_cause_rx = cause_rx; 3174 return rx_done; 3175 } 3176 3177 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3178 { 3179 u32 ctrl3; 3180 3181 /* Set the GMAC & XLG MAC in reset */ 3182 mvpp2_mac_reset_assert(port); 3183 3184 /* Set the MPCS and XPCS in reset */ 3185 mvpp22_pcs_reset_assert(port); 3186 3187 /* comphy reconfiguration */ 3188 mvpp22_comphy_init(port); 3189 3190 /* gop reconfiguration */ 3191 mvpp22_gop_init(port); 3192 3193 mvpp22_pcs_reset_deassert(port); 3194 3195 /* Only GOP port 0 has an XLG MAC */ 3196 if (port->gop_id == 0) { 3197 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3198 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3199 3200 if (mvpp2_is_xlg(port->phy_interface)) 3201 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3202 else 3203 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3204 3205 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3206 } 3207 3208 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) 3209 mvpp2_xlg_max_rx_size_set(port); 3210 else 3211 mvpp2_gmac_max_rx_size_set(port); 3212 } 3213 3214 /* Set hw internals when starting port */ 3215 static void mvpp2_start_dev(struct mvpp2_port *port) 3216 { 3217 int i; 3218 3219 mvpp2_txp_max_tx_size_set(port); 3220 3221 for (i = 0; i < port->nqvecs; i++) 3222 napi_enable(&port->qvecs[i].napi); 3223 3224 /* Enable interrupts on all threads */ 3225 mvpp2_interrupts_enable(port); 3226 3227 if (port->priv->hw_version == MVPP22) 3228 mvpp22_mode_reconfigure(port); 3229 3230 if (port->phylink) { 3231 phylink_start(port->phylink); 3232 } else { 3233 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3234 * configured manually when the interface is started. This will 3235 * be removed as soon as the phylink ACPI support lands in. 3236 */ 3237 struct phylink_link_state state = { 3238 .interface = port->phy_interface, 3239 }; 3240 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 3241 mvpp2_mac_link_up(&port->phylink_config, MLO_AN_INBAND, 3242 port->phy_interface, NULL); 3243 } 3244 3245 netif_tx_start_all_queues(port->dev); 3246 } 3247 3248 /* Set hw internals when stopping port */ 3249 static void mvpp2_stop_dev(struct mvpp2_port *port) 3250 { 3251 int i; 3252 3253 /* Disable interrupts on all threads */ 3254 mvpp2_interrupts_disable(port); 3255 3256 for (i = 0; i < port->nqvecs; i++) 3257 napi_disable(&port->qvecs[i].napi); 3258 3259 if (port->phylink) 3260 phylink_stop(port->phylink); 3261 phy_power_off(port->comphy); 3262 } 3263 3264 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3265 struct ethtool_ringparam *ring) 3266 { 3267 u16 new_rx_pending = ring->rx_pending; 3268 u16 new_tx_pending = ring->tx_pending; 3269 3270 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3271 return -EINVAL; 3272 3273 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3274 new_rx_pending = MVPP2_MAX_RXD_MAX; 3275 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3276 new_rx_pending = ALIGN(ring->rx_pending, 16); 3277 3278 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3279 new_tx_pending = MVPP2_MAX_TXD_MAX; 3280 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3281 new_tx_pending = ALIGN(ring->tx_pending, 32); 3282 3283 /* The Tx ring size cannot be smaller than the minimum number of 3284 * descriptors needed for TSO. 3285 */ 3286 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3287 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3288 3289 if (ring->rx_pending != new_rx_pending) { 3290 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3291 ring->rx_pending, new_rx_pending); 3292 ring->rx_pending = new_rx_pending; 3293 } 3294 3295 if (ring->tx_pending != new_tx_pending) { 3296 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3297 ring->tx_pending, new_tx_pending); 3298 ring->tx_pending = new_tx_pending; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3305 { 3306 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3307 3308 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3309 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3310 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3311 addr[0] = (mac_addr_h >> 24) & 0xFF; 3312 addr[1] = (mac_addr_h >> 16) & 0xFF; 3313 addr[2] = (mac_addr_h >> 8) & 0xFF; 3314 addr[3] = mac_addr_h & 0xFF; 3315 addr[4] = mac_addr_m & 0xFF; 3316 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3317 } 3318 3319 static int mvpp2_irqs_init(struct mvpp2_port *port) 3320 { 3321 int err, i; 3322 3323 for (i = 0; i < port->nqvecs; i++) { 3324 struct mvpp2_queue_vector *qv = port->qvecs + i; 3325 3326 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3327 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 3328 if (!qv->mask) { 3329 err = -ENOMEM; 3330 goto err; 3331 } 3332 3333 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3334 } 3335 3336 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3337 if (err) 3338 goto err; 3339 3340 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3341 unsigned int cpu; 3342 3343 for_each_present_cpu(cpu) { 3344 if (mvpp2_cpu_to_thread(port->priv, cpu) == 3345 qv->sw_thread_id) 3346 cpumask_set_cpu(cpu, qv->mask); 3347 } 3348 3349 irq_set_affinity_hint(qv->irq, qv->mask); 3350 } 3351 } 3352 3353 return 0; 3354 err: 3355 for (i = 0; i < port->nqvecs; i++) { 3356 struct mvpp2_queue_vector *qv = port->qvecs + i; 3357 3358 irq_set_affinity_hint(qv->irq, NULL); 3359 kfree(qv->mask); 3360 qv->mask = NULL; 3361 free_irq(qv->irq, qv); 3362 } 3363 3364 return err; 3365 } 3366 3367 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3368 { 3369 int i; 3370 3371 for (i = 0; i < port->nqvecs; i++) { 3372 struct mvpp2_queue_vector *qv = port->qvecs + i; 3373 3374 irq_set_affinity_hint(qv->irq, NULL); 3375 kfree(qv->mask); 3376 qv->mask = NULL; 3377 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3378 free_irq(qv->irq, qv); 3379 } 3380 } 3381 3382 static bool mvpp22_rss_is_supported(void) 3383 { 3384 return queue_mode == MVPP2_QDIST_MULTI_MODE; 3385 } 3386 3387 static int mvpp2_open(struct net_device *dev) 3388 { 3389 struct mvpp2_port *port = netdev_priv(dev); 3390 struct mvpp2 *priv = port->priv; 3391 unsigned char mac_bcast[ETH_ALEN] = { 3392 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3393 bool valid = false; 3394 int err; 3395 3396 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3397 if (err) { 3398 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3399 return err; 3400 } 3401 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3402 if (err) { 3403 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3404 return err; 3405 } 3406 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3407 if (err) { 3408 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3409 return err; 3410 } 3411 err = mvpp2_prs_def_flow(port); 3412 if (err) { 3413 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3414 return err; 3415 } 3416 3417 /* Allocate the Rx/Tx queues */ 3418 err = mvpp2_setup_rxqs(port); 3419 if (err) { 3420 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3421 return err; 3422 } 3423 3424 err = mvpp2_setup_txqs(port); 3425 if (err) { 3426 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3427 goto err_cleanup_rxqs; 3428 } 3429 3430 err = mvpp2_irqs_init(port); 3431 if (err) { 3432 netdev_err(port->dev, "cannot init IRQs\n"); 3433 goto err_cleanup_txqs; 3434 } 3435 3436 /* Phylink isn't supported yet in ACPI mode */ 3437 if (port->of_node) { 3438 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3439 if (err) { 3440 netdev_err(port->dev, "could not attach PHY (%d)\n", 3441 err); 3442 goto err_free_irq; 3443 } 3444 3445 valid = true; 3446 } 3447 3448 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3449 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3450 dev->name, port); 3451 if (err) { 3452 netdev_err(port->dev, "cannot request link IRQ %d\n", 3453 port->link_irq); 3454 goto err_free_irq; 3455 } 3456 3457 mvpp22_gop_setup_irq(port); 3458 3459 /* In default link is down */ 3460 netif_carrier_off(port->dev); 3461 3462 valid = true; 3463 } else { 3464 port->link_irq = 0; 3465 } 3466 3467 if (!valid) { 3468 netdev_err(port->dev, 3469 "invalid configuration: no dt or link IRQ"); 3470 goto err_free_irq; 3471 } 3472 3473 /* Unmask interrupts on all CPUs */ 3474 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3475 mvpp2_shared_interrupt_mask_unmask(port, false); 3476 3477 mvpp2_start_dev(port); 3478 3479 /* Start hardware statistics gathering */ 3480 queue_delayed_work(priv->stats_queue, &port->stats_work, 3481 MVPP2_MIB_COUNTERS_STATS_DELAY); 3482 3483 return 0; 3484 3485 err_free_irq: 3486 mvpp2_irqs_deinit(port); 3487 err_cleanup_txqs: 3488 mvpp2_cleanup_txqs(port); 3489 err_cleanup_rxqs: 3490 mvpp2_cleanup_rxqs(port); 3491 return err; 3492 } 3493 3494 static int mvpp2_stop(struct net_device *dev) 3495 { 3496 struct mvpp2_port *port = netdev_priv(dev); 3497 struct mvpp2_port_pcpu *port_pcpu; 3498 unsigned int thread; 3499 3500 mvpp2_stop_dev(port); 3501 3502 /* Mask interrupts on all threads */ 3503 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3504 mvpp2_shared_interrupt_mask_unmask(port, true); 3505 3506 if (port->phylink) 3507 phylink_disconnect_phy(port->phylink); 3508 if (port->link_irq) 3509 free_irq(port->link_irq, port); 3510 3511 mvpp2_irqs_deinit(port); 3512 if (!port->has_tx_irqs) { 3513 for (thread = 0; thread < port->priv->nthreads; thread++) { 3514 port_pcpu = per_cpu_ptr(port->pcpu, thread); 3515 3516 hrtimer_cancel(&port_pcpu->tx_done_timer); 3517 port_pcpu->timer_scheduled = false; 3518 tasklet_kill(&port_pcpu->tx_done_tasklet); 3519 } 3520 } 3521 mvpp2_cleanup_rxqs(port); 3522 mvpp2_cleanup_txqs(port); 3523 3524 cancel_delayed_work_sync(&port->stats_work); 3525 3526 mvpp2_mac_reset_assert(port); 3527 mvpp22_pcs_reset_assert(port); 3528 3529 return 0; 3530 } 3531 3532 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3533 struct netdev_hw_addr_list *list) 3534 { 3535 struct netdev_hw_addr *ha; 3536 int ret; 3537 3538 netdev_hw_addr_list_for_each(ha, list) { 3539 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3540 if (ret) 3541 return ret; 3542 } 3543 3544 return 0; 3545 } 3546 3547 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3548 { 3549 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3550 mvpp2_prs_vid_enable_filtering(port); 3551 else 3552 mvpp2_prs_vid_disable_filtering(port); 3553 3554 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3555 MVPP2_PRS_L2_UNI_CAST, enable); 3556 3557 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3558 MVPP2_PRS_L2_MULTI_CAST, enable); 3559 } 3560 3561 static void mvpp2_set_rx_mode(struct net_device *dev) 3562 { 3563 struct mvpp2_port *port = netdev_priv(dev); 3564 3565 /* Clear the whole UC and MC list */ 3566 mvpp2_prs_mac_del_all(port); 3567 3568 if (dev->flags & IFF_PROMISC) { 3569 mvpp2_set_rx_promisc(port, true); 3570 return; 3571 } 3572 3573 mvpp2_set_rx_promisc(port, false); 3574 3575 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3576 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3577 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3578 MVPP2_PRS_L2_UNI_CAST, true); 3579 3580 if (dev->flags & IFF_ALLMULTI) { 3581 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3582 MVPP2_PRS_L2_MULTI_CAST, true); 3583 return; 3584 } 3585 3586 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3587 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3588 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3589 MVPP2_PRS_L2_MULTI_CAST, true); 3590 } 3591 3592 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3593 { 3594 const struct sockaddr *addr = p; 3595 int err; 3596 3597 if (!is_valid_ether_addr(addr->sa_data)) 3598 return -EADDRNOTAVAIL; 3599 3600 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3601 if (err) { 3602 /* Reconfigure parser accept the original MAC address */ 3603 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3604 netdev_err(dev, "failed to change MAC address\n"); 3605 } 3606 return err; 3607 } 3608 3609 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3610 { 3611 struct mvpp2_port *port = netdev_priv(dev); 3612 int err; 3613 3614 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3615 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3616 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3617 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3618 } 3619 3620 if (!netif_running(dev)) { 3621 err = mvpp2_bm_update_mtu(dev, mtu); 3622 if (!err) { 3623 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3624 return 0; 3625 } 3626 3627 /* Reconfigure BM to the original MTU */ 3628 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3629 if (err) 3630 goto log_error; 3631 } 3632 3633 mvpp2_stop_dev(port); 3634 3635 err = mvpp2_bm_update_mtu(dev, mtu); 3636 if (!err) { 3637 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3638 goto out_start; 3639 } 3640 3641 /* Reconfigure BM to the original MTU */ 3642 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3643 if (err) 3644 goto log_error; 3645 3646 out_start: 3647 mvpp2_start_dev(port); 3648 mvpp2_egress_enable(port); 3649 mvpp2_ingress_enable(port); 3650 3651 return 0; 3652 log_error: 3653 netdev_err(dev, "failed to change MTU\n"); 3654 return err; 3655 } 3656 3657 static void 3658 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3659 { 3660 struct mvpp2_port *port = netdev_priv(dev); 3661 unsigned int start; 3662 unsigned int cpu; 3663 3664 for_each_possible_cpu(cpu) { 3665 struct mvpp2_pcpu_stats *cpu_stats; 3666 u64 rx_packets; 3667 u64 rx_bytes; 3668 u64 tx_packets; 3669 u64 tx_bytes; 3670 3671 cpu_stats = per_cpu_ptr(port->stats, cpu); 3672 do { 3673 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3674 rx_packets = cpu_stats->rx_packets; 3675 rx_bytes = cpu_stats->rx_bytes; 3676 tx_packets = cpu_stats->tx_packets; 3677 tx_bytes = cpu_stats->tx_bytes; 3678 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3679 3680 stats->rx_packets += rx_packets; 3681 stats->rx_bytes += rx_bytes; 3682 stats->tx_packets += tx_packets; 3683 stats->tx_bytes += tx_bytes; 3684 } 3685 3686 stats->rx_errors = dev->stats.rx_errors; 3687 stats->rx_dropped = dev->stats.rx_dropped; 3688 stats->tx_dropped = dev->stats.tx_dropped; 3689 } 3690 3691 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3692 { 3693 struct mvpp2_port *port = netdev_priv(dev); 3694 3695 if (!port->phylink) 3696 return -ENOTSUPP; 3697 3698 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3699 } 3700 3701 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3702 { 3703 struct mvpp2_port *port = netdev_priv(dev); 3704 int ret; 3705 3706 ret = mvpp2_prs_vid_entry_add(port, vid); 3707 if (ret) 3708 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3709 MVPP2_PRS_VLAN_FILT_MAX - 1); 3710 return ret; 3711 } 3712 3713 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3714 { 3715 struct mvpp2_port *port = netdev_priv(dev); 3716 3717 mvpp2_prs_vid_entry_remove(port, vid); 3718 return 0; 3719 } 3720 3721 static int mvpp2_set_features(struct net_device *dev, 3722 netdev_features_t features) 3723 { 3724 netdev_features_t changed = dev->features ^ features; 3725 struct mvpp2_port *port = netdev_priv(dev); 3726 3727 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3728 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3729 mvpp2_prs_vid_enable_filtering(port); 3730 } else { 3731 /* Invalidate all registered VID filters for this 3732 * port 3733 */ 3734 mvpp2_prs_vid_remove_all(port); 3735 3736 mvpp2_prs_vid_disable_filtering(port); 3737 } 3738 } 3739 3740 if (changed & NETIF_F_RXHASH) { 3741 if (features & NETIF_F_RXHASH) 3742 mvpp22_port_rss_enable(port); 3743 else 3744 mvpp22_port_rss_disable(port); 3745 } 3746 3747 return 0; 3748 } 3749 3750 /* Ethtool methods */ 3751 3752 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3753 { 3754 struct mvpp2_port *port = netdev_priv(dev); 3755 3756 if (!port->phylink) 3757 return -ENOTSUPP; 3758 3759 return phylink_ethtool_nway_reset(port->phylink); 3760 } 3761 3762 /* Set interrupt coalescing for ethtools */ 3763 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3764 struct ethtool_coalesce *c) 3765 { 3766 struct mvpp2_port *port = netdev_priv(dev); 3767 int queue; 3768 3769 for (queue = 0; queue < port->nrxqs; queue++) { 3770 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3771 3772 rxq->time_coal = c->rx_coalesce_usecs; 3773 rxq->pkts_coal = c->rx_max_coalesced_frames; 3774 mvpp2_rx_pkts_coal_set(port, rxq); 3775 mvpp2_rx_time_coal_set(port, rxq); 3776 } 3777 3778 if (port->has_tx_irqs) { 3779 port->tx_time_coal = c->tx_coalesce_usecs; 3780 mvpp2_tx_time_coal_set(port); 3781 } 3782 3783 for (queue = 0; queue < port->ntxqs; queue++) { 3784 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3785 3786 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3787 3788 if (port->has_tx_irqs) 3789 mvpp2_tx_pkts_coal_set(port, txq); 3790 } 3791 3792 return 0; 3793 } 3794 3795 /* get coalescing for ethtools */ 3796 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3797 struct ethtool_coalesce *c) 3798 { 3799 struct mvpp2_port *port = netdev_priv(dev); 3800 3801 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3802 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3803 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3804 c->tx_coalesce_usecs = port->tx_time_coal; 3805 return 0; 3806 } 3807 3808 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3809 struct ethtool_drvinfo *drvinfo) 3810 { 3811 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3812 sizeof(drvinfo->driver)); 3813 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3814 sizeof(drvinfo->version)); 3815 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3816 sizeof(drvinfo->bus_info)); 3817 } 3818 3819 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3820 struct ethtool_ringparam *ring) 3821 { 3822 struct mvpp2_port *port = netdev_priv(dev); 3823 3824 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3825 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3826 ring->rx_pending = port->rx_ring_size; 3827 ring->tx_pending = port->tx_ring_size; 3828 } 3829 3830 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3831 struct ethtool_ringparam *ring) 3832 { 3833 struct mvpp2_port *port = netdev_priv(dev); 3834 u16 prev_rx_ring_size = port->rx_ring_size; 3835 u16 prev_tx_ring_size = port->tx_ring_size; 3836 int err; 3837 3838 err = mvpp2_check_ringparam_valid(dev, ring); 3839 if (err) 3840 return err; 3841 3842 if (!netif_running(dev)) { 3843 port->rx_ring_size = ring->rx_pending; 3844 port->tx_ring_size = ring->tx_pending; 3845 return 0; 3846 } 3847 3848 /* The interface is running, so we have to force a 3849 * reallocation of the queues 3850 */ 3851 mvpp2_stop_dev(port); 3852 mvpp2_cleanup_rxqs(port); 3853 mvpp2_cleanup_txqs(port); 3854 3855 port->rx_ring_size = ring->rx_pending; 3856 port->tx_ring_size = ring->tx_pending; 3857 3858 err = mvpp2_setup_rxqs(port); 3859 if (err) { 3860 /* Reallocate Rx queues with the original ring size */ 3861 port->rx_ring_size = prev_rx_ring_size; 3862 ring->rx_pending = prev_rx_ring_size; 3863 err = mvpp2_setup_rxqs(port); 3864 if (err) 3865 goto err_out; 3866 } 3867 err = mvpp2_setup_txqs(port); 3868 if (err) { 3869 /* Reallocate Tx queues with the original ring size */ 3870 port->tx_ring_size = prev_tx_ring_size; 3871 ring->tx_pending = prev_tx_ring_size; 3872 err = mvpp2_setup_txqs(port); 3873 if (err) 3874 goto err_clean_rxqs; 3875 } 3876 3877 mvpp2_start_dev(port); 3878 mvpp2_egress_enable(port); 3879 mvpp2_ingress_enable(port); 3880 3881 return 0; 3882 3883 err_clean_rxqs: 3884 mvpp2_cleanup_rxqs(port); 3885 err_out: 3886 netdev_err(dev, "failed to change ring parameters"); 3887 return err; 3888 } 3889 3890 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3891 struct ethtool_pauseparam *pause) 3892 { 3893 struct mvpp2_port *port = netdev_priv(dev); 3894 3895 if (!port->phylink) 3896 return; 3897 3898 phylink_ethtool_get_pauseparam(port->phylink, pause); 3899 } 3900 3901 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3902 struct ethtool_pauseparam *pause) 3903 { 3904 struct mvpp2_port *port = netdev_priv(dev); 3905 3906 if (!port->phylink) 3907 return -ENOTSUPP; 3908 3909 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3910 } 3911 3912 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 3913 struct ethtool_link_ksettings *cmd) 3914 { 3915 struct mvpp2_port *port = netdev_priv(dev); 3916 3917 if (!port->phylink) 3918 return -ENOTSUPP; 3919 3920 return phylink_ethtool_ksettings_get(port->phylink, cmd); 3921 } 3922 3923 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 3924 const struct ethtool_link_ksettings *cmd) 3925 { 3926 struct mvpp2_port *port = netdev_priv(dev); 3927 3928 if (!port->phylink) 3929 return -ENOTSUPP; 3930 3931 return phylink_ethtool_ksettings_set(port->phylink, cmd); 3932 } 3933 3934 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 3935 struct ethtool_rxnfc *info, u32 *rules) 3936 { 3937 struct mvpp2_port *port = netdev_priv(dev); 3938 int ret = 0, i, loc = 0; 3939 3940 if (!mvpp22_rss_is_supported()) 3941 return -EOPNOTSUPP; 3942 3943 switch (info->cmd) { 3944 case ETHTOOL_GRXFH: 3945 ret = mvpp2_ethtool_rxfh_get(port, info); 3946 break; 3947 case ETHTOOL_GRXRINGS: 3948 info->data = port->nrxqs; 3949 break; 3950 case ETHTOOL_GRXCLSRLCNT: 3951 info->rule_cnt = port->n_rfs_rules; 3952 break; 3953 case ETHTOOL_GRXCLSRULE: 3954 ret = mvpp2_ethtool_cls_rule_get(port, info); 3955 break; 3956 case ETHTOOL_GRXCLSRLALL: 3957 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 3958 if (port->rfs_rules[i]) 3959 rules[loc++] = i; 3960 } 3961 break; 3962 default: 3963 return -ENOTSUPP; 3964 } 3965 3966 return ret; 3967 } 3968 3969 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 3970 struct ethtool_rxnfc *info) 3971 { 3972 struct mvpp2_port *port = netdev_priv(dev); 3973 int ret = 0; 3974 3975 if (!mvpp22_rss_is_supported()) 3976 return -EOPNOTSUPP; 3977 3978 switch (info->cmd) { 3979 case ETHTOOL_SRXFH: 3980 ret = mvpp2_ethtool_rxfh_set(port, info); 3981 break; 3982 case ETHTOOL_SRXCLSRLINS: 3983 ret = mvpp2_ethtool_cls_rule_ins(port, info); 3984 break; 3985 case ETHTOOL_SRXCLSRLDEL: 3986 ret = mvpp2_ethtool_cls_rule_del(port, info); 3987 break; 3988 default: 3989 return -EOPNOTSUPP; 3990 } 3991 return ret; 3992 } 3993 3994 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 3995 { 3996 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 3997 } 3998 3999 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 4000 u8 *hfunc) 4001 { 4002 struct mvpp2_port *port = netdev_priv(dev); 4003 int ret = 0; 4004 4005 if (!mvpp22_rss_is_supported()) 4006 return -EOPNOTSUPP; 4007 4008 if (indir) 4009 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 4010 4011 if (hfunc) 4012 *hfunc = ETH_RSS_HASH_CRC32; 4013 4014 return ret; 4015 } 4016 4017 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 4018 const u8 *key, const u8 hfunc) 4019 { 4020 struct mvpp2_port *port = netdev_priv(dev); 4021 int ret = 0; 4022 4023 if (!mvpp22_rss_is_supported()) 4024 return -EOPNOTSUPP; 4025 4026 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4027 return -EOPNOTSUPP; 4028 4029 if (key) 4030 return -EOPNOTSUPP; 4031 4032 if (indir) 4033 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 4034 4035 return ret; 4036 } 4037 4038 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 4039 u8 *key, u8 *hfunc, u32 rss_context) 4040 { 4041 struct mvpp2_port *port = netdev_priv(dev); 4042 int ret = 0; 4043 4044 if (!mvpp22_rss_is_supported()) 4045 return -EOPNOTSUPP; 4046 4047 if (hfunc) 4048 *hfunc = ETH_RSS_HASH_CRC32; 4049 4050 if (indir) 4051 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 4052 4053 return ret; 4054 } 4055 4056 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 4057 const u32 *indir, const u8 *key, 4058 const u8 hfunc, u32 *rss_context, 4059 bool delete) 4060 { 4061 struct mvpp2_port *port = netdev_priv(dev); 4062 int ret; 4063 4064 if (!mvpp22_rss_is_supported()) 4065 return -EOPNOTSUPP; 4066 4067 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4068 return -EOPNOTSUPP; 4069 4070 if (key) 4071 return -EOPNOTSUPP; 4072 4073 if (delete) 4074 return mvpp22_port_rss_ctx_delete(port, *rss_context); 4075 4076 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 4077 ret = mvpp22_port_rss_ctx_create(port, rss_context); 4078 if (ret) 4079 return ret; 4080 } 4081 4082 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 4083 } 4084 /* Device ops */ 4085 4086 static const struct net_device_ops mvpp2_netdev_ops = { 4087 .ndo_open = mvpp2_open, 4088 .ndo_stop = mvpp2_stop, 4089 .ndo_start_xmit = mvpp2_tx, 4090 .ndo_set_rx_mode = mvpp2_set_rx_mode, 4091 .ndo_set_mac_address = mvpp2_set_mac_address, 4092 .ndo_change_mtu = mvpp2_change_mtu, 4093 .ndo_get_stats64 = mvpp2_get_stats64, 4094 .ndo_do_ioctl = mvpp2_ioctl, 4095 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 4096 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 4097 .ndo_set_features = mvpp2_set_features, 4098 }; 4099 4100 static const struct ethtool_ops mvpp2_eth_tool_ops = { 4101 .nway_reset = mvpp2_ethtool_nway_reset, 4102 .get_link = ethtool_op_get_link, 4103 .set_coalesce = mvpp2_ethtool_set_coalesce, 4104 .get_coalesce = mvpp2_ethtool_get_coalesce, 4105 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 4106 .get_ringparam = mvpp2_ethtool_get_ringparam, 4107 .set_ringparam = mvpp2_ethtool_set_ringparam, 4108 .get_strings = mvpp2_ethtool_get_strings, 4109 .get_ethtool_stats = mvpp2_ethtool_get_stats, 4110 .get_sset_count = mvpp2_ethtool_get_sset_count, 4111 .get_pauseparam = mvpp2_ethtool_get_pause_param, 4112 .set_pauseparam = mvpp2_ethtool_set_pause_param, 4113 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 4114 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 4115 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 4116 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 4117 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 4118 .get_rxfh = mvpp2_ethtool_get_rxfh, 4119 .set_rxfh = mvpp2_ethtool_set_rxfh, 4120 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 4121 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 4122 }; 4123 4124 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 4125 * had a single IRQ defined per-port. 4126 */ 4127 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 4128 struct device_node *port_node) 4129 { 4130 struct mvpp2_queue_vector *v = &port->qvecs[0]; 4131 4132 v->first_rxq = 0; 4133 v->nrxqs = port->nrxqs; 4134 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4135 v->sw_thread_id = 0; 4136 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 4137 v->port = port; 4138 v->irq = irq_of_parse_and_map(port_node, 0); 4139 if (v->irq <= 0) 4140 return -EINVAL; 4141 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4142 NAPI_POLL_WEIGHT); 4143 4144 port->nqvecs = 1; 4145 4146 return 0; 4147 } 4148 4149 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 4150 struct device_node *port_node) 4151 { 4152 struct mvpp2 *priv = port->priv; 4153 struct mvpp2_queue_vector *v; 4154 int i, ret; 4155 4156 switch (queue_mode) { 4157 case MVPP2_QDIST_SINGLE_MODE: 4158 port->nqvecs = priv->nthreads + 1; 4159 break; 4160 case MVPP2_QDIST_MULTI_MODE: 4161 port->nqvecs = priv->nthreads; 4162 break; 4163 } 4164 4165 for (i = 0; i < port->nqvecs; i++) { 4166 char irqname[16]; 4167 4168 v = port->qvecs + i; 4169 4170 v->port = port; 4171 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 4172 v->sw_thread_id = i; 4173 v->sw_thread_mask = BIT(i); 4174 4175 if (port->flags & MVPP2_F_DT_COMPAT) 4176 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 4177 else 4178 snprintf(irqname, sizeof(irqname), "hif%d", i); 4179 4180 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 4181 v->first_rxq = i; 4182 v->nrxqs = 1; 4183 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 4184 i == (port->nqvecs - 1)) { 4185 v->first_rxq = 0; 4186 v->nrxqs = port->nrxqs; 4187 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4188 4189 if (port->flags & MVPP2_F_DT_COMPAT) 4190 strncpy(irqname, "rx-shared", sizeof(irqname)); 4191 } 4192 4193 if (port_node) 4194 v->irq = of_irq_get_byname(port_node, irqname); 4195 else 4196 v->irq = fwnode_irq_get(port->fwnode, i); 4197 if (v->irq <= 0) { 4198 ret = -EINVAL; 4199 goto err; 4200 } 4201 4202 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4203 NAPI_POLL_WEIGHT); 4204 } 4205 4206 return 0; 4207 4208 err: 4209 for (i = 0; i < port->nqvecs; i++) 4210 irq_dispose_mapping(port->qvecs[i].irq); 4211 return ret; 4212 } 4213 4214 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 4215 struct device_node *port_node) 4216 { 4217 if (port->has_tx_irqs) 4218 return mvpp2_multi_queue_vectors_init(port, port_node); 4219 else 4220 return mvpp2_simple_queue_vectors_init(port, port_node); 4221 } 4222 4223 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 4224 { 4225 int i; 4226 4227 for (i = 0; i < port->nqvecs; i++) 4228 irq_dispose_mapping(port->qvecs[i].irq); 4229 } 4230 4231 /* Configure Rx queue group interrupt for this port */ 4232 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 4233 { 4234 struct mvpp2 *priv = port->priv; 4235 u32 val; 4236 int i; 4237 4238 if (priv->hw_version == MVPP21) { 4239 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 4240 port->nrxqs); 4241 return; 4242 } 4243 4244 /* Handle the more complicated PPv2.2 case */ 4245 for (i = 0; i < port->nqvecs; i++) { 4246 struct mvpp2_queue_vector *qv = port->qvecs + i; 4247 4248 if (!qv->nrxqs) 4249 continue; 4250 4251 val = qv->sw_thread_id; 4252 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 4253 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 4254 4255 val = qv->first_rxq; 4256 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 4257 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 4258 } 4259 } 4260 4261 /* Initialize port HW */ 4262 static int mvpp2_port_init(struct mvpp2_port *port) 4263 { 4264 struct device *dev = port->dev->dev.parent; 4265 struct mvpp2 *priv = port->priv; 4266 struct mvpp2_txq_pcpu *txq_pcpu; 4267 unsigned int thread; 4268 int queue, err; 4269 4270 /* Checks for hardware constraints */ 4271 if (port->first_rxq + port->nrxqs > 4272 MVPP2_MAX_PORTS * priv->max_port_rxqs) 4273 return -EINVAL; 4274 4275 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 4276 return -EINVAL; 4277 4278 /* Disable port */ 4279 mvpp2_egress_disable(port); 4280 mvpp2_port_disable(port); 4281 4282 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4283 4284 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4285 GFP_KERNEL); 4286 if (!port->txqs) 4287 return -ENOMEM; 4288 4289 /* Associate physical Tx queues to this port and initialize. 4290 * The mapping is predefined. 4291 */ 4292 for (queue = 0; queue < port->ntxqs; queue++) { 4293 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4294 struct mvpp2_tx_queue *txq; 4295 4296 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4297 if (!txq) { 4298 err = -ENOMEM; 4299 goto err_free_percpu; 4300 } 4301 4302 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4303 if (!txq->pcpu) { 4304 err = -ENOMEM; 4305 goto err_free_percpu; 4306 } 4307 4308 txq->id = queue_phy_id; 4309 txq->log_id = queue; 4310 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4311 for (thread = 0; thread < priv->nthreads; thread++) { 4312 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4313 txq_pcpu->thread = thread; 4314 } 4315 4316 port->txqs[queue] = txq; 4317 } 4318 4319 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4320 GFP_KERNEL); 4321 if (!port->rxqs) { 4322 err = -ENOMEM; 4323 goto err_free_percpu; 4324 } 4325 4326 /* Allocate and initialize Rx queue for this port */ 4327 for (queue = 0; queue < port->nrxqs; queue++) { 4328 struct mvpp2_rx_queue *rxq; 4329 4330 /* Map physical Rx queue to port's logical Rx queue */ 4331 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4332 if (!rxq) { 4333 err = -ENOMEM; 4334 goto err_free_percpu; 4335 } 4336 /* Map this Rx queue to a physical queue */ 4337 rxq->id = port->first_rxq + queue; 4338 rxq->port = port->id; 4339 rxq->logic_rxq = queue; 4340 4341 port->rxqs[queue] = rxq; 4342 } 4343 4344 mvpp2_rx_irqs_setup(port); 4345 4346 /* Create Rx descriptor rings */ 4347 for (queue = 0; queue < port->nrxqs; queue++) { 4348 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4349 4350 rxq->size = port->rx_ring_size; 4351 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4352 rxq->time_coal = MVPP2_RX_COAL_USEC; 4353 } 4354 4355 mvpp2_ingress_disable(port); 4356 4357 /* Port default configuration */ 4358 mvpp2_defaults_set(port); 4359 4360 /* Port's classifier configuration */ 4361 mvpp2_cls_oversize_rxq_set(port); 4362 mvpp2_cls_port_config(port); 4363 4364 if (mvpp22_rss_is_supported()) 4365 mvpp22_port_rss_init(port); 4366 4367 /* Provide an initial Rx packet size */ 4368 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4369 4370 /* Initialize pools for swf */ 4371 err = mvpp2_swf_bm_pool_init(port); 4372 if (err) 4373 goto err_free_percpu; 4374 4375 return 0; 4376 4377 err_free_percpu: 4378 for (queue = 0; queue < port->ntxqs; queue++) { 4379 if (!port->txqs[queue]) 4380 continue; 4381 free_percpu(port->txqs[queue]->pcpu); 4382 } 4383 return err; 4384 } 4385 4386 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 4387 unsigned long *flags) 4388 { 4389 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 4390 "tx-cpu3" }; 4391 int i; 4392 4393 for (i = 0; i < 5; i++) 4394 if (of_property_match_string(port_node, "interrupt-names", 4395 irqs[i]) < 0) 4396 return false; 4397 4398 *flags |= MVPP2_F_DT_COMPAT; 4399 return true; 4400 } 4401 4402 /* Checks if the port dt description has the required Tx interrupts: 4403 * - PPv2.1: there are no such interrupts. 4404 * - PPv2.2: 4405 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 4406 * - The new ones have: "hifX" with X in [0..8] 4407 * 4408 * All those variants are supported to keep the backward compatibility. 4409 */ 4410 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 4411 struct device_node *port_node, 4412 unsigned long *flags) 4413 { 4414 char name[5]; 4415 int i; 4416 4417 /* ACPI */ 4418 if (!port_node) 4419 return true; 4420 4421 if (priv->hw_version == MVPP21) 4422 return false; 4423 4424 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 4425 return true; 4426 4427 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 4428 snprintf(name, 5, "hif%d", i); 4429 if (of_property_match_string(port_node, "interrupt-names", 4430 name) < 0) 4431 return false; 4432 } 4433 4434 return true; 4435 } 4436 4437 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4438 struct fwnode_handle *fwnode, 4439 char **mac_from) 4440 { 4441 struct mvpp2_port *port = netdev_priv(dev); 4442 char hw_mac_addr[ETH_ALEN] = {0}; 4443 char fw_mac_addr[ETH_ALEN]; 4444 4445 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4446 *mac_from = "firmware node"; 4447 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4448 return; 4449 } 4450 4451 if (priv->hw_version == MVPP21) { 4452 mvpp21_get_mac_address(port, hw_mac_addr); 4453 if (is_valid_ether_addr(hw_mac_addr)) { 4454 *mac_from = "hardware"; 4455 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4456 return; 4457 } 4458 } 4459 4460 *mac_from = "random"; 4461 eth_hw_addr_random(dev); 4462 } 4463 4464 static void mvpp2_phylink_validate(struct phylink_config *config, 4465 unsigned long *supported, 4466 struct phylink_link_state *state) 4467 { 4468 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4469 phylink_config); 4470 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4471 4472 /* Invalid combinations */ 4473 switch (state->interface) { 4474 case PHY_INTERFACE_MODE_10GKR: 4475 case PHY_INTERFACE_MODE_XAUI: 4476 if (port->gop_id != 0) 4477 goto empty_set; 4478 break; 4479 case PHY_INTERFACE_MODE_RGMII: 4480 case PHY_INTERFACE_MODE_RGMII_ID: 4481 case PHY_INTERFACE_MODE_RGMII_RXID: 4482 case PHY_INTERFACE_MODE_RGMII_TXID: 4483 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) 4484 goto empty_set; 4485 break; 4486 default: 4487 break; 4488 } 4489 4490 phylink_set(mask, Autoneg); 4491 phylink_set_port_modes(mask); 4492 phylink_set(mask, Pause); 4493 phylink_set(mask, Asym_Pause); 4494 4495 switch (state->interface) { 4496 case PHY_INTERFACE_MODE_10GKR: 4497 case PHY_INTERFACE_MODE_XAUI: 4498 case PHY_INTERFACE_MODE_NA: 4499 if (port->gop_id == 0) { 4500 phylink_set(mask, 10000baseT_Full); 4501 phylink_set(mask, 10000baseCR_Full); 4502 phylink_set(mask, 10000baseSR_Full); 4503 phylink_set(mask, 10000baseLR_Full); 4504 phylink_set(mask, 10000baseLRM_Full); 4505 phylink_set(mask, 10000baseER_Full); 4506 phylink_set(mask, 10000baseKR_Full); 4507 } 4508 /* Fall-through */ 4509 case PHY_INTERFACE_MODE_RGMII: 4510 case PHY_INTERFACE_MODE_RGMII_ID: 4511 case PHY_INTERFACE_MODE_RGMII_RXID: 4512 case PHY_INTERFACE_MODE_RGMII_TXID: 4513 case PHY_INTERFACE_MODE_SGMII: 4514 phylink_set(mask, 10baseT_Half); 4515 phylink_set(mask, 10baseT_Full); 4516 phylink_set(mask, 100baseT_Half); 4517 phylink_set(mask, 100baseT_Full); 4518 /* Fall-through */ 4519 case PHY_INTERFACE_MODE_1000BASEX: 4520 case PHY_INTERFACE_MODE_2500BASEX: 4521 phylink_set(mask, 1000baseT_Full); 4522 phylink_set(mask, 1000baseX_Full); 4523 phylink_set(mask, 2500baseT_Full); 4524 phylink_set(mask, 2500baseX_Full); 4525 break; 4526 default: 4527 goto empty_set; 4528 } 4529 4530 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4531 bitmap_and(state->advertising, state->advertising, mask, 4532 __ETHTOOL_LINK_MODE_MASK_NBITS); 4533 return; 4534 4535 empty_set: 4536 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 4537 } 4538 4539 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4540 struct phylink_link_state *state) 4541 { 4542 u32 val; 4543 4544 state->speed = SPEED_10000; 4545 state->duplex = 1; 4546 state->an_complete = 1; 4547 4548 val = readl(port->base + MVPP22_XLG_STATUS); 4549 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4550 4551 state->pause = 0; 4552 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4553 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4554 state->pause |= MLO_PAUSE_TX; 4555 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4556 state->pause |= MLO_PAUSE_RX; 4557 } 4558 4559 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4560 struct phylink_link_state *state) 4561 { 4562 u32 val; 4563 4564 val = readl(port->base + MVPP2_GMAC_STATUS0); 4565 4566 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4567 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4568 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4569 4570 switch (port->phy_interface) { 4571 case PHY_INTERFACE_MODE_1000BASEX: 4572 state->speed = SPEED_1000; 4573 break; 4574 case PHY_INTERFACE_MODE_2500BASEX: 4575 state->speed = SPEED_2500; 4576 break; 4577 default: 4578 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4579 state->speed = SPEED_1000; 4580 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4581 state->speed = SPEED_100; 4582 else 4583 state->speed = SPEED_10; 4584 } 4585 4586 state->pause = 0; 4587 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4588 state->pause |= MLO_PAUSE_RX; 4589 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4590 state->pause |= MLO_PAUSE_TX; 4591 } 4592 4593 static int mvpp2_phylink_mac_link_state(struct phylink_config *config, 4594 struct phylink_link_state *state) 4595 { 4596 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4597 phylink_config); 4598 4599 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4600 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4601 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4602 4603 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4604 mvpp22_xlg_link_state(port, state); 4605 return 1; 4606 } 4607 } 4608 4609 mvpp2_gmac_link_state(port, state); 4610 return 1; 4611 } 4612 4613 static void mvpp2_mac_an_restart(struct phylink_config *config) 4614 { 4615 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4616 phylink_config); 4617 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4618 4619 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 4620 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4621 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 4622 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4623 } 4624 4625 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4626 const struct phylink_link_state *state) 4627 { 4628 u32 old_ctrl0, ctrl0; 4629 u32 old_ctrl4, ctrl4; 4630 4631 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4632 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4633 4634 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS; 4635 4636 if (state->pause & MLO_PAUSE_TX) 4637 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4638 else 4639 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4640 4641 if (state->pause & MLO_PAUSE_RX) 4642 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4643 else 4644 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4645 4646 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4647 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4648 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4649 4650 if (old_ctrl0 != ctrl0) 4651 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4652 if (old_ctrl4 != ctrl4) 4653 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4654 4655 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) { 4656 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) & 4657 MVPP22_XLG_CTRL0_MAC_RESET_DIS)) 4658 continue; 4659 } 4660 } 4661 4662 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4663 const struct phylink_link_state *state) 4664 { 4665 u32 old_an, an; 4666 u32 old_ctrl0, ctrl0; 4667 u32 old_ctrl2, ctrl2; 4668 u32 old_ctrl4, ctrl4; 4669 4670 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4671 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4672 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4673 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4674 4675 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4676 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4677 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4678 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4679 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS); 4680 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4681 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK | 4682 MVPP2_GMAC_PCS_ENABLE_MASK); 4683 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4684 4685 /* Configure port type */ 4686 if (phy_interface_mode_is_8023z(state->interface)) { 4687 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 4688 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4689 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4690 MVPP22_CTRL4_DP_CLK_SEL | 4691 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4692 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4693 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 4694 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4695 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4696 MVPP22_CTRL4_DP_CLK_SEL | 4697 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4698 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4699 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4700 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4701 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4702 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4703 } 4704 4705 /* Configure advertisement bits */ 4706 if (phylink_test(state->advertising, Pause)) 4707 an |= MVPP2_GMAC_FC_ADV_EN; 4708 if (phylink_test(state->advertising, Asym_Pause)) 4709 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4710 4711 /* Configure negotiation style */ 4712 if (!phylink_autoneg_inband(mode)) { 4713 /* Phy or fixed speed - no in-band AN */ 4714 if (state->duplex) 4715 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4716 4717 if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 4718 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4719 else if (state->speed == SPEED_100) 4720 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4721 4722 if (state->pause & MLO_PAUSE_TX) 4723 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4724 if (state->pause & MLO_PAUSE_RX) 4725 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4726 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4727 /* SGMII in-band mode receives the speed and duplex from 4728 * the PHY. Flow control information is not received. */ 4729 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4730 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4731 MVPP2_GMAC_AN_SPEED_EN | 4732 MVPP2_GMAC_AN_DUPLEX_EN; 4733 4734 if (state->pause & MLO_PAUSE_TX) 4735 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4736 if (state->pause & MLO_PAUSE_RX) 4737 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4738 } else if (phy_interface_mode_is_8023z(state->interface)) { 4739 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4740 * they negotiate duplex: they are always operating with a fixed 4741 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4742 * speed and full duplex here. 4743 */ 4744 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4745 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4746 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4747 MVPP2_GMAC_CONFIG_GMII_SPEED | 4748 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4749 4750 if (state->pause & MLO_PAUSE_AN && state->an_enabled) { 4751 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4752 } else { 4753 if (state->pause & MLO_PAUSE_TX) 4754 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4755 if (state->pause & MLO_PAUSE_RX) 4756 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4757 } 4758 } 4759 4760 /* Some fields of the auto-negotiation register require the port to be down when 4761 * their value is updated. 4762 */ 4763 #define MVPP2_GMAC_AN_PORT_DOWN_MASK \ 4764 (MVPP2_GMAC_IN_BAND_AUTONEG | \ 4765 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \ 4766 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \ 4767 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \ 4768 MVPP2_GMAC_AN_DUPLEX_EN) 4769 4770 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK || 4771 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK || 4772 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) { 4773 /* Force link down */ 4774 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4775 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4776 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4777 4778 /* Set the GMAC in a reset state - do this in a way that 4779 * ensures we clear it below. 4780 */ 4781 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4782 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4783 } 4784 4785 if (old_ctrl0 != ctrl0) 4786 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4787 if (old_ctrl2 != ctrl2) 4788 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4789 if (old_ctrl4 != ctrl4) 4790 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4791 if (old_an != an) 4792 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4793 4794 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) { 4795 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 4796 MVPP2_GMAC_PORT_RESET_MASK) 4797 continue; 4798 } 4799 } 4800 4801 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 4802 const struct phylink_link_state *state) 4803 { 4804 struct net_device *dev = to_net_dev(config->dev); 4805 struct mvpp2_port *port = netdev_priv(dev); 4806 bool change_interface = port->phy_interface != state->interface; 4807 4808 /* Check for invalid configuration */ 4809 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) { 4810 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4811 return; 4812 } 4813 4814 /* Make sure the port is disabled when reconfiguring the mode */ 4815 mvpp2_port_disable(port); 4816 4817 if (port->priv->hw_version == MVPP22 && change_interface) { 4818 mvpp22_gop_mask_irq(port); 4819 4820 port->phy_interface = state->interface; 4821 4822 /* Reconfigure the serdes lanes */ 4823 phy_power_off(port->comphy); 4824 mvpp22_mode_reconfigure(port); 4825 } 4826 4827 /* mac (re)configuration */ 4828 if (mvpp2_is_xlg(state->interface)) 4829 mvpp2_xlg_config(port, mode, state); 4830 else if (phy_interface_mode_is_rgmii(state->interface) || 4831 phy_interface_mode_is_8023z(state->interface) || 4832 state->interface == PHY_INTERFACE_MODE_SGMII) 4833 mvpp2_gmac_config(port, mode, state); 4834 4835 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4836 mvpp2_port_loopback_set(port, state); 4837 4838 if (port->priv->hw_version == MVPP22 && change_interface) 4839 mvpp22_gop_unmask_irq(port); 4840 4841 mvpp2_port_enable(port); 4842 } 4843 4844 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 4845 phy_interface_t interface, struct phy_device *phy) 4846 { 4847 struct net_device *dev = to_net_dev(config->dev); 4848 struct mvpp2_port *port = netdev_priv(dev); 4849 u32 val; 4850 4851 if (!phylink_autoneg_inband(mode)) { 4852 if (mvpp2_is_xlg(interface)) { 4853 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4854 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4855 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4856 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4857 } else { 4858 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4859 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4860 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4861 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4862 } 4863 } 4864 4865 mvpp2_port_enable(port); 4866 4867 mvpp2_egress_enable(port); 4868 mvpp2_ingress_enable(port); 4869 netif_tx_wake_all_queues(dev); 4870 } 4871 4872 static void mvpp2_mac_link_down(struct phylink_config *config, 4873 unsigned int mode, phy_interface_t interface) 4874 { 4875 struct net_device *dev = to_net_dev(config->dev); 4876 struct mvpp2_port *port = netdev_priv(dev); 4877 u32 val; 4878 4879 if (!phylink_autoneg_inband(mode)) { 4880 if (mvpp2_is_xlg(interface)) { 4881 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4882 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4883 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4884 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4885 } else { 4886 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4887 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4888 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4889 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4890 } 4891 } 4892 4893 netif_tx_stop_all_queues(dev); 4894 mvpp2_egress_disable(port); 4895 mvpp2_ingress_disable(port); 4896 4897 mvpp2_port_disable(port); 4898 } 4899 4900 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4901 .validate = mvpp2_phylink_validate, 4902 .mac_link_state = mvpp2_phylink_mac_link_state, 4903 .mac_an_restart = mvpp2_mac_an_restart, 4904 .mac_config = mvpp2_mac_config, 4905 .mac_link_up = mvpp2_mac_link_up, 4906 .mac_link_down = mvpp2_mac_link_down, 4907 }; 4908 4909 /* Ports initialization */ 4910 static int mvpp2_port_probe(struct platform_device *pdev, 4911 struct fwnode_handle *port_fwnode, 4912 struct mvpp2 *priv) 4913 { 4914 struct phy *comphy = NULL; 4915 struct mvpp2_port *port; 4916 struct mvpp2_port_pcpu *port_pcpu; 4917 struct device_node *port_node = to_of_node(port_fwnode); 4918 netdev_features_t features; 4919 struct net_device *dev; 4920 struct resource *res; 4921 struct phylink *phylink; 4922 char *mac_from = ""; 4923 unsigned int ntxqs, nrxqs, thread; 4924 unsigned long flags = 0; 4925 bool has_tx_irqs; 4926 u32 id; 4927 int phy_mode; 4928 int err, i; 4929 4930 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 4931 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 4932 dev_err(&pdev->dev, 4933 "not enough IRQs to support multi queue mode\n"); 4934 return -EINVAL; 4935 } 4936 4937 ntxqs = MVPP2_MAX_TXQ; 4938 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) { 4939 nrxqs = 1; 4940 } else { 4941 /* According to the PPv2.2 datasheet and our experiments on 4942 * PPv2.1, RX queues have an allocation granularity of 4 (when 4943 * more than a single one on PPv2.2). 4944 * Round up to nearest multiple of 4. 4945 */ 4946 nrxqs = (num_possible_cpus() + 3) & ~0x3; 4947 if (nrxqs > MVPP2_PORT_MAX_RXQ) 4948 nrxqs = MVPP2_PORT_MAX_RXQ; 4949 } 4950 4951 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 4952 if (!dev) 4953 return -ENOMEM; 4954 4955 phy_mode = fwnode_get_phy_mode(port_fwnode); 4956 if (phy_mode < 0) { 4957 dev_err(&pdev->dev, "incorrect phy mode\n"); 4958 err = phy_mode; 4959 goto err_free_netdev; 4960 } 4961 4962 if (port_node) { 4963 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 4964 if (IS_ERR(comphy)) { 4965 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 4966 err = -EPROBE_DEFER; 4967 goto err_free_netdev; 4968 } 4969 comphy = NULL; 4970 } 4971 } 4972 4973 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 4974 err = -EINVAL; 4975 dev_err(&pdev->dev, "missing port-id value\n"); 4976 goto err_free_netdev; 4977 } 4978 4979 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 4980 dev->watchdog_timeo = 5 * HZ; 4981 dev->netdev_ops = &mvpp2_netdev_ops; 4982 dev->ethtool_ops = &mvpp2_eth_tool_ops; 4983 4984 port = netdev_priv(dev); 4985 port->dev = dev; 4986 port->fwnode = port_fwnode; 4987 port->has_phy = !!of_find_property(port_node, "phy", NULL); 4988 port->ntxqs = ntxqs; 4989 port->nrxqs = nrxqs; 4990 port->priv = priv; 4991 port->has_tx_irqs = has_tx_irqs; 4992 port->flags = flags; 4993 4994 err = mvpp2_queue_vectors_init(port, port_node); 4995 if (err) 4996 goto err_free_netdev; 4997 4998 if (port_node) 4999 port->link_irq = of_irq_get_byname(port_node, "link"); 5000 else 5001 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 5002 if (port->link_irq == -EPROBE_DEFER) { 5003 err = -EPROBE_DEFER; 5004 goto err_deinit_qvecs; 5005 } 5006 if (port->link_irq <= 0) 5007 /* the link irq is optional */ 5008 port->link_irq = 0; 5009 5010 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 5011 port->flags |= MVPP2_F_LOOPBACK; 5012 5013 port->id = id; 5014 if (priv->hw_version == MVPP21) 5015 port->first_rxq = port->id * port->nrxqs; 5016 else 5017 port->first_rxq = port->id * priv->max_port_rxqs; 5018 5019 port->of_node = port_node; 5020 port->phy_interface = phy_mode; 5021 port->comphy = comphy; 5022 5023 if (priv->hw_version == MVPP21) { 5024 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); 5025 port->base = devm_ioremap_resource(&pdev->dev, res); 5026 if (IS_ERR(port->base)) { 5027 err = PTR_ERR(port->base); 5028 goto err_free_irq; 5029 } 5030 5031 port->stats_base = port->priv->lms_base + 5032 MVPP21_MIB_COUNTERS_OFFSET + 5033 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 5034 } else { 5035 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 5036 &port->gop_id)) { 5037 err = -EINVAL; 5038 dev_err(&pdev->dev, "missing gop-port-id value\n"); 5039 goto err_deinit_qvecs; 5040 } 5041 5042 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 5043 port->stats_base = port->priv->iface_base + 5044 MVPP22_MIB_COUNTERS_OFFSET + 5045 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 5046 } 5047 5048 /* Alloc per-cpu and ethtool stats */ 5049 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 5050 if (!port->stats) { 5051 err = -ENOMEM; 5052 goto err_free_irq; 5053 } 5054 5055 port->ethtool_stats = devm_kcalloc(&pdev->dev, 5056 ARRAY_SIZE(mvpp2_ethtool_regs), 5057 sizeof(u64), GFP_KERNEL); 5058 if (!port->ethtool_stats) { 5059 err = -ENOMEM; 5060 goto err_free_stats; 5061 } 5062 5063 mutex_init(&port->gather_stats_lock); 5064 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 5065 5066 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 5067 5068 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 5069 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 5070 SET_NETDEV_DEV(dev, &pdev->dev); 5071 5072 err = mvpp2_port_init(port); 5073 if (err < 0) { 5074 dev_err(&pdev->dev, "failed to init port %d\n", id); 5075 goto err_free_stats; 5076 } 5077 5078 mvpp2_port_periodic_xon_disable(port); 5079 5080 mvpp2_mac_reset_assert(port); 5081 mvpp22_pcs_reset_assert(port); 5082 5083 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 5084 if (!port->pcpu) { 5085 err = -ENOMEM; 5086 goto err_free_txq_pcpu; 5087 } 5088 5089 if (!port->has_tx_irqs) { 5090 for (thread = 0; thread < priv->nthreads; thread++) { 5091 port_pcpu = per_cpu_ptr(port->pcpu, thread); 5092 5093 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 5094 HRTIMER_MODE_REL_PINNED); 5095 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 5096 port_pcpu->timer_scheduled = false; 5097 5098 tasklet_init(&port_pcpu->tx_done_tasklet, 5099 mvpp2_tx_proc_cb, 5100 (unsigned long)dev); 5101 } 5102 } 5103 5104 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5105 NETIF_F_TSO; 5106 dev->features = features | NETIF_F_RXCSUM; 5107 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 5108 NETIF_F_HW_VLAN_CTAG_FILTER; 5109 5110 if (mvpp22_rss_is_supported()) { 5111 dev->hw_features |= NETIF_F_RXHASH; 5112 dev->features |= NETIF_F_NTUPLE; 5113 } 5114 5115 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 5116 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 5117 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 5118 } 5119 5120 dev->vlan_features |= features; 5121 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 5122 dev->priv_flags |= IFF_UNICAST_FLT; 5123 5124 /* MTU range: 68 - 9704 */ 5125 dev->min_mtu = ETH_MIN_MTU; 5126 /* 9704 == 9728 - 20 and rounding to 8 */ 5127 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 5128 dev->dev.of_node = port_node; 5129 5130 /* Phylink isn't used w/ ACPI as of now */ 5131 if (port_node) { 5132 port->phylink_config.dev = &dev->dev; 5133 port->phylink_config.type = PHYLINK_NETDEV; 5134 5135 phylink = phylink_create(&port->phylink_config, port_fwnode, 5136 phy_mode, &mvpp2_phylink_ops); 5137 if (IS_ERR(phylink)) { 5138 err = PTR_ERR(phylink); 5139 goto err_free_port_pcpu; 5140 } 5141 port->phylink = phylink; 5142 } else { 5143 port->phylink = NULL; 5144 } 5145 5146 err = register_netdev(dev); 5147 if (err < 0) { 5148 dev_err(&pdev->dev, "failed to register netdev\n"); 5149 goto err_phylink; 5150 } 5151 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 5152 5153 priv->port_list[priv->port_count++] = port; 5154 5155 return 0; 5156 5157 err_phylink: 5158 if (port->phylink) 5159 phylink_destroy(port->phylink); 5160 err_free_port_pcpu: 5161 free_percpu(port->pcpu); 5162 err_free_txq_pcpu: 5163 for (i = 0; i < port->ntxqs; i++) 5164 free_percpu(port->txqs[i]->pcpu); 5165 err_free_stats: 5166 free_percpu(port->stats); 5167 err_free_irq: 5168 if (port->link_irq) 5169 irq_dispose_mapping(port->link_irq); 5170 err_deinit_qvecs: 5171 mvpp2_queue_vectors_deinit(port); 5172 err_free_netdev: 5173 free_netdev(dev); 5174 return err; 5175 } 5176 5177 /* Ports removal routine */ 5178 static void mvpp2_port_remove(struct mvpp2_port *port) 5179 { 5180 int i; 5181 5182 unregister_netdev(port->dev); 5183 if (port->phylink) 5184 phylink_destroy(port->phylink); 5185 free_percpu(port->pcpu); 5186 free_percpu(port->stats); 5187 for (i = 0; i < port->ntxqs; i++) 5188 free_percpu(port->txqs[i]->pcpu); 5189 mvpp2_queue_vectors_deinit(port); 5190 if (port->link_irq) 5191 irq_dispose_mapping(port->link_irq); 5192 free_netdev(port->dev); 5193 } 5194 5195 /* Initialize decoding windows */ 5196 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 5197 struct mvpp2 *priv) 5198 { 5199 u32 win_enable; 5200 int i; 5201 5202 for (i = 0; i < 6; i++) { 5203 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 5204 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 5205 5206 if (i < 4) 5207 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 5208 } 5209 5210 win_enable = 0; 5211 5212 for (i = 0; i < dram->num_cs; i++) { 5213 const struct mbus_dram_window *cs = dram->cs + i; 5214 5215 mvpp2_write(priv, MVPP2_WIN_BASE(i), 5216 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 5217 dram->mbus_dram_target_id); 5218 5219 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 5220 (cs->size - 1) & 0xffff0000); 5221 5222 win_enable |= (1 << i); 5223 } 5224 5225 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 5226 } 5227 5228 /* Initialize Rx FIFO's */ 5229 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 5230 { 5231 int port; 5232 5233 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5234 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5235 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5236 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5237 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5238 } 5239 5240 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5241 MVPP2_RX_FIFO_PORT_MIN_PKT); 5242 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5243 } 5244 5245 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 5246 { 5247 int port; 5248 5249 /* The FIFO size parameters are set depending on the maximum speed a 5250 * given port can handle: 5251 * - Port 0: 10Gbps 5252 * - Port 1: 2.5Gbps 5253 * - Ports 2 and 3: 1Gbps 5254 */ 5255 5256 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 5257 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 5258 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 5259 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 5260 5261 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 5262 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 5263 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 5264 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 5265 5266 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 5267 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5268 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5269 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5270 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5271 } 5272 5273 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5274 MVPP2_RX_FIFO_PORT_MIN_PKT); 5275 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5276 } 5277 5278 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 5279 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 5280 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 5281 */ 5282 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 5283 { 5284 int port, size, thrs; 5285 5286 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5287 if (port == 0) { 5288 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 5289 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 5290 } else { 5291 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 5292 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 5293 } 5294 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 5295 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 5296 } 5297 } 5298 5299 static void mvpp2_axi_init(struct mvpp2 *priv) 5300 { 5301 u32 val, rdval, wrval; 5302 5303 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 5304 5305 /* AXI Bridge Configuration */ 5306 5307 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 5308 << MVPP22_AXI_ATTR_CACHE_OFFS; 5309 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5310 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5311 5312 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 5313 << MVPP22_AXI_ATTR_CACHE_OFFS; 5314 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5315 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5316 5317 /* BM */ 5318 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 5319 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 5320 5321 /* Descriptors */ 5322 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 5323 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 5324 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 5325 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 5326 5327 /* Buffer Data */ 5328 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 5329 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 5330 5331 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 5332 << MVPP22_AXI_CODE_CACHE_OFFS; 5333 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 5334 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5335 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 5336 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 5337 5338 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 5339 << MVPP22_AXI_CODE_CACHE_OFFS; 5340 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5341 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5342 5343 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 5344 5345 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 5346 << MVPP22_AXI_CODE_CACHE_OFFS; 5347 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5348 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5349 5350 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 5351 } 5352 5353 /* Initialize network controller common part HW */ 5354 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 5355 { 5356 const struct mbus_dram_target_info *dram_target_info; 5357 int err, i; 5358 u32 val; 5359 5360 /* MBUS windows configuration */ 5361 dram_target_info = mv_mbus_dram_info(); 5362 if (dram_target_info) 5363 mvpp2_conf_mbus_windows(dram_target_info, priv); 5364 5365 if (priv->hw_version == MVPP22) 5366 mvpp2_axi_init(priv); 5367 5368 /* Disable HW PHY polling */ 5369 if (priv->hw_version == MVPP21) { 5370 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5371 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 5372 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5373 } else { 5374 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5375 val &= ~MVPP22_SMI_POLLING_EN; 5376 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5377 } 5378 5379 /* Allocate and initialize aggregated TXQs */ 5380 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 5381 sizeof(*priv->aggr_txqs), 5382 GFP_KERNEL); 5383 if (!priv->aggr_txqs) 5384 return -ENOMEM; 5385 5386 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5387 priv->aggr_txqs[i].id = i; 5388 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 5389 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 5390 if (err < 0) 5391 return err; 5392 } 5393 5394 /* Fifo Init */ 5395 if (priv->hw_version == MVPP21) { 5396 mvpp2_rx_fifo_init(priv); 5397 } else { 5398 mvpp22_rx_fifo_init(priv); 5399 mvpp22_tx_fifo_init(priv); 5400 } 5401 5402 if (priv->hw_version == MVPP21) 5403 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 5404 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 5405 5406 /* Allow cache snoop when transmiting packets */ 5407 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 5408 5409 /* Buffer Manager initialization */ 5410 err = mvpp2_bm_init(pdev, priv); 5411 if (err < 0) 5412 return err; 5413 5414 /* Parser default initialization */ 5415 err = mvpp2_prs_default_init(pdev, priv); 5416 if (err < 0) 5417 return err; 5418 5419 /* Classifier default initialization */ 5420 mvpp2_cls_init(priv); 5421 5422 return 0; 5423 } 5424 5425 static int mvpp2_probe(struct platform_device *pdev) 5426 { 5427 const struct acpi_device_id *acpi_id; 5428 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5429 struct fwnode_handle *port_fwnode; 5430 struct mvpp2 *priv; 5431 struct resource *res; 5432 void __iomem *base; 5433 int i, shared; 5434 int err; 5435 5436 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5437 if (!priv) 5438 return -ENOMEM; 5439 5440 if (has_acpi_companion(&pdev->dev)) { 5441 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5442 &pdev->dev); 5443 if (!acpi_id) 5444 return -EINVAL; 5445 priv->hw_version = (unsigned long)acpi_id->driver_data; 5446 } else { 5447 priv->hw_version = 5448 (unsigned long)of_device_get_match_data(&pdev->dev); 5449 } 5450 5451 /* multi queue mode isn't supported on PPV2.1, fallback to single 5452 * mode 5453 */ 5454 if (priv->hw_version == MVPP21) 5455 queue_mode = MVPP2_QDIST_SINGLE_MODE; 5456 5457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5458 base = devm_ioremap_resource(&pdev->dev, res); 5459 if (IS_ERR(base)) 5460 return PTR_ERR(base); 5461 5462 if (priv->hw_version == MVPP21) { 5463 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5464 priv->lms_base = devm_ioremap_resource(&pdev->dev, res); 5465 if (IS_ERR(priv->lms_base)) 5466 return PTR_ERR(priv->lms_base); 5467 } else { 5468 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5469 if (has_acpi_companion(&pdev->dev)) { 5470 /* In case the MDIO memory region is declared in 5471 * the ACPI, it can already appear as 'in-use' 5472 * in the OS. Because it is overlapped by second 5473 * region of the network controller, make 5474 * sure it is released, before requesting it again. 5475 * The care is taken by mvpp2 driver to avoid 5476 * concurrent access to this memory region. 5477 */ 5478 release_resource(res); 5479 } 5480 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5481 if (IS_ERR(priv->iface_base)) 5482 return PTR_ERR(priv->iface_base); 5483 } 5484 5485 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5486 priv->sysctrl_base = 5487 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5488 "marvell,system-controller"); 5489 if (IS_ERR(priv->sysctrl_base)) 5490 /* The system controller regmap is optional for dt 5491 * compatibility reasons. When not provided, the 5492 * configuration of the GoP relies on the 5493 * firmware/bootloader. 5494 */ 5495 priv->sysctrl_base = NULL; 5496 } 5497 5498 mvpp2_setup_bm_pool(); 5499 5500 5501 priv->nthreads = min_t(unsigned int, num_present_cpus(), 5502 MVPP2_MAX_THREADS); 5503 5504 shared = num_present_cpus() - priv->nthreads; 5505 if (shared > 0) 5506 bitmap_fill(&priv->lock_map, 5507 min_t(int, shared, MVPP2_MAX_THREADS)); 5508 5509 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5510 u32 addr_space_sz; 5511 5512 addr_space_sz = (priv->hw_version == MVPP21 ? 5513 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5514 priv->swth_base[i] = base + i * addr_space_sz; 5515 } 5516 5517 if (priv->hw_version == MVPP21) 5518 priv->max_port_rxqs = 8; 5519 else 5520 priv->max_port_rxqs = 32; 5521 5522 if (dev_of_node(&pdev->dev)) { 5523 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5524 if (IS_ERR(priv->pp_clk)) 5525 return PTR_ERR(priv->pp_clk); 5526 err = clk_prepare_enable(priv->pp_clk); 5527 if (err < 0) 5528 return err; 5529 5530 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5531 if (IS_ERR(priv->gop_clk)) { 5532 err = PTR_ERR(priv->gop_clk); 5533 goto err_pp_clk; 5534 } 5535 err = clk_prepare_enable(priv->gop_clk); 5536 if (err < 0) 5537 goto err_pp_clk; 5538 5539 if (priv->hw_version == MVPP22) { 5540 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5541 if (IS_ERR(priv->mg_clk)) { 5542 err = PTR_ERR(priv->mg_clk); 5543 goto err_gop_clk; 5544 } 5545 5546 err = clk_prepare_enable(priv->mg_clk); 5547 if (err < 0) 5548 goto err_gop_clk; 5549 5550 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5551 if (IS_ERR(priv->mg_core_clk)) { 5552 priv->mg_core_clk = NULL; 5553 } else { 5554 err = clk_prepare_enable(priv->mg_core_clk); 5555 if (err < 0) 5556 goto err_mg_clk; 5557 } 5558 } 5559 5560 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5561 if (IS_ERR(priv->axi_clk)) { 5562 err = PTR_ERR(priv->axi_clk); 5563 if (err == -EPROBE_DEFER) 5564 goto err_mg_core_clk; 5565 priv->axi_clk = NULL; 5566 } else { 5567 err = clk_prepare_enable(priv->axi_clk); 5568 if (err < 0) 5569 goto err_mg_core_clk; 5570 } 5571 5572 /* Get system's tclk rate */ 5573 priv->tclk = clk_get_rate(priv->pp_clk); 5574 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5575 &priv->tclk)) { 5576 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5577 return -EINVAL; 5578 } 5579 5580 if (priv->hw_version == MVPP22) { 5581 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5582 if (err) 5583 goto err_axi_clk; 5584 /* Sadly, the BM pools all share the same register to 5585 * store the high 32 bits of their address. So they 5586 * must all have the same high 32 bits, which forces 5587 * us to restrict coherent memory to DMA_BIT_MASK(32). 5588 */ 5589 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5590 if (err) 5591 goto err_axi_clk; 5592 } 5593 5594 /* Initialize network controller */ 5595 err = mvpp2_init(pdev, priv); 5596 if (err < 0) { 5597 dev_err(&pdev->dev, "failed to initialize controller\n"); 5598 goto err_axi_clk; 5599 } 5600 5601 /* Initialize ports */ 5602 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5603 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5604 if (err < 0) 5605 goto err_port_probe; 5606 } 5607 5608 if (priv->port_count == 0) { 5609 dev_err(&pdev->dev, "no ports enabled\n"); 5610 err = -ENODEV; 5611 goto err_axi_clk; 5612 } 5613 5614 /* Statistics must be gathered regularly because some of them (like 5615 * packets counters) are 32-bit registers and could overflow quite 5616 * quickly. For instance, a 10Gb link used at full bandwidth with the 5617 * smallest packets (64B) will overflow a 32-bit counter in less than 5618 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5619 */ 5620 snprintf(priv->queue_name, sizeof(priv->queue_name), 5621 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5622 priv->port_count > 1 ? "+" : ""); 5623 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5624 if (!priv->stats_queue) { 5625 err = -ENOMEM; 5626 goto err_port_probe; 5627 } 5628 5629 mvpp2_dbgfs_init(priv, pdev->name); 5630 5631 platform_set_drvdata(pdev, priv); 5632 return 0; 5633 5634 err_port_probe: 5635 i = 0; 5636 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5637 if (priv->port_list[i]) 5638 mvpp2_port_remove(priv->port_list[i]); 5639 i++; 5640 } 5641 err_axi_clk: 5642 clk_disable_unprepare(priv->axi_clk); 5643 5644 err_mg_core_clk: 5645 if (priv->hw_version == MVPP22) 5646 clk_disable_unprepare(priv->mg_core_clk); 5647 err_mg_clk: 5648 if (priv->hw_version == MVPP22) 5649 clk_disable_unprepare(priv->mg_clk); 5650 err_gop_clk: 5651 clk_disable_unprepare(priv->gop_clk); 5652 err_pp_clk: 5653 clk_disable_unprepare(priv->pp_clk); 5654 return err; 5655 } 5656 5657 static int mvpp2_remove(struct platform_device *pdev) 5658 { 5659 struct mvpp2 *priv = platform_get_drvdata(pdev); 5660 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5661 struct fwnode_handle *port_fwnode; 5662 int i = 0; 5663 5664 mvpp2_dbgfs_cleanup(priv); 5665 5666 flush_workqueue(priv->stats_queue); 5667 destroy_workqueue(priv->stats_queue); 5668 5669 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5670 if (priv->port_list[i]) { 5671 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5672 mvpp2_port_remove(priv->port_list[i]); 5673 } 5674 i++; 5675 } 5676 5677 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5678 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5679 5680 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5681 } 5682 5683 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5684 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5685 5686 dma_free_coherent(&pdev->dev, 5687 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5688 aggr_txq->descs, 5689 aggr_txq->descs_dma); 5690 } 5691 5692 if (is_acpi_node(port_fwnode)) 5693 return 0; 5694 5695 clk_disable_unprepare(priv->axi_clk); 5696 clk_disable_unprepare(priv->mg_core_clk); 5697 clk_disable_unprepare(priv->mg_clk); 5698 clk_disable_unprepare(priv->pp_clk); 5699 clk_disable_unprepare(priv->gop_clk); 5700 5701 return 0; 5702 } 5703 5704 static const struct of_device_id mvpp2_match[] = { 5705 { 5706 .compatible = "marvell,armada-375-pp2", 5707 .data = (void *)MVPP21, 5708 }, 5709 { 5710 .compatible = "marvell,armada-7k-pp22", 5711 .data = (void *)MVPP22, 5712 }, 5713 { } 5714 }; 5715 MODULE_DEVICE_TABLE(of, mvpp2_match); 5716 5717 static const struct acpi_device_id mvpp2_acpi_match[] = { 5718 { "MRVL0110", MVPP22 }, 5719 { }, 5720 }; 5721 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5722 5723 static struct platform_driver mvpp2_driver = { 5724 .probe = mvpp2_probe, 5725 .remove = mvpp2_remove, 5726 .driver = { 5727 .name = MVPP2_DRIVER_NAME, 5728 .of_match_table = mvpp2_match, 5729 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5730 }, 5731 }; 5732 5733 module_platform_driver(mvpp2_driver); 5734 5735 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5736 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5737 MODULE_LICENSE("GPL v2"); 5738