1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 40 #include "mvpp2.h" 41 #include "mvpp2_prs.h" 42 #include "mvpp2_cls.h" 43 44 enum mvpp2_bm_pool_log_num { 45 MVPP2_BM_SHORT, 46 MVPP2_BM_LONG, 47 MVPP2_BM_JUMBO, 48 MVPP2_BM_POOLS_NUM 49 }; 50 51 static struct { 52 int pkt_size; 53 int buf_num; 54 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 55 56 /* The prototype is added here to be used in start_dev when using ACPI. This 57 * will be removed once phylink is used for all modes (dt+ACPI). 58 */ 59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 60 const struct phylink_link_state *state); 61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 62 phy_interface_t interface, struct phy_device *phy); 63 64 /* Queue modes */ 65 #define MVPP2_QDIST_SINGLE_MODE 0 66 #define MVPP2_QDIST_MULTI_MODE 1 67 68 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 69 70 module_param(queue_mode, int, 0444); 71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 72 73 /* Utility/helper methods */ 74 75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 76 { 77 writel(data, priv->swth_base[0] + offset); 78 } 79 80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 81 { 82 return readl(priv->swth_base[0] + offset); 83 } 84 85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 86 { 87 return readl_relaxed(priv->swth_base[0] + offset); 88 } 89 90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 91 { 92 return cpu % priv->nthreads; 93 } 94 95 /* These accessors should be used to access: 96 * 97 * - per-thread registers, where each thread has its own copy of the 98 * register. 99 * 100 * MVPP2_BM_VIRT_ALLOC_REG 101 * MVPP2_BM_ADDR_HIGH_ALLOC 102 * MVPP22_BM_ADDR_HIGH_RLS_REG 103 * MVPP2_BM_VIRT_RLS_REG 104 * MVPP2_ISR_RX_TX_CAUSE_REG 105 * MVPP2_ISR_RX_TX_MASK_REG 106 * MVPP2_TXQ_NUM_REG 107 * MVPP2_AGGR_TXQ_UPDATE_REG 108 * MVPP2_TXQ_RSVD_REQ_REG 109 * MVPP2_TXQ_RSVD_RSLT_REG 110 * MVPP2_TXQ_SENT_REG 111 * MVPP2_RXQ_NUM_REG 112 * 113 * - global registers that must be accessed through a specific thread 114 * window, because they are related to an access to a per-thread 115 * register 116 * 117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 130 */ 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 132 u32 offset, u32 data) 133 { 134 writel(data, priv->swth_base[thread] + offset); 135 } 136 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 138 u32 offset) 139 { 140 return readl(priv->swth_base[thread] + offset); 141 } 142 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 144 u32 offset, u32 data) 145 { 146 writel_relaxed(data, priv->swth_base[thread] + offset); 147 } 148 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 150 u32 offset) 151 { 152 return readl_relaxed(priv->swth_base[thread] + offset); 153 } 154 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 156 struct mvpp2_tx_desc *tx_desc) 157 { 158 if (port->priv->hw_version == MVPP21) 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 160 else 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 162 MVPP2_DESC_DMA_MASK; 163 } 164 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 166 struct mvpp2_tx_desc *tx_desc, 167 dma_addr_t dma_addr) 168 { 169 dma_addr_t addr, offset; 170 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 172 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 173 174 if (port->priv->hw_version == MVPP21) { 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 176 tx_desc->pp21.packet_offset = offset; 177 } else { 178 __le64 val = cpu_to_le64(addr); 179 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 181 tx_desc->pp22.buf_dma_addr_ptp |= val; 182 tx_desc->pp22.packet_offset = offset; 183 } 184 } 185 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 187 struct mvpp2_tx_desc *tx_desc) 188 { 189 if (port->priv->hw_version == MVPP21) 190 return le16_to_cpu(tx_desc->pp21.data_size); 191 else 192 return le16_to_cpu(tx_desc->pp22.data_size); 193 } 194 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 196 struct mvpp2_tx_desc *tx_desc, 197 size_t size) 198 { 199 if (port->priv->hw_version == MVPP21) 200 tx_desc->pp21.data_size = cpu_to_le16(size); 201 else 202 tx_desc->pp22.data_size = cpu_to_le16(size); 203 } 204 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 206 struct mvpp2_tx_desc *tx_desc, 207 unsigned int txq) 208 { 209 if (port->priv->hw_version == MVPP21) 210 tx_desc->pp21.phys_txq = txq; 211 else 212 tx_desc->pp22.phys_txq = txq; 213 } 214 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 216 struct mvpp2_tx_desc *tx_desc, 217 unsigned int command) 218 { 219 if (port->priv->hw_version == MVPP21) 220 tx_desc->pp21.command = cpu_to_le32(command); 221 else 222 tx_desc->pp22.command = cpu_to_le32(command); 223 } 224 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 226 struct mvpp2_tx_desc *tx_desc) 227 { 228 if (port->priv->hw_version == MVPP21) 229 return tx_desc->pp21.packet_offset; 230 else 231 return tx_desc->pp22.packet_offset; 232 } 233 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 235 struct mvpp2_rx_desc *rx_desc) 236 { 237 if (port->priv->hw_version == MVPP21) 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 239 else 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 241 MVPP2_DESC_DMA_MASK; 242 } 243 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 245 struct mvpp2_rx_desc *rx_desc) 246 { 247 if (port->priv->hw_version == MVPP21) 248 return le32_to_cpu(rx_desc->pp21.buf_cookie); 249 else 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 251 MVPP2_DESC_DMA_MASK; 252 } 253 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 255 struct mvpp2_rx_desc *rx_desc) 256 { 257 if (port->priv->hw_version == MVPP21) 258 return le16_to_cpu(rx_desc->pp21.data_size); 259 else 260 return le16_to_cpu(rx_desc->pp22.data_size); 261 } 262 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 264 struct mvpp2_rx_desc *rx_desc) 265 { 266 if (port->priv->hw_version == MVPP21) 267 return le32_to_cpu(rx_desc->pp21.status); 268 else 269 return le32_to_cpu(rx_desc->pp22.status); 270 } 271 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 273 { 274 txq_pcpu->txq_get_index++; 275 if (txq_pcpu->txq_get_index == txq_pcpu->size) 276 txq_pcpu->txq_get_index = 0; 277 } 278 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 280 struct mvpp2_txq_pcpu *txq_pcpu, 281 struct sk_buff *skb, 282 struct mvpp2_tx_desc *tx_desc) 283 { 284 struct mvpp2_txq_pcpu_buf *tx_buf = 285 txq_pcpu->buffs + txq_pcpu->txq_put_index; 286 tx_buf->skb = skb; 287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 289 mvpp2_txdesc_offset_get(port, tx_desc); 290 txq_pcpu->txq_put_index++; 291 if (txq_pcpu->txq_put_index == txq_pcpu->size) 292 txq_pcpu->txq_put_index = 0; 293 } 294 295 /* Get number of physical egress port */ 296 static inline int mvpp2_egress_port(struct mvpp2_port *port) 297 { 298 return MVPP2_MAX_TCONT + port->id; 299 } 300 301 /* Get number of physical TXQ */ 302 static inline int mvpp2_txq_phys(int port, int txq) 303 { 304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 305 } 306 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 return netdev_alloc_frag(pool->frag_size); 311 else 312 return kmalloc(pool->frag_size, GFP_ATOMIC); 313 } 314 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 316 { 317 if (likely(pool->frag_size <= PAGE_SIZE)) 318 skb_free_frag(data); 319 else 320 kfree(data); 321 } 322 323 /* Buffer Manager configuration routines */ 324 325 /* Create pool */ 326 static int mvpp2_bm_pool_create(struct platform_device *pdev, 327 struct mvpp2 *priv, 328 struct mvpp2_bm_pool *bm_pool, int size) 329 { 330 u32 val; 331 332 /* Number of buffer pointers must be a multiple of 16, as per 333 * hardware constraints 334 */ 335 if (!IS_ALIGNED(size, 16)) 336 return -EINVAL; 337 338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 339 * bytes per buffer pointer 340 */ 341 if (priv->hw_version == MVPP21) 342 bm_pool->size_bytes = 2 * sizeof(u32) * size; 343 else 344 bm_pool->size_bytes = 2 * sizeof(u64) * size; 345 346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 347 &bm_pool->dma_addr, 348 GFP_KERNEL); 349 if (!bm_pool->virt_addr) 350 return -ENOMEM; 351 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 353 MVPP2_BM_POOL_PTR_ALIGN)) { 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 355 bm_pool->virt_addr, bm_pool->dma_addr); 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 358 return -ENOMEM; 359 } 360 361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 362 lower_32_bits(bm_pool->dma_addr)); 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 364 365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 366 val |= MVPP2_BM_START_MASK; 367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 368 369 bm_pool->size = size; 370 bm_pool->pkt_size = 0; 371 bm_pool->buf_num = 0; 372 373 return 0; 374 } 375 376 /* Set pool buffer size */ 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 378 struct mvpp2_bm_pool *bm_pool, 379 int buf_size) 380 { 381 u32 val; 382 383 bm_pool->buf_size = buf_size; 384 385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 387 } 388 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 390 struct mvpp2_bm_pool *bm_pool, 391 dma_addr_t *dma_addr, 392 phys_addr_t *phys_addr) 393 { 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 395 396 *dma_addr = mvpp2_thread_read(priv, thread, 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 399 400 if (priv->hw_version == MVPP22) { 401 u32 val; 402 u32 dma_addr_highbits, phys_addr_highbits; 403 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 408 409 if (sizeof(dma_addr_t) == 8) 410 *dma_addr |= (u64)dma_addr_highbits << 32; 411 412 if (sizeof(phys_addr_t) == 8) 413 *phys_addr |= (u64)phys_addr_highbits << 32; 414 } 415 416 put_cpu(); 417 } 418 419 /* Free all buffers from the pool */ 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 421 struct mvpp2_bm_pool *bm_pool, int buf_num) 422 { 423 int i; 424 425 if (buf_num > bm_pool->buf_num) { 426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 427 bm_pool->id, buf_num); 428 buf_num = bm_pool->buf_num; 429 } 430 431 for (i = 0; i < buf_num; i++) { 432 dma_addr_t buf_dma_addr; 433 phys_addr_t buf_phys_addr; 434 void *data; 435 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 437 &buf_dma_addr, &buf_phys_addr); 438 439 dma_unmap_single(dev, buf_dma_addr, 440 bm_pool->buf_size, DMA_FROM_DEVICE); 441 442 data = (void *)phys_to_virt(buf_phys_addr); 443 if (!data) 444 break; 445 446 mvpp2_frag_free(bm_pool, data); 447 } 448 449 /* Update BM driver with number of buffers removed from pool */ 450 bm_pool->buf_num -= i; 451 } 452 453 /* Check number of buffers in BM pool */ 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 455 { 456 int buf_num = 0; 457 458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 459 MVPP22_BM_POOL_PTRS_NUM_MASK; 460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 461 MVPP2_BM_BPPI_PTR_NUM_MASK; 462 463 /* HW has one buffer ready which is not reflected in the counters */ 464 if (buf_num) 465 buf_num += 1; 466 467 return buf_num; 468 } 469 470 /* Cleanup pool */ 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 472 struct mvpp2 *priv, 473 struct mvpp2_bm_pool *bm_pool) 474 { 475 int buf_num; 476 u32 val; 477 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 480 481 /* Check buffer counters after free */ 482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 483 if (buf_num) { 484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 485 bm_pool->id, bm_pool->buf_num); 486 return 0; 487 } 488 489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 490 val |= MVPP2_BM_STOP_MASK; 491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 492 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 494 bm_pool->virt_addr, 495 bm_pool->dma_addr); 496 return 0; 497 } 498 499 static int mvpp2_bm_pools_init(struct platform_device *pdev, 500 struct mvpp2 *priv) 501 { 502 int i, err, size; 503 struct mvpp2_bm_pool *bm_pool; 504 505 /* Create all pools with maximum size */ 506 size = MVPP2_BM_POOL_SIZE_MAX; 507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 508 bm_pool = &priv->bm_pools[i]; 509 bm_pool->id = i; 510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 511 if (err) 512 goto err_unroll_pools; 513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 514 } 515 return 0; 516 517 err_unroll_pools: 518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 519 for (i = i - 1; i >= 0; i--) 520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 521 return err; 522 } 523 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 525 { 526 int i, err; 527 528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 529 /* Mask BM all interrupts */ 530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 531 /* Clear BM cause register */ 532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 533 } 534 535 /* Allocate and initialize BM pools */ 536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 537 sizeof(*priv->bm_pools), GFP_KERNEL); 538 if (!priv->bm_pools) 539 return -ENOMEM; 540 541 err = mvpp2_bm_pools_init(pdev, priv); 542 if (err < 0) 543 return err; 544 return 0; 545 } 546 547 static void mvpp2_setup_bm_pool(void) 548 { 549 /* Short pool */ 550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 552 553 /* Long pool */ 554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 556 557 /* Jumbo pool */ 558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 560 } 561 562 /* Attach long pool to rxq */ 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 564 int lrxq, int long_pool) 565 { 566 u32 val, mask; 567 int prxq; 568 569 /* Get queue physical ID */ 570 prxq = port->rxqs[lrxq]->id; 571 572 if (port->priv->hw_version == MVPP21) 573 mask = MVPP21_RXQ_POOL_LONG_MASK; 574 else 575 mask = MVPP22_RXQ_POOL_LONG_MASK; 576 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 578 val &= ~mask; 579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 581 } 582 583 /* Attach short pool to rxq */ 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 585 int lrxq, int short_pool) 586 { 587 u32 val, mask; 588 int prxq; 589 590 /* Get queue physical ID */ 591 prxq = port->rxqs[lrxq]->id; 592 593 if (port->priv->hw_version == MVPP21) 594 mask = MVPP21_RXQ_POOL_SHORT_MASK; 595 else 596 mask = MVPP22_RXQ_POOL_SHORT_MASK; 597 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 599 val &= ~mask; 600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 602 } 603 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 605 struct mvpp2_bm_pool *bm_pool, 606 dma_addr_t *buf_dma_addr, 607 phys_addr_t *buf_phys_addr, 608 gfp_t gfp_mask) 609 { 610 dma_addr_t dma_addr; 611 void *data; 612 613 data = mvpp2_frag_alloc(bm_pool); 614 if (!data) 615 return NULL; 616 617 dma_addr = dma_map_single(port->dev->dev.parent, data, 618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 619 DMA_FROM_DEVICE); 620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 621 mvpp2_frag_free(bm_pool, data); 622 return NULL; 623 } 624 *buf_dma_addr = dma_addr; 625 *buf_phys_addr = virt_to_phys(data); 626 627 return data; 628 } 629 630 /* Release buffer to BM */ 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 632 dma_addr_t buf_dma_addr, 633 phys_addr_t buf_phys_addr) 634 { 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 636 unsigned long flags = 0; 637 638 if (test_bit(thread, &port->priv->lock_map)) 639 spin_lock_irqsave(&port->bm_lock[thread], flags); 640 641 if (port->priv->hw_version == MVPP22) { 642 u32 val = 0; 643 644 if (sizeof(dma_addr_t) == 8) 645 val |= upper_32_bits(buf_dma_addr) & 646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 647 648 if (sizeof(phys_addr_t) == 8) 649 val |= (upper_32_bits(buf_phys_addr) 650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 652 653 mvpp2_thread_write_relaxed(port->priv, thread, 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 655 } 656 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 658 * returned in the "cookie" field of the RX 659 * descriptor. Instead of storing the virtual address, we 660 * store the physical address 661 */ 662 mvpp2_thread_write_relaxed(port->priv, thread, 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 664 mvpp2_thread_write_relaxed(port->priv, thread, 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 666 667 if (test_bit(thread, &port->priv->lock_map)) 668 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 669 670 put_cpu(); 671 } 672 673 /* Allocate buffers for the pool */ 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 675 struct mvpp2_bm_pool *bm_pool, int buf_num) 676 { 677 int i, buf_size, total_size; 678 dma_addr_t dma_addr; 679 phys_addr_t phys_addr; 680 void *buf; 681 682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 684 685 if (buf_num < 0 || 686 (buf_num + bm_pool->buf_num > bm_pool->size)) { 687 netdev_err(port->dev, 688 "cannot allocate %d buffers for pool %d\n", 689 buf_num, bm_pool->id); 690 return 0; 691 } 692 693 for (i = 0; i < buf_num; i++) { 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 695 &phys_addr, GFP_KERNEL); 696 if (!buf) 697 break; 698 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 700 phys_addr); 701 } 702 703 /* Update BM driver with number of buffers added to pool */ 704 bm_pool->buf_num += i; 705 706 netdev_dbg(port->dev, 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 709 710 netdev_dbg(port->dev, 711 "pool %d: %d of %d buffers added\n", 712 bm_pool->id, i, buf_num); 713 return i; 714 } 715 716 /* Notify the driver that BM pool is being used as specific type and return the 717 * pool pointer on success 718 */ 719 static struct mvpp2_bm_pool * 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 721 { 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 723 int num; 724 725 if (pool >= MVPP2_BM_POOLS_NUM) { 726 netdev_err(port->dev, "Invalid pool %d\n", pool); 727 return NULL; 728 } 729 730 /* Allocate buffers in case BM pool is used as long pool, but packet 731 * size doesn't match MTU or BM pool hasn't being used yet 732 */ 733 if (new_pool->pkt_size == 0) { 734 int pkts_num; 735 736 /* Set default buffer number or free all the buffers in case 737 * the pool is not empty 738 */ 739 pkts_num = new_pool->buf_num; 740 if (pkts_num == 0) 741 pkts_num = mvpp2_pools[pool].buf_num; 742 else 743 mvpp2_bm_bufs_free(port->dev->dev.parent, 744 port->priv, new_pool, pkts_num); 745 746 new_pool->pkt_size = pkt_size; 747 new_pool->frag_size = 748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 749 MVPP2_SKB_SHINFO_SIZE; 750 751 /* Allocate buffers for this pool */ 752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 753 if (num != pkts_num) { 754 WARN(1, "pool %d: %d of %d allocated\n", 755 new_pool->id, num, pkts_num); 756 return NULL; 757 } 758 } 759 760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 762 763 return new_pool; 764 } 765 766 /* Initialize pools for swf */ 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 768 { 769 int rxq; 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 771 772 /* If port pkt_size is higher than 1518B: 773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 775 */ 776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 777 long_log_pool = MVPP2_BM_JUMBO; 778 short_log_pool = MVPP2_BM_LONG; 779 } else { 780 long_log_pool = MVPP2_BM_LONG; 781 short_log_pool = MVPP2_BM_SHORT; 782 } 783 784 if (!port->pool_long) { 785 port->pool_long = 786 mvpp2_bm_pool_use(port, long_log_pool, 787 mvpp2_pools[long_log_pool].pkt_size); 788 if (!port->pool_long) 789 return -ENOMEM; 790 791 port->pool_long->port_map |= BIT(port->id); 792 793 for (rxq = 0; rxq < port->nrxqs; rxq++) 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 795 } 796 797 if (!port->pool_short) { 798 port->pool_short = 799 mvpp2_bm_pool_use(port, short_log_pool, 800 mvpp2_pools[short_log_pool].pkt_size); 801 if (!port->pool_short) 802 return -ENOMEM; 803 804 port->pool_short->port_map |= BIT(port->id); 805 806 for (rxq = 0; rxq < port->nrxqs; rxq++) 807 mvpp2_rxq_short_pool_set(port, rxq, 808 port->pool_short->id); 809 } 810 811 return 0; 812 } 813 814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 815 { 816 struct mvpp2_port *port = netdev_priv(dev); 817 enum mvpp2_bm_pool_log_num new_long_pool; 818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 819 820 /* If port MTU is higher than 1518B: 821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 823 */ 824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 825 new_long_pool = MVPP2_BM_JUMBO; 826 else 827 new_long_pool = MVPP2_BM_LONG; 828 829 if (new_long_pool != port->pool_long->id) { 830 /* Remove port from old short & long pool */ 831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 832 port->pool_long->pkt_size); 833 port->pool_long->port_map &= ~BIT(port->id); 834 port->pool_long = NULL; 835 836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 837 port->pool_short->pkt_size); 838 port->pool_short->port_map &= ~BIT(port->id); 839 port->pool_short = NULL; 840 841 port->pkt_size = pkt_size; 842 843 /* Add port to new short & long pool */ 844 mvpp2_swf_bm_pool_init(port); 845 846 /* Update L4 checksum when jumbo enable/disable on port */ 847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 849 dev->hw_features &= ~(NETIF_F_IP_CSUM | 850 NETIF_F_IPV6_CSUM); 851 } else { 852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 854 } 855 } 856 857 dev->mtu = mtu; 858 dev->wanted_features = dev->features; 859 860 netdev_update_features(dev); 861 return 0; 862 } 863 864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 865 { 866 int i, sw_thread_mask = 0; 867 868 for (i = 0; i < port->nqvecs; i++) 869 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 870 871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 873 } 874 875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 876 { 877 int i, sw_thread_mask = 0; 878 879 for (i = 0; i < port->nqvecs; i++) 880 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 881 882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 884 } 885 886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 887 { 888 struct mvpp2_port *port = qvec->port; 889 890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 892 } 893 894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 895 { 896 struct mvpp2_port *port = qvec->port; 897 898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 900 } 901 902 /* Mask the current thread's Rx/Tx interrupts 903 * Called by on_each_cpu(), guaranteed to run with migration disabled, 904 * using smp_processor_id() is OK. 905 */ 906 static void mvpp2_interrupts_mask(void *arg) 907 { 908 struct mvpp2_port *port = arg; 909 910 /* If the thread isn't used, don't do anything */ 911 if (smp_processor_id() > port->priv->nthreads) 912 return; 913 914 mvpp2_thread_write(port->priv, 915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 917 } 918 919 /* Unmask the current thread's Rx/Tx interrupts. 920 * Called by on_each_cpu(), guaranteed to run with migration disabled, 921 * using smp_processor_id() is OK. 922 */ 923 static void mvpp2_interrupts_unmask(void *arg) 924 { 925 struct mvpp2_port *port = arg; 926 u32 val; 927 928 /* If the thread isn't used, don't do anything */ 929 if (smp_processor_id() > port->priv->nthreads) 930 return; 931 932 val = MVPP2_CAUSE_MISC_SUM_MASK | 933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 934 if (port->has_tx_irqs) 935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 936 937 mvpp2_thread_write(port->priv, 938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 940 } 941 942 static void 943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 944 { 945 u32 val; 946 int i; 947 948 if (port->priv->hw_version != MVPP22) 949 return; 950 951 if (mask) 952 val = 0; 953 else 954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 955 956 for (i = 0; i < port->nqvecs; i++) { 957 struct mvpp2_queue_vector *v = port->qvecs + i; 958 959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 960 continue; 961 962 mvpp2_thread_write(port->priv, v->sw_thread_id, 963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 964 } 965 } 966 967 /* Port configuration routines */ 968 static bool mvpp2_is_xlg(phy_interface_t interface) 969 { 970 return interface == PHY_INTERFACE_MODE_10GKR || 971 interface == PHY_INTERFACE_MODE_XAUI; 972 } 973 974 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 975 { 976 struct mvpp2 *priv = port->priv; 977 u32 val; 978 979 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 980 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 981 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 982 983 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 984 if (port->gop_id == 2) 985 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 986 else if (port->gop_id == 3) 987 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 988 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 989 } 990 991 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 992 { 993 struct mvpp2 *priv = port->priv; 994 u32 val; 995 996 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 997 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 998 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 999 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1000 1001 if (port->gop_id > 1) { 1002 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1003 if (port->gop_id == 2) 1004 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1005 else if (port->gop_id == 3) 1006 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1007 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1008 } 1009 } 1010 1011 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1012 { 1013 struct mvpp2 *priv = port->priv; 1014 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1015 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1016 u32 val; 1017 1018 /* XPCS */ 1019 val = readl(xpcs + MVPP22_XPCS_CFG0); 1020 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1021 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1022 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1023 writel(val, xpcs + MVPP22_XPCS_CFG0); 1024 1025 /* MPCS */ 1026 val = readl(mpcs + MVPP22_MPCS_CTRL); 1027 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1028 writel(val, mpcs + MVPP22_MPCS_CTRL); 1029 1030 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1031 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | 1032 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1033 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1034 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1035 1036 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1037 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; 1038 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1039 } 1040 1041 static int mvpp22_gop_init(struct mvpp2_port *port) 1042 { 1043 struct mvpp2 *priv = port->priv; 1044 u32 val; 1045 1046 if (!priv->sysctrl_base) 1047 return 0; 1048 1049 switch (port->phy_interface) { 1050 case PHY_INTERFACE_MODE_RGMII: 1051 case PHY_INTERFACE_MODE_RGMII_ID: 1052 case PHY_INTERFACE_MODE_RGMII_RXID: 1053 case PHY_INTERFACE_MODE_RGMII_TXID: 1054 if (port->gop_id == 0) 1055 goto invalid_conf; 1056 mvpp22_gop_init_rgmii(port); 1057 break; 1058 case PHY_INTERFACE_MODE_SGMII: 1059 case PHY_INTERFACE_MODE_1000BASEX: 1060 case PHY_INTERFACE_MODE_2500BASEX: 1061 mvpp22_gop_init_sgmii(port); 1062 break; 1063 case PHY_INTERFACE_MODE_10GKR: 1064 if (port->gop_id != 0) 1065 goto invalid_conf; 1066 mvpp22_gop_init_10gkr(port); 1067 break; 1068 default: 1069 goto unsupported_conf; 1070 } 1071 1072 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1073 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1074 GENCONF_PORT_CTRL1_EN(port->gop_id); 1075 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1076 1077 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1078 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1079 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1080 1081 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1082 val |= GENCONF_SOFT_RESET1_GOP; 1083 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1084 1085 unsupported_conf: 1086 return 0; 1087 1088 invalid_conf: 1089 netdev_err(port->dev, "Invalid port configuration\n"); 1090 return -EINVAL; 1091 } 1092 1093 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1094 { 1095 u32 val; 1096 1097 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1098 phy_interface_mode_is_8023z(port->phy_interface) || 1099 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1100 /* Enable the GMAC link status irq for this port */ 1101 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1102 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1103 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1104 } 1105 1106 if (port->gop_id == 0) { 1107 /* Enable the XLG/GIG irqs for this port */ 1108 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1109 if (mvpp2_is_xlg(port->phy_interface)) 1110 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1111 else 1112 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1113 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1114 } 1115 } 1116 1117 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1118 { 1119 u32 val; 1120 1121 if (port->gop_id == 0) { 1122 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1123 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1124 MVPP22_XLG_EXT_INT_MASK_GIG); 1125 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1126 } 1127 1128 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1129 phy_interface_mode_is_8023z(port->phy_interface) || 1130 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1131 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1132 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1133 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1134 } 1135 } 1136 1137 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1138 { 1139 u32 val; 1140 1141 if (port->phylink || 1142 phy_interface_mode_is_rgmii(port->phy_interface) || 1143 phy_interface_mode_is_8023z(port->phy_interface) || 1144 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1145 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1146 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1147 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1148 } 1149 1150 if (port->gop_id == 0) { 1151 val = readl(port->base + MVPP22_XLG_INT_MASK); 1152 val |= MVPP22_XLG_INT_MASK_LINK; 1153 writel(val, port->base + MVPP22_XLG_INT_MASK); 1154 } 1155 1156 mvpp22_gop_unmask_irq(port); 1157 } 1158 1159 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1160 * 1161 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1162 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1163 * differ. 1164 * 1165 * The COMPHY configures the serdes lanes regardless of the actual use of the 1166 * lanes by the physical layer. This is why configurations like 1167 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1168 */ 1169 static int mvpp22_comphy_init(struct mvpp2_port *port) 1170 { 1171 int ret; 1172 1173 if (!port->comphy) 1174 return 0; 1175 1176 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1177 port->phy_interface); 1178 if (ret) 1179 return ret; 1180 1181 return phy_power_on(port->comphy); 1182 } 1183 1184 static void mvpp2_port_enable(struct mvpp2_port *port) 1185 { 1186 u32 val; 1187 1188 /* Only GOP port 0 has an XLG MAC */ 1189 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1190 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1191 val |= MVPP22_XLG_CTRL0_PORT_EN | 1192 MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1193 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1194 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1195 } else { 1196 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1197 val |= MVPP2_GMAC_PORT_EN_MASK; 1198 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1199 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1200 } 1201 } 1202 1203 static void mvpp2_port_disable(struct mvpp2_port *port) 1204 { 1205 u32 val; 1206 1207 /* Only GOP port 0 has an XLG MAC */ 1208 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1209 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1210 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1211 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1212 1213 /* Disable & reset should be done separately */ 1214 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1215 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1216 } else { 1217 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1218 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1219 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1220 } 1221 } 1222 1223 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1224 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1225 { 1226 u32 val; 1227 1228 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1229 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1230 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1231 } 1232 1233 /* Configure loopback port */ 1234 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1235 const struct phylink_link_state *state) 1236 { 1237 u32 val; 1238 1239 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1240 1241 if (state->speed == 1000) 1242 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1243 else 1244 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1245 1246 if (phy_interface_mode_is_8023z(port->phy_interface) || 1247 port->phy_interface == PHY_INTERFACE_MODE_SGMII) 1248 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1249 else 1250 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1251 1252 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1253 } 1254 1255 struct mvpp2_ethtool_counter { 1256 unsigned int offset; 1257 const char string[ETH_GSTRING_LEN]; 1258 bool reg_is_64b; 1259 }; 1260 1261 static u64 mvpp2_read_count(struct mvpp2_port *port, 1262 const struct mvpp2_ethtool_counter *counter) 1263 { 1264 u64 val; 1265 1266 val = readl(port->stats_base + counter->offset); 1267 if (counter->reg_is_64b) 1268 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1269 1270 return val; 1271 } 1272 1273 /* Due to the fact that software statistics and hardware statistics are, by 1274 * design, incremented at different moments in the chain of packet processing, 1275 * it is very likely that incoming packets could have been dropped after being 1276 * counted by hardware but before reaching software statistics (most probably 1277 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1278 * are added in between as well as TSO skb will be split and header bytes added. 1279 * Hence, statistics gathered from userspace with ifconfig (software) and 1280 * ethtool (hardware) cannot be compared. 1281 */ 1282 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { 1283 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1284 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1285 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1286 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1287 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1288 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1289 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1290 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1291 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1292 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1293 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1294 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1295 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1296 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1297 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1298 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1299 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1300 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1301 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1302 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1303 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1304 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1305 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1306 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1307 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1308 { MVPP2_MIB_COLLISION, "collision" }, 1309 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1310 }; 1311 1312 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1313 u8 *data) 1314 { 1315 if (sset == ETH_SS_STATS) { 1316 int i; 1317 1318 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1319 memcpy(data + i * ETH_GSTRING_LEN, 1320 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); 1321 } 1322 } 1323 1324 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1325 { 1326 struct delayed_work *del_work = to_delayed_work(work); 1327 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1328 stats_work); 1329 u64 *pstats; 1330 int i; 1331 1332 mutex_lock(&port->gather_stats_lock); 1333 1334 pstats = port->ethtool_stats; 1335 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1336 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1337 1338 /* No need to read again the counters right after this function if it 1339 * was called asynchronously by the user (ie. use of ethtool). 1340 */ 1341 cancel_delayed_work(&port->stats_work); 1342 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1343 MVPP2_MIB_COUNTERS_STATS_DELAY); 1344 1345 mutex_unlock(&port->gather_stats_lock); 1346 } 1347 1348 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1349 struct ethtool_stats *stats, u64 *data) 1350 { 1351 struct mvpp2_port *port = netdev_priv(dev); 1352 1353 /* Update statistics for the given port, then take the lock to avoid 1354 * concurrent accesses on the ethtool_stats structure during its copy. 1355 */ 1356 mvpp2_gather_hw_statistics(&port->stats_work.work); 1357 1358 mutex_lock(&port->gather_stats_lock); 1359 memcpy(data, port->ethtool_stats, 1360 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); 1361 mutex_unlock(&port->gather_stats_lock); 1362 } 1363 1364 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1365 { 1366 if (sset == ETH_SS_STATS) 1367 return ARRAY_SIZE(mvpp2_ethtool_regs); 1368 1369 return -EOPNOTSUPP; 1370 } 1371 1372 static void mvpp2_port_reset(struct mvpp2_port *port) 1373 { 1374 u32 val; 1375 unsigned int i; 1376 1377 /* Read the GOP statistics to reset the hardware counters */ 1378 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1379 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1380 1381 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1382 MVPP2_GMAC_PORT_RESET_MASK; 1383 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1384 } 1385 1386 /* Change maximum receive size of the port */ 1387 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1388 { 1389 u32 val; 1390 1391 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1392 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1393 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1394 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1395 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1396 } 1397 1398 /* Change maximum receive size of the port */ 1399 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1400 { 1401 u32 val; 1402 1403 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1404 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1405 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1406 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1407 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1408 } 1409 1410 /* Set defaults to the MVPP2 port */ 1411 static void mvpp2_defaults_set(struct mvpp2_port *port) 1412 { 1413 int tx_port_num, val, queue, ptxq, lrxq; 1414 1415 if (port->priv->hw_version == MVPP21) { 1416 /* Update TX FIFO MIN Threshold */ 1417 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1418 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1419 /* Min. TX threshold must be less than minimal packet length */ 1420 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1421 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1422 } 1423 1424 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1425 tx_port_num = mvpp2_egress_port(port); 1426 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1427 tx_port_num); 1428 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1429 1430 /* Set TXQ scheduling to Round-Robin */ 1431 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1432 1433 /* Close bandwidth for all queues */ 1434 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { 1435 ptxq = mvpp2_txq_phys(port->id, queue); 1436 mvpp2_write(port->priv, 1437 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); 1438 } 1439 1440 /* Set refill period to 1 usec, refill tokens 1441 * and bucket size to maximum 1442 */ 1443 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1444 port->priv->tclk / USEC_PER_SEC); 1445 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1446 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1447 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1448 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1449 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1450 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1451 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1452 1453 /* Set MaximumLowLatencyPacketSize value to 256 */ 1454 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1455 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1456 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1457 1458 /* Enable Rx cache snoop */ 1459 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1460 queue = port->rxqs[lrxq]->id; 1461 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1462 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1463 MVPP2_SNOOP_BUF_HDR_MASK; 1464 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1465 } 1466 1467 /* At default, mask all interrupts to all present cpus */ 1468 mvpp2_interrupts_disable(port); 1469 } 1470 1471 /* Enable/disable receiving packets */ 1472 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1473 { 1474 u32 val; 1475 int lrxq, queue; 1476 1477 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1478 queue = port->rxqs[lrxq]->id; 1479 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1480 val &= ~MVPP2_RXQ_DISABLE_MASK; 1481 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1482 } 1483 } 1484 1485 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1486 { 1487 u32 val; 1488 int lrxq, queue; 1489 1490 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1491 queue = port->rxqs[lrxq]->id; 1492 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1493 val |= MVPP2_RXQ_DISABLE_MASK; 1494 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1495 } 1496 } 1497 1498 /* Enable transmit via physical egress queue 1499 * - HW starts take descriptors from DRAM 1500 */ 1501 static void mvpp2_egress_enable(struct mvpp2_port *port) 1502 { 1503 u32 qmap; 1504 int queue; 1505 int tx_port_num = mvpp2_egress_port(port); 1506 1507 /* Enable all initialized TXs. */ 1508 qmap = 0; 1509 for (queue = 0; queue < port->ntxqs; queue++) { 1510 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1511 1512 if (txq->descs) 1513 qmap |= (1 << queue); 1514 } 1515 1516 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1517 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1518 } 1519 1520 /* Disable transmit via physical egress queue 1521 * - HW doesn't take descriptors from DRAM 1522 */ 1523 static void mvpp2_egress_disable(struct mvpp2_port *port) 1524 { 1525 u32 reg_data; 1526 int delay; 1527 int tx_port_num = mvpp2_egress_port(port); 1528 1529 /* Issue stop command for active channels only */ 1530 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1531 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1532 MVPP2_TXP_SCHED_ENQ_MASK; 1533 if (reg_data != 0) 1534 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1535 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1536 1537 /* Wait for all Tx activity to terminate. */ 1538 delay = 0; 1539 do { 1540 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1541 netdev_warn(port->dev, 1542 "Tx stop timed out, status=0x%08x\n", 1543 reg_data); 1544 break; 1545 } 1546 mdelay(1); 1547 delay++; 1548 1549 /* Check port TX Command register that all 1550 * Tx queues are stopped 1551 */ 1552 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1553 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1554 } 1555 1556 /* Rx descriptors helper methods */ 1557 1558 /* Get number of Rx descriptors occupied by received packets */ 1559 static inline int 1560 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1561 { 1562 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1563 1564 return val & MVPP2_RXQ_OCCUPIED_MASK; 1565 } 1566 1567 /* Update Rx queue status with the number of occupied and available 1568 * Rx descriptor slots. 1569 */ 1570 static inline void 1571 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1572 int used_count, int free_count) 1573 { 1574 /* Decrement the number of used descriptors and increment count 1575 * increment the number of free descriptors. 1576 */ 1577 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1578 1579 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1580 } 1581 1582 /* Get pointer to next RX descriptor to be processed by SW */ 1583 static inline struct mvpp2_rx_desc * 1584 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1585 { 1586 int rx_desc = rxq->next_desc_to_proc; 1587 1588 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1589 prefetch(rxq->descs + rxq->next_desc_to_proc); 1590 return rxq->descs + rx_desc; 1591 } 1592 1593 /* Set rx queue offset */ 1594 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1595 int prxq, int offset) 1596 { 1597 u32 val; 1598 1599 /* Convert offset from bytes to units of 32 bytes */ 1600 offset = offset >> 5; 1601 1602 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1603 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1604 1605 /* Offset is in */ 1606 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1607 MVPP2_RXQ_PACKET_OFFSET_MASK); 1608 1609 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1610 } 1611 1612 /* Tx descriptors helper methods */ 1613 1614 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1615 static struct mvpp2_tx_desc * 1616 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1617 { 1618 int tx_desc = txq->next_desc_to_proc; 1619 1620 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1621 return txq->descs + tx_desc; 1622 } 1623 1624 /* Update HW with number of aggregated Tx descriptors to be sent 1625 * 1626 * Called only from mvpp2_tx(), so migration is disabled, using 1627 * smp_processor_id() is OK. 1628 */ 1629 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1630 { 1631 /* aggregated access - relevant TXQ number is written in TX desc */ 1632 mvpp2_thread_write(port->priv, 1633 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1634 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1635 } 1636 1637 /* Check if there are enough free descriptors in aggregated txq. 1638 * If not, update the number of occupied descriptors and repeat the check. 1639 * 1640 * Called only from mvpp2_tx(), so migration is disabled, using 1641 * smp_processor_id() is OK. 1642 */ 1643 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 1644 struct mvpp2_tx_queue *aggr_txq, int num) 1645 { 1646 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1647 /* Update number of occupied aggregated Tx descriptors */ 1648 unsigned int thread = 1649 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1650 u32 val = mvpp2_read_relaxed(port->priv, 1651 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 1652 1653 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1654 1655 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1656 return -ENOMEM; 1657 } 1658 return 0; 1659 } 1660 1661 /* Reserved Tx descriptors allocation request 1662 * 1663 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1664 * only by mvpp2_tx(), so migration is disabled, using 1665 * smp_processor_id() is OK. 1666 */ 1667 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 1668 struct mvpp2_tx_queue *txq, int num) 1669 { 1670 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1671 struct mvpp2 *priv = port->priv; 1672 u32 val; 1673 1674 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1675 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 1676 1677 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 1678 1679 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1680 } 1681 1682 /* Check if there are enough reserved descriptors for transmission. 1683 * If not, request chunk of reserved descriptors and check again. 1684 */ 1685 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 1686 struct mvpp2_tx_queue *txq, 1687 struct mvpp2_txq_pcpu *txq_pcpu, 1688 int num) 1689 { 1690 int req, desc_count; 1691 unsigned int thread; 1692 1693 if (txq_pcpu->reserved_num >= num) 1694 return 0; 1695 1696 /* Not enough descriptors reserved! Update the reserved descriptor 1697 * count and check again. 1698 */ 1699 1700 desc_count = 0; 1701 /* Compute total of used descriptors */ 1702 for (thread = 0; thread < port->priv->nthreads; thread++) { 1703 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1704 1705 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 1706 desc_count += txq_pcpu_aux->count; 1707 desc_count += txq_pcpu_aux->reserved_num; 1708 } 1709 1710 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1711 desc_count += req; 1712 1713 if (desc_count > 1714 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 1715 return -ENOMEM; 1716 1717 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 1718 1719 /* OK, the descriptor could have been updated: check again. */ 1720 if (txq_pcpu->reserved_num < num) 1721 return -ENOMEM; 1722 return 0; 1723 } 1724 1725 /* Release the last allocated Tx descriptor. Useful to handle DMA 1726 * mapping failures in the Tx path. 1727 */ 1728 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1729 { 1730 if (txq->next_desc_to_proc == 0) 1731 txq->next_desc_to_proc = txq->last_desc - 1; 1732 else 1733 txq->next_desc_to_proc--; 1734 } 1735 1736 /* Set Tx descriptors fields relevant for CSUM calculation */ 1737 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 1738 int ip_hdr_len, int l4_proto) 1739 { 1740 u32 command; 1741 1742 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1743 * G_L4_chk, L4_type required only for checksum calculation 1744 */ 1745 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1746 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1747 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1748 1749 if (l3_proto == htons(ETH_P_IP)) { 1750 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1751 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1752 } else { 1753 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1754 } 1755 1756 if (l4_proto == IPPROTO_TCP) { 1757 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1758 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1759 } else if (l4_proto == IPPROTO_UDP) { 1760 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1761 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1762 } else { 1763 command |= MVPP2_TXD_L4_CSUM_NOT; 1764 } 1765 1766 return command; 1767 } 1768 1769 /* Get number of sent descriptors and decrement counter. 1770 * The number of sent descriptors is returned. 1771 * Per-thread access 1772 * 1773 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1774 * (migration disabled) and from the TX completion tasklet (migration 1775 * disabled) so using smp_processor_id() is OK. 1776 */ 1777 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1778 struct mvpp2_tx_queue *txq) 1779 { 1780 u32 val; 1781 1782 /* Reading status reg resets transmitted descriptor counter */ 1783 val = mvpp2_thread_read_relaxed(port->priv, 1784 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1785 MVPP2_TXQ_SENT_REG(txq->id)); 1786 1787 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1788 MVPP2_TRANSMITTED_COUNT_OFFSET; 1789 } 1790 1791 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1792 * disabled, therefore using smp_processor_id() is OK. 1793 */ 1794 static void mvpp2_txq_sent_counter_clear(void *arg) 1795 { 1796 struct mvpp2_port *port = arg; 1797 int queue; 1798 1799 /* If the thread isn't used, don't do anything */ 1800 if (smp_processor_id() > port->priv->nthreads) 1801 return; 1802 1803 for (queue = 0; queue < port->ntxqs; queue++) { 1804 int id = port->txqs[queue]->id; 1805 1806 mvpp2_thread_read(port->priv, 1807 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1808 MVPP2_TXQ_SENT_REG(id)); 1809 } 1810 } 1811 1812 /* Set max sizes for Tx queues */ 1813 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1814 { 1815 u32 val, size, mtu; 1816 int txq, tx_port_num; 1817 1818 mtu = port->pkt_size * 8; 1819 if (mtu > MVPP2_TXP_MTU_MAX) 1820 mtu = MVPP2_TXP_MTU_MAX; 1821 1822 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1823 mtu = 3 * mtu; 1824 1825 /* Indirect access to registers */ 1826 tx_port_num = mvpp2_egress_port(port); 1827 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1828 1829 /* Set MTU */ 1830 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1831 val &= ~MVPP2_TXP_MTU_MAX; 1832 val |= mtu; 1833 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1834 1835 /* TXP token size and all TXQs token size must be larger that MTU */ 1836 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1837 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1838 if (size < mtu) { 1839 size = mtu; 1840 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1841 val |= size; 1842 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1843 } 1844 1845 for (txq = 0; txq < port->ntxqs; txq++) { 1846 val = mvpp2_read(port->priv, 1847 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1848 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1849 1850 if (size < mtu) { 1851 size = mtu; 1852 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1853 val |= size; 1854 mvpp2_write(port->priv, 1855 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1856 val); 1857 } 1858 } 1859 } 1860 1861 /* Set the number of packets that will be received before Rx interrupt 1862 * will be generated by HW. 1863 */ 1864 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1865 struct mvpp2_rx_queue *rxq) 1866 { 1867 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1868 1869 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 1870 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 1871 1872 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 1873 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 1874 rxq->pkts_coal); 1875 1876 put_cpu(); 1877 } 1878 1879 /* For some reason in the LSP this is done on each CPU. Why ? */ 1880 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 1881 struct mvpp2_tx_queue *txq) 1882 { 1883 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1884 u32 val; 1885 1886 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 1887 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 1888 1889 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 1890 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 1891 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 1892 1893 put_cpu(); 1894 } 1895 1896 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 1897 { 1898 u64 tmp = (u64)clk_hz * usec; 1899 1900 do_div(tmp, USEC_PER_SEC); 1901 1902 return tmp > U32_MAX ? U32_MAX : tmp; 1903 } 1904 1905 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 1906 { 1907 u64 tmp = (u64)cycles * USEC_PER_SEC; 1908 1909 do_div(tmp, clk_hz); 1910 1911 return tmp > U32_MAX ? U32_MAX : tmp; 1912 } 1913 1914 /* Set the time delay in usec before Rx interrupt */ 1915 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 1916 struct mvpp2_rx_queue *rxq) 1917 { 1918 unsigned long freq = port->priv->tclk; 1919 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1920 1921 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 1922 rxq->time_coal = 1923 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 1924 1925 /* re-evaluate to get actual register value */ 1926 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1927 } 1928 1929 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 1930 } 1931 1932 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 1933 { 1934 unsigned long freq = port->priv->tclk; 1935 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1936 1937 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 1938 port->tx_time_coal = 1939 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 1940 1941 /* re-evaluate to get actual register value */ 1942 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1943 } 1944 1945 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 1946 } 1947 1948 /* Free Tx queue skbuffs */ 1949 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 1950 struct mvpp2_tx_queue *txq, 1951 struct mvpp2_txq_pcpu *txq_pcpu, int num) 1952 { 1953 int i; 1954 1955 for (i = 0; i < num; i++) { 1956 struct mvpp2_txq_pcpu_buf *tx_buf = 1957 txq_pcpu->buffs + txq_pcpu->txq_get_index; 1958 1959 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 1960 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 1961 tx_buf->size, DMA_TO_DEVICE); 1962 if (tx_buf->skb) 1963 dev_kfree_skb_any(tx_buf->skb); 1964 1965 mvpp2_txq_inc_get(txq_pcpu); 1966 } 1967 } 1968 1969 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 1970 u32 cause) 1971 { 1972 int queue = fls(cause) - 1; 1973 1974 return port->rxqs[queue]; 1975 } 1976 1977 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 1978 u32 cause) 1979 { 1980 int queue = fls(cause) - 1; 1981 1982 return port->txqs[queue]; 1983 } 1984 1985 /* Handle end of transmission */ 1986 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 1987 struct mvpp2_txq_pcpu *txq_pcpu) 1988 { 1989 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 1990 int tx_done; 1991 1992 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 1993 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 1994 1995 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 1996 if (!tx_done) 1997 return; 1998 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 1999 2000 txq_pcpu->count -= tx_done; 2001 2002 if (netif_tx_queue_stopped(nq)) 2003 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2004 netif_tx_wake_queue(nq); 2005 } 2006 2007 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2008 unsigned int thread) 2009 { 2010 struct mvpp2_tx_queue *txq; 2011 struct mvpp2_txq_pcpu *txq_pcpu; 2012 unsigned int tx_todo = 0; 2013 2014 while (cause) { 2015 txq = mvpp2_get_tx_queue(port, cause); 2016 if (!txq) 2017 break; 2018 2019 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2020 2021 if (txq_pcpu->count) { 2022 mvpp2_txq_done(port, txq, txq_pcpu); 2023 tx_todo += txq_pcpu->count; 2024 } 2025 2026 cause &= ~(1 << txq->log_id); 2027 } 2028 return tx_todo; 2029 } 2030 2031 /* Rx/Tx queue initialization/cleanup methods */ 2032 2033 /* Allocate and initialize descriptors for aggr TXQ */ 2034 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2035 struct mvpp2_tx_queue *aggr_txq, 2036 unsigned int thread, struct mvpp2 *priv) 2037 { 2038 u32 txq_dma; 2039 2040 /* Allocate memory for TX descriptors */ 2041 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2042 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2043 &aggr_txq->descs_dma, GFP_KERNEL); 2044 if (!aggr_txq->descs) 2045 return -ENOMEM; 2046 2047 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2048 2049 /* Aggr TXQ no reset WA */ 2050 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2051 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2052 2053 /* Set Tx descriptors queue starting address indirect 2054 * access 2055 */ 2056 if (priv->hw_version == MVPP21) 2057 txq_dma = aggr_txq->descs_dma; 2058 else 2059 txq_dma = aggr_txq->descs_dma >> 2060 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2061 2062 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2063 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2064 MVPP2_AGGR_TXQ_SIZE); 2065 2066 return 0; 2067 } 2068 2069 /* Create a specified Rx queue */ 2070 static int mvpp2_rxq_init(struct mvpp2_port *port, 2071 struct mvpp2_rx_queue *rxq) 2072 2073 { 2074 unsigned int thread; 2075 u32 rxq_dma; 2076 2077 rxq->size = port->rx_ring_size; 2078 2079 /* Allocate memory for RX descriptors */ 2080 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2081 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2082 &rxq->descs_dma, GFP_KERNEL); 2083 if (!rxq->descs) 2084 return -ENOMEM; 2085 2086 rxq->last_desc = rxq->size - 1; 2087 2088 /* Zero occupied and non-occupied counters - direct access */ 2089 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2090 2091 /* Set Rx descriptors queue starting address - indirect access */ 2092 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2093 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2094 if (port->priv->hw_version == MVPP21) 2095 rxq_dma = rxq->descs_dma; 2096 else 2097 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2098 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2099 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2100 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2101 put_cpu(); 2102 2103 /* Set Offset */ 2104 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2105 2106 /* Set coalescing pkts and time */ 2107 mvpp2_rx_pkts_coal_set(port, rxq); 2108 mvpp2_rx_time_coal_set(port, rxq); 2109 2110 /* Add number of descriptors ready for receiving packets */ 2111 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2112 2113 return 0; 2114 } 2115 2116 /* Push packets received by the RXQ to BM pool */ 2117 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2118 struct mvpp2_rx_queue *rxq) 2119 { 2120 int rx_received, i; 2121 2122 rx_received = mvpp2_rxq_received(port, rxq->id); 2123 if (!rx_received) 2124 return; 2125 2126 for (i = 0; i < rx_received; i++) { 2127 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2128 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2129 int pool; 2130 2131 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2132 MVPP2_RXD_BM_POOL_ID_OFFS; 2133 2134 mvpp2_bm_pool_put(port, pool, 2135 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2136 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2137 } 2138 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2139 } 2140 2141 /* Cleanup Rx queue */ 2142 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2143 struct mvpp2_rx_queue *rxq) 2144 { 2145 unsigned int thread; 2146 2147 mvpp2_rxq_drop_pkts(port, rxq); 2148 2149 if (rxq->descs) 2150 dma_free_coherent(port->dev->dev.parent, 2151 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2152 rxq->descs, 2153 rxq->descs_dma); 2154 2155 rxq->descs = NULL; 2156 rxq->last_desc = 0; 2157 rxq->next_desc_to_proc = 0; 2158 rxq->descs_dma = 0; 2159 2160 /* Clear Rx descriptors queue starting address and size; 2161 * free descriptor number 2162 */ 2163 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2164 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2165 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2166 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2167 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2168 put_cpu(); 2169 } 2170 2171 /* Create and initialize a Tx queue */ 2172 static int mvpp2_txq_init(struct mvpp2_port *port, 2173 struct mvpp2_tx_queue *txq) 2174 { 2175 u32 val; 2176 unsigned int thread; 2177 int desc, desc_per_txq, tx_port_num; 2178 struct mvpp2_txq_pcpu *txq_pcpu; 2179 2180 txq->size = port->tx_ring_size; 2181 2182 /* Allocate memory for Tx descriptors */ 2183 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2184 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2185 &txq->descs_dma, GFP_KERNEL); 2186 if (!txq->descs) 2187 return -ENOMEM; 2188 2189 txq->last_desc = txq->size - 1; 2190 2191 /* Set Tx descriptors queue starting address - indirect access */ 2192 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2193 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2194 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2195 txq->descs_dma); 2196 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2197 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2198 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2199 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2200 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2201 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2202 val &= ~MVPP2_TXQ_PENDING_MASK; 2203 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2204 2205 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2206 * for each existing TXQ. 2207 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2208 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2209 */ 2210 desc_per_txq = 16; 2211 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2212 (txq->log_id * desc_per_txq); 2213 2214 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2215 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2216 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2217 put_cpu(); 2218 2219 /* WRR / EJP configuration - indirect access */ 2220 tx_port_num = mvpp2_egress_port(port); 2221 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2222 2223 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2224 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2225 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2226 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2227 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2228 2229 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2230 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2231 val); 2232 2233 for (thread = 0; thread < port->priv->nthreads; thread++) { 2234 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2235 txq_pcpu->size = txq->size; 2236 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2237 sizeof(*txq_pcpu->buffs), 2238 GFP_KERNEL); 2239 if (!txq_pcpu->buffs) 2240 return -ENOMEM; 2241 2242 txq_pcpu->count = 0; 2243 txq_pcpu->reserved_num = 0; 2244 txq_pcpu->txq_put_index = 0; 2245 txq_pcpu->txq_get_index = 0; 2246 txq_pcpu->tso_headers = NULL; 2247 2248 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2249 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2250 2251 txq_pcpu->tso_headers = 2252 dma_alloc_coherent(port->dev->dev.parent, 2253 txq_pcpu->size * TSO_HEADER_SIZE, 2254 &txq_pcpu->tso_headers_dma, 2255 GFP_KERNEL); 2256 if (!txq_pcpu->tso_headers) 2257 return -ENOMEM; 2258 } 2259 2260 return 0; 2261 } 2262 2263 /* Free allocated TXQ resources */ 2264 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2265 struct mvpp2_tx_queue *txq) 2266 { 2267 struct mvpp2_txq_pcpu *txq_pcpu; 2268 unsigned int thread; 2269 2270 for (thread = 0; thread < port->priv->nthreads; thread++) { 2271 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2272 kfree(txq_pcpu->buffs); 2273 2274 if (txq_pcpu->tso_headers) 2275 dma_free_coherent(port->dev->dev.parent, 2276 txq_pcpu->size * TSO_HEADER_SIZE, 2277 txq_pcpu->tso_headers, 2278 txq_pcpu->tso_headers_dma); 2279 2280 txq_pcpu->tso_headers = NULL; 2281 } 2282 2283 if (txq->descs) 2284 dma_free_coherent(port->dev->dev.parent, 2285 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2286 txq->descs, txq->descs_dma); 2287 2288 txq->descs = NULL; 2289 txq->last_desc = 0; 2290 txq->next_desc_to_proc = 0; 2291 txq->descs_dma = 0; 2292 2293 /* Set minimum bandwidth for disabled TXQs */ 2294 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); 2295 2296 /* Set Tx descriptors queue starting address and size */ 2297 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2298 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2299 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2300 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2301 put_cpu(); 2302 } 2303 2304 /* Cleanup Tx ports */ 2305 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2306 { 2307 struct mvpp2_txq_pcpu *txq_pcpu; 2308 int delay, pending; 2309 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2310 u32 val; 2311 2312 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2313 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2314 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2315 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2316 2317 /* The napi queue has been stopped so wait for all packets 2318 * to be transmitted. 2319 */ 2320 delay = 0; 2321 do { 2322 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2323 netdev_warn(port->dev, 2324 "port %d: cleaning queue %d timed out\n", 2325 port->id, txq->log_id); 2326 break; 2327 } 2328 mdelay(1); 2329 delay++; 2330 2331 pending = mvpp2_thread_read(port->priv, thread, 2332 MVPP2_TXQ_PENDING_REG); 2333 pending &= MVPP2_TXQ_PENDING_MASK; 2334 } while (pending); 2335 2336 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2337 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2338 put_cpu(); 2339 2340 for (thread = 0; thread < port->priv->nthreads; thread++) { 2341 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2342 2343 /* Release all packets */ 2344 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2345 2346 /* Reset queue */ 2347 txq_pcpu->count = 0; 2348 txq_pcpu->txq_put_index = 0; 2349 txq_pcpu->txq_get_index = 0; 2350 } 2351 } 2352 2353 /* Cleanup all Tx queues */ 2354 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2355 { 2356 struct mvpp2_tx_queue *txq; 2357 int queue; 2358 u32 val; 2359 2360 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2361 2362 /* Reset Tx ports and delete Tx queues */ 2363 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2364 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2365 2366 for (queue = 0; queue < port->ntxqs; queue++) { 2367 txq = port->txqs[queue]; 2368 mvpp2_txq_clean(port, txq); 2369 mvpp2_txq_deinit(port, txq); 2370 } 2371 2372 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2373 2374 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2375 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2376 } 2377 2378 /* Cleanup all Rx queues */ 2379 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2380 { 2381 int queue; 2382 2383 for (queue = 0; queue < port->nrxqs; queue++) 2384 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2385 } 2386 2387 /* Init all Rx queues for port */ 2388 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2389 { 2390 int queue, err; 2391 2392 for (queue = 0; queue < port->nrxqs; queue++) { 2393 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2394 if (err) 2395 goto err_cleanup; 2396 } 2397 return 0; 2398 2399 err_cleanup: 2400 mvpp2_cleanup_rxqs(port); 2401 return err; 2402 } 2403 2404 /* Init all tx queues for port */ 2405 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2406 { 2407 struct mvpp2_tx_queue *txq; 2408 int queue, err, cpu; 2409 2410 for (queue = 0; queue < port->ntxqs; queue++) { 2411 txq = port->txqs[queue]; 2412 err = mvpp2_txq_init(port, txq); 2413 if (err) 2414 goto err_cleanup; 2415 2416 /* Assign this queue to a CPU */ 2417 cpu = queue % num_present_cpus(); 2418 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue); 2419 } 2420 2421 if (port->has_tx_irqs) { 2422 mvpp2_tx_time_coal_set(port); 2423 for (queue = 0; queue < port->ntxqs; queue++) { 2424 txq = port->txqs[queue]; 2425 mvpp2_tx_pkts_coal_set(port, txq); 2426 } 2427 } 2428 2429 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2430 return 0; 2431 2432 err_cleanup: 2433 mvpp2_cleanup_txqs(port); 2434 return err; 2435 } 2436 2437 /* The callback for per-port interrupt */ 2438 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2439 { 2440 struct mvpp2_queue_vector *qv = dev_id; 2441 2442 mvpp2_qvec_interrupt_disable(qv); 2443 2444 napi_schedule(&qv->napi); 2445 2446 return IRQ_HANDLED; 2447 } 2448 2449 /* Per-port interrupt for link status changes */ 2450 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2451 { 2452 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2453 struct net_device *dev = port->dev; 2454 bool event = false, link = false; 2455 u32 val; 2456 2457 mvpp22_gop_mask_irq(port); 2458 2459 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 2460 val = readl(port->base + MVPP22_XLG_INT_STAT); 2461 if (val & MVPP22_XLG_INT_STAT_LINK) { 2462 event = true; 2463 val = readl(port->base + MVPP22_XLG_STATUS); 2464 if (val & MVPP22_XLG_STATUS_LINK_UP) 2465 link = true; 2466 } 2467 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2468 phy_interface_mode_is_8023z(port->phy_interface) || 2469 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 2470 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2471 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2472 event = true; 2473 val = readl(port->base + MVPP2_GMAC_STATUS0); 2474 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2475 link = true; 2476 } 2477 } 2478 2479 if (port->phylink) { 2480 phylink_mac_change(port->phylink, link); 2481 goto handled; 2482 } 2483 2484 if (!netif_running(dev) || !event) 2485 goto handled; 2486 2487 if (link) { 2488 mvpp2_interrupts_enable(port); 2489 2490 mvpp2_egress_enable(port); 2491 mvpp2_ingress_enable(port); 2492 netif_carrier_on(dev); 2493 netif_tx_wake_all_queues(dev); 2494 } else { 2495 netif_tx_stop_all_queues(dev); 2496 netif_carrier_off(dev); 2497 mvpp2_ingress_disable(port); 2498 mvpp2_egress_disable(port); 2499 2500 mvpp2_interrupts_disable(port); 2501 } 2502 2503 handled: 2504 mvpp22_gop_unmask_irq(port); 2505 return IRQ_HANDLED; 2506 } 2507 2508 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2509 { 2510 ktime_t interval; 2511 2512 if (!port_pcpu->timer_scheduled) { 2513 port_pcpu->timer_scheduled = true; 2514 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2515 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2516 HRTIMER_MODE_REL_PINNED); 2517 } 2518 } 2519 2520 static void mvpp2_tx_proc_cb(unsigned long data) 2521 { 2522 struct net_device *dev = (struct net_device *)data; 2523 struct mvpp2_port *port = netdev_priv(dev); 2524 struct mvpp2_port_pcpu *port_pcpu; 2525 unsigned int tx_todo, cause; 2526 2527 port_pcpu = per_cpu_ptr(port->pcpu, 2528 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2529 2530 if (!netif_running(dev)) 2531 return; 2532 port_pcpu->timer_scheduled = false; 2533 2534 /* Process all the Tx queues */ 2535 cause = (1 << port->ntxqs) - 1; 2536 tx_todo = mvpp2_tx_done(port, cause, 2537 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2538 2539 /* Set the timer in case not all the packets were processed */ 2540 if (tx_todo) 2541 mvpp2_timer_set(port_pcpu); 2542 } 2543 2544 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2545 { 2546 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2547 struct mvpp2_port_pcpu, 2548 tx_done_timer); 2549 2550 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2551 2552 return HRTIMER_NORESTART; 2553 } 2554 2555 /* Main RX/TX processing routines */ 2556 2557 /* Display more error info */ 2558 static void mvpp2_rx_error(struct mvpp2_port *port, 2559 struct mvpp2_rx_desc *rx_desc) 2560 { 2561 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2562 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2563 char *err_str = NULL; 2564 2565 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2566 case MVPP2_RXD_ERR_CRC: 2567 err_str = "crc"; 2568 break; 2569 case MVPP2_RXD_ERR_OVERRUN: 2570 err_str = "overrun"; 2571 break; 2572 case MVPP2_RXD_ERR_RESOURCE: 2573 err_str = "resource"; 2574 break; 2575 } 2576 if (err_str && net_ratelimit()) 2577 netdev_err(port->dev, 2578 "bad rx status %08x (%s error), size=%zu\n", 2579 status, err_str, sz); 2580 } 2581 2582 /* Handle RX checksum offload */ 2583 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2584 struct sk_buff *skb) 2585 { 2586 if (((status & MVPP2_RXD_L3_IP4) && 2587 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2588 (status & MVPP2_RXD_L3_IP6)) 2589 if (((status & MVPP2_RXD_L4_UDP) || 2590 (status & MVPP2_RXD_L4_TCP)) && 2591 (status & MVPP2_RXD_L4_CSUM_OK)) { 2592 skb->csum = 0; 2593 skb->ip_summed = CHECKSUM_UNNECESSARY; 2594 return; 2595 } 2596 2597 skb->ip_summed = CHECKSUM_NONE; 2598 } 2599 2600 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2601 static int mvpp2_rx_refill(struct mvpp2_port *port, 2602 struct mvpp2_bm_pool *bm_pool, int pool) 2603 { 2604 dma_addr_t dma_addr; 2605 phys_addr_t phys_addr; 2606 void *buf; 2607 2608 /* No recycle or too many buffers are in use, so allocate a new skb */ 2609 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2610 GFP_ATOMIC); 2611 if (!buf) 2612 return -ENOMEM; 2613 2614 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2615 2616 return 0; 2617 } 2618 2619 /* Handle tx checksum */ 2620 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2621 { 2622 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2623 int ip_hdr_len = 0; 2624 u8 l4_proto; 2625 __be16 l3_proto = vlan_get_protocol(skb); 2626 2627 if (l3_proto == htons(ETH_P_IP)) { 2628 struct iphdr *ip4h = ip_hdr(skb); 2629 2630 /* Calculate IPv4 checksum and L4 checksum */ 2631 ip_hdr_len = ip4h->ihl; 2632 l4_proto = ip4h->protocol; 2633 } else if (l3_proto == htons(ETH_P_IPV6)) { 2634 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2635 2636 /* Read l4_protocol from one of IPv6 extra headers */ 2637 if (skb_network_header_len(skb) > 0) 2638 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2639 l4_proto = ip6h->nexthdr; 2640 } else { 2641 return MVPP2_TXD_L4_CSUM_NOT; 2642 } 2643 2644 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2645 l3_proto, ip_hdr_len, l4_proto); 2646 } 2647 2648 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2649 } 2650 2651 /* Main rx processing */ 2652 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2653 int rx_todo, struct mvpp2_rx_queue *rxq) 2654 { 2655 struct net_device *dev = port->dev; 2656 int rx_received; 2657 int rx_done = 0; 2658 u32 rcvd_pkts = 0; 2659 u32 rcvd_bytes = 0; 2660 2661 /* Get number of received packets and clamp the to-do */ 2662 rx_received = mvpp2_rxq_received(port, rxq->id); 2663 if (rx_todo > rx_received) 2664 rx_todo = rx_received; 2665 2666 while (rx_done < rx_todo) { 2667 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2668 struct mvpp2_bm_pool *bm_pool; 2669 struct sk_buff *skb; 2670 unsigned int frag_size; 2671 dma_addr_t dma_addr; 2672 phys_addr_t phys_addr; 2673 u32 rx_status; 2674 int pool, rx_bytes, err; 2675 void *data; 2676 2677 rx_done++; 2678 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2679 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2680 rx_bytes -= MVPP2_MH_SIZE; 2681 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2682 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2683 data = (void *)phys_to_virt(phys_addr); 2684 2685 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2686 MVPP2_RXD_BM_POOL_ID_OFFS; 2687 bm_pool = &port->priv->bm_pools[pool]; 2688 2689 /* In case of an error, release the requested buffer pointer 2690 * to the Buffer Manager. This request process is controlled 2691 * by the hardware, and the information about the buffer is 2692 * comprised by the RX descriptor. 2693 */ 2694 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2695 err_drop_frame: 2696 dev->stats.rx_errors++; 2697 mvpp2_rx_error(port, rx_desc); 2698 /* Return the buffer to the pool */ 2699 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2700 continue; 2701 } 2702 2703 if (bm_pool->frag_size > PAGE_SIZE) 2704 frag_size = 0; 2705 else 2706 frag_size = bm_pool->frag_size; 2707 2708 skb = build_skb(data, frag_size); 2709 if (!skb) { 2710 netdev_warn(port->dev, "skb build failed\n"); 2711 goto err_drop_frame; 2712 } 2713 2714 err = mvpp2_rx_refill(port, bm_pool, pool); 2715 if (err) { 2716 netdev_err(port->dev, "failed to refill BM pools\n"); 2717 goto err_drop_frame; 2718 } 2719 2720 dma_unmap_single(dev->dev.parent, dma_addr, 2721 bm_pool->buf_size, DMA_FROM_DEVICE); 2722 2723 rcvd_pkts++; 2724 rcvd_bytes += rx_bytes; 2725 2726 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2727 skb_put(skb, rx_bytes); 2728 skb->protocol = eth_type_trans(skb, dev); 2729 mvpp2_rx_csum(port, rx_status, skb); 2730 2731 napi_gro_receive(napi, skb); 2732 } 2733 2734 if (rcvd_pkts) { 2735 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2736 2737 u64_stats_update_begin(&stats->syncp); 2738 stats->rx_packets += rcvd_pkts; 2739 stats->rx_bytes += rcvd_bytes; 2740 u64_stats_update_end(&stats->syncp); 2741 } 2742 2743 /* Update Rx queue management counters */ 2744 wmb(); 2745 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2746 2747 return rx_todo; 2748 } 2749 2750 static inline void 2751 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2752 struct mvpp2_tx_desc *desc) 2753 { 2754 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2755 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2756 2757 dma_addr_t buf_dma_addr = 2758 mvpp2_txdesc_dma_addr_get(port, desc); 2759 size_t buf_sz = 2760 mvpp2_txdesc_size_get(port, desc); 2761 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2762 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2763 buf_sz, DMA_TO_DEVICE); 2764 mvpp2_txq_desc_put(txq); 2765 } 2766 2767 /* Handle tx fragmentation processing */ 2768 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2769 struct mvpp2_tx_queue *aggr_txq, 2770 struct mvpp2_tx_queue *txq) 2771 { 2772 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2773 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2774 struct mvpp2_tx_desc *tx_desc; 2775 int i; 2776 dma_addr_t buf_dma_addr; 2777 2778 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2779 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2780 void *addr = page_address(frag->page.p) + frag->page_offset; 2781 2782 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2783 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2784 mvpp2_txdesc_size_set(port, tx_desc, frag->size); 2785 2786 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2787 frag->size, DMA_TO_DEVICE); 2788 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2789 mvpp2_txq_desc_put(txq); 2790 goto cleanup; 2791 } 2792 2793 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2794 2795 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2796 /* Last descriptor */ 2797 mvpp2_txdesc_cmd_set(port, tx_desc, 2798 MVPP2_TXD_L_DESC); 2799 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2800 } else { 2801 /* Descriptor in the middle: Not First, Not Last */ 2802 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2803 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2804 } 2805 } 2806 2807 return 0; 2808 cleanup: 2809 /* Release all descriptors that were used to map fragments of 2810 * this packet, as well as the corresponding DMA mappings 2811 */ 2812 for (i = i - 1; i >= 0; i--) { 2813 tx_desc = txq->descs + i; 2814 tx_desc_unmap_put(port, txq, tx_desc); 2815 } 2816 2817 return -ENOMEM; 2818 } 2819 2820 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2821 struct net_device *dev, 2822 struct mvpp2_tx_queue *txq, 2823 struct mvpp2_tx_queue *aggr_txq, 2824 struct mvpp2_txq_pcpu *txq_pcpu, 2825 int hdr_sz) 2826 { 2827 struct mvpp2_port *port = netdev_priv(dev); 2828 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2829 dma_addr_t addr; 2830 2831 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2832 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2833 2834 addr = txq_pcpu->tso_headers_dma + 2835 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2836 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2837 2838 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2839 MVPP2_TXD_F_DESC | 2840 MVPP2_TXD_PADDING_DISABLE); 2841 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2842 } 2843 2844 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2845 struct net_device *dev, struct tso_t *tso, 2846 struct mvpp2_tx_queue *txq, 2847 struct mvpp2_tx_queue *aggr_txq, 2848 struct mvpp2_txq_pcpu *txq_pcpu, 2849 int sz, bool left, bool last) 2850 { 2851 struct mvpp2_port *port = netdev_priv(dev); 2852 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2853 dma_addr_t buf_dma_addr; 2854 2855 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2856 mvpp2_txdesc_size_set(port, tx_desc, sz); 2857 2858 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2859 DMA_TO_DEVICE); 2860 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2861 mvpp2_txq_desc_put(txq); 2862 return -ENOMEM; 2863 } 2864 2865 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2866 2867 if (!left) { 2868 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 2869 if (last) { 2870 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2871 return 0; 2872 } 2873 } else { 2874 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2875 } 2876 2877 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2878 return 0; 2879 } 2880 2881 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 2882 struct mvpp2_tx_queue *txq, 2883 struct mvpp2_tx_queue *aggr_txq, 2884 struct mvpp2_txq_pcpu *txq_pcpu) 2885 { 2886 struct mvpp2_port *port = netdev_priv(dev); 2887 struct tso_t tso; 2888 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 2889 int i, len, descs = 0; 2890 2891 /* Check number of available descriptors */ 2892 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 2893 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 2894 tso_count_descs(skb))) 2895 return 0; 2896 2897 tso_start(skb, &tso); 2898 len = skb->len - hdr_sz; 2899 while (len > 0) { 2900 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 2901 char *hdr = txq_pcpu->tso_headers + 2902 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2903 2904 len -= left; 2905 descs++; 2906 2907 tso_build_hdr(skb, hdr, &tso, left, len == 0); 2908 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 2909 2910 while (left > 0) { 2911 int sz = min_t(int, tso.size, left); 2912 left -= sz; 2913 descs++; 2914 2915 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 2916 txq_pcpu, sz, left, len == 0)) 2917 goto release; 2918 tso_build_data(skb, &tso, sz); 2919 } 2920 } 2921 2922 return descs; 2923 2924 release: 2925 for (i = descs - 1; i >= 0; i--) { 2926 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 2927 tx_desc_unmap_put(port, txq, tx_desc); 2928 } 2929 return 0; 2930 } 2931 2932 /* Main tx processing */ 2933 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 2934 { 2935 struct mvpp2_port *port = netdev_priv(dev); 2936 struct mvpp2_tx_queue *txq, *aggr_txq; 2937 struct mvpp2_txq_pcpu *txq_pcpu; 2938 struct mvpp2_tx_desc *tx_desc; 2939 dma_addr_t buf_dma_addr; 2940 unsigned long flags = 0; 2941 unsigned int thread; 2942 int frags = 0; 2943 u16 txq_id; 2944 u32 tx_cmd; 2945 2946 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2947 2948 txq_id = skb_get_queue_mapping(skb); 2949 txq = port->txqs[txq_id]; 2950 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2951 aggr_txq = &port->priv->aggr_txqs[thread]; 2952 2953 if (test_bit(thread, &port->priv->lock_map)) 2954 spin_lock_irqsave(&port->tx_lock[thread], flags); 2955 2956 if (skb_is_gso(skb)) { 2957 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 2958 goto out; 2959 } 2960 frags = skb_shinfo(skb)->nr_frags + 1; 2961 2962 /* Check number of available descriptors */ 2963 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 2964 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 2965 frags = 0; 2966 goto out; 2967 } 2968 2969 /* Get a descriptor for the first part of the packet */ 2970 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2971 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2972 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 2973 2974 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 2975 skb_headlen(skb), DMA_TO_DEVICE); 2976 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2977 mvpp2_txq_desc_put(txq); 2978 frags = 0; 2979 goto out; 2980 } 2981 2982 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2983 2984 tx_cmd = mvpp2_skb_tx_csum(port, skb); 2985 2986 if (frags == 1) { 2987 /* First and Last descriptor */ 2988 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 2989 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2990 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2991 } else { 2992 /* First but not Last */ 2993 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 2994 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2995 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2996 2997 /* Continue with other skb fragments */ 2998 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 2999 tx_desc_unmap_put(port, txq, tx_desc); 3000 frags = 0; 3001 } 3002 } 3003 3004 out: 3005 if (frags > 0) { 3006 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 3007 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 3008 3009 txq_pcpu->reserved_num -= frags; 3010 txq_pcpu->count += frags; 3011 aggr_txq->count += frags; 3012 3013 /* Enable transmit */ 3014 wmb(); 3015 mvpp2_aggr_txq_pend_desc_add(port, frags); 3016 3017 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3018 netif_tx_stop_queue(nq); 3019 3020 u64_stats_update_begin(&stats->syncp); 3021 stats->tx_packets++; 3022 stats->tx_bytes += skb->len; 3023 u64_stats_update_end(&stats->syncp); 3024 } else { 3025 dev->stats.tx_dropped++; 3026 dev_kfree_skb_any(skb); 3027 } 3028 3029 /* Finalize TX processing */ 3030 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3031 mvpp2_txq_done(port, txq, txq_pcpu); 3032 3033 /* Set the timer in case not all frags were processed */ 3034 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3035 txq_pcpu->count > 0) { 3036 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 3037 3038 mvpp2_timer_set(port_pcpu); 3039 } 3040 3041 if (test_bit(thread, &port->priv->lock_map)) 3042 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 3043 3044 return NETDEV_TX_OK; 3045 } 3046 3047 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3048 { 3049 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3050 netdev_err(dev, "FCS error\n"); 3051 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3052 netdev_err(dev, "rx fifo overrun error\n"); 3053 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3054 netdev_err(dev, "tx fifo underrun error\n"); 3055 } 3056 3057 static int mvpp2_poll(struct napi_struct *napi, int budget) 3058 { 3059 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3060 int rx_done = 0; 3061 struct mvpp2_port *port = netdev_priv(napi->dev); 3062 struct mvpp2_queue_vector *qv; 3063 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3064 3065 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3066 3067 /* Rx/Tx cause register 3068 * 3069 * Bits 0-15: each bit indicates received packets on the Rx queue 3070 * (bit 0 is for Rx queue 0). 3071 * 3072 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3073 * (bit 16 is for Tx queue 0). 3074 * 3075 * Each CPU has its own Rx/Tx cause register 3076 */ 3077 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 3078 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3079 3080 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3081 if (cause_misc) { 3082 mvpp2_cause_error(port->dev, cause_misc); 3083 3084 /* Clear the cause register */ 3085 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3086 mvpp2_thread_write(port->priv, thread, 3087 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3088 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3089 } 3090 3091 if (port->has_tx_irqs) { 3092 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3093 if (cause_tx) { 3094 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3095 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3096 } 3097 } 3098 3099 /* Process RX packets */ 3100 cause_rx = cause_rx_tx & 3101 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 3102 cause_rx <<= qv->first_rxq; 3103 cause_rx |= qv->pending_cause_rx; 3104 while (cause_rx && budget > 0) { 3105 int count; 3106 struct mvpp2_rx_queue *rxq; 3107 3108 rxq = mvpp2_get_rx_queue(port, cause_rx); 3109 if (!rxq) 3110 break; 3111 3112 count = mvpp2_rx(port, napi, budget, rxq); 3113 rx_done += count; 3114 budget -= count; 3115 if (budget > 0) { 3116 /* Clear the bit associated to this Rx queue 3117 * so that next iteration will continue from 3118 * the next Rx queue. 3119 */ 3120 cause_rx &= ~(1 << rxq->logic_rxq); 3121 } 3122 } 3123 3124 if (budget > 0) { 3125 cause_rx = 0; 3126 napi_complete_done(napi, rx_done); 3127 3128 mvpp2_qvec_interrupt_enable(qv); 3129 } 3130 qv->pending_cause_rx = cause_rx; 3131 return rx_done; 3132 } 3133 3134 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3135 { 3136 u32 ctrl3; 3137 3138 /* comphy reconfiguration */ 3139 mvpp22_comphy_init(port); 3140 3141 /* gop reconfiguration */ 3142 mvpp22_gop_init(port); 3143 3144 /* Only GOP port 0 has an XLG MAC */ 3145 if (port->gop_id == 0) { 3146 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3147 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3148 3149 if (mvpp2_is_xlg(port->phy_interface)) 3150 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3151 else 3152 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3153 3154 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3155 } 3156 3157 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) 3158 mvpp2_xlg_max_rx_size_set(port); 3159 else 3160 mvpp2_gmac_max_rx_size_set(port); 3161 } 3162 3163 /* Set hw internals when starting port */ 3164 static void mvpp2_start_dev(struct mvpp2_port *port) 3165 { 3166 int i; 3167 3168 mvpp2_txp_max_tx_size_set(port); 3169 3170 for (i = 0; i < port->nqvecs; i++) 3171 napi_enable(&port->qvecs[i].napi); 3172 3173 /* Enable interrupts on all threads */ 3174 mvpp2_interrupts_enable(port); 3175 3176 if (port->priv->hw_version == MVPP22) 3177 mvpp22_mode_reconfigure(port); 3178 3179 if (port->phylink) { 3180 phylink_start(port->phylink); 3181 } else { 3182 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3183 * configured manually when the interface is started. This will 3184 * be removed as soon as the phylink ACPI support lands in. 3185 */ 3186 struct phylink_link_state state = { 3187 .interface = port->phy_interface, 3188 }; 3189 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state); 3190 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface, 3191 NULL); 3192 } 3193 3194 netif_tx_start_all_queues(port->dev); 3195 } 3196 3197 /* Set hw internals when stopping port */ 3198 static void mvpp2_stop_dev(struct mvpp2_port *port) 3199 { 3200 int i; 3201 3202 /* Disable interrupts on all threads */ 3203 mvpp2_interrupts_disable(port); 3204 3205 for (i = 0; i < port->nqvecs; i++) 3206 napi_disable(&port->qvecs[i].napi); 3207 3208 if (port->phylink) 3209 phylink_stop(port->phylink); 3210 phy_power_off(port->comphy); 3211 } 3212 3213 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3214 struct ethtool_ringparam *ring) 3215 { 3216 u16 new_rx_pending = ring->rx_pending; 3217 u16 new_tx_pending = ring->tx_pending; 3218 3219 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3220 return -EINVAL; 3221 3222 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3223 new_rx_pending = MVPP2_MAX_RXD_MAX; 3224 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3225 new_rx_pending = ALIGN(ring->rx_pending, 16); 3226 3227 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3228 new_tx_pending = MVPP2_MAX_TXD_MAX; 3229 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3230 new_tx_pending = ALIGN(ring->tx_pending, 32); 3231 3232 /* The Tx ring size cannot be smaller than the minimum number of 3233 * descriptors needed for TSO. 3234 */ 3235 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3236 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3237 3238 if (ring->rx_pending != new_rx_pending) { 3239 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3240 ring->rx_pending, new_rx_pending); 3241 ring->rx_pending = new_rx_pending; 3242 } 3243 3244 if (ring->tx_pending != new_tx_pending) { 3245 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3246 ring->tx_pending, new_tx_pending); 3247 ring->tx_pending = new_tx_pending; 3248 } 3249 3250 return 0; 3251 } 3252 3253 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3254 { 3255 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3256 3257 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3258 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3259 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3260 addr[0] = (mac_addr_h >> 24) & 0xFF; 3261 addr[1] = (mac_addr_h >> 16) & 0xFF; 3262 addr[2] = (mac_addr_h >> 8) & 0xFF; 3263 addr[3] = mac_addr_h & 0xFF; 3264 addr[4] = mac_addr_m & 0xFF; 3265 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3266 } 3267 3268 static int mvpp2_irqs_init(struct mvpp2_port *port) 3269 { 3270 int err, i; 3271 3272 for (i = 0; i < port->nqvecs; i++) { 3273 struct mvpp2_queue_vector *qv = port->qvecs + i; 3274 3275 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3276 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 3277 if (!qv->mask) { 3278 err = -ENOMEM; 3279 goto err; 3280 } 3281 3282 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3283 } 3284 3285 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3286 if (err) 3287 goto err; 3288 3289 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3290 unsigned int cpu; 3291 3292 for_each_present_cpu(cpu) { 3293 if (mvpp2_cpu_to_thread(port->priv, cpu) == 3294 qv->sw_thread_id) 3295 cpumask_set_cpu(cpu, qv->mask); 3296 } 3297 3298 irq_set_affinity_hint(qv->irq, qv->mask); 3299 } 3300 } 3301 3302 return 0; 3303 err: 3304 for (i = 0; i < port->nqvecs; i++) { 3305 struct mvpp2_queue_vector *qv = port->qvecs + i; 3306 3307 irq_set_affinity_hint(qv->irq, NULL); 3308 kfree(qv->mask); 3309 qv->mask = NULL; 3310 free_irq(qv->irq, qv); 3311 } 3312 3313 return err; 3314 } 3315 3316 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3317 { 3318 int i; 3319 3320 for (i = 0; i < port->nqvecs; i++) { 3321 struct mvpp2_queue_vector *qv = port->qvecs + i; 3322 3323 irq_set_affinity_hint(qv->irq, NULL); 3324 kfree(qv->mask); 3325 qv->mask = NULL; 3326 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3327 free_irq(qv->irq, qv); 3328 } 3329 } 3330 3331 static bool mvpp22_rss_is_supported(void) 3332 { 3333 return queue_mode == MVPP2_QDIST_MULTI_MODE; 3334 } 3335 3336 static int mvpp2_open(struct net_device *dev) 3337 { 3338 struct mvpp2_port *port = netdev_priv(dev); 3339 struct mvpp2 *priv = port->priv; 3340 unsigned char mac_bcast[ETH_ALEN] = { 3341 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3342 bool valid = false; 3343 int err; 3344 3345 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3346 if (err) { 3347 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3348 return err; 3349 } 3350 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3351 if (err) { 3352 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3353 return err; 3354 } 3355 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3356 if (err) { 3357 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3358 return err; 3359 } 3360 err = mvpp2_prs_def_flow(port); 3361 if (err) { 3362 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3363 return err; 3364 } 3365 3366 /* Allocate the Rx/Tx queues */ 3367 err = mvpp2_setup_rxqs(port); 3368 if (err) { 3369 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3370 return err; 3371 } 3372 3373 err = mvpp2_setup_txqs(port); 3374 if (err) { 3375 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3376 goto err_cleanup_rxqs; 3377 } 3378 3379 err = mvpp2_irqs_init(port); 3380 if (err) { 3381 netdev_err(port->dev, "cannot init IRQs\n"); 3382 goto err_cleanup_txqs; 3383 } 3384 3385 /* Phylink isn't supported yet in ACPI mode */ 3386 if (port->of_node) { 3387 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3388 if (err) { 3389 netdev_err(port->dev, "could not attach PHY (%d)\n", 3390 err); 3391 goto err_free_irq; 3392 } 3393 3394 valid = true; 3395 } 3396 3397 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3398 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3399 dev->name, port); 3400 if (err) { 3401 netdev_err(port->dev, "cannot request link IRQ %d\n", 3402 port->link_irq); 3403 goto err_free_irq; 3404 } 3405 3406 mvpp22_gop_setup_irq(port); 3407 3408 /* In default link is down */ 3409 netif_carrier_off(port->dev); 3410 3411 valid = true; 3412 } else { 3413 port->link_irq = 0; 3414 } 3415 3416 if (!valid) { 3417 netdev_err(port->dev, 3418 "invalid configuration: no dt or link IRQ"); 3419 goto err_free_irq; 3420 } 3421 3422 /* Unmask interrupts on all CPUs */ 3423 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3424 mvpp2_shared_interrupt_mask_unmask(port, false); 3425 3426 mvpp2_start_dev(port); 3427 3428 /* Start hardware statistics gathering */ 3429 queue_delayed_work(priv->stats_queue, &port->stats_work, 3430 MVPP2_MIB_COUNTERS_STATS_DELAY); 3431 3432 return 0; 3433 3434 err_free_irq: 3435 mvpp2_irqs_deinit(port); 3436 err_cleanup_txqs: 3437 mvpp2_cleanup_txqs(port); 3438 err_cleanup_rxqs: 3439 mvpp2_cleanup_rxqs(port); 3440 return err; 3441 } 3442 3443 static int mvpp2_stop(struct net_device *dev) 3444 { 3445 struct mvpp2_port *port = netdev_priv(dev); 3446 struct mvpp2_port_pcpu *port_pcpu; 3447 unsigned int thread; 3448 3449 mvpp2_stop_dev(port); 3450 3451 /* Mask interrupts on all threads */ 3452 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3453 mvpp2_shared_interrupt_mask_unmask(port, true); 3454 3455 if (port->phylink) 3456 phylink_disconnect_phy(port->phylink); 3457 if (port->link_irq) 3458 free_irq(port->link_irq, port); 3459 3460 mvpp2_irqs_deinit(port); 3461 if (!port->has_tx_irqs) { 3462 for (thread = 0; thread < port->priv->nthreads; thread++) { 3463 port_pcpu = per_cpu_ptr(port->pcpu, thread); 3464 3465 hrtimer_cancel(&port_pcpu->tx_done_timer); 3466 port_pcpu->timer_scheduled = false; 3467 tasklet_kill(&port_pcpu->tx_done_tasklet); 3468 } 3469 } 3470 mvpp2_cleanup_rxqs(port); 3471 mvpp2_cleanup_txqs(port); 3472 3473 cancel_delayed_work_sync(&port->stats_work); 3474 3475 return 0; 3476 } 3477 3478 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3479 struct netdev_hw_addr_list *list) 3480 { 3481 struct netdev_hw_addr *ha; 3482 int ret; 3483 3484 netdev_hw_addr_list_for_each(ha, list) { 3485 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3486 if (ret) 3487 return ret; 3488 } 3489 3490 return 0; 3491 } 3492 3493 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3494 { 3495 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3496 mvpp2_prs_vid_enable_filtering(port); 3497 else 3498 mvpp2_prs_vid_disable_filtering(port); 3499 3500 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3501 MVPP2_PRS_L2_UNI_CAST, enable); 3502 3503 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3504 MVPP2_PRS_L2_MULTI_CAST, enable); 3505 } 3506 3507 static void mvpp2_set_rx_mode(struct net_device *dev) 3508 { 3509 struct mvpp2_port *port = netdev_priv(dev); 3510 3511 /* Clear the whole UC and MC list */ 3512 mvpp2_prs_mac_del_all(port); 3513 3514 if (dev->flags & IFF_PROMISC) { 3515 mvpp2_set_rx_promisc(port, true); 3516 return; 3517 } 3518 3519 mvpp2_set_rx_promisc(port, false); 3520 3521 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3522 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3523 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3524 MVPP2_PRS_L2_UNI_CAST, true); 3525 3526 if (dev->flags & IFF_ALLMULTI) { 3527 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3528 MVPP2_PRS_L2_MULTI_CAST, true); 3529 return; 3530 } 3531 3532 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3533 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3534 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3535 MVPP2_PRS_L2_MULTI_CAST, true); 3536 } 3537 3538 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3539 { 3540 const struct sockaddr *addr = p; 3541 int err; 3542 3543 if (!is_valid_ether_addr(addr->sa_data)) 3544 return -EADDRNOTAVAIL; 3545 3546 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3547 if (err) { 3548 /* Reconfigure parser accept the original MAC address */ 3549 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3550 netdev_err(dev, "failed to change MAC address\n"); 3551 } 3552 return err; 3553 } 3554 3555 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3556 { 3557 struct mvpp2_port *port = netdev_priv(dev); 3558 int err; 3559 3560 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3561 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3562 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3563 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3564 } 3565 3566 if (!netif_running(dev)) { 3567 err = mvpp2_bm_update_mtu(dev, mtu); 3568 if (!err) { 3569 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3570 return 0; 3571 } 3572 3573 /* Reconfigure BM to the original MTU */ 3574 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3575 if (err) 3576 goto log_error; 3577 } 3578 3579 mvpp2_stop_dev(port); 3580 3581 err = mvpp2_bm_update_mtu(dev, mtu); 3582 if (!err) { 3583 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3584 goto out_start; 3585 } 3586 3587 /* Reconfigure BM to the original MTU */ 3588 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3589 if (err) 3590 goto log_error; 3591 3592 out_start: 3593 mvpp2_start_dev(port); 3594 mvpp2_egress_enable(port); 3595 mvpp2_ingress_enable(port); 3596 3597 return 0; 3598 log_error: 3599 netdev_err(dev, "failed to change MTU\n"); 3600 return err; 3601 } 3602 3603 static void 3604 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3605 { 3606 struct mvpp2_port *port = netdev_priv(dev); 3607 unsigned int start; 3608 unsigned int cpu; 3609 3610 for_each_possible_cpu(cpu) { 3611 struct mvpp2_pcpu_stats *cpu_stats; 3612 u64 rx_packets; 3613 u64 rx_bytes; 3614 u64 tx_packets; 3615 u64 tx_bytes; 3616 3617 cpu_stats = per_cpu_ptr(port->stats, cpu); 3618 do { 3619 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3620 rx_packets = cpu_stats->rx_packets; 3621 rx_bytes = cpu_stats->rx_bytes; 3622 tx_packets = cpu_stats->tx_packets; 3623 tx_bytes = cpu_stats->tx_bytes; 3624 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3625 3626 stats->rx_packets += rx_packets; 3627 stats->rx_bytes += rx_bytes; 3628 stats->tx_packets += tx_packets; 3629 stats->tx_bytes += tx_bytes; 3630 } 3631 3632 stats->rx_errors = dev->stats.rx_errors; 3633 stats->rx_dropped = dev->stats.rx_dropped; 3634 stats->tx_dropped = dev->stats.tx_dropped; 3635 } 3636 3637 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3638 { 3639 struct mvpp2_port *port = netdev_priv(dev); 3640 3641 if (!port->phylink) 3642 return -ENOTSUPP; 3643 3644 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3645 } 3646 3647 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3648 { 3649 struct mvpp2_port *port = netdev_priv(dev); 3650 int ret; 3651 3652 ret = mvpp2_prs_vid_entry_add(port, vid); 3653 if (ret) 3654 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3655 MVPP2_PRS_VLAN_FILT_MAX - 1); 3656 return ret; 3657 } 3658 3659 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3660 { 3661 struct mvpp2_port *port = netdev_priv(dev); 3662 3663 mvpp2_prs_vid_entry_remove(port, vid); 3664 return 0; 3665 } 3666 3667 static int mvpp2_set_features(struct net_device *dev, 3668 netdev_features_t features) 3669 { 3670 netdev_features_t changed = dev->features ^ features; 3671 struct mvpp2_port *port = netdev_priv(dev); 3672 3673 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3674 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3675 mvpp2_prs_vid_enable_filtering(port); 3676 } else { 3677 /* Invalidate all registered VID filters for this 3678 * port 3679 */ 3680 mvpp2_prs_vid_remove_all(port); 3681 3682 mvpp2_prs_vid_disable_filtering(port); 3683 } 3684 } 3685 3686 if (changed & NETIF_F_RXHASH) { 3687 if (features & NETIF_F_RXHASH) 3688 mvpp22_rss_enable(port); 3689 else 3690 mvpp22_rss_disable(port); 3691 } 3692 3693 return 0; 3694 } 3695 3696 /* Ethtool methods */ 3697 3698 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3699 { 3700 struct mvpp2_port *port = netdev_priv(dev); 3701 3702 if (!port->phylink) 3703 return -ENOTSUPP; 3704 3705 return phylink_ethtool_nway_reset(port->phylink); 3706 } 3707 3708 /* Set interrupt coalescing for ethtools */ 3709 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3710 struct ethtool_coalesce *c) 3711 { 3712 struct mvpp2_port *port = netdev_priv(dev); 3713 int queue; 3714 3715 for (queue = 0; queue < port->nrxqs; queue++) { 3716 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3717 3718 rxq->time_coal = c->rx_coalesce_usecs; 3719 rxq->pkts_coal = c->rx_max_coalesced_frames; 3720 mvpp2_rx_pkts_coal_set(port, rxq); 3721 mvpp2_rx_time_coal_set(port, rxq); 3722 } 3723 3724 if (port->has_tx_irqs) { 3725 port->tx_time_coal = c->tx_coalesce_usecs; 3726 mvpp2_tx_time_coal_set(port); 3727 } 3728 3729 for (queue = 0; queue < port->ntxqs; queue++) { 3730 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3731 3732 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3733 3734 if (port->has_tx_irqs) 3735 mvpp2_tx_pkts_coal_set(port, txq); 3736 } 3737 3738 return 0; 3739 } 3740 3741 /* get coalescing for ethtools */ 3742 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3743 struct ethtool_coalesce *c) 3744 { 3745 struct mvpp2_port *port = netdev_priv(dev); 3746 3747 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3748 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3749 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3750 c->tx_coalesce_usecs = port->tx_time_coal; 3751 return 0; 3752 } 3753 3754 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3755 struct ethtool_drvinfo *drvinfo) 3756 { 3757 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3758 sizeof(drvinfo->driver)); 3759 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3760 sizeof(drvinfo->version)); 3761 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3762 sizeof(drvinfo->bus_info)); 3763 } 3764 3765 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3766 struct ethtool_ringparam *ring) 3767 { 3768 struct mvpp2_port *port = netdev_priv(dev); 3769 3770 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3771 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3772 ring->rx_pending = port->rx_ring_size; 3773 ring->tx_pending = port->tx_ring_size; 3774 } 3775 3776 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3777 struct ethtool_ringparam *ring) 3778 { 3779 struct mvpp2_port *port = netdev_priv(dev); 3780 u16 prev_rx_ring_size = port->rx_ring_size; 3781 u16 prev_tx_ring_size = port->tx_ring_size; 3782 int err; 3783 3784 err = mvpp2_check_ringparam_valid(dev, ring); 3785 if (err) 3786 return err; 3787 3788 if (!netif_running(dev)) { 3789 port->rx_ring_size = ring->rx_pending; 3790 port->tx_ring_size = ring->tx_pending; 3791 return 0; 3792 } 3793 3794 /* The interface is running, so we have to force a 3795 * reallocation of the queues 3796 */ 3797 mvpp2_stop_dev(port); 3798 mvpp2_cleanup_rxqs(port); 3799 mvpp2_cleanup_txqs(port); 3800 3801 port->rx_ring_size = ring->rx_pending; 3802 port->tx_ring_size = ring->tx_pending; 3803 3804 err = mvpp2_setup_rxqs(port); 3805 if (err) { 3806 /* Reallocate Rx queues with the original ring size */ 3807 port->rx_ring_size = prev_rx_ring_size; 3808 ring->rx_pending = prev_rx_ring_size; 3809 err = mvpp2_setup_rxqs(port); 3810 if (err) 3811 goto err_out; 3812 } 3813 err = mvpp2_setup_txqs(port); 3814 if (err) { 3815 /* Reallocate Tx queues with the original ring size */ 3816 port->tx_ring_size = prev_tx_ring_size; 3817 ring->tx_pending = prev_tx_ring_size; 3818 err = mvpp2_setup_txqs(port); 3819 if (err) 3820 goto err_clean_rxqs; 3821 } 3822 3823 mvpp2_start_dev(port); 3824 mvpp2_egress_enable(port); 3825 mvpp2_ingress_enable(port); 3826 3827 return 0; 3828 3829 err_clean_rxqs: 3830 mvpp2_cleanup_rxqs(port); 3831 err_out: 3832 netdev_err(dev, "failed to change ring parameters"); 3833 return err; 3834 } 3835 3836 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3837 struct ethtool_pauseparam *pause) 3838 { 3839 struct mvpp2_port *port = netdev_priv(dev); 3840 3841 if (!port->phylink) 3842 return; 3843 3844 phylink_ethtool_get_pauseparam(port->phylink, pause); 3845 } 3846 3847 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3848 struct ethtool_pauseparam *pause) 3849 { 3850 struct mvpp2_port *port = netdev_priv(dev); 3851 3852 if (!port->phylink) 3853 return -ENOTSUPP; 3854 3855 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3856 } 3857 3858 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 3859 struct ethtool_link_ksettings *cmd) 3860 { 3861 struct mvpp2_port *port = netdev_priv(dev); 3862 3863 if (!port->phylink) 3864 return -ENOTSUPP; 3865 3866 return phylink_ethtool_ksettings_get(port->phylink, cmd); 3867 } 3868 3869 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 3870 const struct ethtool_link_ksettings *cmd) 3871 { 3872 struct mvpp2_port *port = netdev_priv(dev); 3873 3874 if (!port->phylink) 3875 return -ENOTSUPP; 3876 3877 return phylink_ethtool_ksettings_set(port->phylink, cmd); 3878 } 3879 3880 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 3881 struct ethtool_rxnfc *info, u32 *rules) 3882 { 3883 struct mvpp2_port *port = netdev_priv(dev); 3884 int ret = 0; 3885 3886 if (!mvpp22_rss_is_supported()) 3887 return -EOPNOTSUPP; 3888 3889 switch (info->cmd) { 3890 case ETHTOOL_GRXFH: 3891 ret = mvpp2_ethtool_rxfh_get(port, info); 3892 break; 3893 case ETHTOOL_GRXRINGS: 3894 info->data = port->nrxqs; 3895 break; 3896 default: 3897 return -ENOTSUPP; 3898 } 3899 3900 return ret; 3901 } 3902 3903 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 3904 struct ethtool_rxnfc *info) 3905 { 3906 struct mvpp2_port *port = netdev_priv(dev); 3907 int ret = 0; 3908 3909 if (!mvpp22_rss_is_supported()) 3910 return -EOPNOTSUPP; 3911 3912 switch (info->cmd) { 3913 case ETHTOOL_SRXFH: 3914 ret = mvpp2_ethtool_rxfh_set(port, info); 3915 break; 3916 default: 3917 return -EOPNOTSUPP; 3918 } 3919 return ret; 3920 } 3921 3922 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 3923 { 3924 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 3925 } 3926 3927 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3928 u8 *hfunc) 3929 { 3930 struct mvpp2_port *port = netdev_priv(dev); 3931 3932 if (!mvpp22_rss_is_supported()) 3933 return -EOPNOTSUPP; 3934 3935 if (indir) 3936 memcpy(indir, port->indir, 3937 ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); 3938 3939 if (hfunc) 3940 *hfunc = ETH_RSS_HASH_CRC32; 3941 3942 return 0; 3943 } 3944 3945 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 3946 const u8 *key, const u8 hfunc) 3947 { 3948 struct mvpp2_port *port = netdev_priv(dev); 3949 3950 if (!mvpp22_rss_is_supported()) 3951 return -EOPNOTSUPP; 3952 3953 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 3954 return -EOPNOTSUPP; 3955 3956 if (key) 3957 return -EOPNOTSUPP; 3958 3959 if (indir) { 3960 memcpy(port->indir, indir, 3961 ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); 3962 mvpp22_rss_fill_table(port, port->id); 3963 } 3964 3965 return 0; 3966 } 3967 3968 /* Device ops */ 3969 3970 static const struct net_device_ops mvpp2_netdev_ops = { 3971 .ndo_open = mvpp2_open, 3972 .ndo_stop = mvpp2_stop, 3973 .ndo_start_xmit = mvpp2_tx, 3974 .ndo_set_rx_mode = mvpp2_set_rx_mode, 3975 .ndo_set_mac_address = mvpp2_set_mac_address, 3976 .ndo_change_mtu = mvpp2_change_mtu, 3977 .ndo_get_stats64 = mvpp2_get_stats64, 3978 .ndo_do_ioctl = mvpp2_ioctl, 3979 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 3980 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 3981 .ndo_set_features = mvpp2_set_features, 3982 }; 3983 3984 static const struct ethtool_ops mvpp2_eth_tool_ops = { 3985 .nway_reset = mvpp2_ethtool_nway_reset, 3986 .get_link = ethtool_op_get_link, 3987 .set_coalesce = mvpp2_ethtool_set_coalesce, 3988 .get_coalesce = mvpp2_ethtool_get_coalesce, 3989 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 3990 .get_ringparam = mvpp2_ethtool_get_ringparam, 3991 .set_ringparam = mvpp2_ethtool_set_ringparam, 3992 .get_strings = mvpp2_ethtool_get_strings, 3993 .get_ethtool_stats = mvpp2_ethtool_get_stats, 3994 .get_sset_count = mvpp2_ethtool_get_sset_count, 3995 .get_pauseparam = mvpp2_ethtool_get_pause_param, 3996 .set_pauseparam = mvpp2_ethtool_set_pause_param, 3997 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 3998 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 3999 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 4000 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 4001 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 4002 .get_rxfh = mvpp2_ethtool_get_rxfh, 4003 .set_rxfh = mvpp2_ethtool_set_rxfh, 4004 4005 }; 4006 4007 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 4008 * had a single IRQ defined per-port. 4009 */ 4010 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 4011 struct device_node *port_node) 4012 { 4013 struct mvpp2_queue_vector *v = &port->qvecs[0]; 4014 4015 v->first_rxq = 0; 4016 v->nrxqs = port->nrxqs; 4017 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4018 v->sw_thread_id = 0; 4019 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 4020 v->port = port; 4021 v->irq = irq_of_parse_and_map(port_node, 0); 4022 if (v->irq <= 0) 4023 return -EINVAL; 4024 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4025 NAPI_POLL_WEIGHT); 4026 4027 port->nqvecs = 1; 4028 4029 return 0; 4030 } 4031 4032 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 4033 struct device_node *port_node) 4034 { 4035 struct mvpp2 *priv = port->priv; 4036 struct mvpp2_queue_vector *v; 4037 int i, ret; 4038 4039 switch (queue_mode) { 4040 case MVPP2_QDIST_SINGLE_MODE: 4041 port->nqvecs = priv->nthreads + 1; 4042 break; 4043 case MVPP2_QDIST_MULTI_MODE: 4044 port->nqvecs = priv->nthreads; 4045 break; 4046 } 4047 4048 for (i = 0; i < port->nqvecs; i++) { 4049 char irqname[16]; 4050 4051 v = port->qvecs + i; 4052 4053 v->port = port; 4054 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 4055 v->sw_thread_id = i; 4056 v->sw_thread_mask = BIT(i); 4057 4058 if (port->flags & MVPP2_F_DT_COMPAT) 4059 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 4060 else 4061 snprintf(irqname, sizeof(irqname), "hif%d", i); 4062 4063 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 4064 v->first_rxq = i * MVPP2_DEFAULT_RXQ; 4065 v->nrxqs = MVPP2_DEFAULT_RXQ; 4066 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 4067 i == (port->nqvecs - 1)) { 4068 v->first_rxq = 0; 4069 v->nrxqs = port->nrxqs; 4070 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4071 4072 if (port->flags & MVPP2_F_DT_COMPAT) 4073 strncpy(irqname, "rx-shared", sizeof(irqname)); 4074 } 4075 4076 if (port_node) 4077 v->irq = of_irq_get_byname(port_node, irqname); 4078 else 4079 v->irq = fwnode_irq_get(port->fwnode, i); 4080 if (v->irq <= 0) { 4081 ret = -EINVAL; 4082 goto err; 4083 } 4084 4085 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4086 NAPI_POLL_WEIGHT); 4087 } 4088 4089 return 0; 4090 4091 err: 4092 for (i = 0; i < port->nqvecs; i++) 4093 irq_dispose_mapping(port->qvecs[i].irq); 4094 return ret; 4095 } 4096 4097 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 4098 struct device_node *port_node) 4099 { 4100 if (port->has_tx_irqs) 4101 return mvpp2_multi_queue_vectors_init(port, port_node); 4102 else 4103 return mvpp2_simple_queue_vectors_init(port, port_node); 4104 } 4105 4106 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 4107 { 4108 int i; 4109 4110 for (i = 0; i < port->nqvecs; i++) 4111 irq_dispose_mapping(port->qvecs[i].irq); 4112 } 4113 4114 /* Configure Rx queue group interrupt for this port */ 4115 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 4116 { 4117 struct mvpp2 *priv = port->priv; 4118 u32 val; 4119 int i; 4120 4121 if (priv->hw_version == MVPP21) { 4122 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 4123 port->nrxqs); 4124 return; 4125 } 4126 4127 /* Handle the more complicated PPv2.2 case */ 4128 for (i = 0; i < port->nqvecs; i++) { 4129 struct mvpp2_queue_vector *qv = port->qvecs + i; 4130 4131 if (!qv->nrxqs) 4132 continue; 4133 4134 val = qv->sw_thread_id; 4135 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 4136 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 4137 4138 val = qv->first_rxq; 4139 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 4140 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 4141 } 4142 } 4143 4144 /* Initialize port HW */ 4145 static int mvpp2_port_init(struct mvpp2_port *port) 4146 { 4147 struct device *dev = port->dev->dev.parent; 4148 struct mvpp2 *priv = port->priv; 4149 struct mvpp2_txq_pcpu *txq_pcpu; 4150 unsigned int thread; 4151 int queue, err; 4152 4153 /* Checks for hardware constraints */ 4154 if (port->first_rxq + port->nrxqs > 4155 MVPP2_MAX_PORTS * priv->max_port_rxqs) 4156 return -EINVAL; 4157 4158 if (port->nrxqs % MVPP2_DEFAULT_RXQ || 4159 port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 4160 return -EINVAL; 4161 4162 /* Disable port */ 4163 mvpp2_egress_disable(port); 4164 mvpp2_port_disable(port); 4165 4166 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4167 4168 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4169 GFP_KERNEL); 4170 if (!port->txqs) 4171 return -ENOMEM; 4172 4173 /* Associate physical Tx queues to this port and initialize. 4174 * The mapping is predefined. 4175 */ 4176 for (queue = 0; queue < port->ntxqs; queue++) { 4177 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4178 struct mvpp2_tx_queue *txq; 4179 4180 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4181 if (!txq) { 4182 err = -ENOMEM; 4183 goto err_free_percpu; 4184 } 4185 4186 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4187 if (!txq->pcpu) { 4188 err = -ENOMEM; 4189 goto err_free_percpu; 4190 } 4191 4192 txq->id = queue_phy_id; 4193 txq->log_id = queue; 4194 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4195 for (thread = 0; thread < priv->nthreads; thread++) { 4196 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4197 txq_pcpu->thread = thread; 4198 } 4199 4200 port->txqs[queue] = txq; 4201 } 4202 4203 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4204 GFP_KERNEL); 4205 if (!port->rxqs) { 4206 err = -ENOMEM; 4207 goto err_free_percpu; 4208 } 4209 4210 /* Allocate and initialize Rx queue for this port */ 4211 for (queue = 0; queue < port->nrxqs; queue++) { 4212 struct mvpp2_rx_queue *rxq; 4213 4214 /* Map physical Rx queue to port's logical Rx queue */ 4215 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4216 if (!rxq) { 4217 err = -ENOMEM; 4218 goto err_free_percpu; 4219 } 4220 /* Map this Rx queue to a physical queue */ 4221 rxq->id = port->first_rxq + queue; 4222 rxq->port = port->id; 4223 rxq->logic_rxq = queue; 4224 4225 port->rxqs[queue] = rxq; 4226 } 4227 4228 mvpp2_rx_irqs_setup(port); 4229 4230 /* Create Rx descriptor rings */ 4231 for (queue = 0; queue < port->nrxqs; queue++) { 4232 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4233 4234 rxq->size = port->rx_ring_size; 4235 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4236 rxq->time_coal = MVPP2_RX_COAL_USEC; 4237 } 4238 4239 mvpp2_ingress_disable(port); 4240 4241 /* Port default configuration */ 4242 mvpp2_defaults_set(port); 4243 4244 /* Port's classifier configuration */ 4245 mvpp2_cls_oversize_rxq_set(port); 4246 mvpp2_cls_port_config(port); 4247 4248 if (mvpp22_rss_is_supported()) 4249 mvpp22_rss_port_init(port); 4250 4251 /* Provide an initial Rx packet size */ 4252 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4253 4254 /* Initialize pools for swf */ 4255 err = mvpp2_swf_bm_pool_init(port); 4256 if (err) 4257 goto err_free_percpu; 4258 4259 return 0; 4260 4261 err_free_percpu: 4262 for (queue = 0; queue < port->ntxqs; queue++) { 4263 if (!port->txqs[queue]) 4264 continue; 4265 free_percpu(port->txqs[queue]->pcpu); 4266 } 4267 return err; 4268 } 4269 4270 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 4271 unsigned long *flags) 4272 { 4273 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 4274 "tx-cpu3" }; 4275 int i; 4276 4277 for (i = 0; i < 5; i++) 4278 if (of_property_match_string(port_node, "interrupt-names", 4279 irqs[i]) < 0) 4280 return false; 4281 4282 *flags |= MVPP2_F_DT_COMPAT; 4283 return true; 4284 } 4285 4286 /* Checks if the port dt description has the required Tx interrupts: 4287 * - PPv2.1: there are no such interrupts. 4288 * - PPv2.2: 4289 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 4290 * - The new ones have: "hifX" with X in [0..8] 4291 * 4292 * All those variants are supported to keep the backward compatibility. 4293 */ 4294 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 4295 struct device_node *port_node, 4296 unsigned long *flags) 4297 { 4298 char name[5]; 4299 int i; 4300 4301 /* ACPI */ 4302 if (!port_node) 4303 return true; 4304 4305 if (priv->hw_version == MVPP21) 4306 return false; 4307 4308 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 4309 return true; 4310 4311 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 4312 snprintf(name, 5, "hif%d", i); 4313 if (of_property_match_string(port_node, "interrupt-names", 4314 name) < 0) 4315 return false; 4316 } 4317 4318 return true; 4319 } 4320 4321 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4322 struct fwnode_handle *fwnode, 4323 char **mac_from) 4324 { 4325 struct mvpp2_port *port = netdev_priv(dev); 4326 char hw_mac_addr[ETH_ALEN] = {0}; 4327 char fw_mac_addr[ETH_ALEN]; 4328 4329 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4330 *mac_from = "firmware node"; 4331 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4332 return; 4333 } 4334 4335 if (priv->hw_version == MVPP21) { 4336 mvpp21_get_mac_address(port, hw_mac_addr); 4337 if (is_valid_ether_addr(hw_mac_addr)) { 4338 *mac_from = "hardware"; 4339 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4340 return; 4341 } 4342 } 4343 4344 *mac_from = "random"; 4345 eth_hw_addr_random(dev); 4346 } 4347 4348 static void mvpp2_phylink_validate(struct net_device *dev, 4349 unsigned long *supported, 4350 struct phylink_link_state *state) 4351 { 4352 struct mvpp2_port *port = netdev_priv(dev); 4353 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4354 4355 /* Invalid combinations */ 4356 switch (state->interface) { 4357 case PHY_INTERFACE_MODE_10GKR: 4358 case PHY_INTERFACE_MODE_XAUI: 4359 if (port->gop_id != 0) 4360 goto empty_set; 4361 break; 4362 case PHY_INTERFACE_MODE_RGMII: 4363 case PHY_INTERFACE_MODE_RGMII_ID: 4364 case PHY_INTERFACE_MODE_RGMII_RXID: 4365 case PHY_INTERFACE_MODE_RGMII_TXID: 4366 if (port->gop_id == 0) 4367 goto empty_set; 4368 break; 4369 default: 4370 break; 4371 } 4372 4373 phylink_set(mask, Autoneg); 4374 phylink_set_port_modes(mask); 4375 phylink_set(mask, Pause); 4376 phylink_set(mask, Asym_Pause); 4377 4378 switch (state->interface) { 4379 case PHY_INTERFACE_MODE_10GKR: 4380 case PHY_INTERFACE_MODE_XAUI: 4381 case PHY_INTERFACE_MODE_NA: 4382 if (port->gop_id == 0) { 4383 phylink_set(mask, 10000baseT_Full); 4384 phylink_set(mask, 10000baseCR_Full); 4385 phylink_set(mask, 10000baseSR_Full); 4386 phylink_set(mask, 10000baseLR_Full); 4387 phylink_set(mask, 10000baseLRM_Full); 4388 phylink_set(mask, 10000baseER_Full); 4389 phylink_set(mask, 10000baseKR_Full); 4390 } 4391 /* Fall-through */ 4392 case PHY_INTERFACE_MODE_RGMII: 4393 case PHY_INTERFACE_MODE_RGMII_ID: 4394 case PHY_INTERFACE_MODE_RGMII_RXID: 4395 case PHY_INTERFACE_MODE_RGMII_TXID: 4396 case PHY_INTERFACE_MODE_SGMII: 4397 phylink_set(mask, 10baseT_Half); 4398 phylink_set(mask, 10baseT_Full); 4399 phylink_set(mask, 100baseT_Half); 4400 phylink_set(mask, 100baseT_Full); 4401 /* Fall-through */ 4402 case PHY_INTERFACE_MODE_1000BASEX: 4403 case PHY_INTERFACE_MODE_2500BASEX: 4404 phylink_set(mask, 1000baseT_Full); 4405 phylink_set(mask, 1000baseX_Full); 4406 phylink_set(mask, 2500baseX_Full); 4407 break; 4408 default: 4409 goto empty_set; 4410 } 4411 4412 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4413 bitmap_and(state->advertising, state->advertising, mask, 4414 __ETHTOOL_LINK_MODE_MASK_NBITS); 4415 return; 4416 4417 empty_set: 4418 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 4419 } 4420 4421 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4422 struct phylink_link_state *state) 4423 { 4424 u32 val; 4425 4426 state->speed = SPEED_10000; 4427 state->duplex = 1; 4428 state->an_complete = 1; 4429 4430 val = readl(port->base + MVPP22_XLG_STATUS); 4431 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4432 4433 state->pause = 0; 4434 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4435 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4436 state->pause |= MLO_PAUSE_TX; 4437 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4438 state->pause |= MLO_PAUSE_RX; 4439 } 4440 4441 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4442 struct phylink_link_state *state) 4443 { 4444 u32 val; 4445 4446 val = readl(port->base + MVPP2_GMAC_STATUS0); 4447 4448 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4449 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4450 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4451 4452 switch (port->phy_interface) { 4453 case PHY_INTERFACE_MODE_1000BASEX: 4454 state->speed = SPEED_1000; 4455 break; 4456 case PHY_INTERFACE_MODE_2500BASEX: 4457 state->speed = SPEED_2500; 4458 break; 4459 default: 4460 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4461 state->speed = SPEED_1000; 4462 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4463 state->speed = SPEED_100; 4464 else 4465 state->speed = SPEED_10; 4466 } 4467 4468 state->pause = 0; 4469 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4470 state->pause |= MLO_PAUSE_RX; 4471 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4472 state->pause |= MLO_PAUSE_TX; 4473 } 4474 4475 static int mvpp2_phylink_mac_link_state(struct net_device *dev, 4476 struct phylink_link_state *state) 4477 { 4478 struct mvpp2_port *port = netdev_priv(dev); 4479 4480 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4481 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4482 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4483 4484 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4485 mvpp22_xlg_link_state(port, state); 4486 return 1; 4487 } 4488 } 4489 4490 mvpp2_gmac_link_state(port, state); 4491 return 1; 4492 } 4493 4494 static void mvpp2_mac_an_restart(struct net_device *dev) 4495 { 4496 struct mvpp2_port *port = netdev_priv(dev); 4497 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4498 4499 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 4500 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4501 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 4502 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4503 } 4504 4505 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4506 const struct phylink_link_state *state) 4507 { 4508 u32 ctrl0, ctrl4; 4509 4510 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4511 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4512 4513 if (state->pause & MLO_PAUSE_TX) 4514 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4515 else 4516 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4517 4518 if (state->pause & MLO_PAUSE_RX) 4519 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4520 else 4521 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4522 4523 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4524 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4525 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4526 4527 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4528 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4529 } 4530 4531 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4532 const struct phylink_link_state *state) 4533 { 4534 u32 old_an, an; 4535 u32 old_ctrl0, ctrl0; 4536 u32 old_ctrl2, ctrl2; 4537 u32 old_ctrl4, ctrl4; 4538 4539 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4540 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4541 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4542 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4543 4544 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4545 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4546 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4547 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4548 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS); 4549 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4550 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK | 4551 MVPP2_GMAC_PCS_ENABLE_MASK); 4552 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4553 4554 /* Configure port type */ 4555 if (phy_interface_mode_is_8023z(state->interface)) { 4556 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 4557 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4558 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4559 MVPP22_CTRL4_DP_CLK_SEL | 4560 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4561 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4562 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 4563 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4564 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4565 MVPP22_CTRL4_DP_CLK_SEL | 4566 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4567 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4568 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4569 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4570 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4571 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4572 } 4573 4574 /* Configure advertisement bits */ 4575 if (phylink_test(state->advertising, Pause)) 4576 an |= MVPP2_GMAC_FC_ADV_EN; 4577 if (phylink_test(state->advertising, Asym_Pause)) 4578 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4579 4580 /* Configure negotiation style */ 4581 if (!phylink_autoneg_inband(mode)) { 4582 /* Phy or fixed speed - no in-band AN */ 4583 if (state->duplex) 4584 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4585 4586 if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 4587 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4588 else if (state->speed == SPEED_100) 4589 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4590 4591 if (state->pause & MLO_PAUSE_TX) 4592 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4593 if (state->pause & MLO_PAUSE_RX) 4594 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4595 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4596 /* SGMII in-band mode receives the speed and duplex from 4597 * the PHY. Flow control information is not received. */ 4598 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4599 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4600 MVPP2_GMAC_AN_SPEED_EN | 4601 MVPP2_GMAC_AN_DUPLEX_EN; 4602 4603 if (state->pause & MLO_PAUSE_TX) 4604 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4605 if (state->pause & MLO_PAUSE_RX) 4606 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4607 } else if (phy_interface_mode_is_8023z(state->interface)) { 4608 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4609 * they negotiate duplex: they are always operating with a fixed 4610 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4611 * speed and full duplex here. 4612 */ 4613 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4614 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4615 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4616 MVPP2_GMAC_CONFIG_GMII_SPEED | 4617 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4618 4619 if (state->pause & MLO_PAUSE_AN && state->an_enabled) { 4620 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4621 } else { 4622 if (state->pause & MLO_PAUSE_TX) 4623 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4624 if (state->pause & MLO_PAUSE_RX) 4625 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4626 } 4627 } 4628 4629 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK || 4630 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK || 4631 (old_an ^ an) & MVPP2_GMAC_IN_BAND_AUTONEG) { 4632 /* Force link down */ 4633 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4634 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4635 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4636 4637 /* Set the GMAC in a reset state - do this in a way that 4638 * ensures we clear it below. 4639 */ 4640 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4641 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4642 } 4643 4644 if (old_ctrl0 != ctrl0) 4645 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4646 if (old_ctrl2 != ctrl2) 4647 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4648 if (old_ctrl4 != ctrl4) 4649 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4650 if (old_an != an) 4651 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4652 4653 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) { 4654 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 4655 MVPP2_GMAC_PORT_RESET_MASK) 4656 continue; 4657 } 4658 } 4659 4660 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 4661 const struct phylink_link_state *state) 4662 { 4663 struct mvpp2_port *port = netdev_priv(dev); 4664 bool change_interface = port->phy_interface != state->interface; 4665 4666 /* Check for invalid configuration */ 4667 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) { 4668 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4669 return; 4670 } 4671 4672 /* Make sure the port is disabled when reconfiguring the mode */ 4673 mvpp2_port_disable(port); 4674 if (change_interface) { 4675 mvpp22_gop_mask_irq(port); 4676 4677 if (port->priv->hw_version == MVPP22) { 4678 port->phy_interface = state->interface; 4679 4680 /* Reconfigure the serdes lanes */ 4681 phy_power_off(port->comphy); 4682 mvpp22_mode_reconfigure(port); 4683 } 4684 } 4685 4686 /* mac (re)configuration */ 4687 if (mvpp2_is_xlg(state->interface)) 4688 mvpp2_xlg_config(port, mode, state); 4689 else if (phy_interface_mode_is_rgmii(state->interface) || 4690 phy_interface_mode_is_8023z(state->interface) || 4691 state->interface == PHY_INTERFACE_MODE_SGMII) 4692 mvpp2_gmac_config(port, mode, state); 4693 4694 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4695 mvpp2_port_loopback_set(port, state); 4696 4697 if (change_interface) 4698 mvpp22_gop_unmask_irq(port); 4699 4700 mvpp2_port_enable(port); 4701 } 4702 4703 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 4704 phy_interface_t interface, struct phy_device *phy) 4705 { 4706 struct mvpp2_port *port = netdev_priv(dev); 4707 u32 val; 4708 4709 if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) { 4710 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4711 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4712 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4713 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4714 } 4715 4716 mvpp2_port_enable(port); 4717 4718 mvpp2_egress_enable(port); 4719 mvpp2_ingress_enable(port); 4720 netif_tx_wake_all_queues(dev); 4721 } 4722 4723 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode, 4724 phy_interface_t interface) 4725 { 4726 struct mvpp2_port *port = netdev_priv(dev); 4727 u32 val; 4728 4729 if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) { 4730 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4731 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4732 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4733 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4734 } 4735 4736 netif_tx_stop_all_queues(dev); 4737 mvpp2_egress_disable(port); 4738 mvpp2_ingress_disable(port); 4739 4740 /* When using link interrupts to notify phylink of a MAC state change, 4741 * we do not want the port to be disabled (we want to receive further 4742 * interrupts, to be notified when the port will have a link later). 4743 */ 4744 if (!port->has_phy) 4745 return; 4746 4747 mvpp2_port_disable(port); 4748 } 4749 4750 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4751 .validate = mvpp2_phylink_validate, 4752 .mac_link_state = mvpp2_phylink_mac_link_state, 4753 .mac_an_restart = mvpp2_mac_an_restart, 4754 .mac_config = mvpp2_mac_config, 4755 .mac_link_up = mvpp2_mac_link_up, 4756 .mac_link_down = mvpp2_mac_link_down, 4757 }; 4758 4759 /* Ports initialization */ 4760 static int mvpp2_port_probe(struct platform_device *pdev, 4761 struct fwnode_handle *port_fwnode, 4762 struct mvpp2 *priv) 4763 { 4764 struct phy *comphy = NULL; 4765 struct mvpp2_port *port; 4766 struct mvpp2_port_pcpu *port_pcpu; 4767 struct device_node *port_node = to_of_node(port_fwnode); 4768 struct net_device *dev; 4769 struct resource *res; 4770 struct phylink *phylink; 4771 char *mac_from = ""; 4772 unsigned int ntxqs, nrxqs, thread; 4773 unsigned long flags = 0; 4774 bool has_tx_irqs; 4775 u32 id; 4776 int features; 4777 int phy_mode; 4778 int err, i; 4779 4780 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 4781 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 4782 dev_err(&pdev->dev, 4783 "not enough IRQs to support multi queue mode\n"); 4784 return -EINVAL; 4785 } 4786 4787 ntxqs = MVPP2_MAX_TXQ; 4788 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) 4789 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); 4790 else 4791 nrxqs = MVPP2_DEFAULT_RXQ; 4792 4793 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 4794 if (!dev) 4795 return -ENOMEM; 4796 4797 phy_mode = fwnode_get_phy_mode(port_fwnode); 4798 if (phy_mode < 0) { 4799 dev_err(&pdev->dev, "incorrect phy mode\n"); 4800 err = phy_mode; 4801 goto err_free_netdev; 4802 } 4803 4804 if (port_node) { 4805 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 4806 if (IS_ERR(comphy)) { 4807 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 4808 err = -EPROBE_DEFER; 4809 goto err_free_netdev; 4810 } 4811 comphy = NULL; 4812 } 4813 } 4814 4815 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 4816 err = -EINVAL; 4817 dev_err(&pdev->dev, "missing port-id value\n"); 4818 goto err_free_netdev; 4819 } 4820 4821 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 4822 dev->watchdog_timeo = 5 * HZ; 4823 dev->netdev_ops = &mvpp2_netdev_ops; 4824 dev->ethtool_ops = &mvpp2_eth_tool_ops; 4825 4826 port = netdev_priv(dev); 4827 port->dev = dev; 4828 port->fwnode = port_fwnode; 4829 port->has_phy = !!of_find_property(port_node, "phy", NULL); 4830 port->ntxqs = ntxqs; 4831 port->nrxqs = nrxqs; 4832 port->priv = priv; 4833 port->has_tx_irqs = has_tx_irqs; 4834 port->flags = flags; 4835 4836 err = mvpp2_queue_vectors_init(port, port_node); 4837 if (err) 4838 goto err_free_netdev; 4839 4840 if (port_node) 4841 port->link_irq = of_irq_get_byname(port_node, "link"); 4842 else 4843 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 4844 if (port->link_irq == -EPROBE_DEFER) { 4845 err = -EPROBE_DEFER; 4846 goto err_deinit_qvecs; 4847 } 4848 if (port->link_irq <= 0) 4849 /* the link irq is optional */ 4850 port->link_irq = 0; 4851 4852 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 4853 port->flags |= MVPP2_F_LOOPBACK; 4854 4855 port->id = id; 4856 if (priv->hw_version == MVPP21) 4857 port->first_rxq = port->id * port->nrxqs; 4858 else 4859 port->first_rxq = port->id * priv->max_port_rxqs; 4860 4861 port->of_node = port_node; 4862 port->phy_interface = phy_mode; 4863 port->comphy = comphy; 4864 4865 if (priv->hw_version == MVPP21) { 4866 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); 4867 port->base = devm_ioremap_resource(&pdev->dev, res); 4868 if (IS_ERR(port->base)) { 4869 err = PTR_ERR(port->base); 4870 goto err_free_irq; 4871 } 4872 4873 port->stats_base = port->priv->lms_base + 4874 MVPP21_MIB_COUNTERS_OFFSET + 4875 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 4876 } else { 4877 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 4878 &port->gop_id)) { 4879 err = -EINVAL; 4880 dev_err(&pdev->dev, "missing gop-port-id value\n"); 4881 goto err_deinit_qvecs; 4882 } 4883 4884 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 4885 port->stats_base = port->priv->iface_base + 4886 MVPP22_MIB_COUNTERS_OFFSET + 4887 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 4888 } 4889 4890 /* Alloc per-cpu and ethtool stats */ 4891 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 4892 if (!port->stats) { 4893 err = -ENOMEM; 4894 goto err_free_irq; 4895 } 4896 4897 port->ethtool_stats = devm_kcalloc(&pdev->dev, 4898 ARRAY_SIZE(mvpp2_ethtool_regs), 4899 sizeof(u64), GFP_KERNEL); 4900 if (!port->ethtool_stats) { 4901 err = -ENOMEM; 4902 goto err_free_stats; 4903 } 4904 4905 mutex_init(&port->gather_stats_lock); 4906 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 4907 4908 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 4909 4910 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 4911 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 4912 SET_NETDEV_DEV(dev, &pdev->dev); 4913 4914 err = mvpp2_port_init(port); 4915 if (err < 0) { 4916 dev_err(&pdev->dev, "failed to init port %d\n", id); 4917 goto err_free_stats; 4918 } 4919 4920 mvpp2_port_periodic_xon_disable(port); 4921 4922 mvpp2_port_reset(port); 4923 4924 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 4925 if (!port->pcpu) { 4926 err = -ENOMEM; 4927 goto err_free_txq_pcpu; 4928 } 4929 4930 if (!port->has_tx_irqs) { 4931 for (thread = 0; thread < priv->nthreads; thread++) { 4932 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4933 4934 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 4935 HRTIMER_MODE_REL_PINNED); 4936 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 4937 port_pcpu->timer_scheduled = false; 4938 4939 tasklet_init(&port_pcpu->tx_done_tasklet, 4940 mvpp2_tx_proc_cb, 4941 (unsigned long)dev); 4942 } 4943 } 4944 4945 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4946 NETIF_F_TSO; 4947 dev->features = features | NETIF_F_RXCSUM; 4948 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 4949 NETIF_F_HW_VLAN_CTAG_FILTER; 4950 4951 if (mvpp22_rss_is_supported()) 4952 dev->hw_features |= NETIF_F_RXHASH; 4953 4954 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 4955 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4956 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4957 } 4958 4959 dev->vlan_features |= features; 4960 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 4961 dev->priv_flags |= IFF_UNICAST_FLT; 4962 4963 /* MTU range: 68 - 9704 */ 4964 dev->min_mtu = ETH_MIN_MTU; 4965 /* 9704 == 9728 - 20 and rounding to 8 */ 4966 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 4967 dev->dev.of_node = port_node; 4968 4969 /* Phylink isn't used w/ ACPI as of now */ 4970 if (port_node) { 4971 phylink = phylink_create(dev, port_fwnode, phy_mode, 4972 &mvpp2_phylink_ops); 4973 if (IS_ERR(phylink)) { 4974 err = PTR_ERR(phylink); 4975 goto err_free_port_pcpu; 4976 } 4977 port->phylink = phylink; 4978 } else { 4979 port->phylink = NULL; 4980 } 4981 4982 err = register_netdev(dev); 4983 if (err < 0) { 4984 dev_err(&pdev->dev, "failed to register netdev\n"); 4985 goto err_phylink; 4986 } 4987 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 4988 4989 priv->port_list[priv->port_count++] = port; 4990 4991 return 0; 4992 4993 err_phylink: 4994 if (port->phylink) 4995 phylink_destroy(port->phylink); 4996 err_free_port_pcpu: 4997 free_percpu(port->pcpu); 4998 err_free_txq_pcpu: 4999 for (i = 0; i < port->ntxqs; i++) 5000 free_percpu(port->txqs[i]->pcpu); 5001 err_free_stats: 5002 free_percpu(port->stats); 5003 err_free_irq: 5004 if (port->link_irq) 5005 irq_dispose_mapping(port->link_irq); 5006 err_deinit_qvecs: 5007 mvpp2_queue_vectors_deinit(port); 5008 err_free_netdev: 5009 free_netdev(dev); 5010 return err; 5011 } 5012 5013 /* Ports removal routine */ 5014 static void mvpp2_port_remove(struct mvpp2_port *port) 5015 { 5016 int i; 5017 5018 unregister_netdev(port->dev); 5019 if (port->phylink) 5020 phylink_destroy(port->phylink); 5021 free_percpu(port->pcpu); 5022 free_percpu(port->stats); 5023 for (i = 0; i < port->ntxqs; i++) 5024 free_percpu(port->txqs[i]->pcpu); 5025 mvpp2_queue_vectors_deinit(port); 5026 if (port->link_irq) 5027 irq_dispose_mapping(port->link_irq); 5028 free_netdev(port->dev); 5029 } 5030 5031 /* Initialize decoding windows */ 5032 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 5033 struct mvpp2 *priv) 5034 { 5035 u32 win_enable; 5036 int i; 5037 5038 for (i = 0; i < 6; i++) { 5039 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 5040 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 5041 5042 if (i < 4) 5043 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 5044 } 5045 5046 win_enable = 0; 5047 5048 for (i = 0; i < dram->num_cs; i++) { 5049 const struct mbus_dram_window *cs = dram->cs + i; 5050 5051 mvpp2_write(priv, MVPP2_WIN_BASE(i), 5052 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 5053 dram->mbus_dram_target_id); 5054 5055 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 5056 (cs->size - 1) & 0xffff0000); 5057 5058 win_enable |= (1 << i); 5059 } 5060 5061 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 5062 } 5063 5064 /* Initialize Rx FIFO's */ 5065 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 5066 { 5067 int port; 5068 5069 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5070 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5071 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5072 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5073 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5074 } 5075 5076 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5077 MVPP2_RX_FIFO_PORT_MIN_PKT); 5078 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5079 } 5080 5081 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 5082 { 5083 int port; 5084 5085 /* The FIFO size parameters are set depending on the maximum speed a 5086 * given port can handle: 5087 * - Port 0: 10Gbps 5088 * - Port 1: 2.5Gbps 5089 * - Ports 2 and 3: 1Gbps 5090 */ 5091 5092 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 5093 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 5094 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 5095 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 5096 5097 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 5098 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 5099 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 5100 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 5101 5102 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 5103 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5104 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5105 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5106 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5107 } 5108 5109 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5110 MVPP2_RX_FIFO_PORT_MIN_PKT); 5111 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5112 } 5113 5114 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 5115 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 5116 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 5117 */ 5118 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 5119 { 5120 int port, size, thrs; 5121 5122 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5123 if (port == 0) { 5124 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 5125 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 5126 } else { 5127 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 5128 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 5129 } 5130 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 5131 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 5132 } 5133 } 5134 5135 static void mvpp2_axi_init(struct mvpp2 *priv) 5136 { 5137 u32 val, rdval, wrval; 5138 5139 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 5140 5141 /* AXI Bridge Configuration */ 5142 5143 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 5144 << MVPP22_AXI_ATTR_CACHE_OFFS; 5145 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5146 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5147 5148 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 5149 << MVPP22_AXI_ATTR_CACHE_OFFS; 5150 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5151 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5152 5153 /* BM */ 5154 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 5155 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 5156 5157 /* Descriptors */ 5158 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 5159 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 5160 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 5161 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 5162 5163 /* Buffer Data */ 5164 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 5165 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 5166 5167 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 5168 << MVPP22_AXI_CODE_CACHE_OFFS; 5169 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 5170 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5171 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 5172 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 5173 5174 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 5175 << MVPP22_AXI_CODE_CACHE_OFFS; 5176 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5177 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5178 5179 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 5180 5181 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 5182 << MVPP22_AXI_CODE_CACHE_OFFS; 5183 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5184 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5185 5186 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 5187 } 5188 5189 /* Initialize network controller common part HW */ 5190 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 5191 { 5192 const struct mbus_dram_target_info *dram_target_info; 5193 int err, i; 5194 u32 val; 5195 5196 /* MBUS windows configuration */ 5197 dram_target_info = mv_mbus_dram_info(); 5198 if (dram_target_info) 5199 mvpp2_conf_mbus_windows(dram_target_info, priv); 5200 5201 if (priv->hw_version == MVPP22) 5202 mvpp2_axi_init(priv); 5203 5204 /* Disable HW PHY polling */ 5205 if (priv->hw_version == MVPP21) { 5206 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5207 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 5208 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5209 } else { 5210 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5211 val &= ~MVPP22_SMI_POLLING_EN; 5212 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5213 } 5214 5215 /* Allocate and initialize aggregated TXQs */ 5216 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 5217 sizeof(*priv->aggr_txqs), 5218 GFP_KERNEL); 5219 if (!priv->aggr_txqs) 5220 return -ENOMEM; 5221 5222 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5223 priv->aggr_txqs[i].id = i; 5224 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 5225 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 5226 if (err < 0) 5227 return err; 5228 } 5229 5230 /* Fifo Init */ 5231 if (priv->hw_version == MVPP21) { 5232 mvpp2_rx_fifo_init(priv); 5233 } else { 5234 mvpp22_rx_fifo_init(priv); 5235 mvpp22_tx_fifo_init(priv); 5236 } 5237 5238 if (priv->hw_version == MVPP21) 5239 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 5240 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 5241 5242 /* Allow cache snoop when transmiting packets */ 5243 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 5244 5245 /* Buffer Manager initialization */ 5246 err = mvpp2_bm_init(pdev, priv); 5247 if (err < 0) 5248 return err; 5249 5250 /* Parser default initialization */ 5251 err = mvpp2_prs_default_init(pdev, priv); 5252 if (err < 0) 5253 return err; 5254 5255 /* Classifier default initialization */ 5256 mvpp2_cls_init(priv); 5257 5258 return 0; 5259 } 5260 5261 static int mvpp2_probe(struct platform_device *pdev) 5262 { 5263 const struct acpi_device_id *acpi_id; 5264 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5265 struct fwnode_handle *port_fwnode; 5266 struct mvpp2 *priv; 5267 struct resource *res; 5268 void __iomem *base; 5269 int i, shared; 5270 int err; 5271 5272 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5273 if (!priv) 5274 return -ENOMEM; 5275 5276 if (has_acpi_companion(&pdev->dev)) { 5277 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5278 &pdev->dev); 5279 if (!acpi_id) 5280 return -EINVAL; 5281 priv->hw_version = (unsigned long)acpi_id->driver_data; 5282 } else { 5283 priv->hw_version = 5284 (unsigned long)of_device_get_match_data(&pdev->dev); 5285 } 5286 5287 /* multi queue mode isn't supported on PPV2.1, fallback to single 5288 * mode 5289 */ 5290 if (priv->hw_version == MVPP21) 5291 queue_mode = MVPP2_QDIST_SINGLE_MODE; 5292 5293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5294 base = devm_ioremap_resource(&pdev->dev, res); 5295 if (IS_ERR(base)) 5296 return PTR_ERR(base); 5297 5298 if (priv->hw_version == MVPP21) { 5299 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5300 priv->lms_base = devm_ioremap_resource(&pdev->dev, res); 5301 if (IS_ERR(priv->lms_base)) 5302 return PTR_ERR(priv->lms_base); 5303 } else { 5304 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5305 if (has_acpi_companion(&pdev->dev)) { 5306 /* In case the MDIO memory region is declared in 5307 * the ACPI, it can already appear as 'in-use' 5308 * in the OS. Because it is overlapped by second 5309 * region of the network controller, make 5310 * sure it is released, before requesting it again. 5311 * The care is taken by mvpp2 driver to avoid 5312 * concurrent access to this memory region. 5313 */ 5314 release_resource(res); 5315 } 5316 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5317 if (IS_ERR(priv->iface_base)) 5318 return PTR_ERR(priv->iface_base); 5319 } 5320 5321 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5322 priv->sysctrl_base = 5323 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5324 "marvell,system-controller"); 5325 if (IS_ERR(priv->sysctrl_base)) 5326 /* The system controller regmap is optional for dt 5327 * compatibility reasons. When not provided, the 5328 * configuration of the GoP relies on the 5329 * firmware/bootloader. 5330 */ 5331 priv->sysctrl_base = NULL; 5332 } 5333 5334 mvpp2_setup_bm_pool(); 5335 5336 5337 priv->nthreads = min_t(unsigned int, num_present_cpus(), 5338 MVPP2_MAX_THREADS); 5339 5340 shared = num_present_cpus() - priv->nthreads; 5341 if (shared > 0) 5342 bitmap_fill(&priv->lock_map, 5343 min_t(int, shared, MVPP2_MAX_THREADS)); 5344 5345 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5346 u32 addr_space_sz; 5347 5348 addr_space_sz = (priv->hw_version == MVPP21 ? 5349 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5350 priv->swth_base[i] = base + i * addr_space_sz; 5351 } 5352 5353 if (priv->hw_version == MVPP21) 5354 priv->max_port_rxqs = 8; 5355 else 5356 priv->max_port_rxqs = 32; 5357 5358 if (dev_of_node(&pdev->dev)) { 5359 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5360 if (IS_ERR(priv->pp_clk)) 5361 return PTR_ERR(priv->pp_clk); 5362 err = clk_prepare_enable(priv->pp_clk); 5363 if (err < 0) 5364 return err; 5365 5366 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5367 if (IS_ERR(priv->gop_clk)) { 5368 err = PTR_ERR(priv->gop_clk); 5369 goto err_pp_clk; 5370 } 5371 err = clk_prepare_enable(priv->gop_clk); 5372 if (err < 0) 5373 goto err_pp_clk; 5374 5375 if (priv->hw_version == MVPP22) { 5376 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5377 if (IS_ERR(priv->mg_clk)) { 5378 err = PTR_ERR(priv->mg_clk); 5379 goto err_gop_clk; 5380 } 5381 5382 err = clk_prepare_enable(priv->mg_clk); 5383 if (err < 0) 5384 goto err_gop_clk; 5385 5386 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5387 if (IS_ERR(priv->mg_core_clk)) { 5388 priv->mg_core_clk = NULL; 5389 } else { 5390 err = clk_prepare_enable(priv->mg_core_clk); 5391 if (err < 0) 5392 goto err_mg_clk; 5393 } 5394 } 5395 5396 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5397 if (IS_ERR(priv->axi_clk)) { 5398 err = PTR_ERR(priv->axi_clk); 5399 if (err == -EPROBE_DEFER) 5400 goto err_mg_core_clk; 5401 priv->axi_clk = NULL; 5402 } else { 5403 err = clk_prepare_enable(priv->axi_clk); 5404 if (err < 0) 5405 goto err_mg_core_clk; 5406 } 5407 5408 /* Get system's tclk rate */ 5409 priv->tclk = clk_get_rate(priv->pp_clk); 5410 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5411 &priv->tclk)) { 5412 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5413 return -EINVAL; 5414 } 5415 5416 if (priv->hw_version == MVPP22) { 5417 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5418 if (err) 5419 goto err_axi_clk; 5420 /* Sadly, the BM pools all share the same register to 5421 * store the high 32 bits of their address. So they 5422 * must all have the same high 32 bits, which forces 5423 * us to restrict coherent memory to DMA_BIT_MASK(32). 5424 */ 5425 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5426 if (err) 5427 goto err_axi_clk; 5428 } 5429 5430 /* Initialize network controller */ 5431 err = mvpp2_init(pdev, priv); 5432 if (err < 0) { 5433 dev_err(&pdev->dev, "failed to initialize controller\n"); 5434 goto err_axi_clk; 5435 } 5436 5437 /* Initialize ports */ 5438 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5439 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5440 if (err < 0) 5441 goto err_port_probe; 5442 } 5443 5444 if (priv->port_count == 0) { 5445 dev_err(&pdev->dev, "no ports enabled\n"); 5446 err = -ENODEV; 5447 goto err_axi_clk; 5448 } 5449 5450 /* Statistics must be gathered regularly because some of them (like 5451 * packets counters) are 32-bit registers and could overflow quite 5452 * quickly. For instance, a 10Gb link used at full bandwidth with the 5453 * smallest packets (64B) will overflow a 32-bit counter in less than 5454 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5455 */ 5456 snprintf(priv->queue_name, sizeof(priv->queue_name), 5457 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5458 priv->port_count > 1 ? "+" : ""); 5459 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5460 if (!priv->stats_queue) { 5461 err = -ENOMEM; 5462 goto err_port_probe; 5463 } 5464 5465 mvpp2_dbgfs_init(priv, pdev->name); 5466 5467 platform_set_drvdata(pdev, priv); 5468 return 0; 5469 5470 err_port_probe: 5471 i = 0; 5472 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5473 if (priv->port_list[i]) 5474 mvpp2_port_remove(priv->port_list[i]); 5475 i++; 5476 } 5477 err_axi_clk: 5478 clk_disable_unprepare(priv->axi_clk); 5479 5480 err_mg_core_clk: 5481 if (priv->hw_version == MVPP22) 5482 clk_disable_unprepare(priv->mg_core_clk); 5483 err_mg_clk: 5484 if (priv->hw_version == MVPP22) 5485 clk_disable_unprepare(priv->mg_clk); 5486 err_gop_clk: 5487 clk_disable_unprepare(priv->gop_clk); 5488 err_pp_clk: 5489 clk_disable_unprepare(priv->pp_clk); 5490 return err; 5491 } 5492 5493 static int mvpp2_remove(struct platform_device *pdev) 5494 { 5495 struct mvpp2 *priv = platform_get_drvdata(pdev); 5496 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5497 struct fwnode_handle *port_fwnode; 5498 int i = 0; 5499 5500 mvpp2_dbgfs_cleanup(priv); 5501 5502 flush_workqueue(priv->stats_queue); 5503 destroy_workqueue(priv->stats_queue); 5504 5505 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5506 if (priv->port_list[i]) { 5507 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5508 mvpp2_port_remove(priv->port_list[i]); 5509 } 5510 i++; 5511 } 5512 5513 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5514 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5515 5516 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5517 } 5518 5519 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5520 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5521 5522 dma_free_coherent(&pdev->dev, 5523 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5524 aggr_txq->descs, 5525 aggr_txq->descs_dma); 5526 } 5527 5528 if (is_acpi_node(port_fwnode)) 5529 return 0; 5530 5531 clk_disable_unprepare(priv->axi_clk); 5532 clk_disable_unprepare(priv->mg_core_clk); 5533 clk_disable_unprepare(priv->mg_clk); 5534 clk_disable_unprepare(priv->pp_clk); 5535 clk_disable_unprepare(priv->gop_clk); 5536 5537 return 0; 5538 } 5539 5540 static const struct of_device_id mvpp2_match[] = { 5541 { 5542 .compatible = "marvell,armada-375-pp2", 5543 .data = (void *)MVPP21, 5544 }, 5545 { 5546 .compatible = "marvell,armada-7k-pp22", 5547 .data = (void *)MVPP22, 5548 }, 5549 { } 5550 }; 5551 MODULE_DEVICE_TABLE(of, mvpp2_match); 5552 5553 static const struct acpi_device_id mvpp2_acpi_match[] = { 5554 { "MRVL0110", MVPP22 }, 5555 { }, 5556 }; 5557 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5558 5559 static struct platform_driver mvpp2_driver = { 5560 .probe = mvpp2_probe, 5561 .remove = mvpp2_remove, 5562 .driver = { 5563 .name = MVPP2_DRIVER_NAME, 5564 .of_match_table = mvpp2_match, 5565 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5566 }, 5567 }; 5568 5569 module_platform_driver(mvpp2_driver); 5570 5571 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5572 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5573 MODULE_LICENSE("GPL v2"); 5574