1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 40 #include "mvpp2.h" 41 #include "mvpp2_prs.h" 42 #include "mvpp2_cls.h" 43 44 enum mvpp2_bm_pool_log_num { 45 MVPP2_BM_SHORT, 46 MVPP2_BM_LONG, 47 MVPP2_BM_JUMBO, 48 MVPP2_BM_POOLS_NUM 49 }; 50 51 static struct { 52 int pkt_size; 53 int buf_num; 54 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 55 56 /* The prototype is added here to be used in start_dev when using ACPI. This 57 * will be removed once phylink is used for all modes (dt+ACPI). 58 */ 59 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 60 const struct phylink_link_state *state); 61 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 62 phy_interface_t interface, struct phy_device *phy); 63 64 /* Queue modes */ 65 #define MVPP2_QDIST_SINGLE_MODE 0 66 #define MVPP2_QDIST_MULTI_MODE 1 67 68 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 69 70 module_param(queue_mode, int, 0444); 71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 72 73 /* Utility/helper methods */ 74 75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 76 { 77 writel(data, priv->swth_base[0] + offset); 78 } 79 80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 81 { 82 return readl(priv->swth_base[0] + offset); 83 } 84 85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 86 { 87 return readl_relaxed(priv->swth_base[0] + offset); 88 } 89 90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 91 { 92 return cpu % priv->nthreads; 93 } 94 95 /* These accessors should be used to access: 96 * 97 * - per-thread registers, where each thread has its own copy of the 98 * register. 99 * 100 * MVPP2_BM_VIRT_ALLOC_REG 101 * MVPP2_BM_ADDR_HIGH_ALLOC 102 * MVPP22_BM_ADDR_HIGH_RLS_REG 103 * MVPP2_BM_VIRT_RLS_REG 104 * MVPP2_ISR_RX_TX_CAUSE_REG 105 * MVPP2_ISR_RX_TX_MASK_REG 106 * MVPP2_TXQ_NUM_REG 107 * MVPP2_AGGR_TXQ_UPDATE_REG 108 * MVPP2_TXQ_RSVD_REQ_REG 109 * MVPP2_TXQ_RSVD_RSLT_REG 110 * MVPP2_TXQ_SENT_REG 111 * MVPP2_RXQ_NUM_REG 112 * 113 * - global registers that must be accessed through a specific thread 114 * window, because they are related to an access to a per-thread 115 * register 116 * 117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 130 */ 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 132 u32 offset, u32 data) 133 { 134 writel(data, priv->swth_base[thread] + offset); 135 } 136 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 138 u32 offset) 139 { 140 return readl(priv->swth_base[thread] + offset); 141 } 142 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 144 u32 offset, u32 data) 145 { 146 writel_relaxed(data, priv->swth_base[thread] + offset); 147 } 148 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 150 u32 offset) 151 { 152 return readl_relaxed(priv->swth_base[thread] + offset); 153 } 154 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 156 struct mvpp2_tx_desc *tx_desc) 157 { 158 if (port->priv->hw_version == MVPP21) 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 160 else 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 162 MVPP2_DESC_DMA_MASK; 163 } 164 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 166 struct mvpp2_tx_desc *tx_desc, 167 dma_addr_t dma_addr) 168 { 169 dma_addr_t addr, offset; 170 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 172 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 173 174 if (port->priv->hw_version == MVPP21) { 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 176 tx_desc->pp21.packet_offset = offset; 177 } else { 178 __le64 val = cpu_to_le64(addr); 179 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 181 tx_desc->pp22.buf_dma_addr_ptp |= val; 182 tx_desc->pp22.packet_offset = offset; 183 } 184 } 185 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 187 struct mvpp2_tx_desc *tx_desc) 188 { 189 if (port->priv->hw_version == MVPP21) 190 return le16_to_cpu(tx_desc->pp21.data_size); 191 else 192 return le16_to_cpu(tx_desc->pp22.data_size); 193 } 194 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 196 struct mvpp2_tx_desc *tx_desc, 197 size_t size) 198 { 199 if (port->priv->hw_version == MVPP21) 200 tx_desc->pp21.data_size = cpu_to_le16(size); 201 else 202 tx_desc->pp22.data_size = cpu_to_le16(size); 203 } 204 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 206 struct mvpp2_tx_desc *tx_desc, 207 unsigned int txq) 208 { 209 if (port->priv->hw_version == MVPP21) 210 tx_desc->pp21.phys_txq = txq; 211 else 212 tx_desc->pp22.phys_txq = txq; 213 } 214 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 216 struct mvpp2_tx_desc *tx_desc, 217 unsigned int command) 218 { 219 if (port->priv->hw_version == MVPP21) 220 tx_desc->pp21.command = cpu_to_le32(command); 221 else 222 tx_desc->pp22.command = cpu_to_le32(command); 223 } 224 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 226 struct mvpp2_tx_desc *tx_desc) 227 { 228 if (port->priv->hw_version == MVPP21) 229 return tx_desc->pp21.packet_offset; 230 else 231 return tx_desc->pp22.packet_offset; 232 } 233 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 235 struct mvpp2_rx_desc *rx_desc) 236 { 237 if (port->priv->hw_version == MVPP21) 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 239 else 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 241 MVPP2_DESC_DMA_MASK; 242 } 243 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 245 struct mvpp2_rx_desc *rx_desc) 246 { 247 if (port->priv->hw_version == MVPP21) 248 return le32_to_cpu(rx_desc->pp21.buf_cookie); 249 else 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 251 MVPP2_DESC_DMA_MASK; 252 } 253 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 255 struct mvpp2_rx_desc *rx_desc) 256 { 257 if (port->priv->hw_version == MVPP21) 258 return le16_to_cpu(rx_desc->pp21.data_size); 259 else 260 return le16_to_cpu(rx_desc->pp22.data_size); 261 } 262 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 264 struct mvpp2_rx_desc *rx_desc) 265 { 266 if (port->priv->hw_version == MVPP21) 267 return le32_to_cpu(rx_desc->pp21.status); 268 else 269 return le32_to_cpu(rx_desc->pp22.status); 270 } 271 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 273 { 274 txq_pcpu->txq_get_index++; 275 if (txq_pcpu->txq_get_index == txq_pcpu->size) 276 txq_pcpu->txq_get_index = 0; 277 } 278 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 280 struct mvpp2_txq_pcpu *txq_pcpu, 281 struct sk_buff *skb, 282 struct mvpp2_tx_desc *tx_desc) 283 { 284 struct mvpp2_txq_pcpu_buf *tx_buf = 285 txq_pcpu->buffs + txq_pcpu->txq_put_index; 286 tx_buf->skb = skb; 287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 289 mvpp2_txdesc_offset_get(port, tx_desc); 290 txq_pcpu->txq_put_index++; 291 if (txq_pcpu->txq_put_index == txq_pcpu->size) 292 txq_pcpu->txq_put_index = 0; 293 } 294 295 /* Get number of physical egress port */ 296 static inline int mvpp2_egress_port(struct mvpp2_port *port) 297 { 298 return MVPP2_MAX_TCONT + port->id; 299 } 300 301 /* Get number of physical TXQ */ 302 static inline int mvpp2_txq_phys(int port, int txq) 303 { 304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 305 } 306 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 return netdev_alloc_frag(pool->frag_size); 311 else 312 return kmalloc(pool->frag_size, GFP_ATOMIC); 313 } 314 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 316 { 317 if (likely(pool->frag_size <= PAGE_SIZE)) 318 skb_free_frag(data); 319 else 320 kfree(data); 321 } 322 323 /* Buffer Manager configuration routines */ 324 325 /* Create pool */ 326 static int mvpp2_bm_pool_create(struct platform_device *pdev, 327 struct mvpp2 *priv, 328 struct mvpp2_bm_pool *bm_pool, int size) 329 { 330 u32 val; 331 332 /* Number of buffer pointers must be a multiple of 16, as per 333 * hardware constraints 334 */ 335 if (!IS_ALIGNED(size, 16)) 336 return -EINVAL; 337 338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 339 * bytes per buffer pointer 340 */ 341 if (priv->hw_version == MVPP21) 342 bm_pool->size_bytes = 2 * sizeof(u32) * size; 343 else 344 bm_pool->size_bytes = 2 * sizeof(u64) * size; 345 346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 347 &bm_pool->dma_addr, 348 GFP_KERNEL); 349 if (!bm_pool->virt_addr) 350 return -ENOMEM; 351 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 353 MVPP2_BM_POOL_PTR_ALIGN)) { 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 355 bm_pool->virt_addr, bm_pool->dma_addr); 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 358 return -ENOMEM; 359 } 360 361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 362 lower_32_bits(bm_pool->dma_addr)); 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 364 365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 366 val |= MVPP2_BM_START_MASK; 367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 368 369 bm_pool->size = size; 370 bm_pool->pkt_size = 0; 371 bm_pool->buf_num = 0; 372 373 return 0; 374 } 375 376 /* Set pool buffer size */ 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 378 struct mvpp2_bm_pool *bm_pool, 379 int buf_size) 380 { 381 u32 val; 382 383 bm_pool->buf_size = buf_size; 384 385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 387 } 388 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 390 struct mvpp2_bm_pool *bm_pool, 391 dma_addr_t *dma_addr, 392 phys_addr_t *phys_addr) 393 { 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 395 396 *dma_addr = mvpp2_thread_read(priv, thread, 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 399 400 if (priv->hw_version == MVPP22) { 401 u32 val; 402 u32 dma_addr_highbits, phys_addr_highbits; 403 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 408 409 if (sizeof(dma_addr_t) == 8) 410 *dma_addr |= (u64)dma_addr_highbits << 32; 411 412 if (sizeof(phys_addr_t) == 8) 413 *phys_addr |= (u64)phys_addr_highbits << 32; 414 } 415 416 put_cpu(); 417 } 418 419 /* Free all buffers from the pool */ 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 421 struct mvpp2_bm_pool *bm_pool, int buf_num) 422 { 423 int i; 424 425 if (buf_num > bm_pool->buf_num) { 426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 427 bm_pool->id, buf_num); 428 buf_num = bm_pool->buf_num; 429 } 430 431 for (i = 0; i < buf_num; i++) { 432 dma_addr_t buf_dma_addr; 433 phys_addr_t buf_phys_addr; 434 void *data; 435 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 437 &buf_dma_addr, &buf_phys_addr); 438 439 dma_unmap_single(dev, buf_dma_addr, 440 bm_pool->buf_size, DMA_FROM_DEVICE); 441 442 data = (void *)phys_to_virt(buf_phys_addr); 443 if (!data) 444 break; 445 446 mvpp2_frag_free(bm_pool, data); 447 } 448 449 /* Update BM driver with number of buffers removed from pool */ 450 bm_pool->buf_num -= i; 451 } 452 453 /* Check number of buffers in BM pool */ 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 455 { 456 int buf_num = 0; 457 458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 459 MVPP22_BM_POOL_PTRS_NUM_MASK; 460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 461 MVPP2_BM_BPPI_PTR_NUM_MASK; 462 463 /* HW has one buffer ready which is not reflected in the counters */ 464 if (buf_num) 465 buf_num += 1; 466 467 return buf_num; 468 } 469 470 /* Cleanup pool */ 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 472 struct mvpp2 *priv, 473 struct mvpp2_bm_pool *bm_pool) 474 { 475 int buf_num; 476 u32 val; 477 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 480 481 /* Check buffer counters after free */ 482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 483 if (buf_num) { 484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 485 bm_pool->id, bm_pool->buf_num); 486 return 0; 487 } 488 489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 490 val |= MVPP2_BM_STOP_MASK; 491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 492 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 494 bm_pool->virt_addr, 495 bm_pool->dma_addr); 496 return 0; 497 } 498 499 static int mvpp2_bm_pools_init(struct platform_device *pdev, 500 struct mvpp2 *priv) 501 { 502 int i, err, size; 503 struct mvpp2_bm_pool *bm_pool; 504 505 /* Create all pools with maximum size */ 506 size = MVPP2_BM_POOL_SIZE_MAX; 507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 508 bm_pool = &priv->bm_pools[i]; 509 bm_pool->id = i; 510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 511 if (err) 512 goto err_unroll_pools; 513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 514 } 515 return 0; 516 517 err_unroll_pools: 518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 519 for (i = i - 1; i >= 0; i--) 520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 521 return err; 522 } 523 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 525 { 526 int i, err; 527 528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 529 /* Mask BM all interrupts */ 530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 531 /* Clear BM cause register */ 532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 533 } 534 535 /* Allocate and initialize BM pools */ 536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 537 sizeof(*priv->bm_pools), GFP_KERNEL); 538 if (!priv->bm_pools) 539 return -ENOMEM; 540 541 err = mvpp2_bm_pools_init(pdev, priv); 542 if (err < 0) 543 return err; 544 return 0; 545 } 546 547 static void mvpp2_setup_bm_pool(void) 548 { 549 /* Short pool */ 550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 552 553 /* Long pool */ 554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 556 557 /* Jumbo pool */ 558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 560 } 561 562 /* Attach long pool to rxq */ 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 564 int lrxq, int long_pool) 565 { 566 u32 val, mask; 567 int prxq; 568 569 /* Get queue physical ID */ 570 prxq = port->rxqs[lrxq]->id; 571 572 if (port->priv->hw_version == MVPP21) 573 mask = MVPP21_RXQ_POOL_LONG_MASK; 574 else 575 mask = MVPP22_RXQ_POOL_LONG_MASK; 576 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 578 val &= ~mask; 579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 581 } 582 583 /* Attach short pool to rxq */ 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 585 int lrxq, int short_pool) 586 { 587 u32 val, mask; 588 int prxq; 589 590 /* Get queue physical ID */ 591 prxq = port->rxqs[lrxq]->id; 592 593 if (port->priv->hw_version == MVPP21) 594 mask = MVPP21_RXQ_POOL_SHORT_MASK; 595 else 596 mask = MVPP22_RXQ_POOL_SHORT_MASK; 597 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 599 val &= ~mask; 600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 602 } 603 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 605 struct mvpp2_bm_pool *bm_pool, 606 dma_addr_t *buf_dma_addr, 607 phys_addr_t *buf_phys_addr, 608 gfp_t gfp_mask) 609 { 610 dma_addr_t dma_addr; 611 void *data; 612 613 data = mvpp2_frag_alloc(bm_pool); 614 if (!data) 615 return NULL; 616 617 dma_addr = dma_map_single(port->dev->dev.parent, data, 618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 619 DMA_FROM_DEVICE); 620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 621 mvpp2_frag_free(bm_pool, data); 622 return NULL; 623 } 624 *buf_dma_addr = dma_addr; 625 *buf_phys_addr = virt_to_phys(data); 626 627 return data; 628 } 629 630 /* Release buffer to BM */ 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 632 dma_addr_t buf_dma_addr, 633 phys_addr_t buf_phys_addr) 634 { 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 636 unsigned long flags = 0; 637 638 if (test_bit(thread, &port->priv->lock_map)) 639 spin_lock_irqsave(&port->bm_lock[thread], flags); 640 641 if (port->priv->hw_version == MVPP22) { 642 u32 val = 0; 643 644 if (sizeof(dma_addr_t) == 8) 645 val |= upper_32_bits(buf_dma_addr) & 646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 647 648 if (sizeof(phys_addr_t) == 8) 649 val |= (upper_32_bits(buf_phys_addr) 650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 652 653 mvpp2_thread_write_relaxed(port->priv, thread, 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 655 } 656 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 658 * returned in the "cookie" field of the RX 659 * descriptor. Instead of storing the virtual address, we 660 * store the physical address 661 */ 662 mvpp2_thread_write_relaxed(port->priv, thread, 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 664 mvpp2_thread_write_relaxed(port->priv, thread, 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 666 667 if (test_bit(thread, &port->priv->lock_map)) 668 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 669 670 put_cpu(); 671 } 672 673 /* Allocate buffers for the pool */ 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 675 struct mvpp2_bm_pool *bm_pool, int buf_num) 676 { 677 int i, buf_size, total_size; 678 dma_addr_t dma_addr; 679 phys_addr_t phys_addr; 680 void *buf; 681 682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 684 685 if (buf_num < 0 || 686 (buf_num + bm_pool->buf_num > bm_pool->size)) { 687 netdev_err(port->dev, 688 "cannot allocate %d buffers for pool %d\n", 689 buf_num, bm_pool->id); 690 return 0; 691 } 692 693 for (i = 0; i < buf_num; i++) { 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 695 &phys_addr, GFP_KERNEL); 696 if (!buf) 697 break; 698 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 700 phys_addr); 701 } 702 703 /* Update BM driver with number of buffers added to pool */ 704 bm_pool->buf_num += i; 705 706 netdev_dbg(port->dev, 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 709 710 netdev_dbg(port->dev, 711 "pool %d: %d of %d buffers added\n", 712 bm_pool->id, i, buf_num); 713 return i; 714 } 715 716 /* Notify the driver that BM pool is being used as specific type and return the 717 * pool pointer on success 718 */ 719 static struct mvpp2_bm_pool * 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 721 { 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 723 int num; 724 725 if (pool >= MVPP2_BM_POOLS_NUM) { 726 netdev_err(port->dev, "Invalid pool %d\n", pool); 727 return NULL; 728 } 729 730 /* Allocate buffers in case BM pool is used as long pool, but packet 731 * size doesn't match MTU or BM pool hasn't being used yet 732 */ 733 if (new_pool->pkt_size == 0) { 734 int pkts_num; 735 736 /* Set default buffer number or free all the buffers in case 737 * the pool is not empty 738 */ 739 pkts_num = new_pool->buf_num; 740 if (pkts_num == 0) 741 pkts_num = mvpp2_pools[pool].buf_num; 742 else 743 mvpp2_bm_bufs_free(port->dev->dev.parent, 744 port->priv, new_pool, pkts_num); 745 746 new_pool->pkt_size = pkt_size; 747 new_pool->frag_size = 748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 749 MVPP2_SKB_SHINFO_SIZE; 750 751 /* Allocate buffers for this pool */ 752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 753 if (num != pkts_num) { 754 WARN(1, "pool %d: %d of %d allocated\n", 755 new_pool->id, num, pkts_num); 756 return NULL; 757 } 758 } 759 760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 762 763 return new_pool; 764 } 765 766 /* Initialize pools for swf */ 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 768 { 769 int rxq; 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 771 772 /* If port pkt_size is higher than 1518B: 773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 775 */ 776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 777 long_log_pool = MVPP2_BM_JUMBO; 778 short_log_pool = MVPP2_BM_LONG; 779 } else { 780 long_log_pool = MVPP2_BM_LONG; 781 short_log_pool = MVPP2_BM_SHORT; 782 } 783 784 if (!port->pool_long) { 785 port->pool_long = 786 mvpp2_bm_pool_use(port, long_log_pool, 787 mvpp2_pools[long_log_pool].pkt_size); 788 if (!port->pool_long) 789 return -ENOMEM; 790 791 port->pool_long->port_map |= BIT(port->id); 792 793 for (rxq = 0; rxq < port->nrxqs; rxq++) 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 795 } 796 797 if (!port->pool_short) { 798 port->pool_short = 799 mvpp2_bm_pool_use(port, short_log_pool, 800 mvpp2_pools[short_log_pool].pkt_size); 801 if (!port->pool_short) 802 return -ENOMEM; 803 804 port->pool_short->port_map |= BIT(port->id); 805 806 for (rxq = 0; rxq < port->nrxqs; rxq++) 807 mvpp2_rxq_short_pool_set(port, rxq, 808 port->pool_short->id); 809 } 810 811 return 0; 812 } 813 814 static void mvpp2_set_hw_csum(struct mvpp2_port *port, 815 enum mvpp2_bm_pool_log_num new_long_pool) 816 { 817 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 818 819 /* Update L4 checksum when jumbo enable/disable on port. 820 * Only port 0 supports hardware checksum offload due to 821 * the Tx FIFO size limitation. 822 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 823 * has 7 bits, so the maximum L3 offset is 128. 824 */ 825 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 826 port->dev->features &= ~csums; 827 port->dev->hw_features &= ~csums; 828 } else { 829 port->dev->features |= csums; 830 port->dev->hw_features |= csums; 831 } 832 } 833 834 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 835 { 836 struct mvpp2_port *port = netdev_priv(dev); 837 enum mvpp2_bm_pool_log_num new_long_pool; 838 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 839 840 /* If port MTU is higher than 1518B: 841 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 842 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 843 */ 844 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 845 new_long_pool = MVPP2_BM_JUMBO; 846 else 847 new_long_pool = MVPP2_BM_LONG; 848 849 if (new_long_pool != port->pool_long->id) { 850 /* Remove port from old short & long pool */ 851 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 852 port->pool_long->pkt_size); 853 port->pool_long->port_map &= ~BIT(port->id); 854 port->pool_long = NULL; 855 856 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 857 port->pool_short->pkt_size); 858 port->pool_short->port_map &= ~BIT(port->id); 859 port->pool_short = NULL; 860 861 port->pkt_size = pkt_size; 862 863 /* Add port to new short & long pool */ 864 mvpp2_swf_bm_pool_init(port); 865 866 mvpp2_set_hw_csum(port, new_long_pool); 867 } 868 869 dev->mtu = mtu; 870 dev->wanted_features = dev->features; 871 872 netdev_update_features(dev); 873 return 0; 874 } 875 876 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 877 { 878 int i, sw_thread_mask = 0; 879 880 for (i = 0; i < port->nqvecs; i++) 881 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 882 883 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 884 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 885 } 886 887 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 888 { 889 int i, sw_thread_mask = 0; 890 891 for (i = 0; i < port->nqvecs; i++) 892 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 893 894 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 895 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 896 } 897 898 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 899 { 900 struct mvpp2_port *port = qvec->port; 901 902 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 903 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 904 } 905 906 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 907 { 908 struct mvpp2_port *port = qvec->port; 909 910 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 911 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 912 } 913 914 /* Mask the current thread's Rx/Tx interrupts 915 * Called by on_each_cpu(), guaranteed to run with migration disabled, 916 * using smp_processor_id() is OK. 917 */ 918 static void mvpp2_interrupts_mask(void *arg) 919 { 920 struct mvpp2_port *port = arg; 921 922 /* If the thread isn't used, don't do anything */ 923 if (smp_processor_id() > port->priv->nthreads) 924 return; 925 926 mvpp2_thread_write(port->priv, 927 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 928 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 929 } 930 931 /* Unmask the current thread's Rx/Tx interrupts. 932 * Called by on_each_cpu(), guaranteed to run with migration disabled, 933 * using smp_processor_id() is OK. 934 */ 935 static void mvpp2_interrupts_unmask(void *arg) 936 { 937 struct mvpp2_port *port = arg; 938 u32 val; 939 940 /* If the thread isn't used, don't do anything */ 941 if (smp_processor_id() > port->priv->nthreads) 942 return; 943 944 val = MVPP2_CAUSE_MISC_SUM_MASK | 945 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 946 if (port->has_tx_irqs) 947 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 948 949 mvpp2_thread_write(port->priv, 950 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 951 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 952 } 953 954 static void 955 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 956 { 957 u32 val; 958 int i; 959 960 if (port->priv->hw_version != MVPP22) 961 return; 962 963 if (mask) 964 val = 0; 965 else 966 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 967 968 for (i = 0; i < port->nqvecs; i++) { 969 struct mvpp2_queue_vector *v = port->qvecs + i; 970 971 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 972 continue; 973 974 mvpp2_thread_write(port->priv, v->sw_thread_id, 975 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 976 } 977 } 978 979 /* Port configuration routines */ 980 static bool mvpp2_is_xlg(phy_interface_t interface) 981 { 982 return interface == PHY_INTERFACE_MODE_10GKR || 983 interface == PHY_INTERFACE_MODE_XAUI; 984 } 985 986 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 987 { 988 struct mvpp2 *priv = port->priv; 989 u32 val; 990 991 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 992 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 993 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 994 995 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 996 if (port->gop_id == 2) 997 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 998 else if (port->gop_id == 3) 999 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 1000 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1001 } 1002 1003 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1004 { 1005 struct mvpp2 *priv = port->priv; 1006 u32 val; 1007 1008 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1009 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1010 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1011 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1012 1013 if (port->gop_id > 1) { 1014 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1015 if (port->gop_id == 2) 1016 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1017 else if (port->gop_id == 3) 1018 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1019 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1020 } 1021 } 1022 1023 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1024 { 1025 struct mvpp2 *priv = port->priv; 1026 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1027 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1028 u32 val; 1029 1030 val = readl(xpcs + MVPP22_XPCS_CFG0); 1031 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1032 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1033 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1034 writel(val, xpcs + MVPP22_XPCS_CFG0); 1035 1036 val = readl(mpcs + MVPP22_MPCS_CTRL); 1037 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1038 writel(val, mpcs + MVPP22_MPCS_CTRL); 1039 1040 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1041 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1042 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1043 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1044 } 1045 1046 static int mvpp22_gop_init(struct mvpp2_port *port) 1047 { 1048 struct mvpp2 *priv = port->priv; 1049 u32 val; 1050 1051 if (!priv->sysctrl_base) 1052 return 0; 1053 1054 switch (port->phy_interface) { 1055 case PHY_INTERFACE_MODE_RGMII: 1056 case PHY_INTERFACE_MODE_RGMII_ID: 1057 case PHY_INTERFACE_MODE_RGMII_RXID: 1058 case PHY_INTERFACE_MODE_RGMII_TXID: 1059 if (port->gop_id == 0) 1060 goto invalid_conf; 1061 mvpp22_gop_init_rgmii(port); 1062 break; 1063 case PHY_INTERFACE_MODE_SGMII: 1064 case PHY_INTERFACE_MODE_1000BASEX: 1065 case PHY_INTERFACE_MODE_2500BASEX: 1066 mvpp22_gop_init_sgmii(port); 1067 break; 1068 case PHY_INTERFACE_MODE_10GKR: 1069 if (port->gop_id != 0) 1070 goto invalid_conf; 1071 mvpp22_gop_init_10gkr(port); 1072 break; 1073 default: 1074 goto unsupported_conf; 1075 } 1076 1077 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1078 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1079 GENCONF_PORT_CTRL1_EN(port->gop_id); 1080 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1081 1082 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1083 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1084 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1085 1086 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1087 val |= GENCONF_SOFT_RESET1_GOP; 1088 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1089 1090 unsupported_conf: 1091 return 0; 1092 1093 invalid_conf: 1094 netdev_err(port->dev, "Invalid port configuration\n"); 1095 return -EINVAL; 1096 } 1097 1098 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1099 { 1100 u32 val; 1101 1102 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1103 phy_interface_mode_is_8023z(port->phy_interface) || 1104 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1105 /* Enable the GMAC link status irq for this port */ 1106 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1107 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1108 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1109 } 1110 1111 if (port->gop_id == 0) { 1112 /* Enable the XLG/GIG irqs for this port */ 1113 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1114 if (mvpp2_is_xlg(port->phy_interface)) 1115 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1116 else 1117 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1118 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1119 } 1120 } 1121 1122 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1123 { 1124 u32 val; 1125 1126 if (port->gop_id == 0) { 1127 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1128 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1129 MVPP22_XLG_EXT_INT_MASK_GIG); 1130 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1131 } 1132 1133 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1134 phy_interface_mode_is_8023z(port->phy_interface) || 1135 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1136 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1137 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1138 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1139 } 1140 } 1141 1142 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1143 { 1144 u32 val; 1145 1146 if (port->phylink || 1147 phy_interface_mode_is_rgmii(port->phy_interface) || 1148 phy_interface_mode_is_8023z(port->phy_interface) || 1149 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1150 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1151 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1152 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1153 } 1154 1155 if (port->gop_id == 0) { 1156 val = readl(port->base + MVPP22_XLG_INT_MASK); 1157 val |= MVPP22_XLG_INT_MASK_LINK; 1158 writel(val, port->base + MVPP22_XLG_INT_MASK); 1159 } 1160 1161 mvpp22_gop_unmask_irq(port); 1162 } 1163 1164 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1165 * 1166 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1167 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1168 * differ. 1169 * 1170 * The COMPHY configures the serdes lanes regardless of the actual use of the 1171 * lanes by the physical layer. This is why configurations like 1172 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1173 */ 1174 static int mvpp22_comphy_init(struct mvpp2_port *port) 1175 { 1176 int ret; 1177 1178 if (!port->comphy) 1179 return 0; 1180 1181 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1182 port->phy_interface); 1183 if (ret) 1184 return ret; 1185 1186 return phy_power_on(port->comphy); 1187 } 1188 1189 static void mvpp2_port_enable(struct mvpp2_port *port) 1190 { 1191 u32 val; 1192 1193 /* Only GOP port 0 has an XLG MAC */ 1194 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1195 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1196 val |= MVPP22_XLG_CTRL0_PORT_EN; 1197 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1198 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1199 } else { 1200 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1201 val |= MVPP2_GMAC_PORT_EN_MASK; 1202 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1203 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1204 } 1205 } 1206 1207 static void mvpp2_port_disable(struct mvpp2_port *port) 1208 { 1209 u32 val; 1210 1211 /* Only GOP port 0 has an XLG MAC */ 1212 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1213 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1214 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1215 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1216 } 1217 1218 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1219 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1220 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1221 } 1222 1223 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1224 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1225 { 1226 u32 val; 1227 1228 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1229 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1230 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1231 } 1232 1233 /* Configure loopback port */ 1234 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1235 const struct phylink_link_state *state) 1236 { 1237 u32 val; 1238 1239 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1240 1241 if (state->speed == 1000) 1242 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1243 else 1244 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1245 1246 if (phy_interface_mode_is_8023z(port->phy_interface) || 1247 port->phy_interface == PHY_INTERFACE_MODE_SGMII) 1248 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1249 else 1250 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1251 1252 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1253 } 1254 1255 struct mvpp2_ethtool_counter { 1256 unsigned int offset; 1257 const char string[ETH_GSTRING_LEN]; 1258 bool reg_is_64b; 1259 }; 1260 1261 static u64 mvpp2_read_count(struct mvpp2_port *port, 1262 const struct mvpp2_ethtool_counter *counter) 1263 { 1264 u64 val; 1265 1266 val = readl(port->stats_base + counter->offset); 1267 if (counter->reg_is_64b) 1268 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1269 1270 return val; 1271 } 1272 1273 /* Some counters are accessed indirectly by first writing an index to 1274 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1275 * register we access, it can be a hit counter for some classification tables, 1276 * a counter specific to a rxq, a txq or a buffer pool. 1277 */ 1278 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1279 { 1280 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1281 return mvpp2_read(priv, reg); 1282 } 1283 1284 /* Due to the fact that software statistics and hardware statistics are, by 1285 * design, incremented at different moments in the chain of packet processing, 1286 * it is very likely that incoming packets could have been dropped after being 1287 * counted by hardware but before reaching software statistics (most probably 1288 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1289 * are added in between as well as TSO skb will be split and header bytes added. 1290 * Hence, statistics gathered from userspace with ifconfig (software) and 1291 * ethtool (hardware) cannot be compared. 1292 */ 1293 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1294 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1295 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1296 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1297 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1298 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1299 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1300 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1301 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1302 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1303 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1304 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1305 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1306 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1307 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1308 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1309 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1310 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1311 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1312 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1313 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1314 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1315 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1316 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1317 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1318 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1319 { MVPP2_MIB_COLLISION, "collision" }, 1320 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1321 }; 1322 1323 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1324 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1325 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1326 }; 1327 1328 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1329 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1330 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1331 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1332 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1333 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1334 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1335 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1336 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1337 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1338 }; 1339 1340 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1341 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1342 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1343 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1344 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1345 }; 1346 1347 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1348 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1349 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1350 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs))) 1351 1352 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1353 u8 *data) 1354 { 1355 struct mvpp2_port *port = netdev_priv(netdev); 1356 int i, q; 1357 1358 if (sset != ETH_SS_STATS) 1359 return; 1360 1361 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1362 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1363 ETH_GSTRING_LEN); 1364 data += ETH_GSTRING_LEN; 1365 } 1366 1367 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1368 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1369 ETH_GSTRING_LEN); 1370 data += ETH_GSTRING_LEN; 1371 } 1372 1373 for (q = 0; q < port->ntxqs; q++) { 1374 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1375 snprintf(data, ETH_GSTRING_LEN, 1376 mvpp2_ethtool_txq_regs[i].string, q); 1377 data += ETH_GSTRING_LEN; 1378 } 1379 } 1380 1381 for (q = 0; q < port->nrxqs; q++) { 1382 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1383 snprintf(data, ETH_GSTRING_LEN, 1384 mvpp2_ethtool_rxq_regs[i].string, 1385 q); 1386 data += ETH_GSTRING_LEN; 1387 } 1388 } 1389 } 1390 1391 static void mvpp2_read_stats(struct mvpp2_port *port) 1392 { 1393 u64 *pstats; 1394 int i, q; 1395 1396 pstats = port->ethtool_stats; 1397 1398 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 1399 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 1400 1401 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 1402 *pstats++ += mvpp2_read(port->priv, 1403 mvpp2_ethtool_port_regs[i].offset + 1404 4 * port->id); 1405 1406 for (q = 0; q < port->ntxqs; q++) 1407 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 1408 *pstats++ += mvpp2_read_index(port->priv, 1409 MVPP22_CTRS_TX_CTR(port->id, i), 1410 mvpp2_ethtool_txq_regs[i].offset); 1411 1412 /* Rxqs are numbered from 0 from the user standpoint, but not from the 1413 * driver's. We need to add the port->first_rxq offset. 1414 */ 1415 for (q = 0; q < port->nrxqs; q++) 1416 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 1417 *pstats++ += mvpp2_read_index(port->priv, 1418 port->first_rxq + i, 1419 mvpp2_ethtool_rxq_regs[i].offset); 1420 } 1421 1422 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1423 { 1424 struct delayed_work *del_work = to_delayed_work(work); 1425 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1426 stats_work); 1427 1428 mutex_lock(&port->gather_stats_lock); 1429 1430 mvpp2_read_stats(port); 1431 1432 /* No need to read again the counters right after this function if it 1433 * was called asynchronously by the user (ie. use of ethtool). 1434 */ 1435 cancel_delayed_work(&port->stats_work); 1436 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1437 MVPP2_MIB_COUNTERS_STATS_DELAY); 1438 1439 mutex_unlock(&port->gather_stats_lock); 1440 } 1441 1442 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1443 struct ethtool_stats *stats, u64 *data) 1444 { 1445 struct mvpp2_port *port = netdev_priv(dev); 1446 1447 /* Update statistics for the given port, then take the lock to avoid 1448 * concurrent accesses on the ethtool_stats structure during its copy. 1449 */ 1450 mvpp2_gather_hw_statistics(&port->stats_work.work); 1451 1452 mutex_lock(&port->gather_stats_lock); 1453 memcpy(data, port->ethtool_stats, 1454 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 1455 mutex_unlock(&port->gather_stats_lock); 1456 } 1457 1458 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1459 { 1460 struct mvpp2_port *port = netdev_priv(dev); 1461 1462 if (sset == ETH_SS_STATS) 1463 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 1464 1465 return -EOPNOTSUPP; 1466 } 1467 1468 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 1469 { 1470 u32 val; 1471 1472 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1473 MVPP2_GMAC_PORT_RESET_MASK; 1474 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1475 1476 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 1477 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 1478 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1479 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1480 } 1481 } 1482 1483 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 1484 { 1485 struct mvpp2 *priv = port->priv; 1486 void __iomem *mpcs, *xpcs; 1487 u32 val; 1488 1489 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1490 return; 1491 1492 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1493 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1494 1495 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1496 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1497 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 1498 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1499 1500 val = readl(xpcs + MVPP22_XPCS_CFG0); 1501 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1502 } 1503 1504 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 1505 { 1506 struct mvpp2 *priv = port->priv; 1507 void __iomem *mpcs, *xpcs; 1508 u32 val; 1509 1510 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1511 return; 1512 1513 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1514 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1515 1516 switch (port->phy_interface) { 1517 case PHY_INTERFACE_MODE_10GKR: 1518 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1519 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 1520 MAC_CLK_RESET_SD_TX; 1521 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1522 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1523 break; 1524 case PHY_INTERFACE_MODE_XAUI: 1525 case PHY_INTERFACE_MODE_RXAUI: 1526 val = readl(xpcs + MVPP22_XPCS_CFG0); 1527 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1528 break; 1529 default: 1530 break; 1531 } 1532 } 1533 1534 /* Change maximum receive size of the port */ 1535 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1536 { 1537 u32 val; 1538 1539 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1540 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1541 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1542 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1543 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1544 } 1545 1546 /* Change maximum receive size of the port */ 1547 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1548 { 1549 u32 val; 1550 1551 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1552 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1553 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1554 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1555 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1556 } 1557 1558 /* Set defaults to the MVPP2 port */ 1559 static void mvpp2_defaults_set(struct mvpp2_port *port) 1560 { 1561 int tx_port_num, val, queue, lrxq; 1562 1563 if (port->priv->hw_version == MVPP21) { 1564 /* Update TX FIFO MIN Threshold */ 1565 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1566 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1567 /* Min. TX threshold must be less than minimal packet length */ 1568 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1569 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1570 } 1571 1572 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1573 tx_port_num = mvpp2_egress_port(port); 1574 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1575 tx_port_num); 1576 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1577 1578 /* Set TXQ scheduling to Round-Robin */ 1579 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1580 1581 /* Close bandwidth for all queues */ 1582 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 1583 mvpp2_write(port->priv, 1584 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 1585 1586 /* Set refill period to 1 usec, refill tokens 1587 * and bucket size to maximum 1588 */ 1589 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1590 port->priv->tclk / USEC_PER_SEC); 1591 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1592 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1593 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1594 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1595 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1596 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1597 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1598 1599 /* Set MaximumLowLatencyPacketSize value to 256 */ 1600 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1601 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1602 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1603 1604 /* Enable Rx cache snoop */ 1605 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1606 queue = port->rxqs[lrxq]->id; 1607 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1608 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1609 MVPP2_SNOOP_BUF_HDR_MASK; 1610 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1611 } 1612 1613 /* At default, mask all interrupts to all present cpus */ 1614 mvpp2_interrupts_disable(port); 1615 } 1616 1617 /* Enable/disable receiving packets */ 1618 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1619 { 1620 u32 val; 1621 int lrxq, queue; 1622 1623 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1624 queue = port->rxqs[lrxq]->id; 1625 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1626 val &= ~MVPP2_RXQ_DISABLE_MASK; 1627 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1628 } 1629 } 1630 1631 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1632 { 1633 u32 val; 1634 int lrxq, queue; 1635 1636 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1637 queue = port->rxqs[lrxq]->id; 1638 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1639 val |= MVPP2_RXQ_DISABLE_MASK; 1640 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1641 } 1642 } 1643 1644 /* Enable transmit via physical egress queue 1645 * - HW starts take descriptors from DRAM 1646 */ 1647 static void mvpp2_egress_enable(struct mvpp2_port *port) 1648 { 1649 u32 qmap; 1650 int queue; 1651 int tx_port_num = mvpp2_egress_port(port); 1652 1653 /* Enable all initialized TXs. */ 1654 qmap = 0; 1655 for (queue = 0; queue < port->ntxqs; queue++) { 1656 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1657 1658 if (txq->descs) 1659 qmap |= (1 << queue); 1660 } 1661 1662 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1663 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1664 } 1665 1666 /* Disable transmit via physical egress queue 1667 * - HW doesn't take descriptors from DRAM 1668 */ 1669 static void mvpp2_egress_disable(struct mvpp2_port *port) 1670 { 1671 u32 reg_data; 1672 int delay; 1673 int tx_port_num = mvpp2_egress_port(port); 1674 1675 /* Issue stop command for active channels only */ 1676 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1677 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1678 MVPP2_TXP_SCHED_ENQ_MASK; 1679 if (reg_data != 0) 1680 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1681 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1682 1683 /* Wait for all Tx activity to terminate. */ 1684 delay = 0; 1685 do { 1686 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1687 netdev_warn(port->dev, 1688 "Tx stop timed out, status=0x%08x\n", 1689 reg_data); 1690 break; 1691 } 1692 mdelay(1); 1693 delay++; 1694 1695 /* Check port TX Command register that all 1696 * Tx queues are stopped 1697 */ 1698 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1699 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1700 } 1701 1702 /* Rx descriptors helper methods */ 1703 1704 /* Get number of Rx descriptors occupied by received packets */ 1705 static inline int 1706 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1707 { 1708 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1709 1710 return val & MVPP2_RXQ_OCCUPIED_MASK; 1711 } 1712 1713 /* Update Rx queue status with the number of occupied and available 1714 * Rx descriptor slots. 1715 */ 1716 static inline void 1717 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1718 int used_count, int free_count) 1719 { 1720 /* Decrement the number of used descriptors and increment count 1721 * increment the number of free descriptors. 1722 */ 1723 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1724 1725 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1726 } 1727 1728 /* Get pointer to next RX descriptor to be processed by SW */ 1729 static inline struct mvpp2_rx_desc * 1730 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1731 { 1732 int rx_desc = rxq->next_desc_to_proc; 1733 1734 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1735 prefetch(rxq->descs + rxq->next_desc_to_proc); 1736 return rxq->descs + rx_desc; 1737 } 1738 1739 /* Set rx queue offset */ 1740 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1741 int prxq, int offset) 1742 { 1743 u32 val; 1744 1745 /* Convert offset from bytes to units of 32 bytes */ 1746 offset = offset >> 5; 1747 1748 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1749 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1750 1751 /* Offset is in */ 1752 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1753 MVPP2_RXQ_PACKET_OFFSET_MASK); 1754 1755 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1756 } 1757 1758 /* Tx descriptors helper methods */ 1759 1760 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1761 static struct mvpp2_tx_desc * 1762 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1763 { 1764 int tx_desc = txq->next_desc_to_proc; 1765 1766 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1767 return txq->descs + tx_desc; 1768 } 1769 1770 /* Update HW with number of aggregated Tx descriptors to be sent 1771 * 1772 * Called only from mvpp2_tx(), so migration is disabled, using 1773 * smp_processor_id() is OK. 1774 */ 1775 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1776 { 1777 /* aggregated access - relevant TXQ number is written in TX desc */ 1778 mvpp2_thread_write(port->priv, 1779 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1780 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1781 } 1782 1783 /* Check if there are enough free descriptors in aggregated txq. 1784 * If not, update the number of occupied descriptors and repeat the check. 1785 * 1786 * Called only from mvpp2_tx(), so migration is disabled, using 1787 * smp_processor_id() is OK. 1788 */ 1789 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 1790 struct mvpp2_tx_queue *aggr_txq, int num) 1791 { 1792 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1793 /* Update number of occupied aggregated Tx descriptors */ 1794 unsigned int thread = 1795 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1796 u32 val = mvpp2_read_relaxed(port->priv, 1797 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 1798 1799 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1800 1801 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1802 return -ENOMEM; 1803 } 1804 return 0; 1805 } 1806 1807 /* Reserved Tx descriptors allocation request 1808 * 1809 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1810 * only by mvpp2_tx(), so migration is disabled, using 1811 * smp_processor_id() is OK. 1812 */ 1813 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 1814 struct mvpp2_tx_queue *txq, int num) 1815 { 1816 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1817 struct mvpp2 *priv = port->priv; 1818 u32 val; 1819 1820 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1821 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 1822 1823 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 1824 1825 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1826 } 1827 1828 /* Check if there are enough reserved descriptors for transmission. 1829 * If not, request chunk of reserved descriptors and check again. 1830 */ 1831 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 1832 struct mvpp2_tx_queue *txq, 1833 struct mvpp2_txq_pcpu *txq_pcpu, 1834 int num) 1835 { 1836 int req, desc_count; 1837 unsigned int thread; 1838 1839 if (txq_pcpu->reserved_num >= num) 1840 return 0; 1841 1842 /* Not enough descriptors reserved! Update the reserved descriptor 1843 * count and check again. 1844 */ 1845 1846 desc_count = 0; 1847 /* Compute total of used descriptors */ 1848 for (thread = 0; thread < port->priv->nthreads; thread++) { 1849 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1850 1851 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 1852 desc_count += txq_pcpu_aux->count; 1853 desc_count += txq_pcpu_aux->reserved_num; 1854 } 1855 1856 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1857 desc_count += req; 1858 1859 if (desc_count > 1860 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 1861 return -ENOMEM; 1862 1863 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 1864 1865 /* OK, the descriptor could have been updated: check again. */ 1866 if (txq_pcpu->reserved_num < num) 1867 return -ENOMEM; 1868 return 0; 1869 } 1870 1871 /* Release the last allocated Tx descriptor. Useful to handle DMA 1872 * mapping failures in the Tx path. 1873 */ 1874 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1875 { 1876 if (txq->next_desc_to_proc == 0) 1877 txq->next_desc_to_proc = txq->last_desc - 1; 1878 else 1879 txq->next_desc_to_proc--; 1880 } 1881 1882 /* Set Tx descriptors fields relevant for CSUM calculation */ 1883 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 1884 int ip_hdr_len, int l4_proto) 1885 { 1886 u32 command; 1887 1888 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1889 * G_L4_chk, L4_type required only for checksum calculation 1890 */ 1891 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1892 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1893 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1894 1895 if (l3_proto == htons(ETH_P_IP)) { 1896 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1897 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1898 } else { 1899 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1900 } 1901 1902 if (l4_proto == IPPROTO_TCP) { 1903 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1904 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1905 } else if (l4_proto == IPPROTO_UDP) { 1906 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1907 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1908 } else { 1909 command |= MVPP2_TXD_L4_CSUM_NOT; 1910 } 1911 1912 return command; 1913 } 1914 1915 /* Get number of sent descriptors and decrement counter. 1916 * The number of sent descriptors is returned. 1917 * Per-thread access 1918 * 1919 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1920 * (migration disabled) and from the TX completion tasklet (migration 1921 * disabled) so using smp_processor_id() is OK. 1922 */ 1923 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1924 struct mvpp2_tx_queue *txq) 1925 { 1926 u32 val; 1927 1928 /* Reading status reg resets transmitted descriptor counter */ 1929 val = mvpp2_thread_read_relaxed(port->priv, 1930 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1931 MVPP2_TXQ_SENT_REG(txq->id)); 1932 1933 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1934 MVPP2_TRANSMITTED_COUNT_OFFSET; 1935 } 1936 1937 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1938 * disabled, therefore using smp_processor_id() is OK. 1939 */ 1940 static void mvpp2_txq_sent_counter_clear(void *arg) 1941 { 1942 struct mvpp2_port *port = arg; 1943 int queue; 1944 1945 /* If the thread isn't used, don't do anything */ 1946 if (smp_processor_id() > port->priv->nthreads) 1947 return; 1948 1949 for (queue = 0; queue < port->ntxqs; queue++) { 1950 int id = port->txqs[queue]->id; 1951 1952 mvpp2_thread_read(port->priv, 1953 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1954 MVPP2_TXQ_SENT_REG(id)); 1955 } 1956 } 1957 1958 /* Set max sizes for Tx queues */ 1959 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1960 { 1961 u32 val, size, mtu; 1962 int txq, tx_port_num; 1963 1964 mtu = port->pkt_size * 8; 1965 if (mtu > MVPP2_TXP_MTU_MAX) 1966 mtu = MVPP2_TXP_MTU_MAX; 1967 1968 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1969 mtu = 3 * mtu; 1970 1971 /* Indirect access to registers */ 1972 tx_port_num = mvpp2_egress_port(port); 1973 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1974 1975 /* Set MTU */ 1976 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1977 val &= ~MVPP2_TXP_MTU_MAX; 1978 val |= mtu; 1979 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1980 1981 /* TXP token size and all TXQs token size must be larger that MTU */ 1982 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1983 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1984 if (size < mtu) { 1985 size = mtu; 1986 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1987 val |= size; 1988 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1989 } 1990 1991 for (txq = 0; txq < port->ntxqs; txq++) { 1992 val = mvpp2_read(port->priv, 1993 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1994 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1995 1996 if (size < mtu) { 1997 size = mtu; 1998 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1999 val |= size; 2000 mvpp2_write(port->priv, 2001 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2002 val); 2003 } 2004 } 2005 } 2006 2007 /* Set the number of packets that will be received before Rx interrupt 2008 * will be generated by HW. 2009 */ 2010 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2011 struct mvpp2_rx_queue *rxq) 2012 { 2013 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2014 2015 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2016 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2017 2018 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2019 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2020 rxq->pkts_coal); 2021 2022 put_cpu(); 2023 } 2024 2025 /* For some reason in the LSP this is done on each CPU. Why ? */ 2026 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2027 struct mvpp2_tx_queue *txq) 2028 { 2029 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2030 u32 val; 2031 2032 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2033 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2034 2035 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2036 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2037 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2038 2039 put_cpu(); 2040 } 2041 2042 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2043 { 2044 u64 tmp = (u64)clk_hz * usec; 2045 2046 do_div(tmp, USEC_PER_SEC); 2047 2048 return tmp > U32_MAX ? U32_MAX : tmp; 2049 } 2050 2051 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2052 { 2053 u64 tmp = (u64)cycles * USEC_PER_SEC; 2054 2055 do_div(tmp, clk_hz); 2056 2057 return tmp > U32_MAX ? U32_MAX : tmp; 2058 } 2059 2060 /* Set the time delay in usec before Rx interrupt */ 2061 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2062 struct mvpp2_rx_queue *rxq) 2063 { 2064 unsigned long freq = port->priv->tclk; 2065 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2066 2067 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2068 rxq->time_coal = 2069 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2070 2071 /* re-evaluate to get actual register value */ 2072 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2073 } 2074 2075 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2076 } 2077 2078 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2079 { 2080 unsigned long freq = port->priv->tclk; 2081 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2082 2083 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2084 port->tx_time_coal = 2085 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2086 2087 /* re-evaluate to get actual register value */ 2088 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2089 } 2090 2091 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2092 } 2093 2094 /* Free Tx queue skbuffs */ 2095 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2096 struct mvpp2_tx_queue *txq, 2097 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2098 { 2099 int i; 2100 2101 for (i = 0; i < num; i++) { 2102 struct mvpp2_txq_pcpu_buf *tx_buf = 2103 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2104 2105 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 2106 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2107 tx_buf->size, DMA_TO_DEVICE); 2108 if (tx_buf->skb) 2109 dev_kfree_skb_any(tx_buf->skb); 2110 2111 mvpp2_txq_inc_get(txq_pcpu); 2112 } 2113 } 2114 2115 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2116 u32 cause) 2117 { 2118 int queue = fls(cause) - 1; 2119 2120 return port->rxqs[queue]; 2121 } 2122 2123 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2124 u32 cause) 2125 { 2126 int queue = fls(cause) - 1; 2127 2128 return port->txqs[queue]; 2129 } 2130 2131 /* Handle end of transmission */ 2132 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2133 struct mvpp2_txq_pcpu *txq_pcpu) 2134 { 2135 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2136 int tx_done; 2137 2138 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2139 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2140 2141 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2142 if (!tx_done) 2143 return; 2144 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2145 2146 txq_pcpu->count -= tx_done; 2147 2148 if (netif_tx_queue_stopped(nq)) 2149 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2150 netif_tx_wake_queue(nq); 2151 } 2152 2153 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2154 unsigned int thread) 2155 { 2156 struct mvpp2_tx_queue *txq; 2157 struct mvpp2_txq_pcpu *txq_pcpu; 2158 unsigned int tx_todo = 0; 2159 2160 while (cause) { 2161 txq = mvpp2_get_tx_queue(port, cause); 2162 if (!txq) 2163 break; 2164 2165 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2166 2167 if (txq_pcpu->count) { 2168 mvpp2_txq_done(port, txq, txq_pcpu); 2169 tx_todo += txq_pcpu->count; 2170 } 2171 2172 cause &= ~(1 << txq->log_id); 2173 } 2174 return tx_todo; 2175 } 2176 2177 /* Rx/Tx queue initialization/cleanup methods */ 2178 2179 /* Allocate and initialize descriptors for aggr TXQ */ 2180 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2181 struct mvpp2_tx_queue *aggr_txq, 2182 unsigned int thread, struct mvpp2 *priv) 2183 { 2184 u32 txq_dma; 2185 2186 /* Allocate memory for TX descriptors */ 2187 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2188 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2189 &aggr_txq->descs_dma, GFP_KERNEL); 2190 if (!aggr_txq->descs) 2191 return -ENOMEM; 2192 2193 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2194 2195 /* Aggr TXQ no reset WA */ 2196 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2197 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2198 2199 /* Set Tx descriptors queue starting address indirect 2200 * access 2201 */ 2202 if (priv->hw_version == MVPP21) 2203 txq_dma = aggr_txq->descs_dma; 2204 else 2205 txq_dma = aggr_txq->descs_dma >> 2206 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2207 2208 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2209 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2210 MVPP2_AGGR_TXQ_SIZE); 2211 2212 return 0; 2213 } 2214 2215 /* Create a specified Rx queue */ 2216 static int mvpp2_rxq_init(struct mvpp2_port *port, 2217 struct mvpp2_rx_queue *rxq) 2218 2219 { 2220 unsigned int thread; 2221 u32 rxq_dma; 2222 2223 rxq->size = port->rx_ring_size; 2224 2225 /* Allocate memory for RX descriptors */ 2226 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2227 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2228 &rxq->descs_dma, GFP_KERNEL); 2229 if (!rxq->descs) 2230 return -ENOMEM; 2231 2232 rxq->last_desc = rxq->size - 1; 2233 2234 /* Zero occupied and non-occupied counters - direct access */ 2235 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2236 2237 /* Set Rx descriptors queue starting address - indirect access */ 2238 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2239 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2240 if (port->priv->hw_version == MVPP21) 2241 rxq_dma = rxq->descs_dma; 2242 else 2243 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2244 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2245 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2246 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2247 put_cpu(); 2248 2249 /* Set Offset */ 2250 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2251 2252 /* Set coalescing pkts and time */ 2253 mvpp2_rx_pkts_coal_set(port, rxq); 2254 mvpp2_rx_time_coal_set(port, rxq); 2255 2256 /* Add number of descriptors ready for receiving packets */ 2257 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2258 2259 return 0; 2260 } 2261 2262 /* Push packets received by the RXQ to BM pool */ 2263 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2264 struct mvpp2_rx_queue *rxq) 2265 { 2266 int rx_received, i; 2267 2268 rx_received = mvpp2_rxq_received(port, rxq->id); 2269 if (!rx_received) 2270 return; 2271 2272 for (i = 0; i < rx_received; i++) { 2273 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2274 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2275 int pool; 2276 2277 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2278 MVPP2_RXD_BM_POOL_ID_OFFS; 2279 2280 mvpp2_bm_pool_put(port, pool, 2281 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2282 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2283 } 2284 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2285 } 2286 2287 /* Cleanup Rx queue */ 2288 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2289 struct mvpp2_rx_queue *rxq) 2290 { 2291 unsigned int thread; 2292 2293 mvpp2_rxq_drop_pkts(port, rxq); 2294 2295 if (rxq->descs) 2296 dma_free_coherent(port->dev->dev.parent, 2297 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2298 rxq->descs, 2299 rxq->descs_dma); 2300 2301 rxq->descs = NULL; 2302 rxq->last_desc = 0; 2303 rxq->next_desc_to_proc = 0; 2304 rxq->descs_dma = 0; 2305 2306 /* Clear Rx descriptors queue starting address and size; 2307 * free descriptor number 2308 */ 2309 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2310 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2311 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2312 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2313 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2314 put_cpu(); 2315 } 2316 2317 /* Create and initialize a Tx queue */ 2318 static int mvpp2_txq_init(struct mvpp2_port *port, 2319 struct mvpp2_tx_queue *txq) 2320 { 2321 u32 val; 2322 unsigned int thread; 2323 int desc, desc_per_txq, tx_port_num; 2324 struct mvpp2_txq_pcpu *txq_pcpu; 2325 2326 txq->size = port->tx_ring_size; 2327 2328 /* Allocate memory for Tx descriptors */ 2329 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2330 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2331 &txq->descs_dma, GFP_KERNEL); 2332 if (!txq->descs) 2333 return -ENOMEM; 2334 2335 txq->last_desc = txq->size - 1; 2336 2337 /* Set Tx descriptors queue starting address - indirect access */ 2338 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2339 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2340 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2341 txq->descs_dma); 2342 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2343 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2344 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2345 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2346 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2347 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2348 val &= ~MVPP2_TXQ_PENDING_MASK; 2349 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2350 2351 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2352 * for each existing TXQ. 2353 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2354 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2355 */ 2356 desc_per_txq = 16; 2357 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2358 (txq->log_id * desc_per_txq); 2359 2360 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2361 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2362 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2363 put_cpu(); 2364 2365 /* WRR / EJP configuration - indirect access */ 2366 tx_port_num = mvpp2_egress_port(port); 2367 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2368 2369 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2370 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2371 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2372 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2373 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2374 2375 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2376 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2377 val); 2378 2379 for (thread = 0; thread < port->priv->nthreads; thread++) { 2380 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2381 txq_pcpu->size = txq->size; 2382 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2383 sizeof(*txq_pcpu->buffs), 2384 GFP_KERNEL); 2385 if (!txq_pcpu->buffs) 2386 return -ENOMEM; 2387 2388 txq_pcpu->count = 0; 2389 txq_pcpu->reserved_num = 0; 2390 txq_pcpu->txq_put_index = 0; 2391 txq_pcpu->txq_get_index = 0; 2392 txq_pcpu->tso_headers = NULL; 2393 2394 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2395 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2396 2397 txq_pcpu->tso_headers = 2398 dma_alloc_coherent(port->dev->dev.parent, 2399 txq_pcpu->size * TSO_HEADER_SIZE, 2400 &txq_pcpu->tso_headers_dma, 2401 GFP_KERNEL); 2402 if (!txq_pcpu->tso_headers) 2403 return -ENOMEM; 2404 } 2405 2406 return 0; 2407 } 2408 2409 /* Free allocated TXQ resources */ 2410 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2411 struct mvpp2_tx_queue *txq) 2412 { 2413 struct mvpp2_txq_pcpu *txq_pcpu; 2414 unsigned int thread; 2415 2416 for (thread = 0; thread < port->priv->nthreads; thread++) { 2417 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2418 kfree(txq_pcpu->buffs); 2419 2420 if (txq_pcpu->tso_headers) 2421 dma_free_coherent(port->dev->dev.parent, 2422 txq_pcpu->size * TSO_HEADER_SIZE, 2423 txq_pcpu->tso_headers, 2424 txq_pcpu->tso_headers_dma); 2425 2426 txq_pcpu->tso_headers = NULL; 2427 } 2428 2429 if (txq->descs) 2430 dma_free_coherent(port->dev->dev.parent, 2431 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2432 txq->descs, txq->descs_dma); 2433 2434 txq->descs = NULL; 2435 txq->last_desc = 0; 2436 txq->next_desc_to_proc = 0; 2437 txq->descs_dma = 0; 2438 2439 /* Set minimum bandwidth for disabled TXQs */ 2440 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 2441 2442 /* Set Tx descriptors queue starting address and size */ 2443 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2444 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2445 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2446 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2447 put_cpu(); 2448 } 2449 2450 /* Cleanup Tx ports */ 2451 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2452 { 2453 struct mvpp2_txq_pcpu *txq_pcpu; 2454 int delay, pending; 2455 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2456 u32 val; 2457 2458 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2459 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2460 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2461 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2462 2463 /* The napi queue has been stopped so wait for all packets 2464 * to be transmitted. 2465 */ 2466 delay = 0; 2467 do { 2468 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2469 netdev_warn(port->dev, 2470 "port %d: cleaning queue %d timed out\n", 2471 port->id, txq->log_id); 2472 break; 2473 } 2474 mdelay(1); 2475 delay++; 2476 2477 pending = mvpp2_thread_read(port->priv, thread, 2478 MVPP2_TXQ_PENDING_REG); 2479 pending &= MVPP2_TXQ_PENDING_MASK; 2480 } while (pending); 2481 2482 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2483 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2484 put_cpu(); 2485 2486 for (thread = 0; thread < port->priv->nthreads; thread++) { 2487 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2488 2489 /* Release all packets */ 2490 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2491 2492 /* Reset queue */ 2493 txq_pcpu->count = 0; 2494 txq_pcpu->txq_put_index = 0; 2495 txq_pcpu->txq_get_index = 0; 2496 } 2497 } 2498 2499 /* Cleanup all Tx queues */ 2500 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2501 { 2502 struct mvpp2_tx_queue *txq; 2503 int queue; 2504 u32 val; 2505 2506 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2507 2508 /* Reset Tx ports and delete Tx queues */ 2509 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2510 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2511 2512 for (queue = 0; queue < port->ntxqs; queue++) { 2513 txq = port->txqs[queue]; 2514 mvpp2_txq_clean(port, txq); 2515 mvpp2_txq_deinit(port, txq); 2516 } 2517 2518 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2519 2520 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2521 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2522 } 2523 2524 /* Cleanup all Rx queues */ 2525 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2526 { 2527 int queue; 2528 2529 for (queue = 0; queue < port->nrxqs; queue++) 2530 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2531 } 2532 2533 /* Init all Rx queues for port */ 2534 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2535 { 2536 int queue, err; 2537 2538 for (queue = 0; queue < port->nrxqs; queue++) { 2539 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2540 if (err) 2541 goto err_cleanup; 2542 } 2543 return 0; 2544 2545 err_cleanup: 2546 mvpp2_cleanup_rxqs(port); 2547 return err; 2548 } 2549 2550 /* Init all tx queues for port */ 2551 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2552 { 2553 struct mvpp2_tx_queue *txq; 2554 int queue, err, cpu; 2555 2556 for (queue = 0; queue < port->ntxqs; queue++) { 2557 txq = port->txqs[queue]; 2558 err = mvpp2_txq_init(port, txq); 2559 if (err) 2560 goto err_cleanup; 2561 2562 /* Assign this queue to a CPU */ 2563 cpu = queue % num_present_cpus(); 2564 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue); 2565 } 2566 2567 if (port->has_tx_irqs) { 2568 mvpp2_tx_time_coal_set(port); 2569 for (queue = 0; queue < port->ntxqs; queue++) { 2570 txq = port->txqs[queue]; 2571 mvpp2_tx_pkts_coal_set(port, txq); 2572 } 2573 } 2574 2575 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2576 return 0; 2577 2578 err_cleanup: 2579 mvpp2_cleanup_txqs(port); 2580 return err; 2581 } 2582 2583 /* The callback for per-port interrupt */ 2584 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2585 { 2586 struct mvpp2_queue_vector *qv = dev_id; 2587 2588 mvpp2_qvec_interrupt_disable(qv); 2589 2590 napi_schedule(&qv->napi); 2591 2592 return IRQ_HANDLED; 2593 } 2594 2595 /* Per-port interrupt for link status changes */ 2596 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2597 { 2598 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2599 struct net_device *dev = port->dev; 2600 bool event = false, link = false; 2601 u32 val; 2602 2603 mvpp22_gop_mask_irq(port); 2604 2605 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 2606 val = readl(port->base + MVPP22_XLG_INT_STAT); 2607 if (val & MVPP22_XLG_INT_STAT_LINK) { 2608 event = true; 2609 val = readl(port->base + MVPP22_XLG_STATUS); 2610 if (val & MVPP22_XLG_STATUS_LINK_UP) 2611 link = true; 2612 } 2613 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2614 phy_interface_mode_is_8023z(port->phy_interface) || 2615 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 2616 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2617 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2618 event = true; 2619 val = readl(port->base + MVPP2_GMAC_STATUS0); 2620 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2621 link = true; 2622 } 2623 } 2624 2625 if (port->phylink) { 2626 phylink_mac_change(port->phylink, link); 2627 goto handled; 2628 } 2629 2630 if (!netif_running(dev) || !event) 2631 goto handled; 2632 2633 if (link) { 2634 mvpp2_interrupts_enable(port); 2635 2636 mvpp2_egress_enable(port); 2637 mvpp2_ingress_enable(port); 2638 netif_carrier_on(dev); 2639 netif_tx_wake_all_queues(dev); 2640 } else { 2641 netif_tx_stop_all_queues(dev); 2642 netif_carrier_off(dev); 2643 mvpp2_ingress_disable(port); 2644 mvpp2_egress_disable(port); 2645 2646 mvpp2_interrupts_disable(port); 2647 } 2648 2649 handled: 2650 mvpp22_gop_unmask_irq(port); 2651 return IRQ_HANDLED; 2652 } 2653 2654 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2655 { 2656 ktime_t interval; 2657 2658 if (!port_pcpu->timer_scheduled) { 2659 port_pcpu->timer_scheduled = true; 2660 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2661 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2662 HRTIMER_MODE_REL_PINNED); 2663 } 2664 } 2665 2666 static void mvpp2_tx_proc_cb(unsigned long data) 2667 { 2668 struct net_device *dev = (struct net_device *)data; 2669 struct mvpp2_port *port = netdev_priv(dev); 2670 struct mvpp2_port_pcpu *port_pcpu; 2671 unsigned int tx_todo, cause; 2672 2673 port_pcpu = per_cpu_ptr(port->pcpu, 2674 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2675 2676 if (!netif_running(dev)) 2677 return; 2678 port_pcpu->timer_scheduled = false; 2679 2680 /* Process all the Tx queues */ 2681 cause = (1 << port->ntxqs) - 1; 2682 tx_todo = mvpp2_tx_done(port, cause, 2683 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2684 2685 /* Set the timer in case not all the packets were processed */ 2686 if (tx_todo) 2687 mvpp2_timer_set(port_pcpu); 2688 } 2689 2690 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2691 { 2692 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2693 struct mvpp2_port_pcpu, 2694 tx_done_timer); 2695 2696 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2697 2698 return HRTIMER_NORESTART; 2699 } 2700 2701 /* Main RX/TX processing routines */ 2702 2703 /* Display more error info */ 2704 static void mvpp2_rx_error(struct mvpp2_port *port, 2705 struct mvpp2_rx_desc *rx_desc) 2706 { 2707 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2708 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2709 char *err_str = NULL; 2710 2711 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2712 case MVPP2_RXD_ERR_CRC: 2713 err_str = "crc"; 2714 break; 2715 case MVPP2_RXD_ERR_OVERRUN: 2716 err_str = "overrun"; 2717 break; 2718 case MVPP2_RXD_ERR_RESOURCE: 2719 err_str = "resource"; 2720 break; 2721 } 2722 if (err_str && net_ratelimit()) 2723 netdev_err(port->dev, 2724 "bad rx status %08x (%s error), size=%zu\n", 2725 status, err_str, sz); 2726 } 2727 2728 /* Handle RX checksum offload */ 2729 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2730 struct sk_buff *skb) 2731 { 2732 if (((status & MVPP2_RXD_L3_IP4) && 2733 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2734 (status & MVPP2_RXD_L3_IP6)) 2735 if (((status & MVPP2_RXD_L4_UDP) || 2736 (status & MVPP2_RXD_L4_TCP)) && 2737 (status & MVPP2_RXD_L4_CSUM_OK)) { 2738 skb->csum = 0; 2739 skb->ip_summed = CHECKSUM_UNNECESSARY; 2740 return; 2741 } 2742 2743 skb->ip_summed = CHECKSUM_NONE; 2744 } 2745 2746 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2747 static int mvpp2_rx_refill(struct mvpp2_port *port, 2748 struct mvpp2_bm_pool *bm_pool, int pool) 2749 { 2750 dma_addr_t dma_addr; 2751 phys_addr_t phys_addr; 2752 void *buf; 2753 2754 /* No recycle or too many buffers are in use, so allocate a new skb */ 2755 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2756 GFP_ATOMIC); 2757 if (!buf) 2758 return -ENOMEM; 2759 2760 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2761 2762 return 0; 2763 } 2764 2765 /* Handle tx checksum */ 2766 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2767 { 2768 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2769 int ip_hdr_len = 0; 2770 u8 l4_proto; 2771 __be16 l3_proto = vlan_get_protocol(skb); 2772 2773 if (l3_proto == htons(ETH_P_IP)) { 2774 struct iphdr *ip4h = ip_hdr(skb); 2775 2776 /* Calculate IPv4 checksum and L4 checksum */ 2777 ip_hdr_len = ip4h->ihl; 2778 l4_proto = ip4h->protocol; 2779 } else if (l3_proto == htons(ETH_P_IPV6)) { 2780 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2781 2782 /* Read l4_protocol from one of IPv6 extra headers */ 2783 if (skb_network_header_len(skb) > 0) 2784 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2785 l4_proto = ip6h->nexthdr; 2786 } else { 2787 return MVPP2_TXD_L4_CSUM_NOT; 2788 } 2789 2790 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2791 l3_proto, ip_hdr_len, l4_proto); 2792 } 2793 2794 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2795 } 2796 2797 /* Main rx processing */ 2798 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2799 int rx_todo, struct mvpp2_rx_queue *rxq) 2800 { 2801 struct net_device *dev = port->dev; 2802 int rx_received; 2803 int rx_done = 0; 2804 u32 rcvd_pkts = 0; 2805 u32 rcvd_bytes = 0; 2806 2807 /* Get number of received packets and clamp the to-do */ 2808 rx_received = mvpp2_rxq_received(port, rxq->id); 2809 if (rx_todo > rx_received) 2810 rx_todo = rx_received; 2811 2812 while (rx_done < rx_todo) { 2813 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2814 struct mvpp2_bm_pool *bm_pool; 2815 struct sk_buff *skb; 2816 unsigned int frag_size; 2817 dma_addr_t dma_addr; 2818 phys_addr_t phys_addr; 2819 u32 rx_status; 2820 int pool, rx_bytes, err; 2821 void *data; 2822 2823 rx_done++; 2824 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2825 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2826 rx_bytes -= MVPP2_MH_SIZE; 2827 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2828 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2829 data = (void *)phys_to_virt(phys_addr); 2830 2831 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2832 MVPP2_RXD_BM_POOL_ID_OFFS; 2833 bm_pool = &port->priv->bm_pools[pool]; 2834 2835 /* In case of an error, release the requested buffer pointer 2836 * to the Buffer Manager. This request process is controlled 2837 * by the hardware, and the information about the buffer is 2838 * comprised by the RX descriptor. 2839 */ 2840 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2841 err_drop_frame: 2842 dev->stats.rx_errors++; 2843 mvpp2_rx_error(port, rx_desc); 2844 /* Return the buffer to the pool */ 2845 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2846 continue; 2847 } 2848 2849 if (bm_pool->frag_size > PAGE_SIZE) 2850 frag_size = 0; 2851 else 2852 frag_size = bm_pool->frag_size; 2853 2854 skb = build_skb(data, frag_size); 2855 if (!skb) { 2856 netdev_warn(port->dev, "skb build failed\n"); 2857 goto err_drop_frame; 2858 } 2859 2860 err = mvpp2_rx_refill(port, bm_pool, pool); 2861 if (err) { 2862 netdev_err(port->dev, "failed to refill BM pools\n"); 2863 goto err_drop_frame; 2864 } 2865 2866 dma_unmap_single(dev->dev.parent, dma_addr, 2867 bm_pool->buf_size, DMA_FROM_DEVICE); 2868 2869 rcvd_pkts++; 2870 rcvd_bytes += rx_bytes; 2871 2872 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2873 skb_put(skb, rx_bytes); 2874 skb->protocol = eth_type_trans(skb, dev); 2875 mvpp2_rx_csum(port, rx_status, skb); 2876 2877 napi_gro_receive(napi, skb); 2878 } 2879 2880 if (rcvd_pkts) { 2881 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2882 2883 u64_stats_update_begin(&stats->syncp); 2884 stats->rx_packets += rcvd_pkts; 2885 stats->rx_bytes += rcvd_bytes; 2886 u64_stats_update_end(&stats->syncp); 2887 } 2888 2889 /* Update Rx queue management counters */ 2890 wmb(); 2891 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2892 2893 return rx_todo; 2894 } 2895 2896 static inline void 2897 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2898 struct mvpp2_tx_desc *desc) 2899 { 2900 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2901 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2902 2903 dma_addr_t buf_dma_addr = 2904 mvpp2_txdesc_dma_addr_get(port, desc); 2905 size_t buf_sz = 2906 mvpp2_txdesc_size_get(port, desc); 2907 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2908 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2909 buf_sz, DMA_TO_DEVICE); 2910 mvpp2_txq_desc_put(txq); 2911 } 2912 2913 /* Handle tx fragmentation processing */ 2914 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2915 struct mvpp2_tx_queue *aggr_txq, 2916 struct mvpp2_tx_queue *txq) 2917 { 2918 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2919 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2920 struct mvpp2_tx_desc *tx_desc; 2921 int i; 2922 dma_addr_t buf_dma_addr; 2923 2924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2925 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2926 void *addr = skb_frag_address(frag); 2927 2928 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2929 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2930 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 2931 2932 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2933 skb_frag_size(frag), 2934 DMA_TO_DEVICE); 2935 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2936 mvpp2_txq_desc_put(txq); 2937 goto cleanup; 2938 } 2939 2940 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2941 2942 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2943 /* Last descriptor */ 2944 mvpp2_txdesc_cmd_set(port, tx_desc, 2945 MVPP2_TXD_L_DESC); 2946 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2947 } else { 2948 /* Descriptor in the middle: Not First, Not Last */ 2949 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2950 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2951 } 2952 } 2953 2954 return 0; 2955 cleanup: 2956 /* Release all descriptors that were used to map fragments of 2957 * this packet, as well as the corresponding DMA mappings 2958 */ 2959 for (i = i - 1; i >= 0; i--) { 2960 tx_desc = txq->descs + i; 2961 tx_desc_unmap_put(port, txq, tx_desc); 2962 } 2963 2964 return -ENOMEM; 2965 } 2966 2967 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2968 struct net_device *dev, 2969 struct mvpp2_tx_queue *txq, 2970 struct mvpp2_tx_queue *aggr_txq, 2971 struct mvpp2_txq_pcpu *txq_pcpu, 2972 int hdr_sz) 2973 { 2974 struct mvpp2_port *port = netdev_priv(dev); 2975 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2976 dma_addr_t addr; 2977 2978 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2979 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2980 2981 addr = txq_pcpu->tso_headers_dma + 2982 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2983 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2984 2985 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2986 MVPP2_TXD_F_DESC | 2987 MVPP2_TXD_PADDING_DISABLE); 2988 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2989 } 2990 2991 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2992 struct net_device *dev, struct tso_t *tso, 2993 struct mvpp2_tx_queue *txq, 2994 struct mvpp2_tx_queue *aggr_txq, 2995 struct mvpp2_txq_pcpu *txq_pcpu, 2996 int sz, bool left, bool last) 2997 { 2998 struct mvpp2_port *port = netdev_priv(dev); 2999 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3000 dma_addr_t buf_dma_addr; 3001 3002 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3003 mvpp2_txdesc_size_set(port, tx_desc, sz); 3004 3005 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 3006 DMA_TO_DEVICE); 3007 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3008 mvpp2_txq_desc_put(txq); 3009 return -ENOMEM; 3010 } 3011 3012 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3013 3014 if (!left) { 3015 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 3016 if (last) { 3017 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3018 return 0; 3019 } 3020 } else { 3021 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3022 } 3023 3024 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3025 return 0; 3026 } 3027 3028 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 3029 struct mvpp2_tx_queue *txq, 3030 struct mvpp2_tx_queue *aggr_txq, 3031 struct mvpp2_txq_pcpu *txq_pcpu) 3032 { 3033 struct mvpp2_port *port = netdev_priv(dev); 3034 struct tso_t tso; 3035 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 3036 int i, len, descs = 0; 3037 3038 /* Check number of available descriptors */ 3039 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 3040 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 3041 tso_count_descs(skb))) 3042 return 0; 3043 3044 tso_start(skb, &tso); 3045 len = skb->len - hdr_sz; 3046 while (len > 0) { 3047 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 3048 char *hdr = txq_pcpu->tso_headers + 3049 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3050 3051 len -= left; 3052 descs++; 3053 3054 tso_build_hdr(skb, hdr, &tso, left, len == 0); 3055 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 3056 3057 while (left > 0) { 3058 int sz = min_t(int, tso.size, left); 3059 left -= sz; 3060 descs++; 3061 3062 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 3063 txq_pcpu, sz, left, len == 0)) 3064 goto release; 3065 tso_build_data(skb, &tso, sz); 3066 } 3067 } 3068 3069 return descs; 3070 3071 release: 3072 for (i = descs - 1; i >= 0; i--) { 3073 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 3074 tx_desc_unmap_put(port, txq, tx_desc); 3075 } 3076 return 0; 3077 } 3078 3079 /* Main tx processing */ 3080 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 3081 { 3082 struct mvpp2_port *port = netdev_priv(dev); 3083 struct mvpp2_tx_queue *txq, *aggr_txq; 3084 struct mvpp2_txq_pcpu *txq_pcpu; 3085 struct mvpp2_tx_desc *tx_desc; 3086 dma_addr_t buf_dma_addr; 3087 unsigned long flags = 0; 3088 unsigned int thread; 3089 int frags = 0; 3090 u16 txq_id; 3091 u32 tx_cmd; 3092 3093 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3094 3095 txq_id = skb_get_queue_mapping(skb); 3096 txq = port->txqs[txq_id]; 3097 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3098 aggr_txq = &port->priv->aggr_txqs[thread]; 3099 3100 if (test_bit(thread, &port->priv->lock_map)) 3101 spin_lock_irqsave(&port->tx_lock[thread], flags); 3102 3103 if (skb_is_gso(skb)) { 3104 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 3105 goto out; 3106 } 3107 frags = skb_shinfo(skb)->nr_frags + 1; 3108 3109 /* Check number of available descriptors */ 3110 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 3111 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 3112 frags = 0; 3113 goto out; 3114 } 3115 3116 /* Get a descriptor for the first part of the packet */ 3117 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3118 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3119 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 3120 3121 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 3122 skb_headlen(skb), DMA_TO_DEVICE); 3123 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3124 mvpp2_txq_desc_put(txq); 3125 frags = 0; 3126 goto out; 3127 } 3128 3129 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3130 3131 tx_cmd = mvpp2_skb_tx_csum(port, skb); 3132 3133 if (frags == 1) { 3134 /* First and Last descriptor */ 3135 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3136 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3137 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3138 } else { 3139 /* First but not Last */ 3140 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 3141 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3142 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3143 3144 /* Continue with other skb fragments */ 3145 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 3146 tx_desc_unmap_put(port, txq, tx_desc); 3147 frags = 0; 3148 } 3149 } 3150 3151 out: 3152 if (frags > 0) { 3153 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 3154 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 3155 3156 txq_pcpu->reserved_num -= frags; 3157 txq_pcpu->count += frags; 3158 aggr_txq->count += frags; 3159 3160 /* Enable transmit */ 3161 wmb(); 3162 mvpp2_aggr_txq_pend_desc_add(port, frags); 3163 3164 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3165 netif_tx_stop_queue(nq); 3166 3167 u64_stats_update_begin(&stats->syncp); 3168 stats->tx_packets++; 3169 stats->tx_bytes += skb->len; 3170 u64_stats_update_end(&stats->syncp); 3171 } else { 3172 dev->stats.tx_dropped++; 3173 dev_kfree_skb_any(skb); 3174 } 3175 3176 /* Finalize TX processing */ 3177 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3178 mvpp2_txq_done(port, txq, txq_pcpu); 3179 3180 /* Set the timer in case not all frags were processed */ 3181 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3182 txq_pcpu->count > 0) { 3183 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 3184 3185 mvpp2_timer_set(port_pcpu); 3186 } 3187 3188 if (test_bit(thread, &port->priv->lock_map)) 3189 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 3190 3191 return NETDEV_TX_OK; 3192 } 3193 3194 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3195 { 3196 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3197 netdev_err(dev, "FCS error\n"); 3198 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3199 netdev_err(dev, "rx fifo overrun error\n"); 3200 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3201 netdev_err(dev, "tx fifo underrun error\n"); 3202 } 3203 3204 static int mvpp2_poll(struct napi_struct *napi, int budget) 3205 { 3206 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3207 int rx_done = 0; 3208 struct mvpp2_port *port = netdev_priv(napi->dev); 3209 struct mvpp2_queue_vector *qv; 3210 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3211 3212 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3213 3214 /* Rx/Tx cause register 3215 * 3216 * Bits 0-15: each bit indicates received packets on the Rx queue 3217 * (bit 0 is for Rx queue 0). 3218 * 3219 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3220 * (bit 16 is for Tx queue 0). 3221 * 3222 * Each CPU has its own Rx/Tx cause register 3223 */ 3224 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 3225 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3226 3227 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3228 if (cause_misc) { 3229 mvpp2_cause_error(port->dev, cause_misc); 3230 3231 /* Clear the cause register */ 3232 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3233 mvpp2_thread_write(port->priv, thread, 3234 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3235 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3236 } 3237 3238 if (port->has_tx_irqs) { 3239 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3240 if (cause_tx) { 3241 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3242 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3243 } 3244 } 3245 3246 /* Process RX packets */ 3247 cause_rx = cause_rx_tx & 3248 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 3249 cause_rx <<= qv->first_rxq; 3250 cause_rx |= qv->pending_cause_rx; 3251 while (cause_rx && budget > 0) { 3252 int count; 3253 struct mvpp2_rx_queue *rxq; 3254 3255 rxq = mvpp2_get_rx_queue(port, cause_rx); 3256 if (!rxq) 3257 break; 3258 3259 count = mvpp2_rx(port, napi, budget, rxq); 3260 rx_done += count; 3261 budget -= count; 3262 if (budget > 0) { 3263 /* Clear the bit associated to this Rx queue 3264 * so that next iteration will continue from 3265 * the next Rx queue. 3266 */ 3267 cause_rx &= ~(1 << rxq->logic_rxq); 3268 } 3269 } 3270 3271 if (budget > 0) { 3272 cause_rx = 0; 3273 napi_complete_done(napi, rx_done); 3274 3275 mvpp2_qvec_interrupt_enable(qv); 3276 } 3277 qv->pending_cause_rx = cause_rx; 3278 return rx_done; 3279 } 3280 3281 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3282 { 3283 u32 ctrl3; 3284 3285 /* Set the GMAC & XLG MAC in reset */ 3286 mvpp2_mac_reset_assert(port); 3287 3288 /* Set the MPCS and XPCS in reset */ 3289 mvpp22_pcs_reset_assert(port); 3290 3291 /* comphy reconfiguration */ 3292 mvpp22_comphy_init(port); 3293 3294 /* gop reconfiguration */ 3295 mvpp22_gop_init(port); 3296 3297 mvpp22_pcs_reset_deassert(port); 3298 3299 /* Only GOP port 0 has an XLG MAC */ 3300 if (port->gop_id == 0) { 3301 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3302 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3303 3304 if (mvpp2_is_xlg(port->phy_interface)) 3305 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3306 else 3307 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3308 3309 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3310 } 3311 3312 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) 3313 mvpp2_xlg_max_rx_size_set(port); 3314 else 3315 mvpp2_gmac_max_rx_size_set(port); 3316 } 3317 3318 /* Set hw internals when starting port */ 3319 static void mvpp2_start_dev(struct mvpp2_port *port) 3320 { 3321 int i; 3322 3323 mvpp2_txp_max_tx_size_set(port); 3324 3325 for (i = 0; i < port->nqvecs; i++) 3326 napi_enable(&port->qvecs[i].napi); 3327 3328 /* Enable interrupts on all threads */ 3329 mvpp2_interrupts_enable(port); 3330 3331 if (port->priv->hw_version == MVPP22) 3332 mvpp22_mode_reconfigure(port); 3333 3334 if (port->phylink) { 3335 phylink_start(port->phylink); 3336 } else { 3337 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3338 * configured manually when the interface is started. This will 3339 * be removed as soon as the phylink ACPI support lands in. 3340 */ 3341 struct phylink_link_state state = { 3342 .interface = port->phy_interface, 3343 }; 3344 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 3345 mvpp2_mac_link_up(&port->phylink_config, MLO_AN_INBAND, 3346 port->phy_interface, NULL); 3347 } 3348 3349 netif_tx_start_all_queues(port->dev); 3350 } 3351 3352 /* Set hw internals when stopping port */ 3353 static void mvpp2_stop_dev(struct mvpp2_port *port) 3354 { 3355 int i; 3356 3357 /* Disable interrupts on all threads */ 3358 mvpp2_interrupts_disable(port); 3359 3360 for (i = 0; i < port->nqvecs; i++) 3361 napi_disable(&port->qvecs[i].napi); 3362 3363 if (port->phylink) 3364 phylink_stop(port->phylink); 3365 phy_power_off(port->comphy); 3366 } 3367 3368 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3369 struct ethtool_ringparam *ring) 3370 { 3371 u16 new_rx_pending = ring->rx_pending; 3372 u16 new_tx_pending = ring->tx_pending; 3373 3374 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3375 return -EINVAL; 3376 3377 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3378 new_rx_pending = MVPP2_MAX_RXD_MAX; 3379 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3380 new_rx_pending = ALIGN(ring->rx_pending, 16); 3381 3382 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3383 new_tx_pending = MVPP2_MAX_TXD_MAX; 3384 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3385 new_tx_pending = ALIGN(ring->tx_pending, 32); 3386 3387 /* The Tx ring size cannot be smaller than the minimum number of 3388 * descriptors needed for TSO. 3389 */ 3390 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3391 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3392 3393 if (ring->rx_pending != new_rx_pending) { 3394 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3395 ring->rx_pending, new_rx_pending); 3396 ring->rx_pending = new_rx_pending; 3397 } 3398 3399 if (ring->tx_pending != new_tx_pending) { 3400 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3401 ring->tx_pending, new_tx_pending); 3402 ring->tx_pending = new_tx_pending; 3403 } 3404 3405 return 0; 3406 } 3407 3408 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3409 { 3410 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3411 3412 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3413 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3414 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3415 addr[0] = (mac_addr_h >> 24) & 0xFF; 3416 addr[1] = (mac_addr_h >> 16) & 0xFF; 3417 addr[2] = (mac_addr_h >> 8) & 0xFF; 3418 addr[3] = mac_addr_h & 0xFF; 3419 addr[4] = mac_addr_m & 0xFF; 3420 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3421 } 3422 3423 static int mvpp2_irqs_init(struct mvpp2_port *port) 3424 { 3425 int err, i; 3426 3427 for (i = 0; i < port->nqvecs; i++) { 3428 struct mvpp2_queue_vector *qv = port->qvecs + i; 3429 3430 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3431 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 3432 if (!qv->mask) { 3433 err = -ENOMEM; 3434 goto err; 3435 } 3436 3437 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3438 } 3439 3440 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3441 if (err) 3442 goto err; 3443 3444 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3445 unsigned int cpu; 3446 3447 for_each_present_cpu(cpu) { 3448 if (mvpp2_cpu_to_thread(port->priv, cpu) == 3449 qv->sw_thread_id) 3450 cpumask_set_cpu(cpu, qv->mask); 3451 } 3452 3453 irq_set_affinity_hint(qv->irq, qv->mask); 3454 } 3455 } 3456 3457 return 0; 3458 err: 3459 for (i = 0; i < port->nqvecs; i++) { 3460 struct mvpp2_queue_vector *qv = port->qvecs + i; 3461 3462 irq_set_affinity_hint(qv->irq, NULL); 3463 kfree(qv->mask); 3464 qv->mask = NULL; 3465 free_irq(qv->irq, qv); 3466 } 3467 3468 return err; 3469 } 3470 3471 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3472 { 3473 int i; 3474 3475 for (i = 0; i < port->nqvecs; i++) { 3476 struct mvpp2_queue_vector *qv = port->qvecs + i; 3477 3478 irq_set_affinity_hint(qv->irq, NULL); 3479 kfree(qv->mask); 3480 qv->mask = NULL; 3481 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3482 free_irq(qv->irq, qv); 3483 } 3484 } 3485 3486 static bool mvpp22_rss_is_supported(void) 3487 { 3488 return queue_mode == MVPP2_QDIST_MULTI_MODE; 3489 } 3490 3491 static int mvpp2_open(struct net_device *dev) 3492 { 3493 struct mvpp2_port *port = netdev_priv(dev); 3494 struct mvpp2 *priv = port->priv; 3495 unsigned char mac_bcast[ETH_ALEN] = { 3496 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3497 bool valid = false; 3498 int err; 3499 3500 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3501 if (err) { 3502 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3503 return err; 3504 } 3505 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3506 if (err) { 3507 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3508 return err; 3509 } 3510 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3511 if (err) { 3512 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3513 return err; 3514 } 3515 err = mvpp2_prs_def_flow(port); 3516 if (err) { 3517 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3518 return err; 3519 } 3520 3521 /* Allocate the Rx/Tx queues */ 3522 err = mvpp2_setup_rxqs(port); 3523 if (err) { 3524 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3525 return err; 3526 } 3527 3528 err = mvpp2_setup_txqs(port); 3529 if (err) { 3530 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3531 goto err_cleanup_rxqs; 3532 } 3533 3534 err = mvpp2_irqs_init(port); 3535 if (err) { 3536 netdev_err(port->dev, "cannot init IRQs\n"); 3537 goto err_cleanup_txqs; 3538 } 3539 3540 /* Phylink isn't supported yet in ACPI mode */ 3541 if (port->of_node) { 3542 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3543 if (err) { 3544 netdev_err(port->dev, "could not attach PHY (%d)\n", 3545 err); 3546 goto err_free_irq; 3547 } 3548 3549 valid = true; 3550 } 3551 3552 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3553 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3554 dev->name, port); 3555 if (err) { 3556 netdev_err(port->dev, "cannot request link IRQ %d\n", 3557 port->link_irq); 3558 goto err_free_irq; 3559 } 3560 3561 mvpp22_gop_setup_irq(port); 3562 3563 /* In default link is down */ 3564 netif_carrier_off(port->dev); 3565 3566 valid = true; 3567 } else { 3568 port->link_irq = 0; 3569 } 3570 3571 if (!valid) { 3572 netdev_err(port->dev, 3573 "invalid configuration: no dt or link IRQ"); 3574 goto err_free_irq; 3575 } 3576 3577 /* Unmask interrupts on all CPUs */ 3578 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3579 mvpp2_shared_interrupt_mask_unmask(port, false); 3580 3581 mvpp2_start_dev(port); 3582 3583 /* Start hardware statistics gathering */ 3584 queue_delayed_work(priv->stats_queue, &port->stats_work, 3585 MVPP2_MIB_COUNTERS_STATS_DELAY); 3586 3587 return 0; 3588 3589 err_free_irq: 3590 mvpp2_irqs_deinit(port); 3591 err_cleanup_txqs: 3592 mvpp2_cleanup_txqs(port); 3593 err_cleanup_rxqs: 3594 mvpp2_cleanup_rxqs(port); 3595 return err; 3596 } 3597 3598 static int mvpp2_stop(struct net_device *dev) 3599 { 3600 struct mvpp2_port *port = netdev_priv(dev); 3601 struct mvpp2_port_pcpu *port_pcpu; 3602 unsigned int thread; 3603 3604 mvpp2_stop_dev(port); 3605 3606 /* Mask interrupts on all threads */ 3607 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3608 mvpp2_shared_interrupt_mask_unmask(port, true); 3609 3610 if (port->phylink) 3611 phylink_disconnect_phy(port->phylink); 3612 if (port->link_irq) 3613 free_irq(port->link_irq, port); 3614 3615 mvpp2_irqs_deinit(port); 3616 if (!port->has_tx_irqs) { 3617 for (thread = 0; thread < port->priv->nthreads; thread++) { 3618 port_pcpu = per_cpu_ptr(port->pcpu, thread); 3619 3620 hrtimer_cancel(&port_pcpu->tx_done_timer); 3621 port_pcpu->timer_scheduled = false; 3622 tasklet_kill(&port_pcpu->tx_done_tasklet); 3623 } 3624 } 3625 mvpp2_cleanup_rxqs(port); 3626 mvpp2_cleanup_txqs(port); 3627 3628 cancel_delayed_work_sync(&port->stats_work); 3629 3630 mvpp2_mac_reset_assert(port); 3631 mvpp22_pcs_reset_assert(port); 3632 3633 return 0; 3634 } 3635 3636 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3637 struct netdev_hw_addr_list *list) 3638 { 3639 struct netdev_hw_addr *ha; 3640 int ret; 3641 3642 netdev_hw_addr_list_for_each(ha, list) { 3643 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3644 if (ret) 3645 return ret; 3646 } 3647 3648 return 0; 3649 } 3650 3651 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3652 { 3653 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3654 mvpp2_prs_vid_enable_filtering(port); 3655 else 3656 mvpp2_prs_vid_disable_filtering(port); 3657 3658 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3659 MVPP2_PRS_L2_UNI_CAST, enable); 3660 3661 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3662 MVPP2_PRS_L2_MULTI_CAST, enable); 3663 } 3664 3665 static void mvpp2_set_rx_mode(struct net_device *dev) 3666 { 3667 struct mvpp2_port *port = netdev_priv(dev); 3668 3669 /* Clear the whole UC and MC list */ 3670 mvpp2_prs_mac_del_all(port); 3671 3672 if (dev->flags & IFF_PROMISC) { 3673 mvpp2_set_rx_promisc(port, true); 3674 return; 3675 } 3676 3677 mvpp2_set_rx_promisc(port, false); 3678 3679 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3680 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3681 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3682 MVPP2_PRS_L2_UNI_CAST, true); 3683 3684 if (dev->flags & IFF_ALLMULTI) { 3685 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3686 MVPP2_PRS_L2_MULTI_CAST, true); 3687 return; 3688 } 3689 3690 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3691 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3692 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3693 MVPP2_PRS_L2_MULTI_CAST, true); 3694 } 3695 3696 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3697 { 3698 const struct sockaddr *addr = p; 3699 int err; 3700 3701 if (!is_valid_ether_addr(addr->sa_data)) 3702 return -EADDRNOTAVAIL; 3703 3704 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3705 if (err) { 3706 /* Reconfigure parser accept the original MAC address */ 3707 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3708 netdev_err(dev, "failed to change MAC address\n"); 3709 } 3710 return err; 3711 } 3712 3713 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3714 { 3715 struct mvpp2_port *port = netdev_priv(dev); 3716 bool running = netif_running(dev); 3717 int err; 3718 3719 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3720 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3721 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3722 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3723 } 3724 3725 if (running) 3726 mvpp2_stop_dev(port); 3727 3728 err = mvpp2_bm_update_mtu(dev, mtu); 3729 if (err) { 3730 netdev_err(dev, "failed to change MTU\n"); 3731 /* Reconfigure BM to the original MTU */ 3732 mvpp2_bm_update_mtu(dev, dev->mtu); 3733 } else { 3734 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3735 } 3736 3737 if (running) { 3738 mvpp2_start_dev(port); 3739 mvpp2_egress_enable(port); 3740 mvpp2_ingress_enable(port); 3741 } 3742 3743 return err; 3744 } 3745 3746 static void 3747 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3748 { 3749 struct mvpp2_port *port = netdev_priv(dev); 3750 unsigned int start; 3751 unsigned int cpu; 3752 3753 for_each_possible_cpu(cpu) { 3754 struct mvpp2_pcpu_stats *cpu_stats; 3755 u64 rx_packets; 3756 u64 rx_bytes; 3757 u64 tx_packets; 3758 u64 tx_bytes; 3759 3760 cpu_stats = per_cpu_ptr(port->stats, cpu); 3761 do { 3762 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3763 rx_packets = cpu_stats->rx_packets; 3764 rx_bytes = cpu_stats->rx_bytes; 3765 tx_packets = cpu_stats->tx_packets; 3766 tx_bytes = cpu_stats->tx_bytes; 3767 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3768 3769 stats->rx_packets += rx_packets; 3770 stats->rx_bytes += rx_bytes; 3771 stats->tx_packets += tx_packets; 3772 stats->tx_bytes += tx_bytes; 3773 } 3774 3775 stats->rx_errors = dev->stats.rx_errors; 3776 stats->rx_dropped = dev->stats.rx_dropped; 3777 stats->tx_dropped = dev->stats.tx_dropped; 3778 } 3779 3780 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3781 { 3782 struct mvpp2_port *port = netdev_priv(dev); 3783 3784 if (!port->phylink) 3785 return -ENOTSUPP; 3786 3787 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3788 } 3789 3790 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3791 { 3792 struct mvpp2_port *port = netdev_priv(dev); 3793 int ret; 3794 3795 ret = mvpp2_prs_vid_entry_add(port, vid); 3796 if (ret) 3797 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3798 MVPP2_PRS_VLAN_FILT_MAX - 1); 3799 return ret; 3800 } 3801 3802 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3803 { 3804 struct mvpp2_port *port = netdev_priv(dev); 3805 3806 mvpp2_prs_vid_entry_remove(port, vid); 3807 return 0; 3808 } 3809 3810 static int mvpp2_set_features(struct net_device *dev, 3811 netdev_features_t features) 3812 { 3813 netdev_features_t changed = dev->features ^ features; 3814 struct mvpp2_port *port = netdev_priv(dev); 3815 3816 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3817 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3818 mvpp2_prs_vid_enable_filtering(port); 3819 } else { 3820 /* Invalidate all registered VID filters for this 3821 * port 3822 */ 3823 mvpp2_prs_vid_remove_all(port); 3824 3825 mvpp2_prs_vid_disable_filtering(port); 3826 } 3827 } 3828 3829 if (changed & NETIF_F_RXHASH) { 3830 if (features & NETIF_F_RXHASH) 3831 mvpp22_port_rss_enable(port); 3832 else 3833 mvpp22_port_rss_disable(port); 3834 } 3835 3836 return 0; 3837 } 3838 3839 /* Ethtool methods */ 3840 3841 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3842 { 3843 struct mvpp2_port *port = netdev_priv(dev); 3844 3845 if (!port->phylink) 3846 return -ENOTSUPP; 3847 3848 return phylink_ethtool_nway_reset(port->phylink); 3849 } 3850 3851 /* Set interrupt coalescing for ethtools */ 3852 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3853 struct ethtool_coalesce *c) 3854 { 3855 struct mvpp2_port *port = netdev_priv(dev); 3856 int queue; 3857 3858 for (queue = 0; queue < port->nrxqs; queue++) { 3859 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3860 3861 rxq->time_coal = c->rx_coalesce_usecs; 3862 rxq->pkts_coal = c->rx_max_coalesced_frames; 3863 mvpp2_rx_pkts_coal_set(port, rxq); 3864 mvpp2_rx_time_coal_set(port, rxq); 3865 } 3866 3867 if (port->has_tx_irqs) { 3868 port->tx_time_coal = c->tx_coalesce_usecs; 3869 mvpp2_tx_time_coal_set(port); 3870 } 3871 3872 for (queue = 0; queue < port->ntxqs; queue++) { 3873 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3874 3875 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3876 3877 if (port->has_tx_irqs) 3878 mvpp2_tx_pkts_coal_set(port, txq); 3879 } 3880 3881 return 0; 3882 } 3883 3884 /* get coalescing for ethtools */ 3885 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3886 struct ethtool_coalesce *c) 3887 { 3888 struct mvpp2_port *port = netdev_priv(dev); 3889 3890 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3891 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3892 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3893 c->tx_coalesce_usecs = port->tx_time_coal; 3894 return 0; 3895 } 3896 3897 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3898 struct ethtool_drvinfo *drvinfo) 3899 { 3900 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3901 sizeof(drvinfo->driver)); 3902 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3903 sizeof(drvinfo->version)); 3904 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3905 sizeof(drvinfo->bus_info)); 3906 } 3907 3908 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3909 struct ethtool_ringparam *ring) 3910 { 3911 struct mvpp2_port *port = netdev_priv(dev); 3912 3913 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3914 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3915 ring->rx_pending = port->rx_ring_size; 3916 ring->tx_pending = port->tx_ring_size; 3917 } 3918 3919 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3920 struct ethtool_ringparam *ring) 3921 { 3922 struct mvpp2_port *port = netdev_priv(dev); 3923 u16 prev_rx_ring_size = port->rx_ring_size; 3924 u16 prev_tx_ring_size = port->tx_ring_size; 3925 int err; 3926 3927 err = mvpp2_check_ringparam_valid(dev, ring); 3928 if (err) 3929 return err; 3930 3931 if (!netif_running(dev)) { 3932 port->rx_ring_size = ring->rx_pending; 3933 port->tx_ring_size = ring->tx_pending; 3934 return 0; 3935 } 3936 3937 /* The interface is running, so we have to force a 3938 * reallocation of the queues 3939 */ 3940 mvpp2_stop_dev(port); 3941 mvpp2_cleanup_rxqs(port); 3942 mvpp2_cleanup_txqs(port); 3943 3944 port->rx_ring_size = ring->rx_pending; 3945 port->tx_ring_size = ring->tx_pending; 3946 3947 err = mvpp2_setup_rxqs(port); 3948 if (err) { 3949 /* Reallocate Rx queues with the original ring size */ 3950 port->rx_ring_size = prev_rx_ring_size; 3951 ring->rx_pending = prev_rx_ring_size; 3952 err = mvpp2_setup_rxqs(port); 3953 if (err) 3954 goto err_out; 3955 } 3956 err = mvpp2_setup_txqs(port); 3957 if (err) { 3958 /* Reallocate Tx queues with the original ring size */ 3959 port->tx_ring_size = prev_tx_ring_size; 3960 ring->tx_pending = prev_tx_ring_size; 3961 err = mvpp2_setup_txqs(port); 3962 if (err) 3963 goto err_clean_rxqs; 3964 } 3965 3966 mvpp2_start_dev(port); 3967 mvpp2_egress_enable(port); 3968 mvpp2_ingress_enable(port); 3969 3970 return 0; 3971 3972 err_clean_rxqs: 3973 mvpp2_cleanup_rxqs(port); 3974 err_out: 3975 netdev_err(dev, "failed to change ring parameters"); 3976 return err; 3977 } 3978 3979 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3980 struct ethtool_pauseparam *pause) 3981 { 3982 struct mvpp2_port *port = netdev_priv(dev); 3983 3984 if (!port->phylink) 3985 return; 3986 3987 phylink_ethtool_get_pauseparam(port->phylink, pause); 3988 } 3989 3990 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3991 struct ethtool_pauseparam *pause) 3992 { 3993 struct mvpp2_port *port = netdev_priv(dev); 3994 3995 if (!port->phylink) 3996 return -ENOTSUPP; 3997 3998 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3999 } 4000 4001 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 4002 struct ethtool_link_ksettings *cmd) 4003 { 4004 struct mvpp2_port *port = netdev_priv(dev); 4005 4006 if (!port->phylink) 4007 return -ENOTSUPP; 4008 4009 return phylink_ethtool_ksettings_get(port->phylink, cmd); 4010 } 4011 4012 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 4013 const struct ethtool_link_ksettings *cmd) 4014 { 4015 struct mvpp2_port *port = netdev_priv(dev); 4016 4017 if (!port->phylink) 4018 return -ENOTSUPP; 4019 4020 return phylink_ethtool_ksettings_set(port->phylink, cmd); 4021 } 4022 4023 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 4024 struct ethtool_rxnfc *info, u32 *rules) 4025 { 4026 struct mvpp2_port *port = netdev_priv(dev); 4027 int ret = 0, i, loc = 0; 4028 4029 if (!mvpp22_rss_is_supported()) 4030 return -EOPNOTSUPP; 4031 4032 switch (info->cmd) { 4033 case ETHTOOL_GRXFH: 4034 ret = mvpp2_ethtool_rxfh_get(port, info); 4035 break; 4036 case ETHTOOL_GRXRINGS: 4037 info->data = port->nrxqs; 4038 break; 4039 case ETHTOOL_GRXCLSRLCNT: 4040 info->rule_cnt = port->n_rfs_rules; 4041 break; 4042 case ETHTOOL_GRXCLSRULE: 4043 ret = mvpp2_ethtool_cls_rule_get(port, info); 4044 break; 4045 case ETHTOOL_GRXCLSRLALL: 4046 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 4047 if (port->rfs_rules[i]) 4048 rules[loc++] = i; 4049 } 4050 break; 4051 default: 4052 return -ENOTSUPP; 4053 } 4054 4055 return ret; 4056 } 4057 4058 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 4059 struct ethtool_rxnfc *info) 4060 { 4061 struct mvpp2_port *port = netdev_priv(dev); 4062 int ret = 0; 4063 4064 if (!mvpp22_rss_is_supported()) 4065 return -EOPNOTSUPP; 4066 4067 switch (info->cmd) { 4068 case ETHTOOL_SRXFH: 4069 ret = mvpp2_ethtool_rxfh_set(port, info); 4070 break; 4071 case ETHTOOL_SRXCLSRLINS: 4072 ret = mvpp2_ethtool_cls_rule_ins(port, info); 4073 break; 4074 case ETHTOOL_SRXCLSRLDEL: 4075 ret = mvpp2_ethtool_cls_rule_del(port, info); 4076 break; 4077 default: 4078 return -EOPNOTSUPP; 4079 } 4080 return ret; 4081 } 4082 4083 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 4084 { 4085 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 4086 } 4087 4088 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 4089 u8 *hfunc) 4090 { 4091 struct mvpp2_port *port = netdev_priv(dev); 4092 int ret = 0; 4093 4094 if (!mvpp22_rss_is_supported()) 4095 return -EOPNOTSUPP; 4096 4097 if (indir) 4098 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 4099 4100 if (hfunc) 4101 *hfunc = ETH_RSS_HASH_CRC32; 4102 4103 return ret; 4104 } 4105 4106 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 4107 const u8 *key, const u8 hfunc) 4108 { 4109 struct mvpp2_port *port = netdev_priv(dev); 4110 int ret = 0; 4111 4112 if (!mvpp22_rss_is_supported()) 4113 return -EOPNOTSUPP; 4114 4115 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4116 return -EOPNOTSUPP; 4117 4118 if (key) 4119 return -EOPNOTSUPP; 4120 4121 if (indir) 4122 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 4123 4124 return ret; 4125 } 4126 4127 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 4128 u8 *key, u8 *hfunc, u32 rss_context) 4129 { 4130 struct mvpp2_port *port = netdev_priv(dev); 4131 int ret = 0; 4132 4133 if (!mvpp22_rss_is_supported()) 4134 return -EOPNOTSUPP; 4135 4136 if (hfunc) 4137 *hfunc = ETH_RSS_HASH_CRC32; 4138 4139 if (indir) 4140 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 4141 4142 return ret; 4143 } 4144 4145 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 4146 const u32 *indir, const u8 *key, 4147 const u8 hfunc, u32 *rss_context, 4148 bool delete) 4149 { 4150 struct mvpp2_port *port = netdev_priv(dev); 4151 int ret; 4152 4153 if (!mvpp22_rss_is_supported()) 4154 return -EOPNOTSUPP; 4155 4156 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4157 return -EOPNOTSUPP; 4158 4159 if (key) 4160 return -EOPNOTSUPP; 4161 4162 if (delete) 4163 return mvpp22_port_rss_ctx_delete(port, *rss_context); 4164 4165 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 4166 ret = mvpp22_port_rss_ctx_create(port, rss_context); 4167 if (ret) 4168 return ret; 4169 } 4170 4171 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 4172 } 4173 /* Device ops */ 4174 4175 static const struct net_device_ops mvpp2_netdev_ops = { 4176 .ndo_open = mvpp2_open, 4177 .ndo_stop = mvpp2_stop, 4178 .ndo_start_xmit = mvpp2_tx, 4179 .ndo_set_rx_mode = mvpp2_set_rx_mode, 4180 .ndo_set_mac_address = mvpp2_set_mac_address, 4181 .ndo_change_mtu = mvpp2_change_mtu, 4182 .ndo_get_stats64 = mvpp2_get_stats64, 4183 .ndo_do_ioctl = mvpp2_ioctl, 4184 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 4185 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 4186 .ndo_set_features = mvpp2_set_features, 4187 }; 4188 4189 static const struct ethtool_ops mvpp2_eth_tool_ops = { 4190 .nway_reset = mvpp2_ethtool_nway_reset, 4191 .get_link = ethtool_op_get_link, 4192 .set_coalesce = mvpp2_ethtool_set_coalesce, 4193 .get_coalesce = mvpp2_ethtool_get_coalesce, 4194 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 4195 .get_ringparam = mvpp2_ethtool_get_ringparam, 4196 .set_ringparam = mvpp2_ethtool_set_ringparam, 4197 .get_strings = mvpp2_ethtool_get_strings, 4198 .get_ethtool_stats = mvpp2_ethtool_get_stats, 4199 .get_sset_count = mvpp2_ethtool_get_sset_count, 4200 .get_pauseparam = mvpp2_ethtool_get_pause_param, 4201 .set_pauseparam = mvpp2_ethtool_set_pause_param, 4202 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 4203 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 4204 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 4205 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 4206 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 4207 .get_rxfh = mvpp2_ethtool_get_rxfh, 4208 .set_rxfh = mvpp2_ethtool_set_rxfh, 4209 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 4210 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 4211 }; 4212 4213 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 4214 * had a single IRQ defined per-port. 4215 */ 4216 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 4217 struct device_node *port_node) 4218 { 4219 struct mvpp2_queue_vector *v = &port->qvecs[0]; 4220 4221 v->first_rxq = 0; 4222 v->nrxqs = port->nrxqs; 4223 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4224 v->sw_thread_id = 0; 4225 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 4226 v->port = port; 4227 v->irq = irq_of_parse_and_map(port_node, 0); 4228 if (v->irq <= 0) 4229 return -EINVAL; 4230 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4231 NAPI_POLL_WEIGHT); 4232 4233 port->nqvecs = 1; 4234 4235 return 0; 4236 } 4237 4238 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 4239 struct device_node *port_node) 4240 { 4241 struct mvpp2 *priv = port->priv; 4242 struct mvpp2_queue_vector *v; 4243 int i, ret; 4244 4245 switch (queue_mode) { 4246 case MVPP2_QDIST_SINGLE_MODE: 4247 port->nqvecs = priv->nthreads + 1; 4248 break; 4249 case MVPP2_QDIST_MULTI_MODE: 4250 port->nqvecs = priv->nthreads; 4251 break; 4252 } 4253 4254 for (i = 0; i < port->nqvecs; i++) { 4255 char irqname[16]; 4256 4257 v = port->qvecs + i; 4258 4259 v->port = port; 4260 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 4261 v->sw_thread_id = i; 4262 v->sw_thread_mask = BIT(i); 4263 4264 if (port->flags & MVPP2_F_DT_COMPAT) 4265 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 4266 else 4267 snprintf(irqname, sizeof(irqname), "hif%d", i); 4268 4269 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 4270 v->first_rxq = i; 4271 v->nrxqs = 1; 4272 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 4273 i == (port->nqvecs - 1)) { 4274 v->first_rxq = 0; 4275 v->nrxqs = port->nrxqs; 4276 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4277 4278 if (port->flags & MVPP2_F_DT_COMPAT) 4279 strncpy(irqname, "rx-shared", sizeof(irqname)); 4280 } 4281 4282 if (port_node) 4283 v->irq = of_irq_get_byname(port_node, irqname); 4284 else 4285 v->irq = fwnode_irq_get(port->fwnode, i); 4286 if (v->irq <= 0) { 4287 ret = -EINVAL; 4288 goto err; 4289 } 4290 4291 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4292 NAPI_POLL_WEIGHT); 4293 } 4294 4295 return 0; 4296 4297 err: 4298 for (i = 0; i < port->nqvecs; i++) 4299 irq_dispose_mapping(port->qvecs[i].irq); 4300 return ret; 4301 } 4302 4303 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 4304 struct device_node *port_node) 4305 { 4306 if (port->has_tx_irqs) 4307 return mvpp2_multi_queue_vectors_init(port, port_node); 4308 else 4309 return mvpp2_simple_queue_vectors_init(port, port_node); 4310 } 4311 4312 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 4313 { 4314 int i; 4315 4316 for (i = 0; i < port->nqvecs; i++) 4317 irq_dispose_mapping(port->qvecs[i].irq); 4318 } 4319 4320 /* Configure Rx queue group interrupt for this port */ 4321 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 4322 { 4323 struct mvpp2 *priv = port->priv; 4324 u32 val; 4325 int i; 4326 4327 if (priv->hw_version == MVPP21) { 4328 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 4329 port->nrxqs); 4330 return; 4331 } 4332 4333 /* Handle the more complicated PPv2.2 case */ 4334 for (i = 0; i < port->nqvecs; i++) { 4335 struct mvpp2_queue_vector *qv = port->qvecs + i; 4336 4337 if (!qv->nrxqs) 4338 continue; 4339 4340 val = qv->sw_thread_id; 4341 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 4342 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 4343 4344 val = qv->first_rxq; 4345 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 4346 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 4347 } 4348 } 4349 4350 /* Initialize port HW */ 4351 static int mvpp2_port_init(struct mvpp2_port *port) 4352 { 4353 struct device *dev = port->dev->dev.parent; 4354 struct mvpp2 *priv = port->priv; 4355 struct mvpp2_txq_pcpu *txq_pcpu; 4356 unsigned int thread; 4357 int queue, err; 4358 4359 /* Checks for hardware constraints */ 4360 if (port->first_rxq + port->nrxqs > 4361 MVPP2_MAX_PORTS * priv->max_port_rxqs) 4362 return -EINVAL; 4363 4364 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 4365 return -EINVAL; 4366 4367 /* Disable port */ 4368 mvpp2_egress_disable(port); 4369 mvpp2_port_disable(port); 4370 4371 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4372 4373 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4374 GFP_KERNEL); 4375 if (!port->txqs) 4376 return -ENOMEM; 4377 4378 /* Associate physical Tx queues to this port and initialize. 4379 * The mapping is predefined. 4380 */ 4381 for (queue = 0; queue < port->ntxqs; queue++) { 4382 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4383 struct mvpp2_tx_queue *txq; 4384 4385 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4386 if (!txq) { 4387 err = -ENOMEM; 4388 goto err_free_percpu; 4389 } 4390 4391 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4392 if (!txq->pcpu) { 4393 err = -ENOMEM; 4394 goto err_free_percpu; 4395 } 4396 4397 txq->id = queue_phy_id; 4398 txq->log_id = queue; 4399 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4400 for (thread = 0; thread < priv->nthreads; thread++) { 4401 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4402 txq_pcpu->thread = thread; 4403 } 4404 4405 port->txqs[queue] = txq; 4406 } 4407 4408 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4409 GFP_KERNEL); 4410 if (!port->rxqs) { 4411 err = -ENOMEM; 4412 goto err_free_percpu; 4413 } 4414 4415 /* Allocate and initialize Rx queue for this port */ 4416 for (queue = 0; queue < port->nrxqs; queue++) { 4417 struct mvpp2_rx_queue *rxq; 4418 4419 /* Map physical Rx queue to port's logical Rx queue */ 4420 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4421 if (!rxq) { 4422 err = -ENOMEM; 4423 goto err_free_percpu; 4424 } 4425 /* Map this Rx queue to a physical queue */ 4426 rxq->id = port->first_rxq + queue; 4427 rxq->port = port->id; 4428 rxq->logic_rxq = queue; 4429 4430 port->rxqs[queue] = rxq; 4431 } 4432 4433 mvpp2_rx_irqs_setup(port); 4434 4435 /* Create Rx descriptor rings */ 4436 for (queue = 0; queue < port->nrxqs; queue++) { 4437 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4438 4439 rxq->size = port->rx_ring_size; 4440 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4441 rxq->time_coal = MVPP2_RX_COAL_USEC; 4442 } 4443 4444 mvpp2_ingress_disable(port); 4445 4446 /* Port default configuration */ 4447 mvpp2_defaults_set(port); 4448 4449 /* Port's classifier configuration */ 4450 mvpp2_cls_oversize_rxq_set(port); 4451 mvpp2_cls_port_config(port); 4452 4453 if (mvpp22_rss_is_supported()) 4454 mvpp22_port_rss_init(port); 4455 4456 /* Provide an initial Rx packet size */ 4457 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4458 4459 /* Initialize pools for swf */ 4460 err = mvpp2_swf_bm_pool_init(port); 4461 if (err) 4462 goto err_free_percpu; 4463 4464 /* Clear all port stats */ 4465 mvpp2_read_stats(port); 4466 memset(port->ethtool_stats, 0, 4467 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 4468 4469 return 0; 4470 4471 err_free_percpu: 4472 for (queue = 0; queue < port->ntxqs; queue++) { 4473 if (!port->txqs[queue]) 4474 continue; 4475 free_percpu(port->txqs[queue]->pcpu); 4476 } 4477 return err; 4478 } 4479 4480 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 4481 unsigned long *flags) 4482 { 4483 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 4484 "tx-cpu3" }; 4485 int i; 4486 4487 for (i = 0; i < 5; i++) 4488 if (of_property_match_string(port_node, "interrupt-names", 4489 irqs[i]) < 0) 4490 return false; 4491 4492 *flags |= MVPP2_F_DT_COMPAT; 4493 return true; 4494 } 4495 4496 /* Checks if the port dt description has the required Tx interrupts: 4497 * - PPv2.1: there are no such interrupts. 4498 * - PPv2.2: 4499 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 4500 * - The new ones have: "hifX" with X in [0..8] 4501 * 4502 * All those variants are supported to keep the backward compatibility. 4503 */ 4504 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 4505 struct device_node *port_node, 4506 unsigned long *flags) 4507 { 4508 char name[5]; 4509 int i; 4510 4511 /* ACPI */ 4512 if (!port_node) 4513 return true; 4514 4515 if (priv->hw_version == MVPP21) 4516 return false; 4517 4518 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 4519 return true; 4520 4521 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 4522 snprintf(name, 5, "hif%d", i); 4523 if (of_property_match_string(port_node, "interrupt-names", 4524 name) < 0) 4525 return false; 4526 } 4527 4528 return true; 4529 } 4530 4531 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4532 struct fwnode_handle *fwnode, 4533 char **mac_from) 4534 { 4535 struct mvpp2_port *port = netdev_priv(dev); 4536 char hw_mac_addr[ETH_ALEN] = {0}; 4537 char fw_mac_addr[ETH_ALEN]; 4538 4539 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4540 *mac_from = "firmware node"; 4541 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4542 return; 4543 } 4544 4545 if (priv->hw_version == MVPP21) { 4546 mvpp21_get_mac_address(port, hw_mac_addr); 4547 if (is_valid_ether_addr(hw_mac_addr)) { 4548 *mac_from = "hardware"; 4549 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4550 return; 4551 } 4552 } 4553 4554 *mac_from = "random"; 4555 eth_hw_addr_random(dev); 4556 } 4557 4558 static void mvpp2_phylink_validate(struct phylink_config *config, 4559 unsigned long *supported, 4560 struct phylink_link_state *state) 4561 { 4562 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4563 phylink_config); 4564 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4565 4566 /* Invalid combinations */ 4567 switch (state->interface) { 4568 case PHY_INTERFACE_MODE_10GKR: 4569 case PHY_INTERFACE_MODE_XAUI: 4570 if (port->gop_id != 0) 4571 goto empty_set; 4572 break; 4573 case PHY_INTERFACE_MODE_RGMII: 4574 case PHY_INTERFACE_MODE_RGMII_ID: 4575 case PHY_INTERFACE_MODE_RGMII_RXID: 4576 case PHY_INTERFACE_MODE_RGMII_TXID: 4577 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) 4578 goto empty_set; 4579 break; 4580 default: 4581 break; 4582 } 4583 4584 phylink_set(mask, Autoneg); 4585 phylink_set_port_modes(mask); 4586 phylink_set(mask, Pause); 4587 phylink_set(mask, Asym_Pause); 4588 4589 switch (state->interface) { 4590 case PHY_INTERFACE_MODE_10GKR: 4591 case PHY_INTERFACE_MODE_XAUI: 4592 case PHY_INTERFACE_MODE_NA: 4593 if (port->gop_id == 0) { 4594 phylink_set(mask, 10000baseT_Full); 4595 phylink_set(mask, 10000baseCR_Full); 4596 phylink_set(mask, 10000baseSR_Full); 4597 phylink_set(mask, 10000baseLR_Full); 4598 phylink_set(mask, 10000baseLRM_Full); 4599 phylink_set(mask, 10000baseER_Full); 4600 phylink_set(mask, 10000baseKR_Full); 4601 } 4602 /* Fall-through */ 4603 case PHY_INTERFACE_MODE_RGMII: 4604 case PHY_INTERFACE_MODE_RGMII_ID: 4605 case PHY_INTERFACE_MODE_RGMII_RXID: 4606 case PHY_INTERFACE_MODE_RGMII_TXID: 4607 case PHY_INTERFACE_MODE_SGMII: 4608 phylink_set(mask, 10baseT_Half); 4609 phylink_set(mask, 10baseT_Full); 4610 phylink_set(mask, 100baseT_Half); 4611 phylink_set(mask, 100baseT_Full); 4612 /* Fall-through */ 4613 case PHY_INTERFACE_MODE_1000BASEX: 4614 case PHY_INTERFACE_MODE_2500BASEX: 4615 phylink_set(mask, 1000baseT_Full); 4616 phylink_set(mask, 1000baseX_Full); 4617 phylink_set(mask, 2500baseT_Full); 4618 phylink_set(mask, 2500baseX_Full); 4619 break; 4620 default: 4621 goto empty_set; 4622 } 4623 4624 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4625 bitmap_and(state->advertising, state->advertising, mask, 4626 __ETHTOOL_LINK_MODE_MASK_NBITS); 4627 return; 4628 4629 empty_set: 4630 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 4631 } 4632 4633 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4634 struct phylink_link_state *state) 4635 { 4636 u32 val; 4637 4638 state->speed = SPEED_10000; 4639 state->duplex = 1; 4640 state->an_complete = 1; 4641 4642 val = readl(port->base + MVPP22_XLG_STATUS); 4643 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4644 4645 state->pause = 0; 4646 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4647 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4648 state->pause |= MLO_PAUSE_TX; 4649 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4650 state->pause |= MLO_PAUSE_RX; 4651 } 4652 4653 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4654 struct phylink_link_state *state) 4655 { 4656 u32 val; 4657 4658 val = readl(port->base + MVPP2_GMAC_STATUS0); 4659 4660 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4661 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4662 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4663 4664 switch (port->phy_interface) { 4665 case PHY_INTERFACE_MODE_1000BASEX: 4666 state->speed = SPEED_1000; 4667 break; 4668 case PHY_INTERFACE_MODE_2500BASEX: 4669 state->speed = SPEED_2500; 4670 break; 4671 default: 4672 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4673 state->speed = SPEED_1000; 4674 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4675 state->speed = SPEED_100; 4676 else 4677 state->speed = SPEED_10; 4678 } 4679 4680 state->pause = 0; 4681 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4682 state->pause |= MLO_PAUSE_RX; 4683 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4684 state->pause |= MLO_PAUSE_TX; 4685 } 4686 4687 static int mvpp2_phylink_mac_link_state(struct phylink_config *config, 4688 struct phylink_link_state *state) 4689 { 4690 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4691 phylink_config); 4692 4693 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4694 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4695 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4696 4697 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4698 mvpp22_xlg_link_state(port, state); 4699 return 1; 4700 } 4701 } 4702 4703 mvpp2_gmac_link_state(port, state); 4704 return 1; 4705 } 4706 4707 static void mvpp2_mac_an_restart(struct phylink_config *config) 4708 { 4709 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4710 phylink_config); 4711 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4712 4713 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 4714 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4715 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 4716 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4717 } 4718 4719 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4720 const struct phylink_link_state *state) 4721 { 4722 u32 old_ctrl0, ctrl0; 4723 u32 old_ctrl4, ctrl4; 4724 4725 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4726 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4727 4728 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS; 4729 4730 if (state->pause & MLO_PAUSE_TX) 4731 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4732 else 4733 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4734 4735 if (state->pause & MLO_PAUSE_RX) 4736 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4737 else 4738 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4739 4740 ctrl4 &= ~(MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 4741 MVPP22_XLG_CTRL4_EN_IDLE_CHECK); 4742 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC; 4743 4744 if (old_ctrl0 != ctrl0) 4745 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4746 if (old_ctrl4 != ctrl4) 4747 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4748 4749 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) { 4750 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) & 4751 MVPP22_XLG_CTRL0_MAC_RESET_DIS)) 4752 continue; 4753 } 4754 } 4755 4756 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4757 const struct phylink_link_state *state) 4758 { 4759 u32 old_an, an; 4760 u32 old_ctrl0, ctrl0; 4761 u32 old_ctrl2, ctrl2; 4762 u32 old_ctrl4, ctrl4; 4763 4764 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4765 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4766 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4767 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4768 4769 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4770 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4771 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4772 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4773 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS); 4774 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4775 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK | 4776 MVPP2_GMAC_PCS_ENABLE_MASK); 4777 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4778 4779 /* Configure port type */ 4780 if (phy_interface_mode_is_8023z(state->interface)) { 4781 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 4782 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4783 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4784 MVPP22_CTRL4_DP_CLK_SEL | 4785 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4786 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4787 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 4788 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4789 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4790 MVPP22_CTRL4_DP_CLK_SEL | 4791 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4792 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4793 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4794 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4795 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4796 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4797 } 4798 4799 /* Configure advertisement bits */ 4800 if (phylink_test(state->advertising, Pause)) 4801 an |= MVPP2_GMAC_FC_ADV_EN; 4802 if (phylink_test(state->advertising, Asym_Pause)) 4803 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4804 4805 /* Configure negotiation style */ 4806 if (!phylink_autoneg_inband(mode)) { 4807 /* Phy or fixed speed - no in-band AN */ 4808 if (state->duplex) 4809 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4810 4811 if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 4812 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4813 else if (state->speed == SPEED_100) 4814 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4815 4816 if (state->pause & MLO_PAUSE_TX) 4817 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4818 if (state->pause & MLO_PAUSE_RX) 4819 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4820 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4821 /* SGMII in-band mode receives the speed and duplex from 4822 * the PHY. Flow control information is not received. */ 4823 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4824 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4825 MVPP2_GMAC_AN_SPEED_EN | 4826 MVPP2_GMAC_AN_DUPLEX_EN; 4827 4828 if (state->pause & MLO_PAUSE_TX) 4829 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4830 if (state->pause & MLO_PAUSE_RX) 4831 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4832 } else if (phy_interface_mode_is_8023z(state->interface)) { 4833 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4834 * they negotiate duplex: they are always operating with a fixed 4835 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4836 * speed and full duplex here. 4837 */ 4838 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4839 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4840 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4841 MVPP2_GMAC_CONFIG_GMII_SPEED | 4842 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4843 4844 if (state->pause & MLO_PAUSE_AN && state->an_enabled) { 4845 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4846 } else { 4847 if (state->pause & MLO_PAUSE_TX) 4848 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4849 if (state->pause & MLO_PAUSE_RX) 4850 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4851 } 4852 } 4853 4854 /* Some fields of the auto-negotiation register require the port to be down when 4855 * their value is updated. 4856 */ 4857 #define MVPP2_GMAC_AN_PORT_DOWN_MASK \ 4858 (MVPP2_GMAC_IN_BAND_AUTONEG | \ 4859 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \ 4860 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \ 4861 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \ 4862 MVPP2_GMAC_AN_DUPLEX_EN) 4863 4864 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK || 4865 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK || 4866 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) { 4867 /* Force link down */ 4868 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4869 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4870 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4871 4872 /* Set the GMAC in a reset state - do this in a way that 4873 * ensures we clear it below. 4874 */ 4875 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4876 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4877 } 4878 4879 if (old_ctrl0 != ctrl0) 4880 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4881 if (old_ctrl2 != ctrl2) 4882 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4883 if (old_ctrl4 != ctrl4) 4884 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4885 if (old_an != an) 4886 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4887 4888 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) { 4889 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 4890 MVPP2_GMAC_PORT_RESET_MASK) 4891 continue; 4892 } 4893 } 4894 4895 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 4896 const struct phylink_link_state *state) 4897 { 4898 struct net_device *dev = to_net_dev(config->dev); 4899 struct mvpp2_port *port = netdev_priv(dev); 4900 bool change_interface = port->phy_interface != state->interface; 4901 4902 /* Check for invalid configuration */ 4903 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) { 4904 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4905 return; 4906 } 4907 4908 /* Make sure the port is disabled when reconfiguring the mode */ 4909 mvpp2_port_disable(port); 4910 4911 if (port->priv->hw_version == MVPP22 && change_interface) { 4912 mvpp22_gop_mask_irq(port); 4913 4914 port->phy_interface = state->interface; 4915 4916 /* Reconfigure the serdes lanes */ 4917 phy_power_off(port->comphy); 4918 mvpp22_mode_reconfigure(port); 4919 } 4920 4921 /* mac (re)configuration */ 4922 if (mvpp2_is_xlg(state->interface)) 4923 mvpp2_xlg_config(port, mode, state); 4924 else if (phy_interface_mode_is_rgmii(state->interface) || 4925 phy_interface_mode_is_8023z(state->interface) || 4926 state->interface == PHY_INTERFACE_MODE_SGMII) 4927 mvpp2_gmac_config(port, mode, state); 4928 4929 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4930 mvpp2_port_loopback_set(port, state); 4931 4932 if (port->priv->hw_version == MVPP22 && change_interface) 4933 mvpp22_gop_unmask_irq(port); 4934 4935 mvpp2_port_enable(port); 4936 } 4937 4938 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 4939 phy_interface_t interface, struct phy_device *phy) 4940 { 4941 struct net_device *dev = to_net_dev(config->dev); 4942 struct mvpp2_port *port = netdev_priv(dev); 4943 u32 val; 4944 4945 if (!phylink_autoneg_inband(mode)) { 4946 if (mvpp2_is_xlg(interface)) { 4947 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4948 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4949 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4950 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4951 } else { 4952 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4953 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4954 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4955 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4956 } 4957 } 4958 4959 mvpp2_port_enable(port); 4960 4961 mvpp2_egress_enable(port); 4962 mvpp2_ingress_enable(port); 4963 netif_tx_wake_all_queues(dev); 4964 } 4965 4966 static void mvpp2_mac_link_down(struct phylink_config *config, 4967 unsigned int mode, phy_interface_t interface) 4968 { 4969 struct net_device *dev = to_net_dev(config->dev); 4970 struct mvpp2_port *port = netdev_priv(dev); 4971 u32 val; 4972 4973 if (!phylink_autoneg_inband(mode)) { 4974 if (mvpp2_is_xlg(interface)) { 4975 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4976 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4977 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4978 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4979 } else { 4980 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4981 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4982 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4983 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4984 } 4985 } 4986 4987 netif_tx_stop_all_queues(dev); 4988 mvpp2_egress_disable(port); 4989 mvpp2_ingress_disable(port); 4990 4991 mvpp2_port_disable(port); 4992 } 4993 4994 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4995 .validate = mvpp2_phylink_validate, 4996 .mac_link_state = mvpp2_phylink_mac_link_state, 4997 .mac_an_restart = mvpp2_mac_an_restart, 4998 .mac_config = mvpp2_mac_config, 4999 .mac_link_up = mvpp2_mac_link_up, 5000 .mac_link_down = mvpp2_mac_link_down, 5001 }; 5002 5003 /* Ports initialization */ 5004 static int mvpp2_port_probe(struct platform_device *pdev, 5005 struct fwnode_handle *port_fwnode, 5006 struct mvpp2 *priv) 5007 { 5008 struct phy *comphy = NULL; 5009 struct mvpp2_port *port; 5010 struct mvpp2_port_pcpu *port_pcpu; 5011 struct device_node *port_node = to_of_node(port_fwnode); 5012 netdev_features_t features; 5013 struct net_device *dev; 5014 struct phylink *phylink; 5015 char *mac_from = ""; 5016 unsigned int ntxqs, nrxqs, thread; 5017 unsigned long flags = 0; 5018 bool has_tx_irqs; 5019 u32 id; 5020 int phy_mode; 5021 int err, i; 5022 5023 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 5024 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 5025 dev_err(&pdev->dev, 5026 "not enough IRQs to support multi queue mode\n"); 5027 return -EINVAL; 5028 } 5029 5030 ntxqs = MVPP2_MAX_TXQ; 5031 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) { 5032 nrxqs = 1; 5033 } else { 5034 /* According to the PPv2.2 datasheet and our experiments on 5035 * PPv2.1, RX queues have an allocation granularity of 4 (when 5036 * more than a single one on PPv2.2). 5037 * Round up to nearest multiple of 4. 5038 */ 5039 nrxqs = (num_possible_cpus() + 3) & ~0x3; 5040 if (nrxqs > MVPP2_PORT_MAX_RXQ) 5041 nrxqs = MVPP2_PORT_MAX_RXQ; 5042 } 5043 5044 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 5045 if (!dev) 5046 return -ENOMEM; 5047 5048 phy_mode = fwnode_get_phy_mode(port_fwnode); 5049 if (phy_mode < 0) { 5050 dev_err(&pdev->dev, "incorrect phy mode\n"); 5051 err = phy_mode; 5052 goto err_free_netdev; 5053 } 5054 5055 if (port_node) { 5056 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 5057 if (IS_ERR(comphy)) { 5058 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 5059 err = -EPROBE_DEFER; 5060 goto err_free_netdev; 5061 } 5062 comphy = NULL; 5063 } 5064 } 5065 5066 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 5067 err = -EINVAL; 5068 dev_err(&pdev->dev, "missing port-id value\n"); 5069 goto err_free_netdev; 5070 } 5071 5072 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 5073 dev->watchdog_timeo = 5 * HZ; 5074 dev->netdev_ops = &mvpp2_netdev_ops; 5075 dev->ethtool_ops = &mvpp2_eth_tool_ops; 5076 5077 port = netdev_priv(dev); 5078 port->dev = dev; 5079 port->fwnode = port_fwnode; 5080 port->has_phy = !!of_find_property(port_node, "phy", NULL); 5081 port->ntxqs = ntxqs; 5082 port->nrxqs = nrxqs; 5083 port->priv = priv; 5084 port->has_tx_irqs = has_tx_irqs; 5085 port->flags = flags; 5086 5087 err = mvpp2_queue_vectors_init(port, port_node); 5088 if (err) 5089 goto err_free_netdev; 5090 5091 if (port_node) 5092 port->link_irq = of_irq_get_byname(port_node, "link"); 5093 else 5094 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 5095 if (port->link_irq == -EPROBE_DEFER) { 5096 err = -EPROBE_DEFER; 5097 goto err_deinit_qvecs; 5098 } 5099 if (port->link_irq <= 0) 5100 /* the link irq is optional */ 5101 port->link_irq = 0; 5102 5103 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 5104 port->flags |= MVPP2_F_LOOPBACK; 5105 5106 port->id = id; 5107 if (priv->hw_version == MVPP21) 5108 port->first_rxq = port->id * port->nrxqs; 5109 else 5110 port->first_rxq = port->id * priv->max_port_rxqs; 5111 5112 port->of_node = port_node; 5113 port->phy_interface = phy_mode; 5114 port->comphy = comphy; 5115 5116 if (priv->hw_version == MVPP21) { 5117 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 5118 if (IS_ERR(port->base)) { 5119 err = PTR_ERR(port->base); 5120 goto err_free_irq; 5121 } 5122 5123 port->stats_base = port->priv->lms_base + 5124 MVPP21_MIB_COUNTERS_OFFSET + 5125 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 5126 } else { 5127 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 5128 &port->gop_id)) { 5129 err = -EINVAL; 5130 dev_err(&pdev->dev, "missing gop-port-id value\n"); 5131 goto err_deinit_qvecs; 5132 } 5133 5134 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 5135 port->stats_base = port->priv->iface_base + 5136 MVPP22_MIB_COUNTERS_OFFSET + 5137 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 5138 } 5139 5140 /* Alloc per-cpu and ethtool stats */ 5141 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 5142 if (!port->stats) { 5143 err = -ENOMEM; 5144 goto err_free_irq; 5145 } 5146 5147 port->ethtool_stats = devm_kcalloc(&pdev->dev, 5148 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 5149 sizeof(u64), GFP_KERNEL); 5150 if (!port->ethtool_stats) { 5151 err = -ENOMEM; 5152 goto err_free_stats; 5153 } 5154 5155 mutex_init(&port->gather_stats_lock); 5156 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 5157 5158 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 5159 5160 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 5161 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 5162 SET_NETDEV_DEV(dev, &pdev->dev); 5163 5164 err = mvpp2_port_init(port); 5165 if (err < 0) { 5166 dev_err(&pdev->dev, "failed to init port %d\n", id); 5167 goto err_free_stats; 5168 } 5169 5170 mvpp2_port_periodic_xon_disable(port); 5171 5172 mvpp2_mac_reset_assert(port); 5173 mvpp22_pcs_reset_assert(port); 5174 5175 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 5176 if (!port->pcpu) { 5177 err = -ENOMEM; 5178 goto err_free_txq_pcpu; 5179 } 5180 5181 if (!port->has_tx_irqs) { 5182 for (thread = 0; thread < priv->nthreads; thread++) { 5183 port_pcpu = per_cpu_ptr(port->pcpu, thread); 5184 5185 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 5186 HRTIMER_MODE_REL_PINNED); 5187 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 5188 port_pcpu->timer_scheduled = false; 5189 5190 tasklet_init(&port_pcpu->tx_done_tasklet, 5191 mvpp2_tx_proc_cb, 5192 (unsigned long)dev); 5193 } 5194 } 5195 5196 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5197 NETIF_F_TSO; 5198 dev->features = features | NETIF_F_RXCSUM; 5199 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 5200 NETIF_F_HW_VLAN_CTAG_FILTER; 5201 5202 if (mvpp22_rss_is_supported()) { 5203 dev->hw_features |= NETIF_F_RXHASH; 5204 dev->features |= NETIF_F_NTUPLE; 5205 } 5206 5207 mvpp2_set_hw_csum(port, port->pool_long->id); 5208 5209 dev->vlan_features |= features; 5210 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 5211 dev->priv_flags |= IFF_UNICAST_FLT; 5212 5213 /* MTU range: 68 - 9704 */ 5214 dev->min_mtu = ETH_MIN_MTU; 5215 /* 9704 == 9728 - 20 and rounding to 8 */ 5216 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 5217 dev->dev.of_node = port_node; 5218 5219 /* Phylink isn't used w/ ACPI as of now */ 5220 if (port_node) { 5221 port->phylink_config.dev = &dev->dev; 5222 port->phylink_config.type = PHYLINK_NETDEV; 5223 5224 phylink = phylink_create(&port->phylink_config, port_fwnode, 5225 phy_mode, &mvpp2_phylink_ops); 5226 if (IS_ERR(phylink)) { 5227 err = PTR_ERR(phylink); 5228 goto err_free_port_pcpu; 5229 } 5230 port->phylink = phylink; 5231 } else { 5232 port->phylink = NULL; 5233 } 5234 5235 err = register_netdev(dev); 5236 if (err < 0) { 5237 dev_err(&pdev->dev, "failed to register netdev\n"); 5238 goto err_phylink; 5239 } 5240 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 5241 5242 priv->port_list[priv->port_count++] = port; 5243 5244 return 0; 5245 5246 err_phylink: 5247 if (port->phylink) 5248 phylink_destroy(port->phylink); 5249 err_free_port_pcpu: 5250 free_percpu(port->pcpu); 5251 err_free_txq_pcpu: 5252 for (i = 0; i < port->ntxqs; i++) 5253 free_percpu(port->txqs[i]->pcpu); 5254 err_free_stats: 5255 free_percpu(port->stats); 5256 err_free_irq: 5257 if (port->link_irq) 5258 irq_dispose_mapping(port->link_irq); 5259 err_deinit_qvecs: 5260 mvpp2_queue_vectors_deinit(port); 5261 err_free_netdev: 5262 free_netdev(dev); 5263 return err; 5264 } 5265 5266 /* Ports removal routine */ 5267 static void mvpp2_port_remove(struct mvpp2_port *port) 5268 { 5269 int i; 5270 5271 unregister_netdev(port->dev); 5272 if (port->phylink) 5273 phylink_destroy(port->phylink); 5274 free_percpu(port->pcpu); 5275 free_percpu(port->stats); 5276 for (i = 0; i < port->ntxqs; i++) 5277 free_percpu(port->txqs[i]->pcpu); 5278 mvpp2_queue_vectors_deinit(port); 5279 if (port->link_irq) 5280 irq_dispose_mapping(port->link_irq); 5281 free_netdev(port->dev); 5282 } 5283 5284 /* Initialize decoding windows */ 5285 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 5286 struct mvpp2 *priv) 5287 { 5288 u32 win_enable; 5289 int i; 5290 5291 for (i = 0; i < 6; i++) { 5292 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 5293 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 5294 5295 if (i < 4) 5296 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 5297 } 5298 5299 win_enable = 0; 5300 5301 for (i = 0; i < dram->num_cs; i++) { 5302 const struct mbus_dram_window *cs = dram->cs + i; 5303 5304 mvpp2_write(priv, MVPP2_WIN_BASE(i), 5305 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 5306 dram->mbus_dram_target_id); 5307 5308 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 5309 (cs->size - 1) & 0xffff0000); 5310 5311 win_enable |= (1 << i); 5312 } 5313 5314 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 5315 } 5316 5317 /* Initialize Rx FIFO's */ 5318 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 5319 { 5320 int port; 5321 5322 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5323 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5324 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5325 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5326 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5327 } 5328 5329 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5330 MVPP2_RX_FIFO_PORT_MIN_PKT); 5331 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5332 } 5333 5334 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 5335 { 5336 int port; 5337 5338 /* The FIFO size parameters are set depending on the maximum speed a 5339 * given port can handle: 5340 * - Port 0: 10Gbps 5341 * - Port 1: 2.5Gbps 5342 * - Ports 2 and 3: 1Gbps 5343 */ 5344 5345 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 5346 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 5347 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 5348 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 5349 5350 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 5351 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 5352 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 5353 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 5354 5355 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 5356 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5357 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5358 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5359 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5360 } 5361 5362 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5363 MVPP2_RX_FIFO_PORT_MIN_PKT); 5364 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5365 } 5366 5367 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 5368 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 5369 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 5370 */ 5371 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 5372 { 5373 int port, size, thrs; 5374 5375 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5376 if (port == 0) { 5377 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 5378 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 5379 } else { 5380 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 5381 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 5382 } 5383 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 5384 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 5385 } 5386 } 5387 5388 static void mvpp2_axi_init(struct mvpp2 *priv) 5389 { 5390 u32 val, rdval, wrval; 5391 5392 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 5393 5394 /* AXI Bridge Configuration */ 5395 5396 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 5397 << MVPP22_AXI_ATTR_CACHE_OFFS; 5398 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5399 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5400 5401 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 5402 << MVPP22_AXI_ATTR_CACHE_OFFS; 5403 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5404 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5405 5406 /* BM */ 5407 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 5408 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 5409 5410 /* Descriptors */ 5411 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 5412 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 5413 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 5414 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 5415 5416 /* Buffer Data */ 5417 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 5418 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 5419 5420 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 5421 << MVPP22_AXI_CODE_CACHE_OFFS; 5422 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 5423 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5424 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 5425 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 5426 5427 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 5428 << MVPP22_AXI_CODE_CACHE_OFFS; 5429 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5430 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5431 5432 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 5433 5434 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 5435 << MVPP22_AXI_CODE_CACHE_OFFS; 5436 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5437 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5438 5439 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 5440 } 5441 5442 /* Initialize network controller common part HW */ 5443 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 5444 { 5445 const struct mbus_dram_target_info *dram_target_info; 5446 int err, i; 5447 u32 val; 5448 5449 /* MBUS windows configuration */ 5450 dram_target_info = mv_mbus_dram_info(); 5451 if (dram_target_info) 5452 mvpp2_conf_mbus_windows(dram_target_info, priv); 5453 5454 if (priv->hw_version == MVPP22) 5455 mvpp2_axi_init(priv); 5456 5457 /* Disable HW PHY polling */ 5458 if (priv->hw_version == MVPP21) { 5459 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5460 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 5461 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5462 } else { 5463 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5464 val &= ~MVPP22_SMI_POLLING_EN; 5465 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5466 } 5467 5468 /* Allocate and initialize aggregated TXQs */ 5469 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 5470 sizeof(*priv->aggr_txqs), 5471 GFP_KERNEL); 5472 if (!priv->aggr_txqs) 5473 return -ENOMEM; 5474 5475 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5476 priv->aggr_txqs[i].id = i; 5477 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 5478 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 5479 if (err < 0) 5480 return err; 5481 } 5482 5483 /* Fifo Init */ 5484 if (priv->hw_version == MVPP21) { 5485 mvpp2_rx_fifo_init(priv); 5486 } else { 5487 mvpp22_rx_fifo_init(priv); 5488 mvpp22_tx_fifo_init(priv); 5489 } 5490 5491 if (priv->hw_version == MVPP21) 5492 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 5493 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 5494 5495 /* Allow cache snoop when transmiting packets */ 5496 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 5497 5498 /* Buffer Manager initialization */ 5499 err = mvpp2_bm_init(pdev, priv); 5500 if (err < 0) 5501 return err; 5502 5503 /* Parser default initialization */ 5504 err = mvpp2_prs_default_init(pdev, priv); 5505 if (err < 0) 5506 return err; 5507 5508 /* Classifier default initialization */ 5509 mvpp2_cls_init(priv); 5510 5511 return 0; 5512 } 5513 5514 static int mvpp2_probe(struct platform_device *pdev) 5515 { 5516 const struct acpi_device_id *acpi_id; 5517 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5518 struct fwnode_handle *port_fwnode; 5519 struct mvpp2 *priv; 5520 struct resource *res; 5521 void __iomem *base; 5522 int i, shared; 5523 int err; 5524 5525 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5526 if (!priv) 5527 return -ENOMEM; 5528 5529 if (has_acpi_companion(&pdev->dev)) { 5530 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5531 &pdev->dev); 5532 if (!acpi_id) 5533 return -EINVAL; 5534 priv->hw_version = (unsigned long)acpi_id->driver_data; 5535 } else { 5536 priv->hw_version = 5537 (unsigned long)of_device_get_match_data(&pdev->dev); 5538 } 5539 5540 /* multi queue mode isn't supported on PPV2.1, fallback to single 5541 * mode 5542 */ 5543 if (priv->hw_version == MVPP21) 5544 queue_mode = MVPP2_QDIST_SINGLE_MODE; 5545 5546 base = devm_platform_ioremap_resource(pdev, 0); 5547 if (IS_ERR(base)) 5548 return PTR_ERR(base); 5549 5550 if (priv->hw_version == MVPP21) { 5551 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 5552 if (IS_ERR(priv->lms_base)) 5553 return PTR_ERR(priv->lms_base); 5554 } else { 5555 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5556 if (has_acpi_companion(&pdev->dev)) { 5557 /* In case the MDIO memory region is declared in 5558 * the ACPI, it can already appear as 'in-use' 5559 * in the OS. Because it is overlapped by second 5560 * region of the network controller, make 5561 * sure it is released, before requesting it again. 5562 * The care is taken by mvpp2 driver to avoid 5563 * concurrent access to this memory region. 5564 */ 5565 release_resource(res); 5566 } 5567 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5568 if (IS_ERR(priv->iface_base)) 5569 return PTR_ERR(priv->iface_base); 5570 } 5571 5572 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5573 priv->sysctrl_base = 5574 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5575 "marvell,system-controller"); 5576 if (IS_ERR(priv->sysctrl_base)) 5577 /* The system controller regmap is optional for dt 5578 * compatibility reasons. When not provided, the 5579 * configuration of the GoP relies on the 5580 * firmware/bootloader. 5581 */ 5582 priv->sysctrl_base = NULL; 5583 } 5584 5585 mvpp2_setup_bm_pool(); 5586 5587 5588 priv->nthreads = min_t(unsigned int, num_present_cpus(), 5589 MVPP2_MAX_THREADS); 5590 5591 shared = num_present_cpus() - priv->nthreads; 5592 if (shared > 0) 5593 bitmap_fill(&priv->lock_map, 5594 min_t(int, shared, MVPP2_MAX_THREADS)); 5595 5596 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5597 u32 addr_space_sz; 5598 5599 addr_space_sz = (priv->hw_version == MVPP21 ? 5600 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5601 priv->swth_base[i] = base + i * addr_space_sz; 5602 } 5603 5604 if (priv->hw_version == MVPP21) 5605 priv->max_port_rxqs = 8; 5606 else 5607 priv->max_port_rxqs = 32; 5608 5609 if (dev_of_node(&pdev->dev)) { 5610 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5611 if (IS_ERR(priv->pp_clk)) 5612 return PTR_ERR(priv->pp_clk); 5613 err = clk_prepare_enable(priv->pp_clk); 5614 if (err < 0) 5615 return err; 5616 5617 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5618 if (IS_ERR(priv->gop_clk)) { 5619 err = PTR_ERR(priv->gop_clk); 5620 goto err_pp_clk; 5621 } 5622 err = clk_prepare_enable(priv->gop_clk); 5623 if (err < 0) 5624 goto err_pp_clk; 5625 5626 if (priv->hw_version == MVPP22) { 5627 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5628 if (IS_ERR(priv->mg_clk)) { 5629 err = PTR_ERR(priv->mg_clk); 5630 goto err_gop_clk; 5631 } 5632 5633 err = clk_prepare_enable(priv->mg_clk); 5634 if (err < 0) 5635 goto err_gop_clk; 5636 5637 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5638 if (IS_ERR(priv->mg_core_clk)) { 5639 priv->mg_core_clk = NULL; 5640 } else { 5641 err = clk_prepare_enable(priv->mg_core_clk); 5642 if (err < 0) 5643 goto err_mg_clk; 5644 } 5645 } 5646 5647 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5648 if (IS_ERR(priv->axi_clk)) { 5649 err = PTR_ERR(priv->axi_clk); 5650 if (err == -EPROBE_DEFER) 5651 goto err_mg_core_clk; 5652 priv->axi_clk = NULL; 5653 } else { 5654 err = clk_prepare_enable(priv->axi_clk); 5655 if (err < 0) 5656 goto err_mg_core_clk; 5657 } 5658 5659 /* Get system's tclk rate */ 5660 priv->tclk = clk_get_rate(priv->pp_clk); 5661 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5662 &priv->tclk)) { 5663 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5664 return -EINVAL; 5665 } 5666 5667 if (priv->hw_version == MVPP22) { 5668 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5669 if (err) 5670 goto err_axi_clk; 5671 /* Sadly, the BM pools all share the same register to 5672 * store the high 32 bits of their address. So they 5673 * must all have the same high 32 bits, which forces 5674 * us to restrict coherent memory to DMA_BIT_MASK(32). 5675 */ 5676 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5677 if (err) 5678 goto err_axi_clk; 5679 } 5680 5681 /* Initialize network controller */ 5682 err = mvpp2_init(pdev, priv); 5683 if (err < 0) { 5684 dev_err(&pdev->dev, "failed to initialize controller\n"); 5685 goto err_axi_clk; 5686 } 5687 5688 /* Initialize ports */ 5689 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5690 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5691 if (err < 0) 5692 goto err_port_probe; 5693 } 5694 5695 if (priv->port_count == 0) { 5696 dev_err(&pdev->dev, "no ports enabled\n"); 5697 err = -ENODEV; 5698 goto err_axi_clk; 5699 } 5700 5701 /* Statistics must be gathered regularly because some of them (like 5702 * packets counters) are 32-bit registers and could overflow quite 5703 * quickly. For instance, a 10Gb link used at full bandwidth with the 5704 * smallest packets (64B) will overflow a 32-bit counter in less than 5705 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5706 */ 5707 snprintf(priv->queue_name, sizeof(priv->queue_name), 5708 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5709 priv->port_count > 1 ? "+" : ""); 5710 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5711 if (!priv->stats_queue) { 5712 err = -ENOMEM; 5713 goto err_port_probe; 5714 } 5715 5716 mvpp2_dbgfs_init(priv, pdev->name); 5717 5718 platform_set_drvdata(pdev, priv); 5719 return 0; 5720 5721 err_port_probe: 5722 i = 0; 5723 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5724 if (priv->port_list[i]) 5725 mvpp2_port_remove(priv->port_list[i]); 5726 i++; 5727 } 5728 err_axi_clk: 5729 clk_disable_unprepare(priv->axi_clk); 5730 5731 err_mg_core_clk: 5732 if (priv->hw_version == MVPP22) 5733 clk_disable_unprepare(priv->mg_core_clk); 5734 err_mg_clk: 5735 if (priv->hw_version == MVPP22) 5736 clk_disable_unprepare(priv->mg_clk); 5737 err_gop_clk: 5738 clk_disable_unprepare(priv->gop_clk); 5739 err_pp_clk: 5740 clk_disable_unprepare(priv->pp_clk); 5741 return err; 5742 } 5743 5744 static int mvpp2_remove(struct platform_device *pdev) 5745 { 5746 struct mvpp2 *priv = platform_get_drvdata(pdev); 5747 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5748 struct fwnode_handle *port_fwnode; 5749 int i = 0; 5750 5751 mvpp2_dbgfs_cleanup(priv); 5752 5753 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5754 if (priv->port_list[i]) { 5755 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5756 mvpp2_port_remove(priv->port_list[i]); 5757 } 5758 i++; 5759 } 5760 5761 destroy_workqueue(priv->stats_queue); 5762 5763 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5764 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5765 5766 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5767 } 5768 5769 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5770 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5771 5772 dma_free_coherent(&pdev->dev, 5773 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5774 aggr_txq->descs, 5775 aggr_txq->descs_dma); 5776 } 5777 5778 if (is_acpi_node(port_fwnode)) 5779 return 0; 5780 5781 clk_disable_unprepare(priv->axi_clk); 5782 clk_disable_unprepare(priv->mg_core_clk); 5783 clk_disable_unprepare(priv->mg_clk); 5784 clk_disable_unprepare(priv->pp_clk); 5785 clk_disable_unprepare(priv->gop_clk); 5786 5787 return 0; 5788 } 5789 5790 static const struct of_device_id mvpp2_match[] = { 5791 { 5792 .compatible = "marvell,armada-375-pp2", 5793 .data = (void *)MVPP21, 5794 }, 5795 { 5796 .compatible = "marvell,armada-7k-pp22", 5797 .data = (void *)MVPP22, 5798 }, 5799 { } 5800 }; 5801 MODULE_DEVICE_TABLE(of, mvpp2_match); 5802 5803 static const struct acpi_device_id mvpp2_acpi_match[] = { 5804 { "MRVL0110", MVPP22 }, 5805 { }, 5806 }; 5807 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5808 5809 static struct platform_driver mvpp2_driver = { 5810 .probe = mvpp2_probe, 5811 .remove = mvpp2_remove, 5812 .driver = { 5813 .name = MVPP2_DRIVER_NAME, 5814 .of_match_table = mvpp2_match, 5815 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5816 }, 5817 }; 5818 5819 module_platform_driver(mvpp2_driver); 5820 5821 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5822 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5823 MODULE_LICENSE("GPL v2"); 5824