1 /* 2 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Marcin Wojtas <mw@semihalf.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/kernel.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/platform_device.h> 18 #include <linux/skbuff.h> 19 #include <linux/inetdevice.h> 20 #include <linux/mbus.h> 21 #include <linux/module.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/interrupt.h> 24 #include <linux/cpumask.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/of_net.h> 29 #include <linux/of_address.h> 30 #include <linux/of_device.h> 31 #include <linux/phy.h> 32 #include <linux/phylink.h> 33 #include <linux/phy/phy.h> 34 #include <linux/clk.h> 35 #include <linux/hrtimer.h> 36 #include <linux/ktime.h> 37 #include <linux/regmap.h> 38 #include <uapi/linux/ppp_defs.h> 39 #include <net/ip.h> 40 #include <net/ipv6.h> 41 #include <net/tso.h> 42 43 #include "mvpp2.h" 44 #include "mvpp2_prs.h" 45 #include "mvpp2_cls.h" 46 47 enum mvpp2_bm_pool_log_num { 48 MVPP2_BM_SHORT, 49 MVPP2_BM_LONG, 50 MVPP2_BM_JUMBO, 51 MVPP2_BM_POOLS_NUM 52 }; 53 54 static struct { 55 int pkt_size; 56 int buf_num; 57 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 58 59 /* The prototype is added here to be used in start_dev when using ACPI. This 60 * will be removed once phylink is used for all modes (dt+ACPI). 61 */ 62 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 63 const struct phylink_link_state *state); 64 65 /* Queue modes */ 66 #define MVPP2_QDIST_SINGLE_MODE 0 67 #define MVPP2_QDIST_MULTI_MODE 1 68 69 static int queue_mode = MVPP2_QDIST_SINGLE_MODE; 70 71 module_param(queue_mode, int, 0444); 72 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 73 74 /* Utility/helper methods */ 75 76 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 77 { 78 writel(data, priv->swth_base[0] + offset); 79 } 80 81 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 82 { 83 return readl(priv->swth_base[0] + offset); 84 } 85 86 u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 87 { 88 return readl_relaxed(priv->swth_base[0] + offset); 89 } 90 /* These accessors should be used to access: 91 * 92 * - per-CPU registers, where each CPU has its own copy of the 93 * register. 94 * 95 * MVPP2_BM_VIRT_ALLOC_REG 96 * MVPP2_BM_ADDR_HIGH_ALLOC 97 * MVPP22_BM_ADDR_HIGH_RLS_REG 98 * MVPP2_BM_VIRT_RLS_REG 99 * MVPP2_ISR_RX_TX_CAUSE_REG 100 * MVPP2_ISR_RX_TX_MASK_REG 101 * MVPP2_TXQ_NUM_REG 102 * MVPP2_AGGR_TXQ_UPDATE_REG 103 * MVPP2_TXQ_RSVD_REQ_REG 104 * MVPP2_TXQ_RSVD_RSLT_REG 105 * MVPP2_TXQ_SENT_REG 106 * MVPP2_RXQ_NUM_REG 107 * 108 * - global registers that must be accessed through a specific CPU 109 * window, because they are related to an access to a per-CPU 110 * register 111 * 112 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 113 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 114 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 115 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 116 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 117 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 118 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 119 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 120 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 121 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 122 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 123 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 125 */ 126 void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, 127 u32 offset, u32 data) 128 { 129 writel(data, priv->swth_base[cpu] + offset); 130 } 131 132 u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, 133 u32 offset) 134 { 135 return readl(priv->swth_base[cpu] + offset); 136 } 137 138 void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, 139 u32 offset, u32 data) 140 { 141 writel_relaxed(data, priv->swth_base[cpu] + offset); 142 } 143 144 static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu, 145 u32 offset) 146 { 147 return readl_relaxed(priv->swth_base[cpu] + offset); 148 } 149 150 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 151 struct mvpp2_tx_desc *tx_desc) 152 { 153 if (port->priv->hw_version == MVPP21) 154 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 155 else 156 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 157 MVPP2_DESC_DMA_MASK; 158 } 159 160 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 161 struct mvpp2_tx_desc *tx_desc, 162 dma_addr_t dma_addr) 163 { 164 dma_addr_t addr, offset; 165 166 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 167 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 168 169 if (port->priv->hw_version == MVPP21) { 170 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 171 tx_desc->pp21.packet_offset = offset; 172 } else { 173 __le64 val = cpu_to_le64(addr); 174 175 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 176 tx_desc->pp22.buf_dma_addr_ptp |= val; 177 tx_desc->pp22.packet_offset = offset; 178 } 179 } 180 181 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 182 struct mvpp2_tx_desc *tx_desc) 183 { 184 if (port->priv->hw_version == MVPP21) 185 return le16_to_cpu(tx_desc->pp21.data_size); 186 else 187 return le16_to_cpu(tx_desc->pp22.data_size); 188 } 189 190 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 191 struct mvpp2_tx_desc *tx_desc, 192 size_t size) 193 { 194 if (port->priv->hw_version == MVPP21) 195 tx_desc->pp21.data_size = cpu_to_le16(size); 196 else 197 tx_desc->pp22.data_size = cpu_to_le16(size); 198 } 199 200 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 201 struct mvpp2_tx_desc *tx_desc, 202 unsigned int txq) 203 { 204 if (port->priv->hw_version == MVPP21) 205 tx_desc->pp21.phys_txq = txq; 206 else 207 tx_desc->pp22.phys_txq = txq; 208 } 209 210 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 211 struct mvpp2_tx_desc *tx_desc, 212 unsigned int command) 213 { 214 if (port->priv->hw_version == MVPP21) 215 tx_desc->pp21.command = cpu_to_le32(command); 216 else 217 tx_desc->pp22.command = cpu_to_le32(command); 218 } 219 220 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 221 struct mvpp2_tx_desc *tx_desc) 222 { 223 if (port->priv->hw_version == MVPP21) 224 return tx_desc->pp21.packet_offset; 225 else 226 return tx_desc->pp22.packet_offset; 227 } 228 229 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 230 struct mvpp2_rx_desc *rx_desc) 231 { 232 if (port->priv->hw_version == MVPP21) 233 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 234 else 235 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 236 MVPP2_DESC_DMA_MASK; 237 } 238 239 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 240 struct mvpp2_rx_desc *rx_desc) 241 { 242 if (port->priv->hw_version == MVPP21) 243 return le32_to_cpu(rx_desc->pp21.buf_cookie); 244 else 245 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 246 MVPP2_DESC_DMA_MASK; 247 } 248 249 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 250 struct mvpp2_rx_desc *rx_desc) 251 { 252 if (port->priv->hw_version == MVPP21) 253 return le16_to_cpu(rx_desc->pp21.data_size); 254 else 255 return le16_to_cpu(rx_desc->pp22.data_size); 256 } 257 258 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 259 struct mvpp2_rx_desc *rx_desc) 260 { 261 if (port->priv->hw_version == MVPP21) 262 return le32_to_cpu(rx_desc->pp21.status); 263 else 264 return le32_to_cpu(rx_desc->pp22.status); 265 } 266 267 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 268 { 269 txq_pcpu->txq_get_index++; 270 if (txq_pcpu->txq_get_index == txq_pcpu->size) 271 txq_pcpu->txq_get_index = 0; 272 } 273 274 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 275 struct mvpp2_txq_pcpu *txq_pcpu, 276 struct sk_buff *skb, 277 struct mvpp2_tx_desc *tx_desc) 278 { 279 struct mvpp2_txq_pcpu_buf *tx_buf = 280 txq_pcpu->buffs + txq_pcpu->txq_put_index; 281 tx_buf->skb = skb; 282 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 283 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 284 mvpp2_txdesc_offset_get(port, tx_desc); 285 txq_pcpu->txq_put_index++; 286 if (txq_pcpu->txq_put_index == txq_pcpu->size) 287 txq_pcpu->txq_put_index = 0; 288 } 289 290 /* Get number of physical egress port */ 291 static inline int mvpp2_egress_port(struct mvpp2_port *port) 292 { 293 return MVPP2_MAX_TCONT + port->id; 294 } 295 296 /* Get number of physical TXQ */ 297 static inline int mvpp2_txq_phys(int port, int txq) 298 { 299 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 300 } 301 302 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 303 { 304 if (likely(pool->frag_size <= PAGE_SIZE)) 305 return netdev_alloc_frag(pool->frag_size); 306 else 307 return kmalloc(pool->frag_size, GFP_ATOMIC); 308 } 309 310 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 311 { 312 if (likely(pool->frag_size <= PAGE_SIZE)) 313 skb_free_frag(data); 314 else 315 kfree(data); 316 } 317 318 /* Buffer Manager configuration routines */ 319 320 /* Create pool */ 321 static int mvpp2_bm_pool_create(struct platform_device *pdev, 322 struct mvpp2 *priv, 323 struct mvpp2_bm_pool *bm_pool, int size) 324 { 325 u32 val; 326 327 /* Number of buffer pointers must be a multiple of 16, as per 328 * hardware constraints 329 */ 330 if (!IS_ALIGNED(size, 16)) 331 return -EINVAL; 332 333 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 334 * bytes per buffer pointer 335 */ 336 if (priv->hw_version == MVPP21) 337 bm_pool->size_bytes = 2 * sizeof(u32) * size; 338 else 339 bm_pool->size_bytes = 2 * sizeof(u64) * size; 340 341 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 342 &bm_pool->dma_addr, 343 GFP_KERNEL); 344 if (!bm_pool->virt_addr) 345 return -ENOMEM; 346 347 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 348 MVPP2_BM_POOL_PTR_ALIGN)) { 349 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 350 bm_pool->virt_addr, bm_pool->dma_addr); 351 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 352 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 353 return -ENOMEM; 354 } 355 356 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 357 lower_32_bits(bm_pool->dma_addr)); 358 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 359 360 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 361 val |= MVPP2_BM_START_MASK; 362 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 363 364 bm_pool->size = size; 365 bm_pool->pkt_size = 0; 366 bm_pool->buf_num = 0; 367 368 return 0; 369 } 370 371 /* Set pool buffer size */ 372 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 373 struct mvpp2_bm_pool *bm_pool, 374 int buf_size) 375 { 376 u32 val; 377 378 bm_pool->buf_size = buf_size; 379 380 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 381 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 382 } 383 384 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 385 struct mvpp2_bm_pool *bm_pool, 386 dma_addr_t *dma_addr, 387 phys_addr_t *phys_addr) 388 { 389 int cpu = get_cpu(); 390 391 *dma_addr = mvpp2_percpu_read(priv, cpu, 392 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 393 *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); 394 395 if (priv->hw_version == MVPP22) { 396 u32 val; 397 u32 dma_addr_highbits, phys_addr_highbits; 398 399 val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); 400 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 401 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 402 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 403 404 if (sizeof(dma_addr_t) == 8) 405 *dma_addr |= (u64)dma_addr_highbits << 32; 406 407 if (sizeof(phys_addr_t) == 8) 408 *phys_addr |= (u64)phys_addr_highbits << 32; 409 } 410 411 put_cpu(); 412 } 413 414 /* Free all buffers from the pool */ 415 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 416 struct mvpp2_bm_pool *bm_pool, int buf_num) 417 { 418 int i; 419 420 if (buf_num > bm_pool->buf_num) { 421 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 422 bm_pool->id, buf_num); 423 buf_num = bm_pool->buf_num; 424 } 425 426 for (i = 0; i < buf_num; i++) { 427 dma_addr_t buf_dma_addr; 428 phys_addr_t buf_phys_addr; 429 void *data; 430 431 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 432 &buf_dma_addr, &buf_phys_addr); 433 434 dma_unmap_single(dev, buf_dma_addr, 435 bm_pool->buf_size, DMA_FROM_DEVICE); 436 437 data = (void *)phys_to_virt(buf_phys_addr); 438 if (!data) 439 break; 440 441 mvpp2_frag_free(bm_pool, data); 442 } 443 444 /* Update BM driver with number of buffers removed from pool */ 445 bm_pool->buf_num -= i; 446 } 447 448 /* Check number of buffers in BM pool */ 449 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 450 { 451 int buf_num = 0; 452 453 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 454 MVPP22_BM_POOL_PTRS_NUM_MASK; 455 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 456 MVPP2_BM_BPPI_PTR_NUM_MASK; 457 458 /* HW has one buffer ready which is not reflected in the counters */ 459 if (buf_num) 460 buf_num += 1; 461 462 return buf_num; 463 } 464 465 /* Cleanup pool */ 466 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 467 struct mvpp2 *priv, 468 struct mvpp2_bm_pool *bm_pool) 469 { 470 int buf_num; 471 u32 val; 472 473 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 474 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 475 476 /* Check buffer counters after free */ 477 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 478 if (buf_num) { 479 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 480 bm_pool->id, bm_pool->buf_num); 481 return 0; 482 } 483 484 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 485 val |= MVPP2_BM_STOP_MASK; 486 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 487 488 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 489 bm_pool->virt_addr, 490 bm_pool->dma_addr); 491 return 0; 492 } 493 494 static int mvpp2_bm_pools_init(struct platform_device *pdev, 495 struct mvpp2 *priv) 496 { 497 int i, err, size; 498 struct mvpp2_bm_pool *bm_pool; 499 500 /* Create all pools with maximum size */ 501 size = MVPP2_BM_POOL_SIZE_MAX; 502 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 503 bm_pool = &priv->bm_pools[i]; 504 bm_pool->id = i; 505 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 506 if (err) 507 goto err_unroll_pools; 508 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 509 } 510 return 0; 511 512 err_unroll_pools: 513 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 514 for (i = i - 1; i >= 0; i--) 515 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 516 return err; 517 } 518 519 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 520 { 521 int i, err; 522 523 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 524 /* Mask BM all interrupts */ 525 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 526 /* Clear BM cause register */ 527 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 528 } 529 530 /* Allocate and initialize BM pools */ 531 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 532 sizeof(*priv->bm_pools), GFP_KERNEL); 533 if (!priv->bm_pools) 534 return -ENOMEM; 535 536 err = mvpp2_bm_pools_init(pdev, priv); 537 if (err < 0) 538 return err; 539 return 0; 540 } 541 542 static void mvpp2_setup_bm_pool(void) 543 { 544 /* Short pool */ 545 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 546 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 547 548 /* Long pool */ 549 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 550 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 551 552 /* Jumbo pool */ 553 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 554 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 555 } 556 557 /* Attach long pool to rxq */ 558 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 559 int lrxq, int long_pool) 560 { 561 u32 val, mask; 562 int prxq; 563 564 /* Get queue physical ID */ 565 prxq = port->rxqs[lrxq]->id; 566 567 if (port->priv->hw_version == MVPP21) 568 mask = MVPP21_RXQ_POOL_LONG_MASK; 569 else 570 mask = MVPP22_RXQ_POOL_LONG_MASK; 571 572 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 573 val &= ~mask; 574 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 575 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 576 } 577 578 /* Attach short pool to rxq */ 579 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 580 int lrxq, int short_pool) 581 { 582 u32 val, mask; 583 int prxq; 584 585 /* Get queue physical ID */ 586 prxq = port->rxqs[lrxq]->id; 587 588 if (port->priv->hw_version == MVPP21) 589 mask = MVPP21_RXQ_POOL_SHORT_MASK; 590 else 591 mask = MVPP22_RXQ_POOL_SHORT_MASK; 592 593 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 594 val &= ~mask; 595 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 596 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 597 } 598 599 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 600 struct mvpp2_bm_pool *bm_pool, 601 dma_addr_t *buf_dma_addr, 602 phys_addr_t *buf_phys_addr, 603 gfp_t gfp_mask) 604 { 605 dma_addr_t dma_addr; 606 void *data; 607 608 data = mvpp2_frag_alloc(bm_pool); 609 if (!data) 610 return NULL; 611 612 dma_addr = dma_map_single(port->dev->dev.parent, data, 613 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 614 DMA_FROM_DEVICE); 615 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 616 mvpp2_frag_free(bm_pool, data); 617 return NULL; 618 } 619 *buf_dma_addr = dma_addr; 620 *buf_phys_addr = virt_to_phys(data); 621 622 return data; 623 } 624 625 /* Release buffer to BM */ 626 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 627 dma_addr_t buf_dma_addr, 628 phys_addr_t buf_phys_addr) 629 { 630 int cpu = get_cpu(); 631 632 if (port->priv->hw_version == MVPP22) { 633 u32 val = 0; 634 635 if (sizeof(dma_addr_t) == 8) 636 val |= upper_32_bits(buf_dma_addr) & 637 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 638 639 if (sizeof(phys_addr_t) == 8) 640 val |= (upper_32_bits(buf_phys_addr) 641 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 642 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 643 644 mvpp2_percpu_write_relaxed(port->priv, cpu, 645 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 646 } 647 648 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 649 * returned in the "cookie" field of the RX 650 * descriptor. Instead of storing the virtual address, we 651 * store the physical address 652 */ 653 mvpp2_percpu_write_relaxed(port->priv, cpu, 654 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 655 mvpp2_percpu_write_relaxed(port->priv, cpu, 656 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 657 658 put_cpu(); 659 } 660 661 /* Allocate buffers for the pool */ 662 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 663 struct mvpp2_bm_pool *bm_pool, int buf_num) 664 { 665 int i, buf_size, total_size; 666 dma_addr_t dma_addr; 667 phys_addr_t phys_addr; 668 void *buf; 669 670 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 671 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 672 673 if (buf_num < 0 || 674 (buf_num + bm_pool->buf_num > bm_pool->size)) { 675 netdev_err(port->dev, 676 "cannot allocate %d buffers for pool %d\n", 677 buf_num, bm_pool->id); 678 return 0; 679 } 680 681 for (i = 0; i < buf_num; i++) { 682 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 683 &phys_addr, GFP_KERNEL); 684 if (!buf) 685 break; 686 687 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 688 phys_addr); 689 } 690 691 /* Update BM driver with number of buffers added to pool */ 692 bm_pool->buf_num += i; 693 694 netdev_dbg(port->dev, 695 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 696 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 697 698 netdev_dbg(port->dev, 699 "pool %d: %d of %d buffers added\n", 700 bm_pool->id, i, buf_num); 701 return i; 702 } 703 704 /* Notify the driver that BM pool is being used as specific type and return the 705 * pool pointer on success 706 */ 707 static struct mvpp2_bm_pool * 708 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 709 { 710 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 711 int num; 712 713 if (pool >= MVPP2_BM_POOLS_NUM) { 714 netdev_err(port->dev, "Invalid pool %d\n", pool); 715 return NULL; 716 } 717 718 /* Allocate buffers in case BM pool is used as long pool, but packet 719 * size doesn't match MTU or BM pool hasn't being used yet 720 */ 721 if (new_pool->pkt_size == 0) { 722 int pkts_num; 723 724 /* Set default buffer number or free all the buffers in case 725 * the pool is not empty 726 */ 727 pkts_num = new_pool->buf_num; 728 if (pkts_num == 0) 729 pkts_num = mvpp2_pools[pool].buf_num; 730 else 731 mvpp2_bm_bufs_free(port->dev->dev.parent, 732 port->priv, new_pool, pkts_num); 733 734 new_pool->pkt_size = pkt_size; 735 new_pool->frag_size = 736 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 737 MVPP2_SKB_SHINFO_SIZE; 738 739 /* Allocate buffers for this pool */ 740 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 741 if (num != pkts_num) { 742 WARN(1, "pool %d: %d of %d allocated\n", 743 new_pool->id, num, pkts_num); 744 return NULL; 745 } 746 } 747 748 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 749 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 750 751 return new_pool; 752 } 753 754 /* Initialize pools for swf */ 755 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 756 { 757 int rxq; 758 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 759 760 /* If port pkt_size is higher than 1518B: 761 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 762 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 763 */ 764 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 765 long_log_pool = MVPP2_BM_JUMBO; 766 short_log_pool = MVPP2_BM_LONG; 767 } else { 768 long_log_pool = MVPP2_BM_LONG; 769 short_log_pool = MVPP2_BM_SHORT; 770 } 771 772 if (!port->pool_long) { 773 port->pool_long = 774 mvpp2_bm_pool_use(port, long_log_pool, 775 mvpp2_pools[long_log_pool].pkt_size); 776 if (!port->pool_long) 777 return -ENOMEM; 778 779 port->pool_long->port_map |= BIT(port->id); 780 781 for (rxq = 0; rxq < port->nrxqs; rxq++) 782 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 783 } 784 785 if (!port->pool_short) { 786 port->pool_short = 787 mvpp2_bm_pool_use(port, short_log_pool, 788 mvpp2_pools[short_log_pool].pkt_size); 789 if (!port->pool_short) 790 return -ENOMEM; 791 792 port->pool_short->port_map |= BIT(port->id); 793 794 for (rxq = 0; rxq < port->nrxqs; rxq++) 795 mvpp2_rxq_short_pool_set(port, rxq, 796 port->pool_short->id); 797 } 798 799 return 0; 800 } 801 802 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 803 { 804 struct mvpp2_port *port = netdev_priv(dev); 805 enum mvpp2_bm_pool_log_num new_long_pool; 806 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 807 808 /* If port MTU is higher than 1518B: 809 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 810 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 811 */ 812 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 813 new_long_pool = MVPP2_BM_JUMBO; 814 else 815 new_long_pool = MVPP2_BM_LONG; 816 817 if (new_long_pool != port->pool_long->id) { 818 /* Remove port from old short & long pool */ 819 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 820 port->pool_long->pkt_size); 821 port->pool_long->port_map &= ~BIT(port->id); 822 port->pool_long = NULL; 823 824 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 825 port->pool_short->pkt_size); 826 port->pool_short->port_map &= ~BIT(port->id); 827 port->pool_short = NULL; 828 829 port->pkt_size = pkt_size; 830 831 /* Add port to new short & long pool */ 832 mvpp2_swf_bm_pool_init(port); 833 834 /* Update L4 checksum when jumbo enable/disable on port */ 835 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 836 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 837 dev->hw_features &= ~(NETIF_F_IP_CSUM | 838 NETIF_F_IPV6_CSUM); 839 } else { 840 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 841 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 842 } 843 } 844 845 dev->mtu = mtu; 846 dev->wanted_features = dev->features; 847 848 netdev_update_features(dev); 849 return 0; 850 } 851 852 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 853 { 854 int i, sw_thread_mask = 0; 855 856 for (i = 0; i < port->nqvecs; i++) 857 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 858 859 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 860 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 861 } 862 863 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 864 { 865 int i, sw_thread_mask = 0; 866 867 for (i = 0; i < port->nqvecs; i++) 868 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 869 870 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 871 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 872 } 873 874 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 875 { 876 struct mvpp2_port *port = qvec->port; 877 878 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 879 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 880 } 881 882 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 883 { 884 struct mvpp2_port *port = qvec->port; 885 886 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 887 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 888 } 889 890 /* Mask the current CPU's Rx/Tx interrupts 891 * Called by on_each_cpu(), guaranteed to run with migration disabled, 892 * using smp_processor_id() is OK. 893 */ 894 static void mvpp2_interrupts_mask(void *arg) 895 { 896 struct mvpp2_port *port = arg; 897 898 mvpp2_percpu_write(port->priv, smp_processor_id(), 899 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 900 } 901 902 /* Unmask the current CPU's Rx/Tx interrupts. 903 * Called by on_each_cpu(), guaranteed to run with migration disabled, 904 * using smp_processor_id() is OK. 905 */ 906 static void mvpp2_interrupts_unmask(void *arg) 907 { 908 struct mvpp2_port *port = arg; 909 u32 val; 910 911 val = MVPP2_CAUSE_MISC_SUM_MASK | 912 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 913 if (port->has_tx_irqs) 914 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 915 916 mvpp2_percpu_write(port->priv, smp_processor_id(), 917 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 918 } 919 920 static void 921 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 922 { 923 u32 val; 924 int i; 925 926 if (port->priv->hw_version != MVPP22) 927 return; 928 929 if (mask) 930 val = 0; 931 else 932 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 933 934 for (i = 0; i < port->nqvecs; i++) { 935 struct mvpp2_queue_vector *v = port->qvecs + i; 936 937 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 938 continue; 939 940 mvpp2_percpu_write(port->priv, v->sw_thread_id, 941 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 942 } 943 } 944 945 /* Port configuration routines */ 946 947 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 948 { 949 struct mvpp2 *priv = port->priv; 950 u32 val; 951 952 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 953 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 954 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 955 956 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 957 if (port->gop_id == 2) 958 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 959 else if (port->gop_id == 3) 960 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 961 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 962 } 963 964 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 965 { 966 struct mvpp2 *priv = port->priv; 967 u32 val; 968 969 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 970 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 971 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 972 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 973 974 if (port->gop_id > 1) { 975 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 976 if (port->gop_id == 2) 977 val &= ~GENCONF_CTRL0_PORT0_RGMII; 978 else if (port->gop_id == 3) 979 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 980 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 981 } 982 } 983 984 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 985 { 986 struct mvpp2 *priv = port->priv; 987 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 988 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 989 u32 val; 990 991 /* XPCS */ 992 val = readl(xpcs + MVPP22_XPCS_CFG0); 993 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 994 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 995 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 996 writel(val, xpcs + MVPP22_XPCS_CFG0); 997 998 /* MPCS */ 999 val = readl(mpcs + MVPP22_MPCS_CTRL); 1000 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1001 writel(val, mpcs + MVPP22_MPCS_CTRL); 1002 1003 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1004 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | 1005 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1006 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1007 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1008 1009 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1010 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; 1011 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1012 } 1013 1014 static int mvpp22_gop_init(struct mvpp2_port *port) 1015 { 1016 struct mvpp2 *priv = port->priv; 1017 u32 val; 1018 1019 if (!priv->sysctrl_base) 1020 return 0; 1021 1022 switch (port->phy_interface) { 1023 case PHY_INTERFACE_MODE_RGMII: 1024 case PHY_INTERFACE_MODE_RGMII_ID: 1025 case PHY_INTERFACE_MODE_RGMII_RXID: 1026 case PHY_INTERFACE_MODE_RGMII_TXID: 1027 if (port->gop_id == 0) 1028 goto invalid_conf; 1029 mvpp22_gop_init_rgmii(port); 1030 break; 1031 case PHY_INTERFACE_MODE_SGMII: 1032 case PHY_INTERFACE_MODE_1000BASEX: 1033 case PHY_INTERFACE_MODE_2500BASEX: 1034 mvpp22_gop_init_sgmii(port); 1035 break; 1036 case PHY_INTERFACE_MODE_10GKR: 1037 if (port->gop_id != 0) 1038 goto invalid_conf; 1039 mvpp22_gop_init_10gkr(port); 1040 break; 1041 default: 1042 goto unsupported_conf; 1043 } 1044 1045 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1046 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1047 GENCONF_PORT_CTRL1_EN(port->gop_id); 1048 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1049 1050 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1051 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1052 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1053 1054 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1055 val |= GENCONF_SOFT_RESET1_GOP; 1056 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1057 1058 unsupported_conf: 1059 return 0; 1060 1061 invalid_conf: 1062 netdev_err(port->dev, "Invalid port configuration\n"); 1063 return -EINVAL; 1064 } 1065 1066 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1067 { 1068 u32 val; 1069 1070 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1071 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1072 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1073 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1074 /* Enable the GMAC link status irq for this port */ 1075 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1076 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1077 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1078 } 1079 1080 if (port->gop_id == 0) { 1081 /* Enable the XLG/GIG irqs for this port */ 1082 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1083 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) 1084 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1085 else 1086 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1087 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1088 } 1089 } 1090 1091 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1092 { 1093 u32 val; 1094 1095 if (port->gop_id == 0) { 1096 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1097 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1098 MVPP22_XLG_EXT_INT_MASK_GIG); 1099 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1100 } 1101 1102 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1103 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1104 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1105 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1106 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1107 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1108 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1109 } 1110 } 1111 1112 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1113 { 1114 u32 val; 1115 1116 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1117 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1118 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1119 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1120 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1121 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1122 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1123 } 1124 1125 if (port->gop_id == 0) { 1126 val = readl(port->base + MVPP22_XLG_INT_MASK); 1127 val |= MVPP22_XLG_INT_MASK_LINK; 1128 writel(val, port->base + MVPP22_XLG_INT_MASK); 1129 } 1130 1131 mvpp22_gop_unmask_irq(port); 1132 } 1133 1134 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1135 * 1136 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1137 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1138 * differ. 1139 * 1140 * The COMPHY configures the serdes lanes regardless of the actual use of the 1141 * lanes by the physical layer. This is why configurations like 1142 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1143 */ 1144 static int mvpp22_comphy_init(struct mvpp2_port *port) 1145 { 1146 enum phy_mode mode; 1147 int ret; 1148 1149 if (!port->comphy) 1150 return 0; 1151 1152 switch (port->phy_interface) { 1153 case PHY_INTERFACE_MODE_SGMII: 1154 case PHY_INTERFACE_MODE_1000BASEX: 1155 mode = PHY_MODE_SGMII; 1156 break; 1157 case PHY_INTERFACE_MODE_2500BASEX: 1158 mode = PHY_MODE_2500SGMII; 1159 break; 1160 case PHY_INTERFACE_MODE_10GKR: 1161 mode = PHY_MODE_10GKR; 1162 break; 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 ret = phy_set_mode(port->comphy, mode); 1168 if (ret) 1169 return ret; 1170 1171 return phy_power_on(port->comphy); 1172 } 1173 1174 static void mvpp2_port_enable(struct mvpp2_port *port) 1175 { 1176 u32 val; 1177 1178 /* Only GOP port 0 has an XLG MAC */ 1179 if (port->gop_id == 0 && 1180 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1181 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1182 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1183 val |= MVPP22_XLG_CTRL0_PORT_EN | 1184 MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1185 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1186 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1187 } else { 1188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1189 val |= MVPP2_GMAC_PORT_EN_MASK; 1190 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1192 } 1193 } 1194 1195 static void mvpp2_port_disable(struct mvpp2_port *port) 1196 { 1197 u32 val; 1198 1199 /* Only GOP port 0 has an XLG MAC */ 1200 if (port->gop_id == 0 && 1201 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1202 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1203 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1204 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1205 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1206 1207 /* Disable & reset should be done separately */ 1208 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1209 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1210 } else { 1211 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1212 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1213 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1214 } 1215 } 1216 1217 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1218 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1219 { 1220 u32 val; 1221 1222 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1223 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1224 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1225 } 1226 1227 /* Configure loopback port */ 1228 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1229 const struct phylink_link_state *state) 1230 { 1231 u32 val; 1232 1233 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1234 1235 if (state->speed == 1000) 1236 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1237 else 1238 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1239 1240 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1241 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1242 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) 1243 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1244 else 1245 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1246 1247 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1248 } 1249 1250 struct mvpp2_ethtool_counter { 1251 unsigned int offset; 1252 const char string[ETH_GSTRING_LEN]; 1253 bool reg_is_64b; 1254 }; 1255 1256 static u64 mvpp2_read_count(struct mvpp2_port *port, 1257 const struct mvpp2_ethtool_counter *counter) 1258 { 1259 u64 val; 1260 1261 val = readl(port->stats_base + counter->offset); 1262 if (counter->reg_is_64b) 1263 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1264 1265 return val; 1266 } 1267 1268 /* Due to the fact that software statistics and hardware statistics are, by 1269 * design, incremented at different moments in the chain of packet processing, 1270 * it is very likely that incoming packets could have been dropped after being 1271 * counted by hardware but before reaching software statistics (most probably 1272 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1273 * are added in between as well as TSO skb will be split and header bytes added. 1274 * Hence, statistics gathered from userspace with ifconfig (software) and 1275 * ethtool (hardware) cannot be compared. 1276 */ 1277 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { 1278 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1279 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1280 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1281 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1282 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1283 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1284 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1285 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1286 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1287 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1288 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1289 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1290 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1291 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1292 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1293 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1294 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1295 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1296 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1297 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1298 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1299 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1300 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1301 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1302 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1303 { MVPP2_MIB_COLLISION, "collision" }, 1304 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1305 }; 1306 1307 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1308 u8 *data) 1309 { 1310 if (sset == ETH_SS_STATS) { 1311 int i; 1312 1313 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1314 memcpy(data + i * ETH_GSTRING_LEN, 1315 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); 1316 } 1317 } 1318 1319 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1320 { 1321 struct delayed_work *del_work = to_delayed_work(work); 1322 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1323 stats_work); 1324 u64 *pstats; 1325 int i; 1326 1327 mutex_lock(&port->gather_stats_lock); 1328 1329 pstats = port->ethtool_stats; 1330 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1331 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1332 1333 /* No need to read again the counters right after this function if it 1334 * was called asynchronously by the user (ie. use of ethtool). 1335 */ 1336 cancel_delayed_work(&port->stats_work); 1337 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1338 MVPP2_MIB_COUNTERS_STATS_DELAY); 1339 1340 mutex_unlock(&port->gather_stats_lock); 1341 } 1342 1343 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1344 struct ethtool_stats *stats, u64 *data) 1345 { 1346 struct mvpp2_port *port = netdev_priv(dev); 1347 1348 /* Update statistics for the given port, then take the lock to avoid 1349 * concurrent accesses on the ethtool_stats structure during its copy. 1350 */ 1351 mvpp2_gather_hw_statistics(&port->stats_work.work); 1352 1353 mutex_lock(&port->gather_stats_lock); 1354 memcpy(data, port->ethtool_stats, 1355 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); 1356 mutex_unlock(&port->gather_stats_lock); 1357 } 1358 1359 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1360 { 1361 if (sset == ETH_SS_STATS) 1362 return ARRAY_SIZE(mvpp2_ethtool_regs); 1363 1364 return -EOPNOTSUPP; 1365 } 1366 1367 static void mvpp2_port_reset(struct mvpp2_port *port) 1368 { 1369 u32 val; 1370 unsigned int i; 1371 1372 /* Read the GOP statistics to reset the hardware counters */ 1373 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1374 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1375 1376 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1377 ~MVPP2_GMAC_PORT_RESET_MASK; 1378 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1379 1380 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1381 MVPP2_GMAC_PORT_RESET_MASK) 1382 continue; 1383 } 1384 1385 /* Change maximum receive size of the port */ 1386 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1387 { 1388 u32 val; 1389 1390 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1391 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1392 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1393 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1394 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1395 } 1396 1397 /* Change maximum receive size of the port */ 1398 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1399 { 1400 u32 val; 1401 1402 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1403 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1404 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1405 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1406 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1407 } 1408 1409 /* Set defaults to the MVPP2 port */ 1410 static void mvpp2_defaults_set(struct mvpp2_port *port) 1411 { 1412 int tx_port_num, val, queue, ptxq, lrxq; 1413 1414 if (port->priv->hw_version == MVPP21) { 1415 /* Update TX FIFO MIN Threshold */ 1416 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1417 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1418 /* Min. TX threshold must be less than minimal packet length */ 1419 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1420 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1421 } 1422 1423 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1424 tx_port_num = mvpp2_egress_port(port); 1425 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1426 tx_port_num); 1427 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1428 1429 /* Close bandwidth for all queues */ 1430 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { 1431 ptxq = mvpp2_txq_phys(port->id, queue); 1432 mvpp2_write(port->priv, 1433 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); 1434 } 1435 1436 /* Set refill period to 1 usec, refill tokens 1437 * and bucket size to maximum 1438 */ 1439 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1440 port->priv->tclk / USEC_PER_SEC); 1441 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1442 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1443 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1444 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1445 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1446 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1447 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1448 1449 /* Set MaximumLowLatencyPacketSize value to 256 */ 1450 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1451 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1452 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1453 1454 /* Enable Rx cache snoop */ 1455 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1456 queue = port->rxqs[lrxq]->id; 1457 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1458 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1459 MVPP2_SNOOP_BUF_HDR_MASK; 1460 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1461 } 1462 1463 /* At default, mask all interrupts to all present cpus */ 1464 mvpp2_interrupts_disable(port); 1465 } 1466 1467 /* Enable/disable receiving packets */ 1468 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1469 { 1470 u32 val; 1471 int lrxq, queue; 1472 1473 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1474 queue = port->rxqs[lrxq]->id; 1475 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1476 val &= ~MVPP2_RXQ_DISABLE_MASK; 1477 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1478 } 1479 } 1480 1481 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1482 { 1483 u32 val; 1484 int lrxq, queue; 1485 1486 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1487 queue = port->rxqs[lrxq]->id; 1488 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1489 val |= MVPP2_RXQ_DISABLE_MASK; 1490 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1491 } 1492 } 1493 1494 /* Enable transmit via physical egress queue 1495 * - HW starts take descriptors from DRAM 1496 */ 1497 static void mvpp2_egress_enable(struct mvpp2_port *port) 1498 { 1499 u32 qmap; 1500 int queue; 1501 int tx_port_num = mvpp2_egress_port(port); 1502 1503 /* Enable all initialized TXs. */ 1504 qmap = 0; 1505 for (queue = 0; queue < port->ntxqs; queue++) { 1506 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1507 1508 if (txq->descs) 1509 qmap |= (1 << queue); 1510 } 1511 1512 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1513 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1514 } 1515 1516 /* Disable transmit via physical egress queue 1517 * - HW doesn't take descriptors from DRAM 1518 */ 1519 static void mvpp2_egress_disable(struct mvpp2_port *port) 1520 { 1521 u32 reg_data; 1522 int delay; 1523 int tx_port_num = mvpp2_egress_port(port); 1524 1525 /* Issue stop command for active channels only */ 1526 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1527 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1528 MVPP2_TXP_SCHED_ENQ_MASK; 1529 if (reg_data != 0) 1530 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1531 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1532 1533 /* Wait for all Tx activity to terminate. */ 1534 delay = 0; 1535 do { 1536 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1537 netdev_warn(port->dev, 1538 "Tx stop timed out, status=0x%08x\n", 1539 reg_data); 1540 break; 1541 } 1542 mdelay(1); 1543 delay++; 1544 1545 /* Check port TX Command register that all 1546 * Tx queues are stopped 1547 */ 1548 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1549 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1550 } 1551 1552 /* Rx descriptors helper methods */ 1553 1554 /* Get number of Rx descriptors occupied by received packets */ 1555 static inline int 1556 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1557 { 1558 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1559 1560 return val & MVPP2_RXQ_OCCUPIED_MASK; 1561 } 1562 1563 /* Update Rx queue status with the number of occupied and available 1564 * Rx descriptor slots. 1565 */ 1566 static inline void 1567 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1568 int used_count, int free_count) 1569 { 1570 /* Decrement the number of used descriptors and increment count 1571 * increment the number of free descriptors. 1572 */ 1573 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1574 1575 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1576 } 1577 1578 /* Get pointer to next RX descriptor to be processed by SW */ 1579 static inline struct mvpp2_rx_desc * 1580 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1581 { 1582 int rx_desc = rxq->next_desc_to_proc; 1583 1584 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1585 prefetch(rxq->descs + rxq->next_desc_to_proc); 1586 return rxq->descs + rx_desc; 1587 } 1588 1589 /* Set rx queue offset */ 1590 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1591 int prxq, int offset) 1592 { 1593 u32 val; 1594 1595 /* Convert offset from bytes to units of 32 bytes */ 1596 offset = offset >> 5; 1597 1598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1599 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1600 1601 /* Offset is in */ 1602 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1603 MVPP2_RXQ_PACKET_OFFSET_MASK); 1604 1605 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1606 } 1607 1608 /* Tx descriptors helper methods */ 1609 1610 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1611 static struct mvpp2_tx_desc * 1612 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1613 { 1614 int tx_desc = txq->next_desc_to_proc; 1615 1616 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1617 return txq->descs + tx_desc; 1618 } 1619 1620 /* Update HW with number of aggregated Tx descriptors to be sent 1621 * 1622 * Called only from mvpp2_tx(), so migration is disabled, using 1623 * smp_processor_id() is OK. 1624 */ 1625 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1626 { 1627 /* aggregated access - relevant TXQ number is written in TX desc */ 1628 mvpp2_percpu_write(port->priv, smp_processor_id(), 1629 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1630 } 1631 1632 /* Check if there are enough free descriptors in aggregated txq. 1633 * If not, update the number of occupied descriptors and repeat the check. 1634 * 1635 * Called only from mvpp2_tx(), so migration is disabled, using 1636 * smp_processor_id() is OK. 1637 */ 1638 static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, 1639 struct mvpp2_tx_queue *aggr_txq, int num) 1640 { 1641 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1642 /* Update number of occupied aggregated Tx descriptors */ 1643 int cpu = smp_processor_id(); 1644 u32 val = mvpp2_read_relaxed(priv, 1645 MVPP2_AGGR_TXQ_STATUS_REG(cpu)); 1646 1647 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1648 1649 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1650 return -ENOMEM; 1651 } 1652 return 0; 1653 } 1654 1655 /* Reserved Tx descriptors allocation request 1656 * 1657 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1658 * only by mvpp2_tx(), so migration is disabled, using 1659 * smp_processor_id() is OK. 1660 */ 1661 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, 1662 struct mvpp2_tx_queue *txq, int num) 1663 { 1664 u32 val; 1665 int cpu = smp_processor_id(); 1666 1667 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1668 mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); 1669 1670 val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); 1671 1672 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1673 } 1674 1675 /* Check if there are enough reserved descriptors for transmission. 1676 * If not, request chunk of reserved descriptors and check again. 1677 */ 1678 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, 1679 struct mvpp2_tx_queue *txq, 1680 struct mvpp2_txq_pcpu *txq_pcpu, 1681 int num) 1682 { 1683 int req, cpu, desc_count; 1684 1685 if (txq_pcpu->reserved_num >= num) 1686 return 0; 1687 1688 /* Not enough descriptors reserved! Update the reserved descriptor 1689 * count and check again. 1690 */ 1691 1692 desc_count = 0; 1693 /* Compute total of used descriptors */ 1694 for_each_present_cpu(cpu) { 1695 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1696 1697 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); 1698 desc_count += txq_pcpu_aux->count; 1699 desc_count += txq_pcpu_aux->reserved_num; 1700 } 1701 1702 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1703 desc_count += req; 1704 1705 if (desc_count > 1706 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) 1707 return -ENOMEM; 1708 1709 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); 1710 1711 /* OK, the descriptor could have been updated: check again. */ 1712 if (txq_pcpu->reserved_num < num) 1713 return -ENOMEM; 1714 return 0; 1715 } 1716 1717 /* Release the last allocated Tx descriptor. Useful to handle DMA 1718 * mapping failures in the Tx path. 1719 */ 1720 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1721 { 1722 if (txq->next_desc_to_proc == 0) 1723 txq->next_desc_to_proc = txq->last_desc - 1; 1724 else 1725 txq->next_desc_to_proc--; 1726 } 1727 1728 /* Set Tx descriptors fields relevant for CSUM calculation */ 1729 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, 1730 int ip_hdr_len, int l4_proto) 1731 { 1732 u32 command; 1733 1734 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1735 * G_L4_chk, L4_type required only for checksum calculation 1736 */ 1737 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1738 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1739 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1740 1741 if (l3_proto == htons(ETH_P_IP)) { 1742 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1743 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1744 } else { 1745 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1746 } 1747 1748 if (l4_proto == IPPROTO_TCP) { 1749 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1750 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1751 } else if (l4_proto == IPPROTO_UDP) { 1752 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1753 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1754 } else { 1755 command |= MVPP2_TXD_L4_CSUM_NOT; 1756 } 1757 1758 return command; 1759 } 1760 1761 /* Get number of sent descriptors and decrement counter. 1762 * The number of sent descriptors is returned. 1763 * Per-CPU access 1764 * 1765 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1766 * (migration disabled) and from the TX completion tasklet (migration 1767 * disabled) so using smp_processor_id() is OK. 1768 */ 1769 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1770 struct mvpp2_tx_queue *txq) 1771 { 1772 u32 val; 1773 1774 /* Reading status reg resets transmitted descriptor counter */ 1775 val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(), 1776 MVPP2_TXQ_SENT_REG(txq->id)); 1777 1778 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1779 MVPP2_TRANSMITTED_COUNT_OFFSET; 1780 } 1781 1782 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1783 * disabled, therefore using smp_processor_id() is OK. 1784 */ 1785 static void mvpp2_txq_sent_counter_clear(void *arg) 1786 { 1787 struct mvpp2_port *port = arg; 1788 int queue; 1789 1790 for (queue = 0; queue < port->ntxqs; queue++) { 1791 int id = port->txqs[queue]->id; 1792 1793 mvpp2_percpu_read(port->priv, smp_processor_id(), 1794 MVPP2_TXQ_SENT_REG(id)); 1795 } 1796 } 1797 1798 /* Set max sizes for Tx queues */ 1799 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1800 { 1801 u32 val, size, mtu; 1802 int txq, tx_port_num; 1803 1804 mtu = port->pkt_size * 8; 1805 if (mtu > MVPP2_TXP_MTU_MAX) 1806 mtu = MVPP2_TXP_MTU_MAX; 1807 1808 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1809 mtu = 3 * mtu; 1810 1811 /* Indirect access to registers */ 1812 tx_port_num = mvpp2_egress_port(port); 1813 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1814 1815 /* Set MTU */ 1816 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1817 val &= ~MVPP2_TXP_MTU_MAX; 1818 val |= mtu; 1819 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1820 1821 /* TXP token size and all TXQs token size must be larger that MTU */ 1822 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1823 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1824 if (size < mtu) { 1825 size = mtu; 1826 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1827 val |= size; 1828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1829 } 1830 1831 for (txq = 0; txq < port->ntxqs; txq++) { 1832 val = mvpp2_read(port->priv, 1833 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1834 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1835 1836 if (size < mtu) { 1837 size = mtu; 1838 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1839 val |= size; 1840 mvpp2_write(port->priv, 1841 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1842 val); 1843 } 1844 } 1845 } 1846 1847 /* Set the number of packets that will be received before Rx interrupt 1848 * will be generated by HW. 1849 */ 1850 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1851 struct mvpp2_rx_queue *rxq) 1852 { 1853 int cpu = get_cpu(); 1854 1855 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 1856 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 1857 1858 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 1859 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, 1860 rxq->pkts_coal); 1861 1862 put_cpu(); 1863 } 1864 1865 /* For some reason in the LSP this is done on each CPU. Why ? */ 1866 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 1867 struct mvpp2_tx_queue *txq) 1868 { 1869 int cpu = get_cpu(); 1870 u32 val; 1871 1872 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 1873 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 1874 1875 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 1876 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 1877 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); 1878 1879 put_cpu(); 1880 } 1881 1882 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 1883 { 1884 u64 tmp = (u64)clk_hz * usec; 1885 1886 do_div(tmp, USEC_PER_SEC); 1887 1888 return tmp > U32_MAX ? U32_MAX : tmp; 1889 } 1890 1891 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 1892 { 1893 u64 tmp = (u64)cycles * USEC_PER_SEC; 1894 1895 do_div(tmp, clk_hz); 1896 1897 return tmp > U32_MAX ? U32_MAX : tmp; 1898 } 1899 1900 /* Set the time delay in usec before Rx interrupt */ 1901 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 1902 struct mvpp2_rx_queue *rxq) 1903 { 1904 unsigned long freq = port->priv->tclk; 1905 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1906 1907 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 1908 rxq->time_coal = 1909 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 1910 1911 /* re-evaluate to get actual register value */ 1912 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1913 } 1914 1915 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 1916 } 1917 1918 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 1919 { 1920 unsigned long freq = port->priv->tclk; 1921 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1922 1923 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 1924 port->tx_time_coal = 1925 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 1926 1927 /* re-evaluate to get actual register value */ 1928 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1929 } 1930 1931 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 1932 } 1933 1934 /* Free Tx queue skbuffs */ 1935 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 1936 struct mvpp2_tx_queue *txq, 1937 struct mvpp2_txq_pcpu *txq_pcpu, int num) 1938 { 1939 int i; 1940 1941 for (i = 0; i < num; i++) { 1942 struct mvpp2_txq_pcpu_buf *tx_buf = 1943 txq_pcpu->buffs + txq_pcpu->txq_get_index; 1944 1945 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 1946 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 1947 tx_buf->size, DMA_TO_DEVICE); 1948 if (tx_buf->skb) 1949 dev_kfree_skb_any(tx_buf->skb); 1950 1951 mvpp2_txq_inc_get(txq_pcpu); 1952 } 1953 } 1954 1955 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 1956 u32 cause) 1957 { 1958 int queue = fls(cause) - 1; 1959 1960 return port->rxqs[queue]; 1961 } 1962 1963 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 1964 u32 cause) 1965 { 1966 int queue = fls(cause) - 1; 1967 1968 return port->txqs[queue]; 1969 } 1970 1971 /* Handle end of transmission */ 1972 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 1973 struct mvpp2_txq_pcpu *txq_pcpu) 1974 { 1975 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 1976 int tx_done; 1977 1978 if (txq_pcpu->cpu != smp_processor_id()) 1979 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 1980 1981 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 1982 if (!tx_done) 1983 return; 1984 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 1985 1986 txq_pcpu->count -= tx_done; 1987 1988 if (netif_tx_queue_stopped(nq)) 1989 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 1990 netif_tx_wake_queue(nq); 1991 } 1992 1993 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 1994 int cpu) 1995 { 1996 struct mvpp2_tx_queue *txq; 1997 struct mvpp2_txq_pcpu *txq_pcpu; 1998 unsigned int tx_todo = 0; 1999 2000 while (cause) { 2001 txq = mvpp2_get_tx_queue(port, cause); 2002 if (!txq) 2003 break; 2004 2005 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2006 2007 if (txq_pcpu->count) { 2008 mvpp2_txq_done(port, txq, txq_pcpu); 2009 tx_todo += txq_pcpu->count; 2010 } 2011 2012 cause &= ~(1 << txq->log_id); 2013 } 2014 return tx_todo; 2015 } 2016 2017 /* Rx/Tx queue initialization/cleanup methods */ 2018 2019 /* Allocate and initialize descriptors for aggr TXQ */ 2020 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2021 struct mvpp2_tx_queue *aggr_txq, int cpu, 2022 struct mvpp2 *priv) 2023 { 2024 u32 txq_dma; 2025 2026 /* Allocate memory for TX descriptors */ 2027 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, 2028 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2029 &aggr_txq->descs_dma, GFP_KERNEL); 2030 if (!aggr_txq->descs) 2031 return -ENOMEM; 2032 2033 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2034 2035 /* Aggr TXQ no reset WA */ 2036 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2037 MVPP2_AGGR_TXQ_INDEX_REG(cpu)); 2038 2039 /* Set Tx descriptors queue starting address indirect 2040 * access 2041 */ 2042 if (priv->hw_version == MVPP21) 2043 txq_dma = aggr_txq->descs_dma; 2044 else 2045 txq_dma = aggr_txq->descs_dma >> 2046 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2047 2048 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); 2049 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), 2050 MVPP2_AGGR_TXQ_SIZE); 2051 2052 return 0; 2053 } 2054 2055 /* Create a specified Rx queue */ 2056 static int mvpp2_rxq_init(struct mvpp2_port *port, 2057 struct mvpp2_rx_queue *rxq) 2058 2059 { 2060 u32 rxq_dma; 2061 int cpu; 2062 2063 rxq->size = port->rx_ring_size; 2064 2065 /* Allocate memory for RX descriptors */ 2066 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2067 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2068 &rxq->descs_dma, GFP_KERNEL); 2069 if (!rxq->descs) 2070 return -ENOMEM; 2071 2072 rxq->last_desc = rxq->size - 1; 2073 2074 /* Zero occupied and non-occupied counters - direct access */ 2075 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2076 2077 /* Set Rx descriptors queue starting address - indirect access */ 2078 cpu = get_cpu(); 2079 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 2080 if (port->priv->hw_version == MVPP21) 2081 rxq_dma = rxq->descs_dma; 2082 else 2083 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2084 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2085 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2086 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); 2087 put_cpu(); 2088 2089 /* Set Offset */ 2090 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2091 2092 /* Set coalescing pkts and time */ 2093 mvpp2_rx_pkts_coal_set(port, rxq); 2094 mvpp2_rx_time_coal_set(port, rxq); 2095 2096 /* Add number of descriptors ready for receiving packets */ 2097 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2098 2099 return 0; 2100 } 2101 2102 /* Push packets received by the RXQ to BM pool */ 2103 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2104 struct mvpp2_rx_queue *rxq) 2105 { 2106 int rx_received, i; 2107 2108 rx_received = mvpp2_rxq_received(port, rxq->id); 2109 if (!rx_received) 2110 return; 2111 2112 for (i = 0; i < rx_received; i++) { 2113 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2114 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2115 int pool; 2116 2117 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2118 MVPP2_RXD_BM_POOL_ID_OFFS; 2119 2120 mvpp2_bm_pool_put(port, pool, 2121 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2122 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2123 } 2124 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2125 } 2126 2127 /* Cleanup Rx queue */ 2128 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2129 struct mvpp2_rx_queue *rxq) 2130 { 2131 int cpu; 2132 2133 mvpp2_rxq_drop_pkts(port, rxq); 2134 2135 if (rxq->descs) 2136 dma_free_coherent(port->dev->dev.parent, 2137 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2138 rxq->descs, 2139 rxq->descs_dma); 2140 2141 rxq->descs = NULL; 2142 rxq->last_desc = 0; 2143 rxq->next_desc_to_proc = 0; 2144 rxq->descs_dma = 0; 2145 2146 /* Clear Rx descriptors queue starting address and size; 2147 * free descriptor number 2148 */ 2149 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2150 cpu = get_cpu(); 2151 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 2152 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); 2153 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); 2154 put_cpu(); 2155 } 2156 2157 /* Create and initialize a Tx queue */ 2158 static int mvpp2_txq_init(struct mvpp2_port *port, 2159 struct mvpp2_tx_queue *txq) 2160 { 2161 u32 val; 2162 int cpu, desc, desc_per_txq, tx_port_num; 2163 struct mvpp2_txq_pcpu *txq_pcpu; 2164 2165 txq->size = port->tx_ring_size; 2166 2167 /* Allocate memory for Tx descriptors */ 2168 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2169 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2170 &txq->descs_dma, GFP_KERNEL); 2171 if (!txq->descs) 2172 return -ENOMEM; 2173 2174 txq->last_desc = txq->size - 1; 2175 2176 /* Set Tx descriptors queue starting address - indirect access */ 2177 cpu = get_cpu(); 2178 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2179 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 2180 txq->descs_dma); 2181 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 2182 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2183 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); 2184 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, 2185 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2186 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); 2187 val &= ~MVPP2_TXQ_PENDING_MASK; 2188 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); 2189 2190 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2191 * for each existing TXQ. 2192 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2193 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2194 */ 2195 desc_per_txq = 16; 2196 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2197 (txq->log_id * desc_per_txq); 2198 2199 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, 2200 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2201 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2202 put_cpu(); 2203 2204 /* WRR / EJP configuration - indirect access */ 2205 tx_port_num = mvpp2_egress_port(port); 2206 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2207 2208 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2209 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2210 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2211 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2212 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2213 2214 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2215 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2216 val); 2217 2218 for_each_present_cpu(cpu) { 2219 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2220 txq_pcpu->size = txq->size; 2221 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2222 sizeof(*txq_pcpu->buffs), 2223 GFP_KERNEL); 2224 if (!txq_pcpu->buffs) 2225 return -ENOMEM; 2226 2227 txq_pcpu->count = 0; 2228 txq_pcpu->reserved_num = 0; 2229 txq_pcpu->txq_put_index = 0; 2230 txq_pcpu->txq_get_index = 0; 2231 txq_pcpu->tso_headers = NULL; 2232 2233 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2234 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2235 2236 txq_pcpu->tso_headers = 2237 dma_alloc_coherent(port->dev->dev.parent, 2238 txq_pcpu->size * TSO_HEADER_SIZE, 2239 &txq_pcpu->tso_headers_dma, 2240 GFP_KERNEL); 2241 if (!txq_pcpu->tso_headers) 2242 return -ENOMEM; 2243 } 2244 2245 return 0; 2246 } 2247 2248 /* Free allocated TXQ resources */ 2249 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2250 struct mvpp2_tx_queue *txq) 2251 { 2252 struct mvpp2_txq_pcpu *txq_pcpu; 2253 int cpu; 2254 2255 for_each_present_cpu(cpu) { 2256 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2257 kfree(txq_pcpu->buffs); 2258 2259 if (txq_pcpu->tso_headers) 2260 dma_free_coherent(port->dev->dev.parent, 2261 txq_pcpu->size * TSO_HEADER_SIZE, 2262 txq_pcpu->tso_headers, 2263 txq_pcpu->tso_headers_dma); 2264 2265 txq_pcpu->tso_headers = NULL; 2266 } 2267 2268 if (txq->descs) 2269 dma_free_coherent(port->dev->dev.parent, 2270 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2271 txq->descs, txq->descs_dma); 2272 2273 txq->descs = NULL; 2274 txq->last_desc = 0; 2275 txq->next_desc_to_proc = 0; 2276 txq->descs_dma = 0; 2277 2278 /* Set minimum bandwidth for disabled TXQs */ 2279 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); 2280 2281 /* Set Tx descriptors queue starting address and size */ 2282 cpu = get_cpu(); 2283 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2284 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); 2285 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); 2286 put_cpu(); 2287 } 2288 2289 /* Cleanup Tx ports */ 2290 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2291 { 2292 struct mvpp2_txq_pcpu *txq_pcpu; 2293 int delay, pending, cpu; 2294 u32 val; 2295 2296 cpu = get_cpu(); 2297 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2298 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); 2299 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2300 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); 2301 2302 /* The napi queue has been stopped so wait for all packets 2303 * to be transmitted. 2304 */ 2305 delay = 0; 2306 do { 2307 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2308 netdev_warn(port->dev, 2309 "port %d: cleaning queue %d timed out\n", 2310 port->id, txq->log_id); 2311 break; 2312 } 2313 mdelay(1); 2314 delay++; 2315 2316 pending = mvpp2_percpu_read(port->priv, cpu, 2317 MVPP2_TXQ_PENDING_REG); 2318 pending &= MVPP2_TXQ_PENDING_MASK; 2319 } while (pending); 2320 2321 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2322 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); 2323 put_cpu(); 2324 2325 for_each_present_cpu(cpu) { 2326 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2327 2328 /* Release all packets */ 2329 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2330 2331 /* Reset queue */ 2332 txq_pcpu->count = 0; 2333 txq_pcpu->txq_put_index = 0; 2334 txq_pcpu->txq_get_index = 0; 2335 } 2336 } 2337 2338 /* Cleanup all Tx queues */ 2339 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2340 { 2341 struct mvpp2_tx_queue *txq; 2342 int queue; 2343 u32 val; 2344 2345 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2346 2347 /* Reset Tx ports and delete Tx queues */ 2348 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2349 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2350 2351 for (queue = 0; queue < port->ntxqs; queue++) { 2352 txq = port->txqs[queue]; 2353 mvpp2_txq_clean(port, txq); 2354 mvpp2_txq_deinit(port, txq); 2355 } 2356 2357 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2358 2359 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2360 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2361 } 2362 2363 /* Cleanup all Rx queues */ 2364 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2365 { 2366 int queue; 2367 2368 for (queue = 0; queue < port->nrxqs; queue++) 2369 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2370 } 2371 2372 /* Init all Rx queues for port */ 2373 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2374 { 2375 int queue, err; 2376 2377 for (queue = 0; queue < port->nrxqs; queue++) { 2378 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2379 if (err) 2380 goto err_cleanup; 2381 } 2382 return 0; 2383 2384 err_cleanup: 2385 mvpp2_cleanup_rxqs(port); 2386 return err; 2387 } 2388 2389 /* Init all tx queues for port */ 2390 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2391 { 2392 struct mvpp2_tx_queue *txq; 2393 int queue, err; 2394 2395 for (queue = 0; queue < port->ntxqs; queue++) { 2396 txq = port->txqs[queue]; 2397 err = mvpp2_txq_init(port, txq); 2398 if (err) 2399 goto err_cleanup; 2400 } 2401 2402 if (port->has_tx_irqs) { 2403 mvpp2_tx_time_coal_set(port); 2404 for (queue = 0; queue < port->ntxqs; queue++) { 2405 txq = port->txqs[queue]; 2406 mvpp2_tx_pkts_coal_set(port, txq); 2407 } 2408 } 2409 2410 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2411 return 0; 2412 2413 err_cleanup: 2414 mvpp2_cleanup_txqs(port); 2415 return err; 2416 } 2417 2418 /* The callback for per-port interrupt */ 2419 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2420 { 2421 struct mvpp2_queue_vector *qv = dev_id; 2422 2423 mvpp2_qvec_interrupt_disable(qv); 2424 2425 napi_schedule(&qv->napi); 2426 2427 return IRQ_HANDLED; 2428 } 2429 2430 /* Per-port interrupt for link status changes */ 2431 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2432 { 2433 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2434 struct net_device *dev = port->dev; 2435 bool event = false, link = false; 2436 u32 val; 2437 2438 mvpp22_gop_mask_irq(port); 2439 2440 if (port->gop_id == 0 && 2441 port->phy_interface == PHY_INTERFACE_MODE_10GKR) { 2442 val = readl(port->base + MVPP22_XLG_INT_STAT); 2443 if (val & MVPP22_XLG_INT_STAT_LINK) { 2444 event = true; 2445 val = readl(port->base + MVPP22_XLG_STATUS); 2446 if (val & MVPP22_XLG_STATUS_LINK_UP) 2447 link = true; 2448 } 2449 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2450 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 2451 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 2452 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 2453 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2454 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2455 event = true; 2456 val = readl(port->base + MVPP2_GMAC_STATUS0); 2457 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2458 link = true; 2459 } 2460 } 2461 2462 if (port->phylink) { 2463 phylink_mac_change(port->phylink, link); 2464 goto handled; 2465 } 2466 2467 if (!netif_running(dev) || !event) 2468 goto handled; 2469 2470 if (link) { 2471 mvpp2_interrupts_enable(port); 2472 2473 mvpp2_egress_enable(port); 2474 mvpp2_ingress_enable(port); 2475 netif_carrier_on(dev); 2476 netif_tx_wake_all_queues(dev); 2477 } else { 2478 netif_tx_stop_all_queues(dev); 2479 netif_carrier_off(dev); 2480 mvpp2_ingress_disable(port); 2481 mvpp2_egress_disable(port); 2482 2483 mvpp2_interrupts_disable(port); 2484 } 2485 2486 handled: 2487 mvpp22_gop_unmask_irq(port); 2488 return IRQ_HANDLED; 2489 } 2490 2491 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2492 { 2493 ktime_t interval; 2494 2495 if (!port_pcpu->timer_scheduled) { 2496 port_pcpu->timer_scheduled = true; 2497 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2498 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2499 HRTIMER_MODE_REL_PINNED); 2500 } 2501 } 2502 2503 static void mvpp2_tx_proc_cb(unsigned long data) 2504 { 2505 struct net_device *dev = (struct net_device *)data; 2506 struct mvpp2_port *port = netdev_priv(dev); 2507 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); 2508 unsigned int tx_todo, cause; 2509 2510 if (!netif_running(dev)) 2511 return; 2512 port_pcpu->timer_scheduled = false; 2513 2514 /* Process all the Tx queues */ 2515 cause = (1 << port->ntxqs) - 1; 2516 tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); 2517 2518 /* Set the timer in case not all the packets were processed */ 2519 if (tx_todo) 2520 mvpp2_timer_set(port_pcpu); 2521 } 2522 2523 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2524 { 2525 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2526 struct mvpp2_port_pcpu, 2527 tx_done_timer); 2528 2529 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2530 2531 return HRTIMER_NORESTART; 2532 } 2533 2534 /* Main RX/TX processing routines */ 2535 2536 /* Display more error info */ 2537 static void mvpp2_rx_error(struct mvpp2_port *port, 2538 struct mvpp2_rx_desc *rx_desc) 2539 { 2540 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2541 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2542 char *err_str = NULL; 2543 2544 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2545 case MVPP2_RXD_ERR_CRC: 2546 err_str = "crc"; 2547 break; 2548 case MVPP2_RXD_ERR_OVERRUN: 2549 err_str = "overrun"; 2550 break; 2551 case MVPP2_RXD_ERR_RESOURCE: 2552 err_str = "resource"; 2553 break; 2554 } 2555 if (err_str && net_ratelimit()) 2556 netdev_err(port->dev, 2557 "bad rx status %08x (%s error), size=%zu\n", 2558 status, err_str, sz); 2559 } 2560 2561 /* Handle RX checksum offload */ 2562 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2563 struct sk_buff *skb) 2564 { 2565 if (((status & MVPP2_RXD_L3_IP4) && 2566 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2567 (status & MVPP2_RXD_L3_IP6)) 2568 if (((status & MVPP2_RXD_L4_UDP) || 2569 (status & MVPP2_RXD_L4_TCP)) && 2570 (status & MVPP2_RXD_L4_CSUM_OK)) { 2571 skb->csum = 0; 2572 skb->ip_summed = CHECKSUM_UNNECESSARY; 2573 return; 2574 } 2575 2576 skb->ip_summed = CHECKSUM_NONE; 2577 } 2578 2579 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2580 static int mvpp2_rx_refill(struct mvpp2_port *port, 2581 struct mvpp2_bm_pool *bm_pool, int pool) 2582 { 2583 dma_addr_t dma_addr; 2584 phys_addr_t phys_addr; 2585 void *buf; 2586 2587 /* No recycle or too many buffers are in use, so allocate a new skb */ 2588 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2589 GFP_ATOMIC); 2590 if (!buf) 2591 return -ENOMEM; 2592 2593 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2594 2595 return 0; 2596 } 2597 2598 /* Handle tx checksum */ 2599 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2600 { 2601 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2602 int ip_hdr_len = 0; 2603 u8 l4_proto; 2604 2605 if (skb->protocol == htons(ETH_P_IP)) { 2606 struct iphdr *ip4h = ip_hdr(skb); 2607 2608 /* Calculate IPv4 checksum and L4 checksum */ 2609 ip_hdr_len = ip4h->ihl; 2610 l4_proto = ip4h->protocol; 2611 } else if (skb->protocol == htons(ETH_P_IPV6)) { 2612 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2613 2614 /* Read l4_protocol from one of IPv6 extra headers */ 2615 if (skb_network_header_len(skb) > 0) 2616 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2617 l4_proto = ip6h->nexthdr; 2618 } else { 2619 return MVPP2_TXD_L4_CSUM_NOT; 2620 } 2621 2622 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2623 skb->protocol, ip_hdr_len, l4_proto); 2624 } 2625 2626 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2627 } 2628 2629 /* Main rx processing */ 2630 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2631 int rx_todo, struct mvpp2_rx_queue *rxq) 2632 { 2633 struct net_device *dev = port->dev; 2634 int rx_received; 2635 int rx_done = 0; 2636 u32 rcvd_pkts = 0; 2637 u32 rcvd_bytes = 0; 2638 2639 /* Get number of received packets and clamp the to-do */ 2640 rx_received = mvpp2_rxq_received(port, rxq->id); 2641 if (rx_todo > rx_received) 2642 rx_todo = rx_received; 2643 2644 while (rx_done < rx_todo) { 2645 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2646 struct mvpp2_bm_pool *bm_pool; 2647 struct sk_buff *skb; 2648 unsigned int frag_size; 2649 dma_addr_t dma_addr; 2650 phys_addr_t phys_addr; 2651 u32 rx_status; 2652 int pool, rx_bytes, err; 2653 void *data; 2654 2655 rx_done++; 2656 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2657 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2658 rx_bytes -= MVPP2_MH_SIZE; 2659 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2660 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2661 data = (void *)phys_to_virt(phys_addr); 2662 2663 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2664 MVPP2_RXD_BM_POOL_ID_OFFS; 2665 bm_pool = &port->priv->bm_pools[pool]; 2666 2667 /* In case of an error, release the requested buffer pointer 2668 * to the Buffer Manager. This request process is controlled 2669 * by the hardware, and the information about the buffer is 2670 * comprised by the RX descriptor. 2671 */ 2672 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2673 err_drop_frame: 2674 dev->stats.rx_errors++; 2675 mvpp2_rx_error(port, rx_desc); 2676 /* Return the buffer to the pool */ 2677 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2678 continue; 2679 } 2680 2681 if (bm_pool->frag_size > PAGE_SIZE) 2682 frag_size = 0; 2683 else 2684 frag_size = bm_pool->frag_size; 2685 2686 skb = build_skb(data, frag_size); 2687 if (!skb) { 2688 netdev_warn(port->dev, "skb build failed\n"); 2689 goto err_drop_frame; 2690 } 2691 2692 err = mvpp2_rx_refill(port, bm_pool, pool); 2693 if (err) { 2694 netdev_err(port->dev, "failed to refill BM pools\n"); 2695 goto err_drop_frame; 2696 } 2697 2698 dma_unmap_single(dev->dev.parent, dma_addr, 2699 bm_pool->buf_size, DMA_FROM_DEVICE); 2700 2701 rcvd_pkts++; 2702 rcvd_bytes += rx_bytes; 2703 2704 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2705 skb_put(skb, rx_bytes); 2706 skb->protocol = eth_type_trans(skb, dev); 2707 mvpp2_rx_csum(port, rx_status, skb); 2708 2709 napi_gro_receive(napi, skb); 2710 } 2711 2712 if (rcvd_pkts) { 2713 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2714 2715 u64_stats_update_begin(&stats->syncp); 2716 stats->rx_packets += rcvd_pkts; 2717 stats->rx_bytes += rcvd_bytes; 2718 u64_stats_update_end(&stats->syncp); 2719 } 2720 2721 /* Update Rx queue management counters */ 2722 wmb(); 2723 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2724 2725 return rx_todo; 2726 } 2727 2728 static inline void 2729 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2730 struct mvpp2_tx_desc *desc) 2731 { 2732 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); 2733 2734 dma_addr_t buf_dma_addr = 2735 mvpp2_txdesc_dma_addr_get(port, desc); 2736 size_t buf_sz = 2737 mvpp2_txdesc_size_get(port, desc); 2738 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2739 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2740 buf_sz, DMA_TO_DEVICE); 2741 mvpp2_txq_desc_put(txq); 2742 } 2743 2744 /* Handle tx fragmentation processing */ 2745 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2746 struct mvpp2_tx_queue *aggr_txq, 2747 struct mvpp2_tx_queue *txq) 2748 { 2749 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); 2750 struct mvpp2_tx_desc *tx_desc; 2751 int i; 2752 dma_addr_t buf_dma_addr; 2753 2754 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2755 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2756 void *addr = page_address(frag->page.p) + frag->page_offset; 2757 2758 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2759 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2760 mvpp2_txdesc_size_set(port, tx_desc, frag->size); 2761 2762 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2763 frag->size, DMA_TO_DEVICE); 2764 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2765 mvpp2_txq_desc_put(txq); 2766 goto cleanup; 2767 } 2768 2769 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2770 2771 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2772 /* Last descriptor */ 2773 mvpp2_txdesc_cmd_set(port, tx_desc, 2774 MVPP2_TXD_L_DESC); 2775 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2776 } else { 2777 /* Descriptor in the middle: Not First, Not Last */ 2778 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2779 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2780 } 2781 } 2782 2783 return 0; 2784 cleanup: 2785 /* Release all descriptors that were used to map fragments of 2786 * this packet, as well as the corresponding DMA mappings 2787 */ 2788 for (i = i - 1; i >= 0; i--) { 2789 tx_desc = txq->descs + i; 2790 tx_desc_unmap_put(port, txq, tx_desc); 2791 } 2792 2793 return -ENOMEM; 2794 } 2795 2796 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2797 struct net_device *dev, 2798 struct mvpp2_tx_queue *txq, 2799 struct mvpp2_tx_queue *aggr_txq, 2800 struct mvpp2_txq_pcpu *txq_pcpu, 2801 int hdr_sz) 2802 { 2803 struct mvpp2_port *port = netdev_priv(dev); 2804 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2805 dma_addr_t addr; 2806 2807 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2808 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2809 2810 addr = txq_pcpu->tso_headers_dma + 2811 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2812 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2813 2814 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2815 MVPP2_TXD_F_DESC | 2816 MVPP2_TXD_PADDING_DISABLE); 2817 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2818 } 2819 2820 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2821 struct net_device *dev, struct tso_t *tso, 2822 struct mvpp2_tx_queue *txq, 2823 struct mvpp2_tx_queue *aggr_txq, 2824 struct mvpp2_txq_pcpu *txq_pcpu, 2825 int sz, bool left, bool last) 2826 { 2827 struct mvpp2_port *port = netdev_priv(dev); 2828 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2829 dma_addr_t buf_dma_addr; 2830 2831 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2832 mvpp2_txdesc_size_set(port, tx_desc, sz); 2833 2834 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2835 DMA_TO_DEVICE); 2836 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2837 mvpp2_txq_desc_put(txq); 2838 return -ENOMEM; 2839 } 2840 2841 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2842 2843 if (!left) { 2844 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 2845 if (last) { 2846 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2847 return 0; 2848 } 2849 } else { 2850 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2851 } 2852 2853 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2854 return 0; 2855 } 2856 2857 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 2858 struct mvpp2_tx_queue *txq, 2859 struct mvpp2_tx_queue *aggr_txq, 2860 struct mvpp2_txq_pcpu *txq_pcpu) 2861 { 2862 struct mvpp2_port *port = netdev_priv(dev); 2863 struct tso_t tso; 2864 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 2865 int i, len, descs = 0; 2866 2867 /* Check number of available descriptors */ 2868 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, 2869 tso_count_descs(skb)) || 2870 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, 2871 tso_count_descs(skb))) 2872 return 0; 2873 2874 tso_start(skb, &tso); 2875 len = skb->len - hdr_sz; 2876 while (len > 0) { 2877 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 2878 char *hdr = txq_pcpu->tso_headers + 2879 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2880 2881 len -= left; 2882 descs++; 2883 2884 tso_build_hdr(skb, hdr, &tso, left, len == 0); 2885 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 2886 2887 while (left > 0) { 2888 int sz = min_t(int, tso.size, left); 2889 left -= sz; 2890 descs++; 2891 2892 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 2893 txq_pcpu, sz, left, len == 0)) 2894 goto release; 2895 tso_build_data(skb, &tso, sz); 2896 } 2897 } 2898 2899 return descs; 2900 2901 release: 2902 for (i = descs - 1; i >= 0; i--) { 2903 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 2904 tx_desc_unmap_put(port, txq, tx_desc); 2905 } 2906 return 0; 2907 } 2908 2909 /* Main tx processing */ 2910 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 2911 { 2912 struct mvpp2_port *port = netdev_priv(dev); 2913 struct mvpp2_tx_queue *txq, *aggr_txq; 2914 struct mvpp2_txq_pcpu *txq_pcpu; 2915 struct mvpp2_tx_desc *tx_desc; 2916 dma_addr_t buf_dma_addr; 2917 int frags = 0; 2918 u16 txq_id; 2919 u32 tx_cmd; 2920 2921 txq_id = skb_get_queue_mapping(skb); 2922 txq = port->txqs[txq_id]; 2923 txq_pcpu = this_cpu_ptr(txq->pcpu); 2924 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; 2925 2926 if (skb_is_gso(skb)) { 2927 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 2928 goto out; 2929 } 2930 frags = skb_shinfo(skb)->nr_frags + 1; 2931 2932 /* Check number of available descriptors */ 2933 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || 2934 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, 2935 txq_pcpu, frags)) { 2936 frags = 0; 2937 goto out; 2938 } 2939 2940 /* Get a descriptor for the first part of the packet */ 2941 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2942 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2943 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 2944 2945 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 2946 skb_headlen(skb), DMA_TO_DEVICE); 2947 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2948 mvpp2_txq_desc_put(txq); 2949 frags = 0; 2950 goto out; 2951 } 2952 2953 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2954 2955 tx_cmd = mvpp2_skb_tx_csum(port, skb); 2956 2957 if (frags == 1) { 2958 /* First and Last descriptor */ 2959 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 2960 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2961 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2962 } else { 2963 /* First but not Last */ 2964 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 2965 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2966 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2967 2968 /* Continue with other skb fragments */ 2969 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 2970 tx_desc_unmap_put(port, txq, tx_desc); 2971 frags = 0; 2972 } 2973 } 2974 2975 out: 2976 if (frags > 0) { 2977 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2978 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2979 2980 txq_pcpu->reserved_num -= frags; 2981 txq_pcpu->count += frags; 2982 aggr_txq->count += frags; 2983 2984 /* Enable transmit */ 2985 wmb(); 2986 mvpp2_aggr_txq_pend_desc_add(port, frags); 2987 2988 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 2989 netif_tx_stop_queue(nq); 2990 2991 u64_stats_update_begin(&stats->syncp); 2992 stats->tx_packets++; 2993 stats->tx_bytes += skb->len; 2994 u64_stats_update_end(&stats->syncp); 2995 } else { 2996 dev->stats.tx_dropped++; 2997 dev_kfree_skb_any(skb); 2998 } 2999 3000 /* Finalize TX processing */ 3001 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3002 mvpp2_txq_done(port, txq, txq_pcpu); 3003 3004 /* Set the timer in case not all frags were processed */ 3005 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3006 txq_pcpu->count > 0) { 3007 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); 3008 3009 mvpp2_timer_set(port_pcpu); 3010 } 3011 3012 return NETDEV_TX_OK; 3013 } 3014 3015 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3016 { 3017 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3018 netdev_err(dev, "FCS error\n"); 3019 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3020 netdev_err(dev, "rx fifo overrun error\n"); 3021 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3022 netdev_err(dev, "tx fifo underrun error\n"); 3023 } 3024 3025 static int mvpp2_poll(struct napi_struct *napi, int budget) 3026 { 3027 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3028 int rx_done = 0; 3029 struct mvpp2_port *port = netdev_priv(napi->dev); 3030 struct mvpp2_queue_vector *qv; 3031 int cpu = smp_processor_id(); 3032 3033 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3034 3035 /* Rx/Tx cause register 3036 * 3037 * Bits 0-15: each bit indicates received packets on the Rx queue 3038 * (bit 0 is for Rx queue 0). 3039 * 3040 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3041 * (bit 16 is for Tx queue 0). 3042 * 3043 * Each CPU has its own Rx/Tx cause register 3044 */ 3045 cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id, 3046 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3047 3048 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3049 if (cause_misc) { 3050 mvpp2_cause_error(port->dev, cause_misc); 3051 3052 /* Clear the cause register */ 3053 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3054 mvpp2_percpu_write(port->priv, cpu, 3055 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3056 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3057 } 3058 3059 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3060 if (cause_tx) { 3061 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3062 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3063 } 3064 3065 /* Process RX packets */ 3066 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 3067 cause_rx <<= qv->first_rxq; 3068 cause_rx |= qv->pending_cause_rx; 3069 while (cause_rx && budget > 0) { 3070 int count; 3071 struct mvpp2_rx_queue *rxq; 3072 3073 rxq = mvpp2_get_rx_queue(port, cause_rx); 3074 if (!rxq) 3075 break; 3076 3077 count = mvpp2_rx(port, napi, budget, rxq); 3078 rx_done += count; 3079 budget -= count; 3080 if (budget > 0) { 3081 /* Clear the bit associated to this Rx queue 3082 * so that next iteration will continue from 3083 * the next Rx queue. 3084 */ 3085 cause_rx &= ~(1 << rxq->logic_rxq); 3086 } 3087 } 3088 3089 if (budget > 0) { 3090 cause_rx = 0; 3091 napi_complete_done(napi, rx_done); 3092 3093 mvpp2_qvec_interrupt_enable(qv); 3094 } 3095 qv->pending_cause_rx = cause_rx; 3096 return rx_done; 3097 } 3098 3099 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3100 { 3101 u32 ctrl3; 3102 3103 /* comphy reconfiguration */ 3104 mvpp22_comphy_init(port); 3105 3106 /* gop reconfiguration */ 3107 mvpp22_gop_init(port); 3108 3109 /* Only GOP port 0 has an XLG MAC */ 3110 if (port->gop_id == 0) { 3111 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3112 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3113 3114 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3115 port->phy_interface == PHY_INTERFACE_MODE_10GKR) 3116 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3117 else 3118 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3119 3120 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3121 } 3122 3123 if (port->gop_id == 0 && 3124 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3125 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) 3126 mvpp2_xlg_max_rx_size_set(port); 3127 else 3128 mvpp2_gmac_max_rx_size_set(port); 3129 } 3130 3131 /* Set hw internals when starting port */ 3132 static void mvpp2_start_dev(struct mvpp2_port *port) 3133 { 3134 int i; 3135 3136 mvpp2_txp_max_tx_size_set(port); 3137 3138 for (i = 0; i < port->nqvecs; i++) 3139 napi_enable(&port->qvecs[i].napi); 3140 3141 /* Enable interrupts on all CPUs */ 3142 mvpp2_interrupts_enable(port); 3143 3144 if (port->priv->hw_version == MVPP22) 3145 mvpp22_mode_reconfigure(port); 3146 3147 if (port->phylink) { 3148 phylink_start(port->phylink); 3149 } else { 3150 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3151 * configured manually when the interface is started. This will 3152 * be removed as soon as the phylink ACPI support lands in. 3153 */ 3154 struct phylink_link_state state = { 3155 .interface = port->phy_interface, 3156 .link = 1, 3157 }; 3158 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state); 3159 } 3160 3161 netif_tx_start_all_queues(port->dev); 3162 } 3163 3164 /* Set hw internals when stopping port */ 3165 static void mvpp2_stop_dev(struct mvpp2_port *port) 3166 { 3167 int i; 3168 3169 /* Disable interrupts on all CPUs */ 3170 mvpp2_interrupts_disable(port); 3171 3172 for (i = 0; i < port->nqvecs; i++) 3173 napi_disable(&port->qvecs[i].napi); 3174 3175 if (port->phylink) 3176 phylink_stop(port->phylink); 3177 phy_power_off(port->comphy); 3178 } 3179 3180 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3181 struct ethtool_ringparam *ring) 3182 { 3183 u16 new_rx_pending = ring->rx_pending; 3184 u16 new_tx_pending = ring->tx_pending; 3185 3186 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3187 return -EINVAL; 3188 3189 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3190 new_rx_pending = MVPP2_MAX_RXD_MAX; 3191 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3192 new_rx_pending = ALIGN(ring->rx_pending, 16); 3193 3194 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3195 new_tx_pending = MVPP2_MAX_TXD_MAX; 3196 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3197 new_tx_pending = ALIGN(ring->tx_pending, 32); 3198 3199 /* The Tx ring size cannot be smaller than the minimum number of 3200 * descriptors needed for TSO. 3201 */ 3202 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3203 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3204 3205 if (ring->rx_pending != new_rx_pending) { 3206 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3207 ring->rx_pending, new_rx_pending); 3208 ring->rx_pending = new_rx_pending; 3209 } 3210 3211 if (ring->tx_pending != new_tx_pending) { 3212 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3213 ring->tx_pending, new_tx_pending); 3214 ring->tx_pending = new_tx_pending; 3215 } 3216 3217 return 0; 3218 } 3219 3220 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3221 { 3222 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3223 3224 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3225 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3226 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3227 addr[0] = (mac_addr_h >> 24) & 0xFF; 3228 addr[1] = (mac_addr_h >> 16) & 0xFF; 3229 addr[2] = (mac_addr_h >> 8) & 0xFF; 3230 addr[3] = mac_addr_h & 0xFF; 3231 addr[4] = mac_addr_m & 0xFF; 3232 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3233 } 3234 3235 static int mvpp2_irqs_init(struct mvpp2_port *port) 3236 { 3237 int err, i; 3238 3239 for (i = 0; i < port->nqvecs; i++) { 3240 struct mvpp2_queue_vector *qv = port->qvecs + i; 3241 3242 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) 3243 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3244 3245 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3246 if (err) 3247 goto err; 3248 3249 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) 3250 irq_set_affinity_hint(qv->irq, 3251 cpumask_of(qv->sw_thread_id)); 3252 } 3253 3254 return 0; 3255 err: 3256 for (i = 0; i < port->nqvecs; i++) { 3257 struct mvpp2_queue_vector *qv = port->qvecs + i; 3258 3259 irq_set_affinity_hint(qv->irq, NULL); 3260 free_irq(qv->irq, qv); 3261 } 3262 3263 return err; 3264 } 3265 3266 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3267 { 3268 int i; 3269 3270 for (i = 0; i < port->nqvecs; i++) { 3271 struct mvpp2_queue_vector *qv = port->qvecs + i; 3272 3273 irq_set_affinity_hint(qv->irq, NULL); 3274 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3275 free_irq(qv->irq, qv); 3276 } 3277 } 3278 3279 static int mvpp2_open(struct net_device *dev) 3280 { 3281 struct mvpp2_port *port = netdev_priv(dev); 3282 struct mvpp2 *priv = port->priv; 3283 unsigned char mac_bcast[ETH_ALEN] = { 3284 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3285 bool valid = false; 3286 int err; 3287 3288 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3289 if (err) { 3290 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3291 return err; 3292 } 3293 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3294 if (err) { 3295 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3296 return err; 3297 } 3298 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3299 if (err) { 3300 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3301 return err; 3302 } 3303 err = mvpp2_prs_def_flow(port); 3304 if (err) { 3305 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3306 return err; 3307 } 3308 3309 /* Allocate the Rx/Tx queues */ 3310 err = mvpp2_setup_rxqs(port); 3311 if (err) { 3312 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3313 return err; 3314 } 3315 3316 err = mvpp2_setup_txqs(port); 3317 if (err) { 3318 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3319 goto err_cleanup_rxqs; 3320 } 3321 3322 err = mvpp2_irqs_init(port); 3323 if (err) { 3324 netdev_err(port->dev, "cannot init IRQs\n"); 3325 goto err_cleanup_txqs; 3326 } 3327 3328 /* Phylink isn't supported yet in ACPI mode */ 3329 if (port->of_node) { 3330 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3331 if (err) { 3332 netdev_err(port->dev, "could not attach PHY (%d)\n", 3333 err); 3334 goto err_free_irq; 3335 } 3336 3337 valid = true; 3338 } 3339 3340 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3341 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3342 dev->name, port); 3343 if (err) { 3344 netdev_err(port->dev, "cannot request link IRQ %d\n", 3345 port->link_irq); 3346 goto err_free_irq; 3347 } 3348 3349 mvpp22_gop_setup_irq(port); 3350 3351 /* In default link is down */ 3352 netif_carrier_off(port->dev); 3353 3354 valid = true; 3355 } else { 3356 port->link_irq = 0; 3357 } 3358 3359 if (!valid) { 3360 netdev_err(port->dev, 3361 "invalid configuration: no dt or link IRQ"); 3362 goto err_free_irq; 3363 } 3364 3365 /* Unmask interrupts on all CPUs */ 3366 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3367 mvpp2_shared_interrupt_mask_unmask(port, false); 3368 3369 mvpp2_start_dev(port); 3370 3371 if (priv->hw_version == MVPP22) 3372 mvpp22_init_rss(port); 3373 3374 /* Start hardware statistics gathering */ 3375 queue_delayed_work(priv->stats_queue, &port->stats_work, 3376 MVPP2_MIB_COUNTERS_STATS_DELAY); 3377 3378 return 0; 3379 3380 err_free_irq: 3381 mvpp2_irqs_deinit(port); 3382 err_cleanup_txqs: 3383 mvpp2_cleanup_txqs(port); 3384 err_cleanup_rxqs: 3385 mvpp2_cleanup_rxqs(port); 3386 return err; 3387 } 3388 3389 static int mvpp2_stop(struct net_device *dev) 3390 { 3391 struct mvpp2_port *port = netdev_priv(dev); 3392 struct mvpp2_port_pcpu *port_pcpu; 3393 int cpu; 3394 3395 mvpp2_stop_dev(port); 3396 3397 /* Mask interrupts on all CPUs */ 3398 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3399 mvpp2_shared_interrupt_mask_unmask(port, true); 3400 3401 if (port->phylink) 3402 phylink_disconnect_phy(port->phylink); 3403 if (port->link_irq) 3404 free_irq(port->link_irq, port); 3405 3406 mvpp2_irqs_deinit(port); 3407 if (!port->has_tx_irqs) { 3408 for_each_present_cpu(cpu) { 3409 port_pcpu = per_cpu_ptr(port->pcpu, cpu); 3410 3411 hrtimer_cancel(&port_pcpu->tx_done_timer); 3412 port_pcpu->timer_scheduled = false; 3413 tasklet_kill(&port_pcpu->tx_done_tasklet); 3414 } 3415 } 3416 mvpp2_cleanup_rxqs(port); 3417 mvpp2_cleanup_txqs(port); 3418 3419 cancel_delayed_work_sync(&port->stats_work); 3420 3421 return 0; 3422 } 3423 3424 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3425 struct netdev_hw_addr_list *list) 3426 { 3427 struct netdev_hw_addr *ha; 3428 int ret; 3429 3430 netdev_hw_addr_list_for_each(ha, list) { 3431 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3432 if (ret) 3433 return ret; 3434 } 3435 3436 return 0; 3437 } 3438 3439 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3440 { 3441 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3442 mvpp2_prs_vid_enable_filtering(port); 3443 else 3444 mvpp2_prs_vid_disable_filtering(port); 3445 3446 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3447 MVPP2_PRS_L2_UNI_CAST, enable); 3448 3449 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3450 MVPP2_PRS_L2_MULTI_CAST, enable); 3451 } 3452 3453 static void mvpp2_set_rx_mode(struct net_device *dev) 3454 { 3455 struct mvpp2_port *port = netdev_priv(dev); 3456 3457 /* Clear the whole UC and MC list */ 3458 mvpp2_prs_mac_del_all(port); 3459 3460 if (dev->flags & IFF_PROMISC) { 3461 mvpp2_set_rx_promisc(port, true); 3462 return; 3463 } 3464 3465 mvpp2_set_rx_promisc(port, false); 3466 3467 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3468 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3469 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3470 MVPP2_PRS_L2_UNI_CAST, true); 3471 3472 if (dev->flags & IFF_ALLMULTI) { 3473 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3474 MVPP2_PRS_L2_MULTI_CAST, true); 3475 return; 3476 } 3477 3478 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3479 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3480 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3481 MVPP2_PRS_L2_MULTI_CAST, true); 3482 } 3483 3484 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3485 { 3486 const struct sockaddr *addr = p; 3487 int err; 3488 3489 if (!is_valid_ether_addr(addr->sa_data)) 3490 return -EADDRNOTAVAIL; 3491 3492 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3493 if (err) { 3494 /* Reconfigure parser accept the original MAC address */ 3495 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3496 netdev_err(dev, "failed to change MAC address\n"); 3497 } 3498 return err; 3499 } 3500 3501 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3502 { 3503 struct mvpp2_port *port = netdev_priv(dev); 3504 int err; 3505 3506 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3507 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3508 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3509 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3510 } 3511 3512 if (!netif_running(dev)) { 3513 err = mvpp2_bm_update_mtu(dev, mtu); 3514 if (!err) { 3515 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3516 return 0; 3517 } 3518 3519 /* Reconfigure BM to the original MTU */ 3520 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3521 if (err) 3522 goto log_error; 3523 } 3524 3525 mvpp2_stop_dev(port); 3526 3527 err = mvpp2_bm_update_mtu(dev, mtu); 3528 if (!err) { 3529 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3530 goto out_start; 3531 } 3532 3533 /* Reconfigure BM to the original MTU */ 3534 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3535 if (err) 3536 goto log_error; 3537 3538 out_start: 3539 mvpp2_start_dev(port); 3540 mvpp2_egress_enable(port); 3541 mvpp2_ingress_enable(port); 3542 3543 return 0; 3544 log_error: 3545 netdev_err(dev, "failed to change MTU\n"); 3546 return err; 3547 } 3548 3549 static void 3550 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3551 { 3552 struct mvpp2_port *port = netdev_priv(dev); 3553 unsigned int start; 3554 int cpu; 3555 3556 for_each_possible_cpu(cpu) { 3557 struct mvpp2_pcpu_stats *cpu_stats; 3558 u64 rx_packets; 3559 u64 rx_bytes; 3560 u64 tx_packets; 3561 u64 tx_bytes; 3562 3563 cpu_stats = per_cpu_ptr(port->stats, cpu); 3564 do { 3565 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3566 rx_packets = cpu_stats->rx_packets; 3567 rx_bytes = cpu_stats->rx_bytes; 3568 tx_packets = cpu_stats->tx_packets; 3569 tx_bytes = cpu_stats->tx_bytes; 3570 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3571 3572 stats->rx_packets += rx_packets; 3573 stats->rx_bytes += rx_bytes; 3574 stats->tx_packets += tx_packets; 3575 stats->tx_bytes += tx_bytes; 3576 } 3577 3578 stats->rx_errors = dev->stats.rx_errors; 3579 stats->rx_dropped = dev->stats.rx_dropped; 3580 stats->tx_dropped = dev->stats.tx_dropped; 3581 } 3582 3583 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3584 { 3585 struct mvpp2_port *port = netdev_priv(dev); 3586 3587 if (!port->phylink) 3588 return -ENOTSUPP; 3589 3590 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3591 } 3592 3593 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3594 { 3595 struct mvpp2_port *port = netdev_priv(dev); 3596 int ret; 3597 3598 ret = mvpp2_prs_vid_entry_add(port, vid); 3599 if (ret) 3600 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3601 MVPP2_PRS_VLAN_FILT_MAX - 1); 3602 return ret; 3603 } 3604 3605 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3606 { 3607 struct mvpp2_port *port = netdev_priv(dev); 3608 3609 mvpp2_prs_vid_entry_remove(port, vid); 3610 return 0; 3611 } 3612 3613 static int mvpp2_set_features(struct net_device *dev, 3614 netdev_features_t features) 3615 { 3616 netdev_features_t changed = dev->features ^ features; 3617 struct mvpp2_port *port = netdev_priv(dev); 3618 3619 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3620 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3621 mvpp2_prs_vid_enable_filtering(port); 3622 } else { 3623 /* Invalidate all registered VID filters for this 3624 * port 3625 */ 3626 mvpp2_prs_vid_remove_all(port); 3627 3628 mvpp2_prs_vid_disable_filtering(port); 3629 } 3630 } 3631 3632 return 0; 3633 } 3634 3635 /* Ethtool methods */ 3636 3637 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3638 { 3639 struct mvpp2_port *port = netdev_priv(dev); 3640 3641 if (!port->phylink) 3642 return -ENOTSUPP; 3643 3644 return phylink_ethtool_nway_reset(port->phylink); 3645 } 3646 3647 /* Set interrupt coalescing for ethtools */ 3648 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3649 struct ethtool_coalesce *c) 3650 { 3651 struct mvpp2_port *port = netdev_priv(dev); 3652 int queue; 3653 3654 for (queue = 0; queue < port->nrxqs; queue++) { 3655 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3656 3657 rxq->time_coal = c->rx_coalesce_usecs; 3658 rxq->pkts_coal = c->rx_max_coalesced_frames; 3659 mvpp2_rx_pkts_coal_set(port, rxq); 3660 mvpp2_rx_time_coal_set(port, rxq); 3661 } 3662 3663 if (port->has_tx_irqs) { 3664 port->tx_time_coal = c->tx_coalesce_usecs; 3665 mvpp2_tx_time_coal_set(port); 3666 } 3667 3668 for (queue = 0; queue < port->ntxqs; queue++) { 3669 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3670 3671 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3672 3673 if (port->has_tx_irqs) 3674 mvpp2_tx_pkts_coal_set(port, txq); 3675 } 3676 3677 return 0; 3678 } 3679 3680 /* get coalescing for ethtools */ 3681 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3682 struct ethtool_coalesce *c) 3683 { 3684 struct mvpp2_port *port = netdev_priv(dev); 3685 3686 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3687 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3688 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3689 c->tx_coalesce_usecs = port->tx_time_coal; 3690 return 0; 3691 } 3692 3693 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3694 struct ethtool_drvinfo *drvinfo) 3695 { 3696 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3697 sizeof(drvinfo->driver)); 3698 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3699 sizeof(drvinfo->version)); 3700 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3701 sizeof(drvinfo->bus_info)); 3702 } 3703 3704 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3705 struct ethtool_ringparam *ring) 3706 { 3707 struct mvpp2_port *port = netdev_priv(dev); 3708 3709 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3710 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3711 ring->rx_pending = port->rx_ring_size; 3712 ring->tx_pending = port->tx_ring_size; 3713 } 3714 3715 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3716 struct ethtool_ringparam *ring) 3717 { 3718 struct mvpp2_port *port = netdev_priv(dev); 3719 u16 prev_rx_ring_size = port->rx_ring_size; 3720 u16 prev_tx_ring_size = port->tx_ring_size; 3721 int err; 3722 3723 err = mvpp2_check_ringparam_valid(dev, ring); 3724 if (err) 3725 return err; 3726 3727 if (!netif_running(dev)) { 3728 port->rx_ring_size = ring->rx_pending; 3729 port->tx_ring_size = ring->tx_pending; 3730 return 0; 3731 } 3732 3733 /* The interface is running, so we have to force a 3734 * reallocation of the queues 3735 */ 3736 mvpp2_stop_dev(port); 3737 mvpp2_cleanup_rxqs(port); 3738 mvpp2_cleanup_txqs(port); 3739 3740 port->rx_ring_size = ring->rx_pending; 3741 port->tx_ring_size = ring->tx_pending; 3742 3743 err = mvpp2_setup_rxqs(port); 3744 if (err) { 3745 /* Reallocate Rx queues with the original ring size */ 3746 port->rx_ring_size = prev_rx_ring_size; 3747 ring->rx_pending = prev_rx_ring_size; 3748 err = mvpp2_setup_rxqs(port); 3749 if (err) 3750 goto err_out; 3751 } 3752 err = mvpp2_setup_txqs(port); 3753 if (err) { 3754 /* Reallocate Tx queues with the original ring size */ 3755 port->tx_ring_size = prev_tx_ring_size; 3756 ring->tx_pending = prev_tx_ring_size; 3757 err = mvpp2_setup_txqs(port); 3758 if (err) 3759 goto err_clean_rxqs; 3760 } 3761 3762 mvpp2_start_dev(port); 3763 mvpp2_egress_enable(port); 3764 mvpp2_ingress_enable(port); 3765 3766 return 0; 3767 3768 err_clean_rxqs: 3769 mvpp2_cleanup_rxqs(port); 3770 err_out: 3771 netdev_err(dev, "failed to change ring parameters"); 3772 return err; 3773 } 3774 3775 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3776 struct ethtool_pauseparam *pause) 3777 { 3778 struct mvpp2_port *port = netdev_priv(dev); 3779 3780 if (!port->phylink) 3781 return; 3782 3783 phylink_ethtool_get_pauseparam(port->phylink, pause); 3784 } 3785 3786 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3787 struct ethtool_pauseparam *pause) 3788 { 3789 struct mvpp2_port *port = netdev_priv(dev); 3790 3791 if (!port->phylink) 3792 return -ENOTSUPP; 3793 3794 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3795 } 3796 3797 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 3798 struct ethtool_link_ksettings *cmd) 3799 { 3800 struct mvpp2_port *port = netdev_priv(dev); 3801 3802 if (!port->phylink) 3803 return -ENOTSUPP; 3804 3805 return phylink_ethtool_ksettings_get(port->phylink, cmd); 3806 } 3807 3808 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 3809 const struct ethtool_link_ksettings *cmd) 3810 { 3811 struct mvpp2_port *port = netdev_priv(dev); 3812 3813 if (!port->phylink) 3814 return -ENOTSUPP; 3815 3816 return phylink_ethtool_ksettings_set(port->phylink, cmd); 3817 } 3818 3819 /* Device ops */ 3820 3821 static const struct net_device_ops mvpp2_netdev_ops = { 3822 .ndo_open = mvpp2_open, 3823 .ndo_stop = mvpp2_stop, 3824 .ndo_start_xmit = mvpp2_tx, 3825 .ndo_set_rx_mode = mvpp2_set_rx_mode, 3826 .ndo_set_mac_address = mvpp2_set_mac_address, 3827 .ndo_change_mtu = mvpp2_change_mtu, 3828 .ndo_get_stats64 = mvpp2_get_stats64, 3829 .ndo_do_ioctl = mvpp2_ioctl, 3830 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 3831 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 3832 .ndo_set_features = mvpp2_set_features, 3833 }; 3834 3835 static const struct ethtool_ops mvpp2_eth_tool_ops = { 3836 .nway_reset = mvpp2_ethtool_nway_reset, 3837 .get_link = ethtool_op_get_link, 3838 .set_coalesce = mvpp2_ethtool_set_coalesce, 3839 .get_coalesce = mvpp2_ethtool_get_coalesce, 3840 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 3841 .get_ringparam = mvpp2_ethtool_get_ringparam, 3842 .set_ringparam = mvpp2_ethtool_set_ringparam, 3843 .get_strings = mvpp2_ethtool_get_strings, 3844 .get_ethtool_stats = mvpp2_ethtool_get_stats, 3845 .get_sset_count = mvpp2_ethtool_get_sset_count, 3846 .get_pauseparam = mvpp2_ethtool_get_pause_param, 3847 .set_pauseparam = mvpp2_ethtool_set_pause_param, 3848 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 3849 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 3850 }; 3851 3852 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 3853 * had a single IRQ defined per-port. 3854 */ 3855 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 3856 struct device_node *port_node) 3857 { 3858 struct mvpp2_queue_vector *v = &port->qvecs[0]; 3859 3860 v->first_rxq = 0; 3861 v->nrxqs = port->nrxqs; 3862 v->type = MVPP2_QUEUE_VECTOR_SHARED; 3863 v->sw_thread_id = 0; 3864 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 3865 v->port = port; 3866 v->irq = irq_of_parse_and_map(port_node, 0); 3867 if (v->irq <= 0) 3868 return -EINVAL; 3869 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 3870 NAPI_POLL_WEIGHT); 3871 3872 port->nqvecs = 1; 3873 3874 return 0; 3875 } 3876 3877 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 3878 struct device_node *port_node) 3879 { 3880 struct mvpp2_queue_vector *v; 3881 int i, ret; 3882 3883 port->nqvecs = num_possible_cpus(); 3884 if (queue_mode == MVPP2_QDIST_SINGLE_MODE) 3885 port->nqvecs += 1; 3886 3887 for (i = 0; i < port->nqvecs; i++) { 3888 char irqname[16]; 3889 3890 v = port->qvecs + i; 3891 3892 v->port = port; 3893 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 3894 v->sw_thread_id = i; 3895 v->sw_thread_mask = BIT(i); 3896 3897 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 3898 3899 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 3900 v->first_rxq = i * MVPP2_DEFAULT_RXQ; 3901 v->nrxqs = MVPP2_DEFAULT_RXQ; 3902 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 3903 i == (port->nqvecs - 1)) { 3904 v->first_rxq = 0; 3905 v->nrxqs = port->nrxqs; 3906 v->type = MVPP2_QUEUE_VECTOR_SHARED; 3907 strncpy(irqname, "rx-shared", sizeof(irqname)); 3908 } 3909 3910 if (port_node) 3911 v->irq = of_irq_get_byname(port_node, irqname); 3912 else 3913 v->irq = fwnode_irq_get(port->fwnode, i); 3914 if (v->irq <= 0) { 3915 ret = -EINVAL; 3916 goto err; 3917 } 3918 3919 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 3920 NAPI_POLL_WEIGHT); 3921 } 3922 3923 return 0; 3924 3925 err: 3926 for (i = 0; i < port->nqvecs; i++) 3927 irq_dispose_mapping(port->qvecs[i].irq); 3928 return ret; 3929 } 3930 3931 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 3932 struct device_node *port_node) 3933 { 3934 if (port->has_tx_irqs) 3935 return mvpp2_multi_queue_vectors_init(port, port_node); 3936 else 3937 return mvpp2_simple_queue_vectors_init(port, port_node); 3938 } 3939 3940 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 3941 { 3942 int i; 3943 3944 for (i = 0; i < port->nqvecs; i++) 3945 irq_dispose_mapping(port->qvecs[i].irq); 3946 } 3947 3948 /* Configure Rx queue group interrupt for this port */ 3949 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 3950 { 3951 struct mvpp2 *priv = port->priv; 3952 u32 val; 3953 int i; 3954 3955 if (priv->hw_version == MVPP21) { 3956 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 3957 port->nrxqs); 3958 return; 3959 } 3960 3961 /* Handle the more complicated PPv2.2 case */ 3962 for (i = 0; i < port->nqvecs; i++) { 3963 struct mvpp2_queue_vector *qv = port->qvecs + i; 3964 3965 if (!qv->nrxqs) 3966 continue; 3967 3968 val = qv->sw_thread_id; 3969 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 3970 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 3971 3972 val = qv->first_rxq; 3973 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 3974 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 3975 } 3976 } 3977 3978 /* Initialize port HW */ 3979 static int mvpp2_port_init(struct mvpp2_port *port) 3980 { 3981 struct device *dev = port->dev->dev.parent; 3982 struct mvpp2 *priv = port->priv; 3983 struct mvpp2_txq_pcpu *txq_pcpu; 3984 int queue, cpu, err; 3985 3986 /* Checks for hardware constraints */ 3987 if (port->first_rxq + port->nrxqs > 3988 MVPP2_MAX_PORTS * priv->max_port_rxqs) 3989 return -EINVAL; 3990 3991 if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || 3992 (port->ntxqs > MVPP2_MAX_TXQ)) 3993 return -EINVAL; 3994 3995 /* Disable port */ 3996 mvpp2_egress_disable(port); 3997 mvpp2_port_disable(port); 3998 3999 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4000 4001 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4002 GFP_KERNEL); 4003 if (!port->txqs) 4004 return -ENOMEM; 4005 4006 /* Associate physical Tx queues to this port and initialize. 4007 * The mapping is predefined. 4008 */ 4009 for (queue = 0; queue < port->ntxqs; queue++) { 4010 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4011 struct mvpp2_tx_queue *txq; 4012 4013 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4014 if (!txq) { 4015 err = -ENOMEM; 4016 goto err_free_percpu; 4017 } 4018 4019 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4020 if (!txq->pcpu) { 4021 err = -ENOMEM; 4022 goto err_free_percpu; 4023 } 4024 4025 txq->id = queue_phy_id; 4026 txq->log_id = queue; 4027 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4028 for_each_present_cpu(cpu) { 4029 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 4030 txq_pcpu->cpu = cpu; 4031 } 4032 4033 port->txqs[queue] = txq; 4034 } 4035 4036 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4037 GFP_KERNEL); 4038 if (!port->rxqs) { 4039 err = -ENOMEM; 4040 goto err_free_percpu; 4041 } 4042 4043 /* Allocate and initialize Rx queue for this port */ 4044 for (queue = 0; queue < port->nrxqs; queue++) { 4045 struct mvpp2_rx_queue *rxq; 4046 4047 /* Map physical Rx queue to port's logical Rx queue */ 4048 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4049 if (!rxq) { 4050 err = -ENOMEM; 4051 goto err_free_percpu; 4052 } 4053 /* Map this Rx queue to a physical queue */ 4054 rxq->id = port->first_rxq + queue; 4055 rxq->port = port->id; 4056 rxq->logic_rxq = queue; 4057 4058 port->rxqs[queue] = rxq; 4059 } 4060 4061 mvpp2_rx_irqs_setup(port); 4062 4063 /* Create Rx descriptor rings */ 4064 for (queue = 0; queue < port->nrxqs; queue++) { 4065 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4066 4067 rxq->size = port->rx_ring_size; 4068 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4069 rxq->time_coal = MVPP2_RX_COAL_USEC; 4070 } 4071 4072 mvpp2_ingress_disable(port); 4073 4074 /* Port default configuration */ 4075 mvpp2_defaults_set(port); 4076 4077 /* Port's classifier configuration */ 4078 mvpp2_cls_oversize_rxq_set(port); 4079 mvpp2_cls_port_config(port); 4080 4081 /* Provide an initial Rx packet size */ 4082 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4083 4084 /* Initialize pools for swf */ 4085 err = mvpp2_swf_bm_pool_init(port); 4086 if (err) 4087 goto err_free_percpu; 4088 4089 return 0; 4090 4091 err_free_percpu: 4092 for (queue = 0; queue < port->ntxqs; queue++) { 4093 if (!port->txqs[queue]) 4094 continue; 4095 free_percpu(port->txqs[queue]->pcpu); 4096 } 4097 return err; 4098 } 4099 4100 /* Checks if the port DT description has the TX interrupts 4101 * described. On PPv2.1, there are no such interrupts. On PPv2.2, 4102 * there are available, but we need to keep support for old DTs. 4103 */ 4104 static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, 4105 struct device_node *port_node) 4106 { 4107 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", 4108 "tx-cpu2", "tx-cpu3" }; 4109 int ret, i; 4110 4111 if (priv->hw_version == MVPP21) 4112 return false; 4113 4114 for (i = 0; i < 5; i++) { 4115 ret = of_property_match_string(port_node, "interrupt-names", 4116 irqs[i]); 4117 if (ret < 0) 4118 return false; 4119 } 4120 4121 return true; 4122 } 4123 4124 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4125 struct fwnode_handle *fwnode, 4126 char **mac_from) 4127 { 4128 struct mvpp2_port *port = netdev_priv(dev); 4129 char hw_mac_addr[ETH_ALEN] = {0}; 4130 char fw_mac_addr[ETH_ALEN]; 4131 4132 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4133 *mac_from = "firmware node"; 4134 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4135 return; 4136 } 4137 4138 if (priv->hw_version == MVPP21) { 4139 mvpp21_get_mac_address(port, hw_mac_addr); 4140 if (is_valid_ether_addr(hw_mac_addr)) { 4141 *mac_from = "hardware"; 4142 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4143 return; 4144 } 4145 } 4146 4147 *mac_from = "random"; 4148 eth_hw_addr_random(dev); 4149 } 4150 4151 static void mvpp2_phylink_validate(struct net_device *dev, 4152 unsigned long *supported, 4153 struct phylink_link_state *state) 4154 { 4155 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4156 4157 phylink_set(mask, Autoneg); 4158 phylink_set_port_modes(mask); 4159 phylink_set(mask, Pause); 4160 phylink_set(mask, Asym_Pause); 4161 4162 switch (state->interface) { 4163 case PHY_INTERFACE_MODE_10GKR: 4164 phylink_set(mask, 10000baseCR_Full); 4165 phylink_set(mask, 10000baseSR_Full); 4166 phylink_set(mask, 10000baseLR_Full); 4167 phylink_set(mask, 10000baseLRM_Full); 4168 phylink_set(mask, 10000baseER_Full); 4169 phylink_set(mask, 10000baseKR_Full); 4170 /* Fall-through */ 4171 default: 4172 phylink_set(mask, 10baseT_Half); 4173 phylink_set(mask, 10baseT_Full); 4174 phylink_set(mask, 100baseT_Half); 4175 phylink_set(mask, 100baseT_Full); 4176 phylink_set(mask, 10000baseT_Full); 4177 /* Fall-through */ 4178 case PHY_INTERFACE_MODE_1000BASEX: 4179 case PHY_INTERFACE_MODE_2500BASEX: 4180 phylink_set(mask, 1000baseT_Full); 4181 phylink_set(mask, 1000baseX_Full); 4182 phylink_set(mask, 2500baseX_Full); 4183 } 4184 4185 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4186 bitmap_and(state->advertising, state->advertising, mask, 4187 __ETHTOOL_LINK_MODE_MASK_NBITS); 4188 } 4189 4190 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4191 struct phylink_link_state *state) 4192 { 4193 u32 val; 4194 4195 state->speed = SPEED_10000; 4196 state->duplex = 1; 4197 state->an_complete = 1; 4198 4199 val = readl(port->base + MVPP22_XLG_STATUS); 4200 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4201 4202 state->pause = 0; 4203 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4204 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4205 state->pause |= MLO_PAUSE_TX; 4206 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4207 state->pause |= MLO_PAUSE_RX; 4208 } 4209 4210 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4211 struct phylink_link_state *state) 4212 { 4213 u32 val; 4214 4215 val = readl(port->base + MVPP2_GMAC_STATUS0); 4216 4217 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4218 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4219 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4220 4221 switch (port->phy_interface) { 4222 case PHY_INTERFACE_MODE_1000BASEX: 4223 state->speed = SPEED_1000; 4224 break; 4225 case PHY_INTERFACE_MODE_2500BASEX: 4226 state->speed = SPEED_2500; 4227 break; 4228 default: 4229 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4230 state->speed = SPEED_1000; 4231 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4232 state->speed = SPEED_100; 4233 else 4234 state->speed = SPEED_10; 4235 } 4236 4237 state->pause = 0; 4238 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4239 state->pause |= MLO_PAUSE_RX; 4240 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4241 state->pause |= MLO_PAUSE_TX; 4242 } 4243 4244 static int mvpp2_phylink_mac_link_state(struct net_device *dev, 4245 struct phylink_link_state *state) 4246 { 4247 struct mvpp2_port *port = netdev_priv(dev); 4248 4249 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4250 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4251 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4252 4253 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4254 mvpp22_xlg_link_state(port, state); 4255 return 1; 4256 } 4257 } 4258 4259 mvpp2_gmac_link_state(port, state); 4260 return 1; 4261 } 4262 4263 static void mvpp2_mac_an_restart(struct net_device *dev) 4264 { 4265 struct mvpp2_port *port = netdev_priv(dev); 4266 u32 val; 4267 4268 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII) 4269 return; 4270 4271 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4272 /* The RESTART_AN bit is cleared by the h/w after restarting the AN 4273 * process. 4274 */ 4275 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG; 4276 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4277 } 4278 4279 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4280 const struct phylink_link_state *state) 4281 { 4282 u32 ctrl0, ctrl4; 4283 4284 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4285 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4286 4287 if (state->pause & MLO_PAUSE_TX) 4288 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4289 if (state->pause & MLO_PAUSE_RX) 4290 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4291 4292 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4293 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4294 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4295 4296 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4297 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4298 } 4299 4300 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4301 const struct phylink_link_state *state) 4302 { 4303 u32 an, ctrl0, ctrl2, ctrl4; 4304 4305 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4306 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4307 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4308 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4309 4310 /* Force link down */ 4311 an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4312 an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4313 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4314 4315 /* Set the GMAC in a reset state */ 4316 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4317 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4318 4319 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4320 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4321 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4322 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4323 MVPP2_GMAC_FORCE_LINK_DOWN); 4324 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4325 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); 4326 4327 if (state->interface == PHY_INTERFACE_MODE_1000BASEX || 4328 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4329 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4330 * they negotiate duplex: they are always operating with a fixed 4331 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4332 * speed and full duplex here. 4333 */ 4334 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4335 an |= MVPP2_GMAC_CONFIG_GMII_SPEED | 4336 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4337 } else if (!phy_interface_mode_is_rgmii(state->interface)) { 4338 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4339 } 4340 4341 if (state->duplex) 4342 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4343 if (phylink_test(state->advertising, Pause)) 4344 an |= MVPP2_GMAC_FC_ADV_EN; 4345 if (phylink_test(state->advertising, Asym_Pause)) 4346 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4347 4348 if (state->interface == PHY_INTERFACE_MODE_SGMII || 4349 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4350 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4351 an |= MVPP2_GMAC_IN_BAND_AUTONEG; 4352 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; 4353 4354 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4355 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4356 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4357 MVPP22_CTRL4_DP_CLK_SEL | 4358 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4359 4360 if (state->pause & MLO_PAUSE_TX) 4361 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4362 if (state->pause & MLO_PAUSE_RX) 4363 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4364 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4365 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS; 4366 4367 if (state->speed == SPEED_1000) 4368 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4369 else if (state->speed == SPEED_100) 4370 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4371 4372 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4373 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4374 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4375 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4376 } 4377 4378 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4379 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4380 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4381 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4382 } 4383 4384 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 4385 const struct phylink_link_state *state) 4386 { 4387 struct mvpp2_port *port = netdev_priv(dev); 4388 4389 /* Check for invalid configuration */ 4390 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) { 4391 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4392 return; 4393 } 4394 4395 netif_tx_stop_all_queues(port->dev); 4396 if (!port->has_phy) 4397 netif_carrier_off(port->dev); 4398 4399 /* Make sure the port is disabled when reconfiguring the mode */ 4400 mvpp2_port_disable(port); 4401 4402 if (port->priv->hw_version == MVPP22 && 4403 port->phy_interface != state->interface) { 4404 port->phy_interface = state->interface; 4405 4406 /* Reconfigure the serdes lanes */ 4407 phy_power_off(port->comphy); 4408 mvpp22_mode_reconfigure(port); 4409 } 4410 4411 /* mac (re)configuration */ 4412 if (state->interface == PHY_INTERFACE_MODE_10GKR) 4413 mvpp2_xlg_config(port, mode, state); 4414 else if (phy_interface_mode_is_rgmii(state->interface) || 4415 state->interface == PHY_INTERFACE_MODE_SGMII || 4416 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4417 state->interface == PHY_INTERFACE_MODE_2500BASEX) 4418 mvpp2_gmac_config(port, mode, state); 4419 4420 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4421 mvpp2_port_loopback_set(port, state); 4422 4423 /* If the port already was up, make sure it's still in the same state */ 4424 if (state->link || !port->has_phy) { 4425 mvpp2_port_enable(port); 4426 4427 mvpp2_egress_enable(port); 4428 mvpp2_ingress_enable(port); 4429 if (!port->has_phy) 4430 netif_carrier_on(dev); 4431 netif_tx_wake_all_queues(dev); 4432 } 4433 } 4434 4435 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 4436 phy_interface_t interface, struct phy_device *phy) 4437 { 4438 struct mvpp2_port *port = netdev_priv(dev); 4439 u32 val; 4440 4441 if (!phylink_autoneg_inband(mode) && 4442 interface != PHY_INTERFACE_MODE_10GKR) { 4443 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4444 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4445 if (phy_interface_mode_is_rgmii(interface)) 4446 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4447 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4448 } 4449 4450 mvpp2_port_enable(port); 4451 4452 mvpp2_egress_enable(port); 4453 mvpp2_ingress_enable(port); 4454 netif_tx_wake_all_queues(dev); 4455 } 4456 4457 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode, 4458 phy_interface_t interface) 4459 { 4460 struct mvpp2_port *port = netdev_priv(dev); 4461 u32 val; 4462 4463 if (!phylink_autoneg_inband(mode) && 4464 interface != PHY_INTERFACE_MODE_10GKR) { 4465 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4466 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4467 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4468 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4469 } 4470 4471 netif_tx_stop_all_queues(dev); 4472 mvpp2_egress_disable(port); 4473 mvpp2_ingress_disable(port); 4474 4475 /* When using link interrupts to notify phylink of a MAC state change, 4476 * we do not want the port to be disabled (we want to receive further 4477 * interrupts, to be notified when the port will have a link later). 4478 */ 4479 if (!port->has_phy) 4480 return; 4481 4482 mvpp2_port_disable(port); 4483 } 4484 4485 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4486 .validate = mvpp2_phylink_validate, 4487 .mac_link_state = mvpp2_phylink_mac_link_state, 4488 .mac_an_restart = mvpp2_mac_an_restart, 4489 .mac_config = mvpp2_mac_config, 4490 .mac_link_up = mvpp2_mac_link_up, 4491 .mac_link_down = mvpp2_mac_link_down, 4492 }; 4493 4494 /* Ports initialization */ 4495 static int mvpp2_port_probe(struct platform_device *pdev, 4496 struct fwnode_handle *port_fwnode, 4497 struct mvpp2 *priv) 4498 { 4499 struct phy *comphy = NULL; 4500 struct mvpp2_port *port; 4501 struct mvpp2_port_pcpu *port_pcpu; 4502 struct device_node *port_node = to_of_node(port_fwnode); 4503 struct net_device *dev; 4504 struct resource *res; 4505 struct phylink *phylink; 4506 char *mac_from = ""; 4507 unsigned int ntxqs, nrxqs; 4508 bool has_tx_irqs; 4509 u32 id; 4510 int features; 4511 int phy_mode; 4512 int err, i, cpu; 4513 4514 if (port_node) { 4515 has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); 4516 } else { 4517 has_tx_irqs = true; 4518 queue_mode = MVPP2_QDIST_MULTI_MODE; 4519 } 4520 4521 if (!has_tx_irqs) 4522 queue_mode = MVPP2_QDIST_SINGLE_MODE; 4523 4524 ntxqs = MVPP2_MAX_TXQ; 4525 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) 4526 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); 4527 else 4528 nrxqs = MVPP2_DEFAULT_RXQ; 4529 4530 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 4531 if (!dev) 4532 return -ENOMEM; 4533 4534 phy_mode = fwnode_get_phy_mode(port_fwnode); 4535 if (phy_mode < 0) { 4536 dev_err(&pdev->dev, "incorrect phy mode\n"); 4537 err = phy_mode; 4538 goto err_free_netdev; 4539 } 4540 4541 if (port_node) { 4542 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 4543 if (IS_ERR(comphy)) { 4544 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 4545 err = -EPROBE_DEFER; 4546 goto err_free_netdev; 4547 } 4548 comphy = NULL; 4549 } 4550 } 4551 4552 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 4553 err = -EINVAL; 4554 dev_err(&pdev->dev, "missing port-id value\n"); 4555 goto err_free_netdev; 4556 } 4557 4558 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 4559 dev->watchdog_timeo = 5 * HZ; 4560 dev->netdev_ops = &mvpp2_netdev_ops; 4561 dev->ethtool_ops = &mvpp2_eth_tool_ops; 4562 4563 port = netdev_priv(dev); 4564 port->dev = dev; 4565 port->fwnode = port_fwnode; 4566 port->has_phy = !!of_find_property(port_node, "phy", NULL); 4567 port->ntxqs = ntxqs; 4568 port->nrxqs = nrxqs; 4569 port->priv = priv; 4570 port->has_tx_irqs = has_tx_irqs; 4571 4572 err = mvpp2_queue_vectors_init(port, port_node); 4573 if (err) 4574 goto err_free_netdev; 4575 4576 if (port_node) 4577 port->link_irq = of_irq_get_byname(port_node, "link"); 4578 else 4579 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 4580 if (port->link_irq == -EPROBE_DEFER) { 4581 err = -EPROBE_DEFER; 4582 goto err_deinit_qvecs; 4583 } 4584 if (port->link_irq <= 0) 4585 /* the link irq is optional */ 4586 port->link_irq = 0; 4587 4588 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 4589 port->flags |= MVPP2_F_LOOPBACK; 4590 4591 port->id = id; 4592 if (priv->hw_version == MVPP21) 4593 port->first_rxq = port->id * port->nrxqs; 4594 else 4595 port->first_rxq = port->id * priv->max_port_rxqs; 4596 4597 port->of_node = port_node; 4598 port->phy_interface = phy_mode; 4599 port->comphy = comphy; 4600 4601 if (priv->hw_version == MVPP21) { 4602 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); 4603 port->base = devm_ioremap_resource(&pdev->dev, res); 4604 if (IS_ERR(port->base)) { 4605 err = PTR_ERR(port->base); 4606 goto err_free_irq; 4607 } 4608 4609 port->stats_base = port->priv->lms_base + 4610 MVPP21_MIB_COUNTERS_OFFSET + 4611 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 4612 } else { 4613 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 4614 &port->gop_id)) { 4615 err = -EINVAL; 4616 dev_err(&pdev->dev, "missing gop-port-id value\n"); 4617 goto err_deinit_qvecs; 4618 } 4619 4620 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 4621 port->stats_base = port->priv->iface_base + 4622 MVPP22_MIB_COUNTERS_OFFSET + 4623 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 4624 } 4625 4626 /* Alloc per-cpu and ethtool stats */ 4627 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 4628 if (!port->stats) { 4629 err = -ENOMEM; 4630 goto err_free_irq; 4631 } 4632 4633 port->ethtool_stats = devm_kcalloc(&pdev->dev, 4634 ARRAY_SIZE(mvpp2_ethtool_regs), 4635 sizeof(u64), GFP_KERNEL); 4636 if (!port->ethtool_stats) { 4637 err = -ENOMEM; 4638 goto err_free_stats; 4639 } 4640 4641 mutex_init(&port->gather_stats_lock); 4642 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 4643 4644 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 4645 4646 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 4647 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 4648 SET_NETDEV_DEV(dev, &pdev->dev); 4649 4650 err = mvpp2_port_init(port); 4651 if (err < 0) { 4652 dev_err(&pdev->dev, "failed to init port %d\n", id); 4653 goto err_free_stats; 4654 } 4655 4656 mvpp2_port_periodic_xon_disable(port); 4657 4658 mvpp2_port_reset(port); 4659 4660 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 4661 if (!port->pcpu) { 4662 err = -ENOMEM; 4663 goto err_free_txq_pcpu; 4664 } 4665 4666 if (!port->has_tx_irqs) { 4667 for_each_present_cpu(cpu) { 4668 port_pcpu = per_cpu_ptr(port->pcpu, cpu); 4669 4670 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 4671 HRTIMER_MODE_REL_PINNED); 4672 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 4673 port_pcpu->timer_scheduled = false; 4674 4675 tasklet_init(&port_pcpu->tx_done_tasklet, 4676 mvpp2_tx_proc_cb, 4677 (unsigned long)dev); 4678 } 4679 } 4680 4681 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4682 NETIF_F_TSO; 4683 dev->features = features | NETIF_F_RXCSUM; 4684 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 4685 NETIF_F_HW_VLAN_CTAG_FILTER; 4686 4687 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 4688 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4689 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4690 } 4691 4692 dev->vlan_features |= features; 4693 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 4694 dev->priv_flags |= IFF_UNICAST_FLT; 4695 4696 /* MTU range: 68 - 9704 */ 4697 dev->min_mtu = ETH_MIN_MTU; 4698 /* 9704 == 9728 - 20 and rounding to 8 */ 4699 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 4700 4701 /* Phylink isn't used w/ ACPI as of now */ 4702 if (port_node) { 4703 phylink = phylink_create(dev, port_fwnode, phy_mode, 4704 &mvpp2_phylink_ops); 4705 if (IS_ERR(phylink)) { 4706 err = PTR_ERR(phylink); 4707 goto err_free_port_pcpu; 4708 } 4709 port->phylink = phylink; 4710 } else { 4711 port->phylink = NULL; 4712 } 4713 4714 err = register_netdev(dev); 4715 if (err < 0) { 4716 dev_err(&pdev->dev, "failed to register netdev\n"); 4717 goto err_phylink; 4718 } 4719 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 4720 4721 priv->port_list[priv->port_count++] = port; 4722 4723 return 0; 4724 4725 err_phylink: 4726 if (port->phylink) 4727 phylink_destroy(port->phylink); 4728 err_free_port_pcpu: 4729 free_percpu(port->pcpu); 4730 err_free_txq_pcpu: 4731 for (i = 0; i < port->ntxqs; i++) 4732 free_percpu(port->txqs[i]->pcpu); 4733 err_free_stats: 4734 free_percpu(port->stats); 4735 err_free_irq: 4736 if (port->link_irq) 4737 irq_dispose_mapping(port->link_irq); 4738 err_deinit_qvecs: 4739 mvpp2_queue_vectors_deinit(port); 4740 err_free_netdev: 4741 free_netdev(dev); 4742 return err; 4743 } 4744 4745 /* Ports removal routine */ 4746 static void mvpp2_port_remove(struct mvpp2_port *port) 4747 { 4748 int i; 4749 4750 unregister_netdev(port->dev); 4751 if (port->phylink) 4752 phylink_destroy(port->phylink); 4753 free_percpu(port->pcpu); 4754 free_percpu(port->stats); 4755 for (i = 0; i < port->ntxqs; i++) 4756 free_percpu(port->txqs[i]->pcpu); 4757 mvpp2_queue_vectors_deinit(port); 4758 if (port->link_irq) 4759 irq_dispose_mapping(port->link_irq); 4760 free_netdev(port->dev); 4761 } 4762 4763 /* Initialize decoding windows */ 4764 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 4765 struct mvpp2 *priv) 4766 { 4767 u32 win_enable; 4768 int i; 4769 4770 for (i = 0; i < 6; i++) { 4771 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 4772 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 4773 4774 if (i < 4) 4775 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 4776 } 4777 4778 win_enable = 0; 4779 4780 for (i = 0; i < dram->num_cs; i++) { 4781 const struct mbus_dram_window *cs = dram->cs + i; 4782 4783 mvpp2_write(priv, MVPP2_WIN_BASE(i), 4784 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 4785 dram->mbus_dram_target_id); 4786 4787 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 4788 (cs->size - 1) & 0xffff0000); 4789 4790 win_enable |= (1 << i); 4791 } 4792 4793 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 4794 } 4795 4796 /* Initialize Rx FIFO's */ 4797 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 4798 { 4799 int port; 4800 4801 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 4802 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 4803 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 4804 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 4805 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 4806 } 4807 4808 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 4809 MVPP2_RX_FIFO_PORT_MIN_PKT); 4810 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 4811 } 4812 4813 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 4814 { 4815 int port; 4816 4817 /* The FIFO size parameters are set depending on the maximum speed a 4818 * given port can handle: 4819 * - Port 0: 10Gbps 4820 * - Port 1: 2.5Gbps 4821 * - Ports 2 and 3: 1Gbps 4822 */ 4823 4824 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 4825 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 4826 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 4827 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 4828 4829 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 4830 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 4831 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 4832 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 4833 4834 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 4835 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 4836 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 4837 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 4838 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 4839 } 4840 4841 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 4842 MVPP2_RX_FIFO_PORT_MIN_PKT); 4843 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 4844 } 4845 4846 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 4847 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 4848 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 4849 */ 4850 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 4851 { 4852 int port, size, thrs; 4853 4854 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 4855 if (port == 0) { 4856 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 4857 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 4858 } else { 4859 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 4860 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 4861 } 4862 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 4863 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 4864 } 4865 } 4866 4867 static void mvpp2_axi_init(struct mvpp2 *priv) 4868 { 4869 u32 val, rdval, wrval; 4870 4871 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 4872 4873 /* AXI Bridge Configuration */ 4874 4875 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 4876 << MVPP22_AXI_ATTR_CACHE_OFFS; 4877 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4878 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 4879 4880 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 4881 << MVPP22_AXI_ATTR_CACHE_OFFS; 4882 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4883 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 4884 4885 /* BM */ 4886 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 4887 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 4888 4889 /* Descriptors */ 4890 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 4891 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 4892 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 4893 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 4894 4895 /* Buffer Data */ 4896 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 4897 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 4898 4899 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 4900 << MVPP22_AXI_CODE_CACHE_OFFS; 4901 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 4902 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4903 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 4904 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 4905 4906 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 4907 << MVPP22_AXI_CODE_CACHE_OFFS; 4908 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4909 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4910 4911 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 4912 4913 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 4914 << MVPP22_AXI_CODE_CACHE_OFFS; 4915 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4916 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4917 4918 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 4919 } 4920 4921 /* Initialize network controller common part HW */ 4922 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 4923 { 4924 const struct mbus_dram_target_info *dram_target_info; 4925 int err, i; 4926 u32 val; 4927 4928 /* MBUS windows configuration */ 4929 dram_target_info = mv_mbus_dram_info(); 4930 if (dram_target_info) 4931 mvpp2_conf_mbus_windows(dram_target_info, priv); 4932 4933 if (priv->hw_version == MVPP22) 4934 mvpp2_axi_init(priv); 4935 4936 /* Disable HW PHY polling */ 4937 if (priv->hw_version == MVPP21) { 4938 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 4939 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 4940 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 4941 } else { 4942 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 4943 val &= ~MVPP22_SMI_POLLING_EN; 4944 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 4945 } 4946 4947 /* Allocate and initialize aggregated TXQs */ 4948 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), 4949 sizeof(*priv->aggr_txqs), 4950 GFP_KERNEL); 4951 if (!priv->aggr_txqs) 4952 return -ENOMEM; 4953 4954 for_each_present_cpu(i) { 4955 priv->aggr_txqs[i].id = i; 4956 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 4957 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 4958 if (err < 0) 4959 return err; 4960 } 4961 4962 /* Fifo Init */ 4963 if (priv->hw_version == MVPP21) { 4964 mvpp2_rx_fifo_init(priv); 4965 } else { 4966 mvpp22_rx_fifo_init(priv); 4967 mvpp22_tx_fifo_init(priv); 4968 } 4969 4970 if (priv->hw_version == MVPP21) 4971 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 4972 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 4973 4974 /* Allow cache snoop when transmiting packets */ 4975 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 4976 4977 /* Buffer Manager initialization */ 4978 err = mvpp2_bm_init(pdev, priv); 4979 if (err < 0) 4980 return err; 4981 4982 /* Parser default initialization */ 4983 err = mvpp2_prs_default_init(pdev, priv); 4984 if (err < 0) 4985 return err; 4986 4987 /* Classifier default initialization */ 4988 mvpp2_cls_init(priv); 4989 4990 return 0; 4991 } 4992 4993 static int mvpp2_probe(struct platform_device *pdev) 4994 { 4995 const struct acpi_device_id *acpi_id; 4996 struct fwnode_handle *fwnode = pdev->dev.fwnode; 4997 struct fwnode_handle *port_fwnode; 4998 struct mvpp2 *priv; 4999 struct resource *res; 5000 void __iomem *base; 5001 int i; 5002 int err; 5003 5004 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5005 if (!priv) 5006 return -ENOMEM; 5007 5008 if (has_acpi_companion(&pdev->dev)) { 5009 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5010 &pdev->dev); 5011 priv->hw_version = (unsigned long)acpi_id->driver_data; 5012 } else { 5013 priv->hw_version = 5014 (unsigned long)of_device_get_match_data(&pdev->dev); 5015 } 5016 5017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5018 base = devm_ioremap_resource(&pdev->dev, res); 5019 if (IS_ERR(base)) 5020 return PTR_ERR(base); 5021 5022 if (priv->hw_version == MVPP21) { 5023 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5024 priv->lms_base = devm_ioremap_resource(&pdev->dev, res); 5025 if (IS_ERR(priv->lms_base)) 5026 return PTR_ERR(priv->lms_base); 5027 } else { 5028 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5029 if (has_acpi_companion(&pdev->dev)) { 5030 /* In case the MDIO memory region is declared in 5031 * the ACPI, it can already appear as 'in-use' 5032 * in the OS. Because it is overlapped by second 5033 * region of the network controller, make 5034 * sure it is released, before requesting it again. 5035 * The care is taken by mvpp2 driver to avoid 5036 * concurrent access to this memory region. 5037 */ 5038 release_resource(res); 5039 } 5040 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5041 if (IS_ERR(priv->iface_base)) 5042 return PTR_ERR(priv->iface_base); 5043 } 5044 5045 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5046 priv->sysctrl_base = 5047 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5048 "marvell,system-controller"); 5049 if (IS_ERR(priv->sysctrl_base)) 5050 /* The system controller regmap is optional for dt 5051 * compatibility reasons. When not provided, the 5052 * configuration of the GoP relies on the 5053 * firmware/bootloader. 5054 */ 5055 priv->sysctrl_base = NULL; 5056 } 5057 5058 mvpp2_setup_bm_pool(); 5059 5060 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5061 u32 addr_space_sz; 5062 5063 addr_space_sz = (priv->hw_version == MVPP21 ? 5064 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5065 priv->swth_base[i] = base + i * addr_space_sz; 5066 } 5067 5068 if (priv->hw_version == MVPP21) 5069 priv->max_port_rxqs = 8; 5070 else 5071 priv->max_port_rxqs = 32; 5072 5073 if (dev_of_node(&pdev->dev)) { 5074 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5075 if (IS_ERR(priv->pp_clk)) 5076 return PTR_ERR(priv->pp_clk); 5077 err = clk_prepare_enable(priv->pp_clk); 5078 if (err < 0) 5079 return err; 5080 5081 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5082 if (IS_ERR(priv->gop_clk)) { 5083 err = PTR_ERR(priv->gop_clk); 5084 goto err_pp_clk; 5085 } 5086 err = clk_prepare_enable(priv->gop_clk); 5087 if (err < 0) 5088 goto err_pp_clk; 5089 5090 if (priv->hw_version == MVPP22) { 5091 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5092 if (IS_ERR(priv->mg_clk)) { 5093 err = PTR_ERR(priv->mg_clk); 5094 goto err_gop_clk; 5095 } 5096 5097 err = clk_prepare_enable(priv->mg_clk); 5098 if (err < 0) 5099 goto err_gop_clk; 5100 5101 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5102 if (IS_ERR(priv->mg_core_clk)) { 5103 priv->mg_core_clk = NULL; 5104 } else { 5105 err = clk_prepare_enable(priv->mg_core_clk); 5106 if (err < 0) 5107 goto err_mg_clk; 5108 } 5109 } 5110 5111 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5112 if (IS_ERR(priv->axi_clk)) { 5113 err = PTR_ERR(priv->axi_clk); 5114 if (err == -EPROBE_DEFER) 5115 goto err_mg_core_clk; 5116 priv->axi_clk = NULL; 5117 } else { 5118 err = clk_prepare_enable(priv->axi_clk); 5119 if (err < 0) 5120 goto err_mg_core_clk; 5121 } 5122 5123 /* Get system's tclk rate */ 5124 priv->tclk = clk_get_rate(priv->pp_clk); 5125 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5126 &priv->tclk)) { 5127 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5128 return -EINVAL; 5129 } 5130 5131 if (priv->hw_version == MVPP22) { 5132 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5133 if (err) 5134 goto err_axi_clk; 5135 /* Sadly, the BM pools all share the same register to 5136 * store the high 32 bits of their address. So they 5137 * must all have the same high 32 bits, which forces 5138 * us to restrict coherent memory to DMA_BIT_MASK(32). 5139 */ 5140 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5141 if (err) 5142 goto err_axi_clk; 5143 } 5144 5145 /* Initialize network controller */ 5146 err = mvpp2_init(pdev, priv); 5147 if (err < 0) { 5148 dev_err(&pdev->dev, "failed to initialize controller\n"); 5149 goto err_axi_clk; 5150 } 5151 5152 /* Initialize ports */ 5153 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5154 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5155 if (err < 0) 5156 goto err_port_probe; 5157 } 5158 5159 if (priv->port_count == 0) { 5160 dev_err(&pdev->dev, "no ports enabled\n"); 5161 err = -ENODEV; 5162 goto err_axi_clk; 5163 } 5164 5165 /* Statistics must be gathered regularly because some of them (like 5166 * packets counters) are 32-bit registers and could overflow quite 5167 * quickly. For instance, a 10Gb link used at full bandwidth with the 5168 * smallest packets (64B) will overflow a 32-bit counter in less than 5169 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5170 */ 5171 snprintf(priv->queue_name, sizeof(priv->queue_name), 5172 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5173 priv->port_count > 1 ? "+" : ""); 5174 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5175 if (!priv->stats_queue) { 5176 err = -ENOMEM; 5177 goto err_port_probe; 5178 } 5179 5180 platform_set_drvdata(pdev, priv); 5181 return 0; 5182 5183 err_port_probe: 5184 i = 0; 5185 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5186 if (priv->port_list[i]) 5187 mvpp2_port_remove(priv->port_list[i]); 5188 i++; 5189 } 5190 err_axi_clk: 5191 clk_disable_unprepare(priv->axi_clk); 5192 5193 err_mg_core_clk: 5194 if (priv->hw_version == MVPP22) 5195 clk_disable_unprepare(priv->mg_core_clk); 5196 err_mg_clk: 5197 if (priv->hw_version == MVPP22) 5198 clk_disable_unprepare(priv->mg_clk); 5199 err_gop_clk: 5200 clk_disable_unprepare(priv->gop_clk); 5201 err_pp_clk: 5202 clk_disable_unprepare(priv->pp_clk); 5203 return err; 5204 } 5205 5206 static int mvpp2_remove(struct platform_device *pdev) 5207 { 5208 struct mvpp2 *priv = platform_get_drvdata(pdev); 5209 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5210 struct fwnode_handle *port_fwnode; 5211 int i = 0; 5212 5213 flush_workqueue(priv->stats_queue); 5214 destroy_workqueue(priv->stats_queue); 5215 5216 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5217 if (priv->port_list[i]) { 5218 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5219 mvpp2_port_remove(priv->port_list[i]); 5220 } 5221 i++; 5222 } 5223 5224 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5225 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5226 5227 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5228 } 5229 5230 for_each_present_cpu(i) { 5231 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5232 5233 dma_free_coherent(&pdev->dev, 5234 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5235 aggr_txq->descs, 5236 aggr_txq->descs_dma); 5237 } 5238 5239 if (is_acpi_node(port_fwnode)) 5240 return 0; 5241 5242 clk_disable_unprepare(priv->axi_clk); 5243 clk_disable_unprepare(priv->mg_core_clk); 5244 clk_disable_unprepare(priv->mg_clk); 5245 clk_disable_unprepare(priv->pp_clk); 5246 clk_disable_unprepare(priv->gop_clk); 5247 5248 return 0; 5249 } 5250 5251 static const struct of_device_id mvpp2_match[] = { 5252 { 5253 .compatible = "marvell,armada-375-pp2", 5254 .data = (void *)MVPP21, 5255 }, 5256 { 5257 .compatible = "marvell,armada-7k-pp22", 5258 .data = (void *)MVPP22, 5259 }, 5260 { } 5261 }; 5262 MODULE_DEVICE_TABLE(of, mvpp2_match); 5263 5264 static const struct acpi_device_id mvpp2_acpi_match[] = { 5265 { "MRVL0110", MVPP22 }, 5266 { }, 5267 }; 5268 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5269 5270 static struct platform_driver mvpp2_driver = { 5271 .probe = mvpp2_probe, 5272 .remove = mvpp2_remove, 5273 .driver = { 5274 .name = MVPP2_DRIVER_NAME, 5275 .of_match_table = mvpp2_match, 5276 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5277 }, 5278 }; 5279 5280 module_platform_driver(mvpp2_driver); 5281 5282 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5283 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5284 MODULE_LICENSE("GPL v2"); 5285