1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RSS and Classifier helpers for Marvell PPv2 Network Controller 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include "mvpp2.h" 11 #include "mvpp2_cls.h" 12 #include "mvpp2_prs.h" 13 14 #define MVPP2_DEF_FLOW(_type, _id, _opts, _ri, _ri_mask) \ 15 { \ 16 .flow_type = _type, \ 17 .flow_id = _id, \ 18 .supported_hash_opts = _opts, \ 19 .prs_ri = { \ 20 .ri = _ri, \ 21 .ri_mask = _ri_mask \ 22 } \ 23 } 24 25 static const struct mvpp2_cls_flow cls_flows[MVPP2_N_PRS_FLOWS] = { 26 /* TCP over IPv4 flows, Not fragmented, no vlan tag */ 27 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_UNTAG, 28 MVPP22_CLS_HEK_IP4_5T, 29 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 | 30 MVPP2_PRS_RI_L4_TCP, 31 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 32 33 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_UNTAG, 34 MVPP22_CLS_HEK_IP4_5T, 35 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT | 36 MVPP2_PRS_RI_L4_TCP, 37 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 38 39 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_UNTAG, 40 MVPP22_CLS_HEK_IP4_5T, 41 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER | 42 MVPP2_PRS_RI_L4_TCP, 43 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 44 45 /* TCP over IPv4 flows, Not fragmented, with vlan tag */ 46 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_TAG, 47 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 48 MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_TCP, 49 MVPP2_PRS_IP_MASK), 50 51 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_TAG, 52 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 53 MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_TCP, 54 MVPP2_PRS_IP_MASK), 55 56 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_NF_TAG, 57 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 58 MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_TCP, 59 MVPP2_PRS_IP_MASK), 60 61 /* TCP over IPv4 flows, fragmented, no vlan tag */ 62 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG, 63 MVPP22_CLS_HEK_IP4_2T, 64 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 | 65 MVPP2_PRS_RI_L4_TCP, 66 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 67 68 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG, 69 MVPP22_CLS_HEK_IP4_2T, 70 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT | 71 MVPP2_PRS_RI_L4_TCP, 72 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 73 74 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG, 75 MVPP22_CLS_HEK_IP4_2T, 76 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER | 77 MVPP2_PRS_RI_L4_TCP, 78 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 79 80 /* TCP over IPv4 flows, fragmented, with vlan tag */ 81 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG, 82 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 83 MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_TCP, 84 MVPP2_PRS_IP_MASK), 85 86 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG, 87 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 88 MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_TCP, 89 MVPP2_PRS_IP_MASK), 90 91 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG, 92 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 93 MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_TCP, 94 MVPP2_PRS_IP_MASK), 95 96 /* UDP over IPv4 flows, Not fragmented, no vlan tag */ 97 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_UNTAG, 98 MVPP22_CLS_HEK_IP4_5T, 99 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 | 100 MVPP2_PRS_RI_L4_UDP, 101 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 102 103 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_UNTAG, 104 MVPP22_CLS_HEK_IP4_5T, 105 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT | 106 MVPP2_PRS_RI_L4_UDP, 107 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 108 109 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_UNTAG, 110 MVPP22_CLS_HEK_IP4_5T, 111 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER | 112 MVPP2_PRS_RI_L4_UDP, 113 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 114 115 /* UDP over IPv4 flows, Not fragmented, with vlan tag */ 116 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_TAG, 117 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 118 MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_UDP, 119 MVPP2_PRS_IP_MASK), 120 121 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_TAG, 122 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 123 MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_UDP, 124 MVPP2_PRS_IP_MASK), 125 126 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_NF_TAG, 127 MVPP22_CLS_HEK_IP4_5T | MVPP22_CLS_HEK_TAGGED, 128 MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_UDP, 129 MVPP2_PRS_IP_MASK), 130 131 /* UDP over IPv4 flows, fragmented, no vlan tag */ 132 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG, 133 MVPP22_CLS_HEK_IP4_2T, 134 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 | 135 MVPP2_PRS_RI_L4_UDP, 136 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 137 138 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG, 139 MVPP22_CLS_HEK_IP4_2T, 140 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT | 141 MVPP2_PRS_RI_L4_UDP, 142 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 143 144 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG, 145 MVPP22_CLS_HEK_IP4_2T, 146 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER | 147 MVPP2_PRS_RI_L4_UDP, 148 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 149 150 /* UDP over IPv4 flows, fragmented, with vlan tag */ 151 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG, 152 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 153 MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_UDP, 154 MVPP2_PRS_IP_MASK), 155 156 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG, 157 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 158 MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_UDP, 159 MVPP2_PRS_IP_MASK), 160 161 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG, 162 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 163 MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_UDP, 164 MVPP2_PRS_IP_MASK), 165 166 /* TCP over IPv6 flows, not fragmented, no vlan tag */ 167 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_NF_UNTAG, 168 MVPP22_CLS_HEK_IP6_5T, 169 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6 | 170 MVPP2_PRS_RI_L4_TCP, 171 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 172 173 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_NF_UNTAG, 174 MVPP22_CLS_HEK_IP6_5T, 175 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6_EXT | 176 MVPP2_PRS_RI_L4_TCP, 177 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 178 179 /* TCP over IPv6 flows, not fragmented, with vlan tag */ 180 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_NF_TAG, 181 MVPP22_CLS_HEK_IP6_5T | MVPP22_CLS_HEK_TAGGED, 182 MVPP2_PRS_RI_L3_IP6 | MVPP2_PRS_RI_L4_TCP, 183 MVPP2_PRS_IP_MASK), 184 185 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_NF_TAG, 186 MVPP22_CLS_HEK_IP6_5T | MVPP22_CLS_HEK_TAGGED, 187 MVPP2_PRS_RI_L3_IP6_EXT | MVPP2_PRS_RI_L4_TCP, 188 MVPP2_PRS_IP_MASK), 189 190 /* TCP over IPv6 flows, fragmented, no vlan tag */ 191 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_FRAG_UNTAG, 192 MVPP22_CLS_HEK_IP6_2T, 193 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6 | 194 MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_TCP, 195 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 196 197 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_FRAG_UNTAG, 198 MVPP22_CLS_HEK_IP6_2T, 199 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6_EXT | 200 MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_TCP, 201 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 202 203 /* TCP over IPv6 flows, fragmented, with vlan tag */ 204 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_FRAG_TAG, 205 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 206 MVPP2_PRS_RI_L3_IP6 | MVPP2_PRS_RI_IP_FRAG_TRUE | 207 MVPP2_PRS_RI_L4_TCP, 208 MVPP2_PRS_IP_MASK), 209 210 MVPP2_DEF_FLOW(MVPP22_FLOW_TCP6, MVPP2_FL_IP6_TCP_FRAG_TAG, 211 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 212 MVPP2_PRS_RI_L3_IP6_EXT | MVPP2_PRS_RI_IP_FRAG_TRUE | 213 MVPP2_PRS_RI_L4_TCP, 214 MVPP2_PRS_IP_MASK), 215 216 /* UDP over IPv6 flows, not fragmented, no vlan tag */ 217 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_NF_UNTAG, 218 MVPP22_CLS_HEK_IP6_5T, 219 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6 | 220 MVPP2_PRS_RI_L4_UDP, 221 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 222 223 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_NF_UNTAG, 224 MVPP22_CLS_HEK_IP6_5T, 225 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6_EXT | 226 MVPP2_PRS_RI_L4_UDP, 227 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 228 229 /* UDP over IPv6 flows, not fragmented, with vlan tag */ 230 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_NF_TAG, 231 MVPP22_CLS_HEK_IP6_5T | MVPP22_CLS_HEK_TAGGED, 232 MVPP2_PRS_RI_L3_IP6 | MVPP2_PRS_RI_L4_UDP, 233 MVPP2_PRS_IP_MASK), 234 235 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_NF_TAG, 236 MVPP22_CLS_HEK_IP6_5T | MVPP22_CLS_HEK_TAGGED, 237 MVPP2_PRS_RI_L3_IP6_EXT | MVPP2_PRS_RI_L4_UDP, 238 MVPP2_PRS_IP_MASK), 239 240 /* UDP over IPv6 flows, fragmented, no vlan tag */ 241 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_FRAG_UNTAG, 242 MVPP22_CLS_HEK_IP6_2T, 243 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6 | 244 MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_UDP, 245 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 246 247 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_FRAG_UNTAG, 248 MVPP22_CLS_HEK_IP6_2T, 249 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6_EXT | 250 MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_UDP, 251 MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK), 252 253 /* UDP over IPv6 flows, fragmented, with vlan tag */ 254 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_FRAG_TAG, 255 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 256 MVPP2_PRS_RI_L3_IP6 | MVPP2_PRS_RI_IP_FRAG_TRUE | 257 MVPP2_PRS_RI_L4_UDP, 258 MVPP2_PRS_IP_MASK), 259 260 MVPP2_DEF_FLOW(MVPP22_FLOW_UDP6, MVPP2_FL_IP6_UDP_FRAG_TAG, 261 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 262 MVPP2_PRS_RI_L3_IP6_EXT | MVPP2_PRS_RI_IP_FRAG_TRUE | 263 MVPP2_PRS_RI_L4_UDP, 264 MVPP2_PRS_IP_MASK), 265 266 /* IPv4 flows, no vlan tag */ 267 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_UNTAG, 268 MVPP22_CLS_HEK_IP4_2T, 269 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4, 270 MVPP2_PRS_RI_VLAN_MASK | MVPP2_PRS_RI_L3_PROTO_MASK), 271 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_UNTAG, 272 MVPP22_CLS_HEK_IP4_2T, 273 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT, 274 MVPP2_PRS_RI_VLAN_MASK | MVPP2_PRS_RI_L3_PROTO_MASK), 275 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_UNTAG, 276 MVPP22_CLS_HEK_IP4_2T, 277 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER, 278 MVPP2_PRS_RI_VLAN_MASK | MVPP2_PRS_RI_L3_PROTO_MASK), 279 280 /* IPv4 flows, with vlan tag */ 281 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_TAG, 282 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 283 MVPP2_PRS_RI_L3_IP4, 284 MVPP2_PRS_RI_L3_PROTO_MASK), 285 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_TAG, 286 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 287 MVPP2_PRS_RI_L3_IP4_OPT, 288 MVPP2_PRS_RI_L3_PROTO_MASK), 289 MVPP2_DEF_FLOW(MVPP22_FLOW_IP4, MVPP2_FL_IP4_TAG, 290 MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED, 291 MVPP2_PRS_RI_L3_IP4_OTHER, 292 MVPP2_PRS_RI_L3_PROTO_MASK), 293 294 /* IPv6 flows, no vlan tag */ 295 MVPP2_DEF_FLOW(MVPP22_FLOW_IP6, MVPP2_FL_IP6_UNTAG, 296 MVPP22_CLS_HEK_IP6_2T, 297 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6, 298 MVPP2_PRS_RI_VLAN_MASK | MVPP2_PRS_RI_L3_PROTO_MASK), 299 MVPP2_DEF_FLOW(MVPP22_FLOW_IP6, MVPP2_FL_IP6_UNTAG, 300 MVPP22_CLS_HEK_IP6_2T, 301 MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP6, 302 MVPP2_PRS_RI_VLAN_MASK | MVPP2_PRS_RI_L3_PROTO_MASK), 303 304 /* IPv6 flows, with vlan tag */ 305 MVPP2_DEF_FLOW(MVPP22_FLOW_IP6, MVPP2_FL_IP6_TAG, 306 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 307 MVPP2_PRS_RI_L3_IP6, 308 MVPP2_PRS_RI_L3_PROTO_MASK), 309 MVPP2_DEF_FLOW(MVPP22_FLOW_IP6, MVPP2_FL_IP6_TAG, 310 MVPP22_CLS_HEK_IP6_2T | MVPP22_CLS_HEK_TAGGED, 311 MVPP2_PRS_RI_L3_IP6, 312 MVPP2_PRS_RI_L3_PROTO_MASK), 313 314 /* Non IP flow, no vlan tag */ 315 MVPP2_DEF_FLOW(MVPP22_FLOW_ETHERNET, MVPP2_FL_NON_IP_UNTAG, 316 0, 317 MVPP2_PRS_RI_VLAN_NONE, 318 MVPP2_PRS_RI_VLAN_MASK), 319 /* Non IP flow, with vlan tag */ 320 MVPP2_DEF_FLOW(MVPP22_FLOW_ETHERNET, MVPP2_FL_NON_IP_TAG, 321 MVPP22_CLS_HEK_OPT_VLAN, 322 0, 0), 323 }; 324 325 u32 mvpp2_cls_flow_hits(struct mvpp2 *priv, int index) 326 { 327 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 328 329 return mvpp2_read(priv, MVPP2_CLS_FLOW_TBL_HIT_CTR); 330 } 331 332 void mvpp2_cls_flow_read(struct mvpp2 *priv, int index, 333 struct mvpp2_cls_flow_entry *fe) 334 { 335 fe->index = index; 336 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, index); 337 fe->data[0] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL0_REG); 338 fe->data[1] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL1_REG); 339 fe->data[2] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL2_REG); 340 } 341 342 /* Update classification flow table registers */ 343 static void mvpp2_cls_flow_write(struct mvpp2 *priv, 344 struct mvpp2_cls_flow_entry *fe) 345 { 346 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); 347 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); 348 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); 349 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); 350 } 351 352 u32 mvpp2_cls_lookup_hits(struct mvpp2 *priv, int index) 353 { 354 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 355 356 return mvpp2_read(priv, MVPP2_CLS_DEC_TBL_HIT_CTR); 357 } 358 359 void mvpp2_cls_lookup_read(struct mvpp2 *priv, int lkpid, int way, 360 struct mvpp2_cls_lookup_entry *le) 361 { 362 u32 val; 363 364 val = (way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | lkpid; 365 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); 366 le->way = way; 367 le->lkpid = lkpid; 368 le->data = mvpp2_read(priv, MVPP2_CLS_LKP_TBL_REG); 369 } 370 371 /* Update classification lookup table register */ 372 static void mvpp2_cls_lookup_write(struct mvpp2 *priv, 373 struct mvpp2_cls_lookup_entry *le) 374 { 375 u32 val; 376 377 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; 378 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); 379 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); 380 } 381 382 /* Operations on flow entry */ 383 static int mvpp2_cls_flow_hek_num_get(struct mvpp2_cls_flow_entry *fe) 384 { 385 return fe->data[1] & MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK; 386 } 387 388 static void mvpp2_cls_flow_hek_num_set(struct mvpp2_cls_flow_entry *fe, 389 int num_of_fields) 390 { 391 fe->data[1] &= ~MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK; 392 fe->data[1] |= MVPP2_CLS_FLOW_TBL1_N_FIELDS(num_of_fields); 393 } 394 395 static int mvpp2_cls_flow_hek_get(struct mvpp2_cls_flow_entry *fe, 396 int field_index) 397 { 398 return (fe->data[2] >> MVPP2_CLS_FLOW_TBL2_FLD_OFFS(field_index)) & 399 MVPP2_CLS_FLOW_TBL2_FLD_MASK; 400 } 401 402 static void mvpp2_cls_flow_hek_set(struct mvpp2_cls_flow_entry *fe, 403 int field_index, int field_id) 404 { 405 fe->data[2] &= ~MVPP2_CLS_FLOW_TBL2_FLD(field_index, 406 MVPP2_CLS_FLOW_TBL2_FLD_MASK); 407 fe->data[2] |= MVPP2_CLS_FLOW_TBL2_FLD(field_index, field_id); 408 } 409 410 static void mvpp2_cls_flow_eng_set(struct mvpp2_cls_flow_entry *fe, 411 int engine) 412 { 413 fe->data[0] &= ~MVPP2_CLS_FLOW_TBL0_ENG(MVPP2_CLS_FLOW_TBL0_ENG_MASK); 414 fe->data[0] |= MVPP2_CLS_FLOW_TBL0_ENG(engine); 415 } 416 417 int mvpp2_cls_flow_eng_get(struct mvpp2_cls_flow_entry *fe) 418 { 419 return (fe->data[0] >> MVPP2_CLS_FLOW_TBL0_OFFS) & 420 MVPP2_CLS_FLOW_TBL0_ENG_MASK; 421 } 422 423 static void mvpp2_cls_flow_port_id_sel(struct mvpp2_cls_flow_entry *fe, 424 bool from_packet) 425 { 426 if (from_packet) 427 fe->data[0] |= MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL; 428 else 429 fe->data[0] &= ~MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL; 430 } 431 432 static void mvpp2_cls_flow_last_set(struct mvpp2_cls_flow_entry *fe, 433 bool is_last) 434 { 435 fe->data[0] &= ~MVPP2_CLS_FLOW_TBL0_LAST; 436 fe->data[0] |= !!is_last; 437 } 438 439 static void mvpp2_cls_flow_pri_set(struct mvpp2_cls_flow_entry *fe, int prio) 440 { 441 fe->data[1] &= ~MVPP2_CLS_FLOW_TBL1_PRIO(MVPP2_CLS_FLOW_TBL1_PRIO_MASK); 442 fe->data[1] |= MVPP2_CLS_FLOW_TBL1_PRIO(prio); 443 } 444 445 static void mvpp2_cls_flow_port_add(struct mvpp2_cls_flow_entry *fe, 446 u32 port) 447 { 448 fe->data[0] |= MVPP2_CLS_FLOW_TBL0_PORT_ID(port); 449 } 450 451 static void mvpp2_cls_flow_port_remove(struct mvpp2_cls_flow_entry *fe, 452 u32 port) 453 { 454 fe->data[0] &= ~MVPP2_CLS_FLOW_TBL0_PORT_ID(port); 455 } 456 457 static void mvpp2_cls_flow_lu_type_set(struct mvpp2_cls_flow_entry *fe, 458 u8 lu_type) 459 { 460 fe->data[1] &= ~MVPP2_CLS_FLOW_TBL1_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK); 461 fe->data[1] |= MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu_type); 462 } 463 464 /* Initialize the parser entry for the given flow */ 465 static void mvpp2_cls_flow_prs_init(struct mvpp2 *priv, 466 const struct mvpp2_cls_flow *flow) 467 { 468 mvpp2_prs_add_flow(priv, flow->flow_id, flow->prs_ri.ri, 469 flow->prs_ri.ri_mask); 470 } 471 472 /* Initialize the Lookup Id table entry for the given flow */ 473 static void mvpp2_cls_flow_lkp_init(struct mvpp2 *priv, 474 const struct mvpp2_cls_flow *flow) 475 { 476 struct mvpp2_cls_lookup_entry le; 477 478 le.way = 0; 479 le.lkpid = flow->flow_id; 480 481 /* The default RxQ for this port is set in the C2 lookup */ 482 le.data = 0; 483 484 /* We point on the first lookup in the sequence for the flow, that is 485 * the C2 lookup. 486 */ 487 le.data |= MVPP2_CLS_LKP_FLOW_PTR(MVPP2_CLS_FLT_FIRST(flow->flow_id)); 488 489 /* CLS is always enabled, RSS is enabled/disabled in C2 lookup */ 490 le.data |= MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; 491 492 mvpp2_cls_lookup_write(priv, &le); 493 } 494 495 static void mvpp2_cls_c2_write(struct mvpp2 *priv, 496 struct mvpp2_cls_c2_entry *c2) 497 { 498 u32 val; 499 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index); 500 501 val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV); 502 if (c2->valid) 503 val &= ~MVPP22_CLS_C2_TCAM_INV_BIT; 504 else 505 val |= MVPP22_CLS_C2_TCAM_INV_BIT; 506 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_INV, val); 507 508 mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act); 509 510 mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]); 511 mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]); 512 mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]); 513 mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]); 514 515 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]); 516 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]); 517 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]); 518 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]); 519 /* Writing TCAM_DATA4 flushes writes to TCAM_DATA0-4 and INV to HW */ 520 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]); 521 } 522 523 void mvpp2_cls_c2_read(struct mvpp2 *priv, int index, 524 struct mvpp2_cls_c2_entry *c2) 525 { 526 u32 val; 527 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, index); 528 529 c2->index = index; 530 531 c2->tcam[0] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA0); 532 c2->tcam[1] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA1); 533 c2->tcam[2] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA2); 534 c2->tcam[3] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA3); 535 c2->tcam[4] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA4); 536 537 c2->act = mvpp2_read(priv, MVPP22_CLS_C2_ACT); 538 539 c2->attr[0] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR0); 540 c2->attr[1] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR1); 541 c2->attr[2] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR2); 542 c2->attr[3] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR3); 543 544 val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV); 545 c2->valid = !(val & MVPP22_CLS_C2_TCAM_INV_BIT); 546 } 547 548 static int mvpp2_cls_ethtool_flow_to_type(int flow_type) 549 { 550 switch (flow_type & ~(FLOW_EXT | FLOW_MAC_EXT | FLOW_RSS)) { 551 case TCP_V4_FLOW: 552 return MVPP22_FLOW_TCP4; 553 case TCP_V6_FLOW: 554 return MVPP22_FLOW_TCP6; 555 case UDP_V4_FLOW: 556 return MVPP22_FLOW_UDP4; 557 case UDP_V6_FLOW: 558 return MVPP22_FLOW_UDP6; 559 case IPV4_FLOW: 560 return MVPP22_FLOW_IP4; 561 case IPV6_FLOW: 562 return MVPP22_FLOW_IP6; 563 default: 564 return -EOPNOTSUPP; 565 } 566 } 567 568 static int mvpp2_cls_c2_port_flow_index(struct mvpp2_port *port, int loc) 569 { 570 return MVPP22_CLS_C2_RFS_LOC(port->id, loc); 571 } 572 573 /* Initialize the flow table entries for the given flow */ 574 static void mvpp2_cls_flow_init(struct mvpp2 *priv, 575 const struct mvpp2_cls_flow *flow) 576 { 577 struct mvpp2_cls_flow_entry fe; 578 int i, pri = 0; 579 580 /* Assign default values to all entries in the flow */ 581 for (i = MVPP2_CLS_FLT_FIRST(flow->flow_id); 582 i <= MVPP2_CLS_FLT_LAST(flow->flow_id); i++) { 583 memset(&fe, 0, sizeof(fe)); 584 fe.index = i; 585 mvpp2_cls_flow_pri_set(&fe, pri++); 586 587 if (i == MVPP2_CLS_FLT_LAST(flow->flow_id)) 588 mvpp2_cls_flow_last_set(&fe, 1); 589 590 mvpp2_cls_flow_write(priv, &fe); 591 } 592 593 /* RSS config C2 lookup */ 594 mvpp2_cls_flow_read(priv, MVPP2_CLS_FLT_C2_RSS_ENTRY(flow->flow_id), 595 &fe); 596 597 mvpp2_cls_flow_eng_set(&fe, MVPP22_CLS_ENGINE_C2); 598 mvpp2_cls_flow_port_id_sel(&fe, true); 599 mvpp2_cls_flow_lu_type_set(&fe, MVPP22_CLS_LU_TYPE_ALL); 600 601 /* Add all ports */ 602 for (i = 0; i < MVPP2_MAX_PORTS; i++) 603 mvpp2_cls_flow_port_add(&fe, BIT(i)); 604 605 mvpp2_cls_flow_write(priv, &fe); 606 607 /* C3Hx lookups */ 608 for (i = 0; i < MVPP2_MAX_PORTS; i++) { 609 mvpp2_cls_flow_read(priv, 610 MVPP2_CLS_FLT_HASH_ENTRY(i, flow->flow_id), 611 &fe); 612 613 /* Set a default engine. Will be overwritten when setting the 614 * real HEK parameters 615 */ 616 mvpp2_cls_flow_eng_set(&fe, MVPP22_CLS_ENGINE_C3HA); 617 mvpp2_cls_flow_port_id_sel(&fe, true); 618 mvpp2_cls_flow_port_add(&fe, BIT(i)); 619 620 mvpp2_cls_flow_write(priv, &fe); 621 } 622 } 623 624 /* Adds a field to the Header Extracted Key generation parameters*/ 625 static int mvpp2_flow_add_hek_field(struct mvpp2_cls_flow_entry *fe, 626 u32 field_id) 627 { 628 int nb_fields = mvpp2_cls_flow_hek_num_get(fe); 629 630 if (nb_fields == MVPP2_FLOW_N_FIELDS) 631 return -EINVAL; 632 633 mvpp2_cls_flow_hek_set(fe, nb_fields, field_id); 634 635 mvpp2_cls_flow_hek_num_set(fe, nb_fields + 1); 636 637 return 0; 638 } 639 640 static int mvpp2_flow_set_hek_fields(struct mvpp2_cls_flow_entry *fe, 641 unsigned long hash_opts) 642 { 643 u32 field_id; 644 int i; 645 646 /* Clear old fields */ 647 mvpp2_cls_flow_hek_num_set(fe, 0); 648 fe->data[2] = 0; 649 650 for_each_set_bit(i, &hash_opts, MVPP22_CLS_HEK_N_FIELDS) { 651 switch (BIT(i)) { 652 case MVPP22_CLS_HEK_OPT_MAC_DA: 653 field_id = MVPP22_CLS_FIELD_MAC_DA; 654 break; 655 case MVPP22_CLS_HEK_OPT_VLAN: 656 field_id = MVPP22_CLS_FIELD_VLAN; 657 break; 658 case MVPP22_CLS_HEK_OPT_VLAN_PRI: 659 field_id = MVPP22_CLS_FIELD_VLAN_PRI; 660 break; 661 case MVPP22_CLS_HEK_OPT_IP4SA: 662 field_id = MVPP22_CLS_FIELD_IP4SA; 663 break; 664 case MVPP22_CLS_HEK_OPT_IP4DA: 665 field_id = MVPP22_CLS_FIELD_IP4DA; 666 break; 667 case MVPP22_CLS_HEK_OPT_IP6SA: 668 field_id = MVPP22_CLS_FIELD_IP6SA; 669 break; 670 case MVPP22_CLS_HEK_OPT_IP6DA: 671 field_id = MVPP22_CLS_FIELD_IP6DA; 672 break; 673 case MVPP22_CLS_HEK_OPT_L4SIP: 674 field_id = MVPP22_CLS_FIELD_L4SIP; 675 break; 676 case MVPP22_CLS_HEK_OPT_L4DIP: 677 field_id = MVPP22_CLS_FIELD_L4DIP; 678 break; 679 default: 680 return -EINVAL; 681 } 682 if (mvpp2_flow_add_hek_field(fe, field_id)) 683 return -EINVAL; 684 } 685 686 return 0; 687 } 688 689 /* Returns the size, in bits, of the corresponding HEK field */ 690 static int mvpp2_cls_hek_field_size(u32 field) 691 { 692 switch (field) { 693 case MVPP22_CLS_HEK_OPT_MAC_DA: 694 return 48; 695 case MVPP22_CLS_HEK_OPT_VLAN: 696 return 12; 697 case MVPP22_CLS_HEK_OPT_VLAN_PRI: 698 return 3; 699 case MVPP22_CLS_HEK_OPT_IP4SA: 700 case MVPP22_CLS_HEK_OPT_IP4DA: 701 return 32; 702 case MVPP22_CLS_HEK_OPT_IP6SA: 703 case MVPP22_CLS_HEK_OPT_IP6DA: 704 return 128; 705 case MVPP22_CLS_HEK_OPT_L4SIP: 706 case MVPP22_CLS_HEK_OPT_L4DIP: 707 return 16; 708 default: 709 return -1; 710 } 711 } 712 713 const struct mvpp2_cls_flow *mvpp2_cls_flow_get(int flow) 714 { 715 if (flow >= MVPP2_N_PRS_FLOWS) 716 return NULL; 717 718 return &cls_flows[flow]; 719 } 720 721 /* Set the hash generation options for the given traffic flow. 722 * One traffic flow (in the ethtool sense) has multiple classification flows, 723 * to handle specific cases such as fragmentation, or the presence of a 724 * VLAN / DSA Tag. 725 * 726 * Each of these individual flows has different constraints, for example we 727 * can't hash fragmented packets on L4 data (else we would risk having packet 728 * re-ordering), so each classification flows masks the options with their 729 * supported ones. 730 * 731 */ 732 static int mvpp2_port_rss_hash_opts_set(struct mvpp2_port *port, int flow_type, 733 u16 requested_opts) 734 { 735 const struct mvpp2_cls_flow *flow; 736 struct mvpp2_cls_flow_entry fe; 737 int i, engine, flow_index; 738 u16 hash_opts; 739 740 for_each_cls_flow_id_with_type(i, flow_type) { 741 flow = mvpp2_cls_flow_get(i); 742 if (!flow) 743 return -EINVAL; 744 745 flow_index = MVPP2_CLS_FLT_HASH_ENTRY(port->id, flow->flow_id); 746 747 mvpp2_cls_flow_read(port->priv, flow_index, &fe); 748 749 hash_opts = flow->supported_hash_opts & requested_opts; 750 751 /* Use C3HB engine to access L4 infos. This adds L4 infos to the 752 * hash parameters 753 */ 754 if (hash_opts & MVPP22_CLS_HEK_L4_OPTS) 755 engine = MVPP22_CLS_ENGINE_C3HB; 756 else 757 engine = MVPP22_CLS_ENGINE_C3HA; 758 759 if (mvpp2_flow_set_hek_fields(&fe, hash_opts)) 760 return -EINVAL; 761 762 mvpp2_cls_flow_eng_set(&fe, engine); 763 764 mvpp2_cls_flow_write(port->priv, &fe); 765 } 766 767 return 0; 768 } 769 770 u16 mvpp2_flow_get_hek_fields(struct mvpp2_cls_flow_entry *fe) 771 { 772 u16 hash_opts = 0; 773 int n_fields, i, field; 774 775 n_fields = mvpp2_cls_flow_hek_num_get(fe); 776 777 for (i = 0; i < n_fields; i++) { 778 field = mvpp2_cls_flow_hek_get(fe, i); 779 780 switch (field) { 781 case MVPP22_CLS_FIELD_MAC_DA: 782 hash_opts |= MVPP22_CLS_HEK_OPT_MAC_DA; 783 break; 784 case MVPP22_CLS_FIELD_VLAN: 785 hash_opts |= MVPP22_CLS_HEK_OPT_VLAN; 786 break; 787 case MVPP22_CLS_FIELD_VLAN_PRI: 788 hash_opts |= MVPP22_CLS_HEK_OPT_VLAN_PRI; 789 break; 790 case MVPP22_CLS_FIELD_L3_PROTO: 791 hash_opts |= MVPP22_CLS_HEK_OPT_L3_PROTO; 792 break; 793 case MVPP22_CLS_FIELD_IP4SA: 794 hash_opts |= MVPP22_CLS_HEK_OPT_IP4SA; 795 break; 796 case MVPP22_CLS_FIELD_IP4DA: 797 hash_opts |= MVPP22_CLS_HEK_OPT_IP4DA; 798 break; 799 case MVPP22_CLS_FIELD_IP6SA: 800 hash_opts |= MVPP22_CLS_HEK_OPT_IP6SA; 801 break; 802 case MVPP22_CLS_FIELD_IP6DA: 803 hash_opts |= MVPP22_CLS_HEK_OPT_IP6DA; 804 break; 805 case MVPP22_CLS_FIELD_L4SIP: 806 hash_opts |= MVPP22_CLS_HEK_OPT_L4SIP; 807 break; 808 case MVPP22_CLS_FIELD_L4DIP: 809 hash_opts |= MVPP22_CLS_HEK_OPT_L4DIP; 810 break; 811 default: 812 break; 813 } 814 } 815 return hash_opts; 816 } 817 818 /* Returns the hash opts for this flow. There are several classifier flows 819 * for one traffic flow, this returns an aggregation of all configurations. 820 */ 821 static u16 mvpp2_port_rss_hash_opts_get(struct mvpp2_port *port, int flow_type) 822 { 823 const struct mvpp2_cls_flow *flow; 824 struct mvpp2_cls_flow_entry fe; 825 int i, flow_index; 826 u16 hash_opts = 0; 827 828 for_each_cls_flow_id_with_type(i, flow_type) { 829 flow = mvpp2_cls_flow_get(i); 830 if (!flow) 831 return 0; 832 833 flow_index = MVPP2_CLS_FLT_HASH_ENTRY(port->id, flow->flow_id); 834 835 mvpp2_cls_flow_read(port->priv, flow_index, &fe); 836 837 hash_opts |= mvpp2_flow_get_hek_fields(&fe); 838 } 839 840 return hash_opts; 841 } 842 843 static void mvpp2_cls_port_init_flows(struct mvpp2 *priv) 844 { 845 const struct mvpp2_cls_flow *flow; 846 int i; 847 848 for (i = 0; i < MVPP2_N_PRS_FLOWS; i++) { 849 flow = mvpp2_cls_flow_get(i); 850 if (!flow) 851 break; 852 853 mvpp2_cls_flow_prs_init(priv, flow); 854 mvpp2_cls_flow_lkp_init(priv, flow); 855 mvpp2_cls_flow_init(priv, flow); 856 } 857 } 858 859 static void mvpp2_port_c2_cls_init(struct mvpp2_port *port) 860 { 861 struct mvpp2_cls_c2_entry c2; 862 u8 qh, ql, pmap; 863 864 memset(&c2, 0, sizeof(c2)); 865 866 c2.index = MVPP22_CLS_C2_RSS_ENTRY(port->id); 867 868 pmap = BIT(port->id); 869 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap); 870 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap)); 871 872 /* Match on Lookup Type */ 873 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK)); 874 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(MVPP22_CLS_LU_TYPE_ALL); 875 876 /* Update RSS status after matching this entry */ 877 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK); 878 879 /* Mark packet as "forwarded to software", needed for RSS */ 880 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK); 881 882 /* Configure the default rx queue : Update Queue Low and Queue High, but 883 * don't lock, since the rx queue selection might be overridden by RSS 884 */ 885 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD) | 886 MVPP22_CLS_C2_ACT_QLOW(MVPP22_C2_UPD); 887 888 qh = (port->first_rxq >> 3) & MVPP22_CLS_C2_ATTR0_QHIGH_MASK; 889 ql = port->first_rxq & MVPP22_CLS_C2_ATTR0_QLOW_MASK; 890 891 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | 892 MVPP22_CLS_C2_ATTR0_QLOW(ql); 893 894 c2.valid = true; 895 896 mvpp2_cls_c2_write(port->priv, &c2); 897 } 898 899 /* Classifier default initialization */ 900 void mvpp2_cls_init(struct mvpp2 *priv) 901 { 902 struct mvpp2_cls_lookup_entry le; 903 struct mvpp2_cls_flow_entry fe; 904 struct mvpp2_cls_c2_entry c2; 905 int index; 906 907 /* Enable classifier */ 908 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); 909 910 /* Clear classifier flow table */ 911 memset(&fe.data, 0, sizeof(fe.data)); 912 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { 913 fe.index = index; 914 mvpp2_cls_flow_write(priv, &fe); 915 } 916 917 /* Clear classifier lookup table */ 918 le.data = 0; 919 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { 920 le.lkpid = index; 921 le.way = 0; 922 mvpp2_cls_lookup_write(priv, &le); 923 924 le.way = 1; 925 mvpp2_cls_lookup_write(priv, &le); 926 } 927 928 /* Clear C2 TCAM engine table */ 929 memset(&c2, 0, sizeof(c2)); 930 c2.valid = false; 931 for (index = 0; index < MVPP22_CLS_C2_N_ENTRIES; index++) { 932 c2.index = index; 933 mvpp2_cls_c2_write(priv, &c2); 934 } 935 936 /* Disable the FIFO stages in C2 engine, which are only used in BIST 937 * mode 938 */ 939 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_CTRL, 940 MVPP22_CLS_C2_TCAM_BYPASS_FIFO); 941 942 mvpp2_cls_port_init_flows(priv); 943 } 944 945 void mvpp2_cls_port_config(struct mvpp2_port *port) 946 { 947 struct mvpp2_cls_lookup_entry le; 948 u32 val; 949 950 /* Set way for the port */ 951 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); 952 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); 953 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); 954 955 /* Pick the entry to be accessed in lookup ID decoding table 956 * according to the way and lkpid. 957 */ 958 le.lkpid = port->id; 959 le.way = 0; 960 le.data = 0; 961 962 /* Set initial CPU queue for receiving packets */ 963 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; 964 le.data |= port->first_rxq; 965 966 /* Disable classification engines */ 967 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; 968 969 /* Update lookup ID table entry */ 970 mvpp2_cls_lookup_write(port->priv, &le); 971 972 mvpp2_port_c2_cls_init(port); 973 } 974 975 u32 mvpp2_cls_c2_hit_count(struct mvpp2 *priv, int c2_index) 976 { 977 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2_index); 978 979 return mvpp2_read(priv, MVPP22_CLS_C2_HIT_CTR); 980 } 981 982 static void mvpp2_rss_port_c2_enable(struct mvpp2_port *port, u32 ctx) 983 { 984 struct mvpp2_cls_c2_entry c2; 985 u8 qh, ql; 986 987 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2); 988 989 /* The RxQ number is used to select the RSS table. It that case, we set 990 * it to be the ctx number. 991 */ 992 qh = (ctx >> 3) & MVPP22_CLS_C2_ATTR0_QHIGH_MASK; 993 ql = ctx & MVPP22_CLS_C2_ATTR0_QLOW_MASK; 994 995 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | 996 MVPP22_CLS_C2_ATTR0_QLOW(ql); 997 998 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN; 999 1000 mvpp2_cls_c2_write(port->priv, &c2); 1001 } 1002 1003 static void mvpp2_rss_port_c2_disable(struct mvpp2_port *port) 1004 { 1005 struct mvpp2_cls_c2_entry c2; 1006 u8 qh, ql; 1007 1008 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2); 1009 1010 /* Reset the default destination RxQ to the port's first rx queue. */ 1011 qh = (port->first_rxq >> 3) & MVPP22_CLS_C2_ATTR0_QHIGH_MASK; 1012 ql = port->first_rxq & MVPP22_CLS_C2_ATTR0_QLOW_MASK; 1013 1014 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | 1015 MVPP22_CLS_C2_ATTR0_QLOW(ql); 1016 1017 c2.attr[2] &= ~MVPP22_CLS_C2_ATTR2_RSS_EN; 1018 1019 mvpp2_cls_c2_write(port->priv, &c2); 1020 } 1021 1022 static inline int mvpp22_rss_ctx(struct mvpp2_port *port, int port_rss_ctx) 1023 { 1024 return port->rss_ctx[port_rss_ctx]; 1025 } 1026 1027 int mvpp22_port_rss_enable(struct mvpp2_port *port) 1028 { 1029 if (mvpp22_rss_ctx(port, 0) < 0) 1030 return -EINVAL; 1031 1032 mvpp2_rss_port_c2_enable(port, mvpp22_rss_ctx(port, 0)); 1033 1034 return 0; 1035 } 1036 1037 int mvpp22_port_rss_disable(struct mvpp2_port *port) 1038 { 1039 if (mvpp22_rss_ctx(port, 0) < 0) 1040 return -EINVAL; 1041 1042 mvpp2_rss_port_c2_disable(port); 1043 1044 return 0; 1045 } 1046 1047 static void mvpp22_port_c2_lookup_disable(struct mvpp2_port *port, int entry) 1048 { 1049 struct mvpp2_cls_c2_entry c2; 1050 1051 mvpp2_cls_c2_read(port->priv, entry, &c2); 1052 1053 /* Clear the port map so that the entry doesn't match anymore */ 1054 c2.tcam[4] &= ~(MVPP22_CLS_C2_PORT_ID(BIT(port->id))); 1055 1056 mvpp2_cls_c2_write(port->priv, &c2); 1057 } 1058 1059 /* Set CPU queue number for oversize packets */ 1060 void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) 1061 { 1062 u32 val; 1063 1064 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), 1065 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); 1066 1067 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), 1068 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); 1069 1070 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); 1071 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); 1072 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); 1073 } 1074 1075 static int mvpp2_port_c2_tcam_rule_add(struct mvpp2_port *port, 1076 struct mvpp2_rfs_rule *rule) 1077 { 1078 struct flow_action_entry *act; 1079 struct mvpp2_cls_c2_entry c2; 1080 u8 qh, ql, pmap; 1081 int index, ctx; 1082 1083 memset(&c2, 0, sizeof(c2)); 1084 1085 index = mvpp2_cls_c2_port_flow_index(port, rule->loc); 1086 if (index < 0) 1087 return -EINVAL; 1088 c2.index = index; 1089 1090 act = &rule->flow->action.entries[0]; 1091 1092 rule->c2_index = c2.index; 1093 1094 c2.tcam[3] = (rule->c2_tcam & 0xffff) | 1095 ((rule->c2_tcam_mask & 0xffff) << 16); 1096 c2.tcam[2] = ((rule->c2_tcam >> 16) & 0xffff) | 1097 (((rule->c2_tcam_mask >> 16) & 0xffff) << 16); 1098 c2.tcam[1] = ((rule->c2_tcam >> 32) & 0xffff) | 1099 (((rule->c2_tcam_mask >> 32) & 0xffff) << 16); 1100 c2.tcam[0] = ((rule->c2_tcam >> 48) & 0xffff) | 1101 (((rule->c2_tcam_mask >> 48) & 0xffff) << 16); 1102 1103 pmap = BIT(port->id); 1104 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap); 1105 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap)); 1106 1107 /* Match on Lookup Type */ 1108 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK)); 1109 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(rule->loc); 1110 1111 if (act->id == FLOW_ACTION_DROP) { 1112 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_RED_LOCK); 1113 } else { 1114 /* We want to keep the default color derived from the Header 1115 * Parser drop entries, for VLAN and MAC filtering. This will 1116 * assign a default color of Green or Red, and we want matches 1117 * with a non-drop action to keep that color. 1118 */ 1119 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_NO_UPD_LOCK); 1120 1121 /* Update RSS status after matching this entry */ 1122 if (act->queue.ctx) 1123 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN; 1124 1125 /* Always lock the RSS_EN decision. We might have high prio 1126 * rules steering to an RXQ, and a lower one steering to RSS, 1127 * we don't want the low prio RSS rule overwriting this flag. 1128 */ 1129 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK); 1130 1131 /* Mark packet as "forwarded to software", needed for RSS */ 1132 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK); 1133 1134 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD_LOCK) | 1135 MVPP22_CLS_C2_ACT_QLOW(MVPP22_C2_UPD_LOCK); 1136 1137 if (act->queue.ctx) { 1138 /* Get the global ctx number */ 1139 ctx = mvpp22_rss_ctx(port, act->queue.ctx); 1140 if (ctx < 0) 1141 return -EINVAL; 1142 1143 qh = (ctx >> 3) & MVPP22_CLS_C2_ATTR0_QHIGH_MASK; 1144 ql = ctx & MVPP22_CLS_C2_ATTR0_QLOW_MASK; 1145 } else { 1146 qh = ((act->queue.index + port->first_rxq) >> 3) & 1147 MVPP22_CLS_C2_ATTR0_QHIGH_MASK; 1148 ql = (act->queue.index + port->first_rxq) & 1149 MVPP22_CLS_C2_ATTR0_QLOW_MASK; 1150 } 1151 1152 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | 1153 MVPP22_CLS_C2_ATTR0_QLOW(ql); 1154 } 1155 1156 c2.valid = true; 1157 1158 mvpp2_cls_c2_write(port->priv, &c2); 1159 1160 return 0; 1161 } 1162 1163 static int mvpp2_port_c2_rfs_rule_insert(struct mvpp2_port *port, 1164 struct mvpp2_rfs_rule *rule) 1165 { 1166 return mvpp2_port_c2_tcam_rule_add(port, rule); 1167 } 1168 1169 static int mvpp2_port_cls_rfs_rule_remove(struct mvpp2_port *port, 1170 struct mvpp2_rfs_rule *rule) 1171 { 1172 const struct mvpp2_cls_flow *flow; 1173 struct mvpp2_cls_flow_entry fe; 1174 int index, i; 1175 1176 for_each_cls_flow_id_containing_type(i, rule->flow_type) { 1177 flow = mvpp2_cls_flow_get(i); 1178 if (!flow) 1179 return 0; 1180 1181 index = MVPP2_CLS_FLT_C2_RFS(port->id, flow->flow_id, rule->loc); 1182 1183 mvpp2_cls_flow_read(port->priv, index, &fe); 1184 mvpp2_cls_flow_port_remove(&fe, BIT(port->id)); 1185 mvpp2_cls_flow_write(port->priv, &fe); 1186 } 1187 1188 if (rule->c2_index >= 0) 1189 mvpp22_port_c2_lookup_disable(port, rule->c2_index); 1190 1191 return 0; 1192 } 1193 1194 static int mvpp2_port_flt_rfs_rule_insert(struct mvpp2_port *port, 1195 struct mvpp2_rfs_rule *rule) 1196 { 1197 const struct mvpp2_cls_flow *flow; 1198 struct mvpp2 *priv = port->priv; 1199 struct mvpp2_cls_flow_entry fe; 1200 int index, ret, i; 1201 1202 if (rule->engine != MVPP22_CLS_ENGINE_C2) 1203 return -EOPNOTSUPP; 1204 1205 ret = mvpp2_port_c2_rfs_rule_insert(port, rule); 1206 if (ret) 1207 return ret; 1208 1209 for_each_cls_flow_id_containing_type(i, rule->flow_type) { 1210 flow = mvpp2_cls_flow_get(i); 1211 if (!flow) 1212 return 0; 1213 1214 if ((rule->hek_fields & flow->supported_hash_opts) != rule->hek_fields) 1215 continue; 1216 1217 index = MVPP2_CLS_FLT_C2_RFS(port->id, flow->flow_id, rule->loc); 1218 1219 mvpp2_cls_flow_read(priv, index, &fe); 1220 mvpp2_cls_flow_eng_set(&fe, rule->engine); 1221 mvpp2_cls_flow_port_id_sel(&fe, true); 1222 mvpp2_flow_set_hek_fields(&fe, rule->hek_fields); 1223 mvpp2_cls_flow_lu_type_set(&fe, rule->loc); 1224 mvpp2_cls_flow_port_add(&fe, 0xf); 1225 1226 mvpp2_cls_flow_write(priv, &fe); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int mvpp2_cls_c2_build_match(struct mvpp2_rfs_rule *rule) 1233 { 1234 struct flow_rule *flow = rule->flow; 1235 int offs = 0; 1236 1237 /* The order of insertion in C2 tcam must match the order in which 1238 * the fields are found in the header 1239 */ 1240 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 1241 struct flow_match_vlan match; 1242 1243 flow_rule_match_vlan(flow, &match); 1244 if (match.mask->vlan_id) { 1245 rule->hek_fields |= MVPP22_CLS_HEK_OPT_VLAN; 1246 1247 rule->c2_tcam |= ((u64)match.key->vlan_id) << offs; 1248 rule->c2_tcam_mask |= ((u64)match.mask->vlan_id) << offs; 1249 1250 /* Don't update the offset yet */ 1251 } 1252 1253 if (match.mask->vlan_priority) { 1254 rule->hek_fields |= MVPP22_CLS_HEK_OPT_VLAN_PRI; 1255 1256 /* VLAN pri is always at offset 13 relative to the 1257 * current offset 1258 */ 1259 rule->c2_tcam |= ((u64)match.key->vlan_priority) << 1260 (offs + 13); 1261 rule->c2_tcam_mask |= ((u64)match.mask->vlan_priority) << 1262 (offs + 13); 1263 } 1264 1265 if (match.mask->vlan_dei) 1266 return -EOPNOTSUPP; 1267 1268 /* vlan id and prio always seem to take a full 16-bit slot in 1269 * the Header Extracted Key. 1270 */ 1271 offs += 16; 1272 } 1273 1274 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 1275 struct flow_match_ports match; 1276 1277 flow_rule_match_ports(flow, &match); 1278 if (match.mask->src) { 1279 rule->hek_fields |= MVPP22_CLS_HEK_OPT_L4SIP; 1280 1281 rule->c2_tcam |= ((u64)ntohs(match.key->src)) << offs; 1282 rule->c2_tcam_mask |= ((u64)ntohs(match.mask->src)) << offs; 1283 offs += mvpp2_cls_hek_field_size(MVPP22_CLS_HEK_OPT_L4SIP); 1284 } 1285 1286 if (match.mask->dst) { 1287 rule->hek_fields |= MVPP22_CLS_HEK_OPT_L4DIP; 1288 1289 rule->c2_tcam |= ((u64)ntohs(match.key->dst)) << offs; 1290 rule->c2_tcam_mask |= ((u64)ntohs(match.mask->dst)) << offs; 1291 offs += mvpp2_cls_hek_field_size(MVPP22_CLS_HEK_OPT_L4DIP); 1292 } 1293 } 1294 1295 if (hweight16(rule->hek_fields) > MVPP2_FLOW_N_FIELDS) 1296 return -EOPNOTSUPP; 1297 1298 return 0; 1299 } 1300 1301 static int mvpp2_cls_rfs_parse_rule(struct mvpp2_rfs_rule *rule) 1302 { 1303 struct flow_rule *flow = rule->flow; 1304 struct flow_action_entry *act; 1305 1306 act = &flow->action.entries[0]; 1307 if (act->id != FLOW_ACTION_QUEUE && act->id != FLOW_ACTION_DROP) 1308 return -EOPNOTSUPP; 1309 1310 /* When both an RSS context and an queue index are set, the index 1311 * is considered as an offset to be added to the indirection table 1312 * entries. We don't support this, so reject this rule. 1313 */ 1314 if (act->queue.ctx && act->queue.index) 1315 return -EOPNOTSUPP; 1316 1317 /* For now, only use the C2 engine which has a HEK size limited to 64 1318 * bits for TCAM matching. 1319 */ 1320 rule->engine = MVPP22_CLS_ENGINE_C2; 1321 1322 if (mvpp2_cls_c2_build_match(rule)) 1323 return -EINVAL; 1324 1325 return 0; 1326 } 1327 1328 int mvpp2_ethtool_cls_rule_get(struct mvpp2_port *port, 1329 struct ethtool_rxnfc *rxnfc) 1330 { 1331 struct mvpp2_ethtool_fs *efs; 1332 1333 if (rxnfc->fs.location >= MVPP2_N_RFS_ENTRIES_PER_FLOW) 1334 return -EINVAL; 1335 1336 efs = port->rfs_rules[rxnfc->fs.location]; 1337 if (!efs) 1338 return -ENOENT; 1339 1340 memcpy(rxnfc, &efs->rxnfc, sizeof(efs->rxnfc)); 1341 1342 return 0; 1343 } 1344 1345 int mvpp2_ethtool_cls_rule_ins(struct mvpp2_port *port, 1346 struct ethtool_rxnfc *info) 1347 { 1348 struct ethtool_rx_flow_spec_input input = {}; 1349 struct ethtool_rx_flow_rule *ethtool_rule; 1350 struct mvpp2_ethtool_fs *efs, *old_efs; 1351 int ret = 0; 1352 1353 if (info->fs.location >= MVPP2_N_RFS_ENTRIES_PER_FLOW) 1354 return -EINVAL; 1355 1356 efs = kzalloc(sizeof(*efs), GFP_KERNEL); 1357 if (!efs) 1358 return -ENOMEM; 1359 1360 input.fs = &info->fs; 1361 1362 /* We need to manually set the rss_ctx, since this info isn't present 1363 * in info->fs 1364 */ 1365 if (info->fs.flow_type & FLOW_RSS) 1366 input.rss_ctx = info->rss_context; 1367 1368 ethtool_rule = ethtool_rx_flow_rule_create(&input); 1369 if (IS_ERR(ethtool_rule)) { 1370 ret = PTR_ERR(ethtool_rule); 1371 goto clean_rule; 1372 } 1373 1374 efs->rule.flow = ethtool_rule->rule; 1375 efs->rule.flow_type = mvpp2_cls_ethtool_flow_to_type(info->fs.flow_type); 1376 1377 ret = mvpp2_cls_rfs_parse_rule(&efs->rule); 1378 if (ret) 1379 goto clean_eth_rule; 1380 1381 efs->rule.loc = info->fs.location; 1382 1383 /* Replace an already existing rule */ 1384 if (port->rfs_rules[efs->rule.loc]) { 1385 old_efs = port->rfs_rules[efs->rule.loc]; 1386 ret = mvpp2_port_cls_rfs_rule_remove(port, &old_efs->rule); 1387 if (ret) 1388 goto clean_eth_rule; 1389 kfree(old_efs); 1390 port->n_rfs_rules--; 1391 } 1392 1393 ret = mvpp2_port_flt_rfs_rule_insert(port, &efs->rule); 1394 if (ret) 1395 goto clean_eth_rule; 1396 1397 ethtool_rx_flow_rule_destroy(ethtool_rule); 1398 efs->rule.flow = NULL; 1399 1400 memcpy(&efs->rxnfc, info, sizeof(*info)); 1401 port->rfs_rules[efs->rule.loc] = efs; 1402 port->n_rfs_rules++; 1403 1404 return ret; 1405 1406 clean_eth_rule: 1407 ethtool_rx_flow_rule_destroy(ethtool_rule); 1408 clean_rule: 1409 kfree(efs); 1410 return ret; 1411 } 1412 1413 int mvpp2_ethtool_cls_rule_del(struct mvpp2_port *port, 1414 struct ethtool_rxnfc *info) 1415 { 1416 struct mvpp2_ethtool_fs *efs; 1417 int ret; 1418 1419 efs = port->rfs_rules[info->fs.location]; 1420 if (!efs) 1421 return -EINVAL; 1422 1423 /* Remove the rule from the engines. */ 1424 ret = mvpp2_port_cls_rfs_rule_remove(port, &efs->rule); 1425 if (ret) 1426 return ret; 1427 1428 port->n_rfs_rules--; 1429 port->rfs_rules[info->fs.location] = NULL; 1430 kfree(efs); 1431 1432 return 0; 1433 } 1434 1435 static inline u32 mvpp22_rxfh_indir(struct mvpp2_port *port, u32 rxq) 1436 { 1437 int nrxqs, cpu, cpus = num_possible_cpus(); 1438 1439 /* Number of RXQs per CPU */ 1440 nrxqs = port->nrxqs / cpus; 1441 1442 /* CPU that will handle this rx queue */ 1443 cpu = rxq / nrxqs; 1444 1445 if (!cpu_online(cpu)) 1446 return port->first_rxq; 1447 1448 /* Indirection to better distribute the paquets on the CPUs when 1449 * configuring the RSS queues. 1450 */ 1451 return port->first_rxq + ((rxq * nrxqs + rxq / cpus) % port->nrxqs); 1452 } 1453 1454 static void mvpp22_rss_fill_table(struct mvpp2_port *port, 1455 struct mvpp2_rss_table *table, 1456 u32 rss_ctx) 1457 { 1458 struct mvpp2 *priv = port->priv; 1459 int i; 1460 1461 for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) { 1462 u32 sel = MVPP22_RSS_INDEX_TABLE(rss_ctx) | 1463 MVPP22_RSS_INDEX_TABLE_ENTRY(i); 1464 mvpp2_write(priv, MVPP22_RSS_INDEX, sel); 1465 1466 mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY, 1467 mvpp22_rxfh_indir(port, table->indir[i])); 1468 } 1469 } 1470 1471 static int mvpp22_rss_context_create(struct mvpp2_port *port, u32 *rss_ctx) 1472 { 1473 struct mvpp2 *priv = port->priv; 1474 u32 ctx; 1475 1476 /* Find the first free RSS table */ 1477 for (ctx = 0; ctx < MVPP22_N_RSS_TABLES; ctx++) { 1478 if (!priv->rss_tables[ctx]) 1479 break; 1480 } 1481 1482 if (ctx == MVPP22_N_RSS_TABLES) 1483 return -EINVAL; 1484 1485 priv->rss_tables[ctx] = kzalloc(sizeof(*priv->rss_tables[ctx]), 1486 GFP_KERNEL); 1487 if (!priv->rss_tables[ctx]) 1488 return -ENOMEM; 1489 1490 *rss_ctx = ctx; 1491 1492 /* Set the table width: replace the whole classifier Rx queue number 1493 * with the ones configured in RSS table entries. 1494 */ 1495 mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(ctx)); 1496 mvpp2_write(priv, MVPP22_RSS_WIDTH, 8); 1497 1498 mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_QUEUE(ctx)); 1499 mvpp2_write(priv, MVPP22_RXQ2RSS_TABLE, MVPP22_RSS_TABLE_POINTER(ctx)); 1500 1501 return 0; 1502 } 1503 1504 int mvpp22_port_rss_ctx_create(struct mvpp2_port *port, u32 *port_ctx) 1505 { 1506 u32 rss_ctx; 1507 int ret, i; 1508 1509 ret = mvpp22_rss_context_create(port, &rss_ctx); 1510 if (ret) 1511 return ret; 1512 1513 /* Find the first available context number in the port, starting from 1. 1514 * Context 0 on each port is reserved for the default context. 1515 */ 1516 for (i = 1; i < MVPP22_N_RSS_TABLES; i++) { 1517 if (port->rss_ctx[i] < 0) 1518 break; 1519 } 1520 1521 if (i == MVPP22_N_RSS_TABLES) 1522 return -EINVAL; 1523 1524 port->rss_ctx[i] = rss_ctx; 1525 *port_ctx = i; 1526 1527 return 0; 1528 } 1529 1530 static struct mvpp2_rss_table *mvpp22_rss_table_get(struct mvpp2 *priv, 1531 int rss_ctx) 1532 { 1533 if (rss_ctx < 0 || rss_ctx >= MVPP22_N_RSS_TABLES) 1534 return NULL; 1535 1536 return priv->rss_tables[rss_ctx]; 1537 } 1538 1539 int mvpp22_port_rss_ctx_delete(struct mvpp2_port *port, u32 port_ctx) 1540 { 1541 struct mvpp2 *priv = port->priv; 1542 struct ethtool_rxnfc *rxnfc; 1543 int i, rss_ctx, ret; 1544 1545 rss_ctx = mvpp22_rss_ctx(port, port_ctx); 1546 1547 if (rss_ctx < 0 || rss_ctx >= MVPP22_N_RSS_TABLES) 1548 return -EINVAL; 1549 1550 /* Invalidate any active classification rule that use this context */ 1551 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 1552 if (!port->rfs_rules[i]) 1553 continue; 1554 1555 rxnfc = &port->rfs_rules[i]->rxnfc; 1556 if (!(rxnfc->fs.flow_type & FLOW_RSS) || 1557 rxnfc->rss_context != port_ctx) 1558 continue; 1559 1560 ret = mvpp2_ethtool_cls_rule_del(port, rxnfc); 1561 if (ret) { 1562 netdev_warn(port->dev, 1563 "couldn't remove classification rule %d associated to this context", 1564 rxnfc->fs.location); 1565 } 1566 } 1567 1568 kfree(priv->rss_tables[rss_ctx]); 1569 1570 priv->rss_tables[rss_ctx] = NULL; 1571 port->rss_ctx[port_ctx] = -1; 1572 1573 return 0; 1574 } 1575 1576 int mvpp22_port_rss_ctx_indir_set(struct mvpp2_port *port, u32 port_ctx, 1577 const u32 *indir) 1578 { 1579 int rss_ctx = mvpp22_rss_ctx(port, port_ctx); 1580 struct mvpp2_rss_table *rss_table = mvpp22_rss_table_get(port->priv, 1581 rss_ctx); 1582 1583 if (!rss_table) 1584 return -EINVAL; 1585 1586 memcpy(rss_table->indir, indir, 1587 MVPP22_RSS_TABLE_ENTRIES * sizeof(rss_table->indir[0])); 1588 1589 mvpp22_rss_fill_table(port, rss_table, rss_ctx); 1590 1591 return 0; 1592 } 1593 1594 int mvpp22_port_rss_ctx_indir_get(struct mvpp2_port *port, u32 port_ctx, 1595 u32 *indir) 1596 { 1597 int rss_ctx = mvpp22_rss_ctx(port, port_ctx); 1598 struct mvpp2_rss_table *rss_table = mvpp22_rss_table_get(port->priv, 1599 rss_ctx); 1600 1601 if (!rss_table) 1602 return -EINVAL; 1603 1604 memcpy(indir, rss_table->indir, 1605 MVPP22_RSS_TABLE_ENTRIES * sizeof(rss_table->indir[0])); 1606 1607 return 0; 1608 } 1609 1610 int mvpp2_ethtool_rxfh_set(struct mvpp2_port *port, struct ethtool_rxnfc *info) 1611 { 1612 u16 hash_opts = 0; 1613 u32 flow_type; 1614 1615 flow_type = mvpp2_cls_ethtool_flow_to_type(info->flow_type); 1616 1617 switch (flow_type) { 1618 case MVPP22_FLOW_TCP4: 1619 case MVPP22_FLOW_UDP4: 1620 case MVPP22_FLOW_TCP6: 1621 case MVPP22_FLOW_UDP6: 1622 if (info->data & RXH_L4_B_0_1) 1623 hash_opts |= MVPP22_CLS_HEK_OPT_L4SIP; 1624 if (info->data & RXH_L4_B_2_3) 1625 hash_opts |= MVPP22_CLS_HEK_OPT_L4DIP; 1626 /* Fallthrough */ 1627 case MVPP22_FLOW_IP4: 1628 case MVPP22_FLOW_IP6: 1629 if (info->data & RXH_L2DA) 1630 hash_opts |= MVPP22_CLS_HEK_OPT_MAC_DA; 1631 if (info->data & RXH_VLAN) 1632 hash_opts |= MVPP22_CLS_HEK_OPT_VLAN; 1633 if (info->data & RXH_L3_PROTO) 1634 hash_opts |= MVPP22_CLS_HEK_OPT_L3_PROTO; 1635 if (info->data & RXH_IP_SRC) 1636 hash_opts |= (MVPP22_CLS_HEK_OPT_IP4SA | 1637 MVPP22_CLS_HEK_OPT_IP6SA); 1638 if (info->data & RXH_IP_DST) 1639 hash_opts |= (MVPP22_CLS_HEK_OPT_IP4DA | 1640 MVPP22_CLS_HEK_OPT_IP6DA); 1641 break; 1642 default: return -EOPNOTSUPP; 1643 } 1644 1645 return mvpp2_port_rss_hash_opts_set(port, flow_type, hash_opts); 1646 } 1647 1648 int mvpp2_ethtool_rxfh_get(struct mvpp2_port *port, struct ethtool_rxnfc *info) 1649 { 1650 unsigned long hash_opts; 1651 u32 flow_type; 1652 int i; 1653 1654 flow_type = mvpp2_cls_ethtool_flow_to_type(info->flow_type); 1655 1656 hash_opts = mvpp2_port_rss_hash_opts_get(port, flow_type); 1657 info->data = 0; 1658 1659 for_each_set_bit(i, &hash_opts, MVPP22_CLS_HEK_N_FIELDS) { 1660 switch (BIT(i)) { 1661 case MVPP22_CLS_HEK_OPT_MAC_DA: 1662 info->data |= RXH_L2DA; 1663 break; 1664 case MVPP22_CLS_HEK_OPT_VLAN: 1665 info->data |= RXH_VLAN; 1666 break; 1667 case MVPP22_CLS_HEK_OPT_L3_PROTO: 1668 info->data |= RXH_L3_PROTO; 1669 break; 1670 case MVPP22_CLS_HEK_OPT_IP4SA: 1671 case MVPP22_CLS_HEK_OPT_IP6SA: 1672 info->data |= RXH_IP_SRC; 1673 break; 1674 case MVPP22_CLS_HEK_OPT_IP4DA: 1675 case MVPP22_CLS_HEK_OPT_IP6DA: 1676 info->data |= RXH_IP_DST; 1677 break; 1678 case MVPP22_CLS_HEK_OPT_L4SIP: 1679 info->data |= RXH_L4_B_0_1; 1680 break; 1681 case MVPP22_CLS_HEK_OPT_L4DIP: 1682 info->data |= RXH_L4_B_2_3; 1683 break; 1684 default: 1685 return -EINVAL; 1686 } 1687 } 1688 return 0; 1689 } 1690 1691 int mvpp22_port_rss_init(struct mvpp2_port *port) 1692 { 1693 struct mvpp2_rss_table *table; 1694 u32 context = 0; 1695 int i, ret; 1696 1697 for (i = 0; i < MVPP22_N_RSS_TABLES; i++) 1698 port->rss_ctx[i] = -1; 1699 1700 ret = mvpp22_rss_context_create(port, &context); 1701 if (ret) 1702 return ret; 1703 1704 table = mvpp22_rss_table_get(port->priv, context); 1705 if (!table) 1706 return -EINVAL; 1707 1708 port->rss_ctx[0] = context; 1709 1710 /* Configure the first table to evenly distribute the packets across 1711 * real Rx Queues. The table entries map a hash to a port Rx Queue. 1712 */ 1713 for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) 1714 table->indir[i] = ethtool_rxfh_indir_default(i, port->nrxqs); 1715 1716 mvpp22_rss_fill_table(port, table, mvpp22_rss_ctx(port, 0)); 1717 1718 /* Configure default flows */ 1719 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_IP4, MVPP22_CLS_HEK_IP4_2T); 1720 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_IP6, MVPP22_CLS_HEK_IP6_2T); 1721 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_TCP4, MVPP22_CLS_HEK_IP4_5T); 1722 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_TCP6, MVPP22_CLS_HEK_IP6_5T); 1723 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_UDP4, MVPP22_CLS_HEK_IP4_5T); 1724 mvpp2_port_rss_hash_opts_set(port, MVPP22_FLOW_UDP6, MVPP22_CLS_HEK_IP6_5T); 1725 1726 return 0; 1727 } 1728