1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 #ifndef _MVPP2_H_ 10 #define _MVPP2_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/phy.h> 16 #include <linux/phylink.h> 17 18 /* Fifo Registers */ 19 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 20 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 21 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 22 #define MVPP2_RX_FIFO_INIT_REG 0x64 23 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 24 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 25 26 /* RX DMA Top Registers */ 27 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 28 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 29 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 30 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 31 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 32 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 33 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 34 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 35 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 36 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 37 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 38 #define MVPP2_RXQ_POOL_LONG_OFFS 24 39 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 40 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 41 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 42 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 43 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 44 45 /* Top Registers */ 46 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 47 #define MVPP2_DSA_EXTENDED BIT(5) 48 49 /* Parser Registers */ 50 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 51 #define MVPP2_PRS_PORT_LU_MAX 0xf 52 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 53 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 54 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 55 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 56 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 57 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 58 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 59 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 60 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 61 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 62 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 63 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 64 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 65 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 66 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 67 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240 68 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244 69 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0) 70 71 /* RSS Registers */ 72 #define MVPP22_RSS_INDEX 0x1500 73 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 74 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 75 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 76 #define MVPP22_RXQ2RSS_TABLE 0x1504 77 #define MVPP22_RSS_TABLE_POINTER(p) (p) 78 #define MVPP22_RSS_TABLE_ENTRY 0x1508 79 #define MVPP22_RSS_WIDTH 0x150c 80 81 /* Classifier Registers */ 82 #define MVPP2_CLS_MODE_REG 0x1800 83 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 84 #define MVPP2_CLS_PORT_WAY_REG 0x1810 85 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 86 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 87 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 88 #define MVPP2_CLS_LKP_TBL_REG 0x1818 89 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 90 #define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16) 91 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 92 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 93 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 94 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) 95 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7 96 #define MVPP2_CLS_FLOW_TBL0_OFFS 1 97 #define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1) 98 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff 99 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) 100 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) 101 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 102 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7 103 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x) 104 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f 105 #define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9) 106 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7 107 #define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15) 108 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 109 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f 110 #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6) 111 #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6)) 112 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 113 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 114 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 115 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 116 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 117 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 118 119 /* Classifier C2 engine Registers */ 120 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00 121 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10 122 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14 123 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18 124 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c 125 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20 126 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) 127 #define MVPP22_CLS_C2_HIT_CTR 0x1b50 128 #define MVPP22_CLS_C2_ACT 0x1b60 129 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19) 130 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13) 131 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11) 132 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9) 133 #define MVPP22_CLS_C2_ATTR0 0x1b64 134 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24) 135 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f 136 #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24 137 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21) 138 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7 139 #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21 140 #define MVPP22_CLS_C2_ATTR1 0x1b68 141 #define MVPP22_CLS_C2_ATTR2 0x1b6c 142 #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) 143 #define MVPP22_CLS_C2_ATTR3 0x1b70 144 145 /* Descriptor Manager Top Registers */ 146 #define MVPP2_RXQ_NUM_REG 0x2040 147 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 148 #define MVPP22_DESC_ADDR_OFFS 8 149 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 150 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 151 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 152 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 153 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 154 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 155 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 156 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 157 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 158 #define MVPP2_RXQ_THRESH_REG 0x204c 159 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 160 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 161 #define MVPP2_RXQ_INDEX_REG 0x2050 162 #define MVPP2_TXQ_NUM_REG 0x2080 163 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 164 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 165 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 166 #define MVPP2_TXQ_THRESH_REG 0x2094 167 #define MVPP2_TXQ_THRESH_OFFSET 16 168 #define MVPP2_TXQ_THRESH_MASK 0x3fff 169 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 170 #define MVPP2_TXQ_INDEX_REG 0x2098 171 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 172 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 173 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 174 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 175 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 176 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 177 #define MVPP2_TXQ_PENDING_REG 0x20a0 178 #define MVPP2_TXQ_PENDING_MASK 0x3fff 179 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 180 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 181 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 182 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 183 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 184 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 185 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 186 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 187 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 188 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 189 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 190 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 191 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 192 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 193 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 194 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 195 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 196 197 /* MBUS bridge registers */ 198 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 199 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 200 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 201 #define MVPP2_BASE_ADDR_ENABLE 0x4060 202 203 /* AXI Bridge Registers */ 204 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 205 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 206 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 207 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 208 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 209 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 210 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 211 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 212 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 213 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 214 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 215 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 216 217 /* Values for AXI Bridge registers */ 218 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 219 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 220 221 #define MVPP22_AXI_CODE_CACHE_OFFS 0 222 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 223 224 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 225 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 226 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 227 228 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 229 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 230 231 /* Interrupt Cause and Mask registers */ 232 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 233 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 234 235 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 236 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 237 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 238 239 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 240 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 241 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 242 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 243 244 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 245 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 246 247 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 248 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 249 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 250 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 251 252 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 253 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 254 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 255 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 256 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \ 257 ((version) == MVPP21 ? 0xffff : 0xff) 258 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 259 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 260 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 261 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 262 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 263 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 264 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 265 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 266 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 267 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 268 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 269 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 270 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 271 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 272 273 /* Buffer Manager registers */ 274 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 275 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 276 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 277 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 278 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 279 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 280 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 281 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 282 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 283 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 284 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 285 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 286 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 287 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 288 #define MVPP2_BM_START_MASK BIT(0) 289 #define MVPP2_BM_STOP_MASK BIT(1) 290 #define MVPP2_BM_STATE_MASK BIT(4) 291 #define MVPP2_BM_LOW_THRESH_OFFS 8 292 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 293 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 294 MVPP2_BM_LOW_THRESH_OFFS) 295 #define MVPP2_BM_HIGH_THRESH_OFFS 16 296 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 297 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 298 MVPP2_BM_HIGH_THRESH_OFFS) 299 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 300 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 301 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 302 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 303 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 304 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 305 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 306 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 307 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 308 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 309 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 310 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 311 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 312 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 313 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 314 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 315 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 316 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 317 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 318 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 319 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 320 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 321 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 322 323 /* Hit counters registers */ 324 #define MVPP2_CTRS_IDX 0x7040 325 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700 326 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704 327 328 /* TX Scheduler registers */ 329 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 330 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 331 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 332 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 333 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 334 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014 335 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 336 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 337 #define MVPP2_TXP_MTU_MAX 0x7FFFF 338 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 339 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 340 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 341 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 342 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 343 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 344 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 345 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 346 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 347 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 348 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 349 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 350 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 351 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 352 353 /* TX general registers */ 354 #define MVPP2_TX_SNOOP_REG 0x8800 355 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 356 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 357 358 /* LMS registers */ 359 #define MVPP2_SRC_ADDR_MIDDLE 0x24 360 #define MVPP2_SRC_ADDR_HIGH 0x28 361 #define MVPP2_PHY_AN_CFG0_REG 0x34 362 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 363 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 364 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 365 366 /* Per-port registers */ 367 #define MVPP2_GMAC_CTRL_0_REG 0x0 368 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 369 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 370 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 371 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 372 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 373 #define MVPP2_GMAC_CTRL_1_REG 0x4 374 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 375 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 376 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 377 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 378 #define MVPP2_GMAC_SA_LOW_OFFS 7 379 #define MVPP2_GMAC_CTRL_2_REG 0x8 380 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 381 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 382 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 383 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 384 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 385 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 386 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 387 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 388 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 389 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 390 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 391 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 392 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 393 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 394 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 395 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 396 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 397 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 398 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 399 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 400 #define MVPP2_GMAC_STATUS0 0x10 401 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 402 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 403 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 404 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 405 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4) 406 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5) 407 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 408 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 409 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 410 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 411 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 412 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 413 #define MVPP22_GMAC_INT_STAT 0x20 414 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 415 #define MVPP22_GMAC_INT_MASK 0x24 416 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 417 #define MVPP22_GMAC_CTRL_4_REG 0x90 418 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 419 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 420 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 421 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 422 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 423 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 424 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 425 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 426 427 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 428 * relative to port->base. 429 */ 430 #define MVPP22_XLG_CTRL0_REG 0x100 431 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 432 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 433 #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2) 434 #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3) 435 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 436 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 437 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 438 #define MVPP22_XLG_CTRL1_REG 0x104 439 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 440 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 441 #define MVPP22_XLG_STATUS 0x10c 442 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 443 #define MVPP22_XLG_INT_STAT 0x114 444 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 445 #define MVPP22_XLG_INT_MASK 0x118 446 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 447 #define MVPP22_XLG_CTRL3_REG 0x11c 448 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 449 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 450 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 451 #define MVPP22_XLG_EXT_INT_MASK 0x15c 452 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 453 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 454 #define MVPP22_XLG_CTRL4_REG 0x184 455 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 456 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 457 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 458 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 459 460 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 461 #define MVPP22_SMI_MISC_CFG_REG 0x1204 462 #define MVPP22_SMI_POLLING_EN BIT(10) 463 464 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 465 466 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 467 468 /* Descriptor ring Macros */ 469 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 470 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 471 472 /* XPCS registers. PPv2.2 only */ 473 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 474 #define MVPP22_MPCS_CTRL 0x14 475 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 476 #define MVPP22_MPCS_CLK_RESET 0x14c 477 #define MAC_CLK_RESET_SD_TX BIT(0) 478 #define MAC_CLK_RESET_SD_RX BIT(1) 479 #define MAC_CLK_RESET_MAC BIT(2) 480 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 481 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 482 483 /* XPCS registers. PPv2.2 only */ 484 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 485 #define MVPP22_XPCS_CFG0 0x0 486 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0) 487 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 488 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 489 490 /* System controller registers. Accessed through a regmap. */ 491 #define GENCONF_SOFT_RESET1 0x1108 492 #define GENCONF_SOFT_RESET1_GOP BIT(6) 493 #define GENCONF_PORT_CTRL0 0x1110 494 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 495 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 496 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 497 #define GENCONF_PORT_CTRL1 0x1114 498 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 499 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 500 #define GENCONF_CTRL0 0x1120 501 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 502 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 503 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 504 505 /* Various constants */ 506 507 /* Coalescing */ 508 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 509 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 510 #define MVPP2_TXDONE_COAL_USEC 1000 511 #define MVPP2_RX_COAL_PKTS 32 512 #define MVPP2_RX_COAL_USEC 64 513 514 /* The two bytes Marvell header. Either contains a special value used 515 * by Marvell switches when a specific hardware mode is enabled (not 516 * supported by this driver) or is filled automatically by zeroes on 517 * the RX side. Those two bytes being at the front of the Ethernet 518 * header, they allow to have the IP header aligned on a 4 bytes 519 * boundary automatically: the hardware skips those two bytes on its 520 * own. 521 */ 522 #define MVPP2_MH_SIZE 2 523 #define MVPP2_ETH_TYPE_LEN 2 524 #define MVPP2_PPPOE_HDR_SIZE 8 525 #define MVPP2_VLAN_TAG_LEN 4 526 #define MVPP2_VLAN_TAG_EDSA_LEN 8 527 528 /* Lbtd 802.3 type */ 529 #define MVPP2_IP_LBDT_TYPE 0xfffa 530 531 #define MVPP2_TX_CSUM_MAX_SIZE 9800 532 533 /* Timeout constants */ 534 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 535 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 536 537 #define MVPP2_TX_MTU_MAX 0x7ffff 538 539 /* Maximum number of T-CONTs of PON port */ 540 #define MVPP2_MAX_TCONT 16 541 542 /* Maximum number of supported ports */ 543 #define MVPP2_MAX_PORTS 4 544 545 /* Maximum number of TXQs used by single port */ 546 #define MVPP2_MAX_TXQ 8 547 548 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 549 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 550 * multiply this value by two to count the maximum number of skb descs needed. 551 */ 552 #define MVPP2_MAX_TSO_SEGS 300 553 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 554 555 /* Max number of RXQs per port */ 556 #define MVPP2_PORT_MAX_RXQ 32 557 558 /* Max number of Rx descriptors */ 559 #define MVPP2_MAX_RXD_MAX 1024 560 #define MVPP2_MAX_RXD_DFLT 128 561 562 /* Max number of Tx descriptors */ 563 #define MVPP2_MAX_TXD_MAX 2048 564 #define MVPP2_MAX_TXD_DFLT 1024 565 566 /* Amount of Tx descriptors that can be reserved at once by CPU */ 567 #define MVPP2_CPU_DESC_CHUNK 64 568 569 /* Max number of Tx descriptors in each aggregated queue */ 570 #define MVPP2_AGGR_TXQ_SIZE 256 571 572 /* Descriptor aligned size */ 573 #define MVPP2_DESC_ALIGNED_SIZE 32 574 575 /* Descriptor alignment mask */ 576 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 577 578 /* RX FIFO constants */ 579 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 580 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 581 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 582 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 583 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 584 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 585 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 586 587 /* TX FIFO constants */ 588 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 589 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 590 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 591 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 592 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 593 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 594 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 595 596 /* RX buffer constants */ 597 #define MVPP2_SKB_SHINFO_SIZE \ 598 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 599 600 #define MVPP2_RX_PKT_SIZE(mtu) \ 601 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 602 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 603 604 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 605 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 606 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 607 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) 608 609 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 610 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 611 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 612 613 /* RSS constants */ 614 #define MVPP22_RSS_TABLE_ENTRIES 32 615 616 /* IPv6 max L3 address size */ 617 #define MVPP2_MAX_L3_ADDR_SIZE 16 618 619 /* Port flags */ 620 #define MVPP2_F_LOOPBACK BIT(0) 621 #define MVPP2_F_DT_COMPAT BIT(1) 622 623 /* Marvell tag types */ 624 enum mvpp2_tag_type { 625 MVPP2_TAG_TYPE_NONE = 0, 626 MVPP2_TAG_TYPE_MH = 1, 627 MVPP2_TAG_TYPE_DSA = 2, 628 MVPP2_TAG_TYPE_EDSA = 3, 629 MVPP2_TAG_TYPE_VLAN = 4, 630 MVPP2_TAG_TYPE_LAST = 5 631 }; 632 633 /* L2 cast enum */ 634 enum mvpp2_prs_l2_cast { 635 MVPP2_PRS_L2_UNI_CAST, 636 MVPP2_PRS_L2_MULTI_CAST, 637 }; 638 639 /* L3 cast enum */ 640 enum mvpp2_prs_l3_cast { 641 MVPP2_PRS_L3_UNI_CAST, 642 MVPP2_PRS_L3_MULTI_CAST, 643 MVPP2_PRS_L3_BROAD_CAST 644 }; 645 646 /* BM constants */ 647 #define MVPP2_BM_JUMBO_BUF_NUM 512 648 #define MVPP2_BM_LONG_BUF_NUM 1024 649 #define MVPP2_BM_SHORT_BUF_NUM 2048 650 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 651 #define MVPP2_BM_POOL_PTR_ALIGN 128 652 653 /* BM cookie (32 bits) definition */ 654 #define MVPP2_BM_COOKIE_POOL_OFFS 8 655 #define MVPP2_BM_COOKIE_CPU_OFFS 24 656 657 #define MVPP2_BM_SHORT_FRAME_SIZE 512 658 #define MVPP2_BM_LONG_FRAME_SIZE 2048 659 #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 660 /* BM short pool packet size 661 * These value assure that for SWF the total number 662 * of bytes allocated for each buffer will be 512 663 */ 664 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 665 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 666 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 667 668 #define MVPP21_ADDR_SPACE_SZ 0 669 #define MVPP22_ADDR_SPACE_SZ SZ_64K 670 671 #define MVPP2_MAX_THREADS 9 672 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 673 674 /* GMAC MIB Counters register definitions */ 675 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 676 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 677 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 678 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 679 680 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 681 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 682 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 683 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 684 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 685 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 686 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 687 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 688 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 689 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 690 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 691 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 692 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 693 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 694 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 695 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 696 #define MVPP2_MIB_FC_SENT 0x54 697 #define MVPP2_MIB_FC_RCVD 0x58 698 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 699 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 700 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 701 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 702 #define MVPP2_MIB_JABBER_RCVD 0x6c 703 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 704 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 705 #define MVPP2_MIB_COLLISION 0x78 706 #define MVPP2_MIB_LATE_COLLISION 0x7c 707 708 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 709 710 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 711 712 /* Definitions */ 713 714 /* Shared Packet Processor resources */ 715 struct mvpp2 { 716 /* Shared registers' base addresses */ 717 void __iomem *lms_base; 718 void __iomem *iface_base; 719 720 /* On PPv2.2, each "software thread" can access the base 721 * register through a separate address space, each 64 KB apart 722 * from each other. Typically, such address spaces will be 723 * used per CPU. 724 */ 725 void __iomem *swth_base[MVPP2_MAX_THREADS]; 726 727 /* On PPv2.2, some port control registers are located into the system 728 * controller space. These registers are accessible through a regmap. 729 */ 730 struct regmap *sysctrl_base; 731 732 /* Common clocks */ 733 struct clk *pp_clk; 734 struct clk *gop_clk; 735 struct clk *mg_clk; 736 struct clk *mg_core_clk; 737 struct clk *axi_clk; 738 739 /* List of pointers to port structures */ 740 int port_count; 741 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 742 743 /* Number of Tx threads used */ 744 unsigned int nthreads; 745 /* Map of threads needing locking */ 746 unsigned long lock_map; 747 748 /* Aggregated TXQs */ 749 struct mvpp2_tx_queue *aggr_txqs; 750 751 /* BM pools */ 752 struct mvpp2_bm_pool *bm_pools; 753 754 /* PRS shadow table */ 755 struct mvpp2_prs_shadow *prs_shadow; 756 /* PRS auxiliary table for double vlan entries control */ 757 bool *prs_double_vlans; 758 759 /* Tclk value */ 760 u32 tclk; 761 762 /* HW version */ 763 enum { MVPP21, MVPP22 } hw_version; 764 765 /* Maximum number of RXQs per port */ 766 unsigned int max_port_rxqs; 767 768 /* Workqueue to gather hardware statistics */ 769 char queue_name[30]; 770 struct workqueue_struct *stats_queue; 771 772 /* Debugfs root entry */ 773 struct dentry *dbgfs_dir; 774 }; 775 776 struct mvpp2_pcpu_stats { 777 struct u64_stats_sync syncp; 778 u64 rx_packets; 779 u64 rx_bytes; 780 u64 tx_packets; 781 u64 tx_bytes; 782 }; 783 784 /* Per-CPU port control */ 785 struct mvpp2_port_pcpu { 786 struct hrtimer tx_done_timer; 787 bool timer_scheduled; 788 /* Tasklet for egress finalization */ 789 struct tasklet_struct tx_done_tasklet; 790 }; 791 792 struct mvpp2_queue_vector { 793 int irq; 794 struct napi_struct napi; 795 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 796 int sw_thread_id; 797 u16 sw_thread_mask; 798 int first_rxq; 799 int nrxqs; 800 u32 pending_cause_rx; 801 struct mvpp2_port *port; 802 struct cpumask *mask; 803 }; 804 805 struct mvpp2_port { 806 u8 id; 807 808 /* Index of the port from the "group of ports" complex point 809 * of view. This is specific to PPv2.2. 810 */ 811 int gop_id; 812 813 int link_irq; 814 815 struct mvpp2 *priv; 816 817 /* Firmware node associated to the port */ 818 struct fwnode_handle *fwnode; 819 820 /* Is a PHY always connected to the port */ 821 bool has_phy; 822 823 /* Per-port registers' base address */ 824 void __iomem *base; 825 void __iomem *stats_base; 826 827 struct mvpp2_rx_queue **rxqs; 828 unsigned int nrxqs; 829 struct mvpp2_tx_queue **txqs; 830 unsigned int ntxqs; 831 struct net_device *dev; 832 833 int pkt_size; 834 835 /* Per-CPU port control */ 836 struct mvpp2_port_pcpu __percpu *pcpu; 837 838 /* Protect the BM refills and the Tx paths when a thread is used on more 839 * than a single CPU. 840 */ 841 spinlock_t bm_lock[MVPP2_MAX_THREADS]; 842 spinlock_t tx_lock[MVPP2_MAX_THREADS]; 843 844 /* Flags */ 845 unsigned long flags; 846 847 u16 tx_ring_size; 848 u16 rx_ring_size; 849 struct mvpp2_pcpu_stats __percpu *stats; 850 u64 *ethtool_stats; 851 852 /* Per-port work and its lock to gather hardware statistics */ 853 struct mutex gather_stats_lock; 854 struct delayed_work stats_work; 855 856 struct device_node *of_node; 857 858 phy_interface_t phy_interface; 859 struct phylink *phylink; 860 struct phy *comphy; 861 862 struct mvpp2_bm_pool *pool_long; 863 struct mvpp2_bm_pool *pool_short; 864 865 /* Index of first port's physical RXQ */ 866 u8 first_rxq; 867 868 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 869 unsigned int nqvecs; 870 bool has_tx_irqs; 871 872 u32 tx_time_coal; 873 874 /* RSS indirection table */ 875 u32 indir[MVPP22_RSS_TABLE_ENTRIES]; 876 }; 877 878 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 879 * layout of the transmit and reception DMA descriptors, and their 880 * layout is therefore defined by the hardware design 881 */ 882 883 #define MVPP2_TXD_L3_OFF_SHIFT 0 884 #define MVPP2_TXD_IP_HLEN_SHIFT 8 885 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 886 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 887 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 888 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 889 #define MVPP2_TXD_L4_UDP BIT(24) 890 #define MVPP2_TXD_L3_IP6 BIT(26) 891 #define MVPP2_TXD_L_DESC BIT(28) 892 #define MVPP2_TXD_F_DESC BIT(29) 893 894 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 895 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 896 #define MVPP2_RXD_ERR_CRC 0x0 897 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 898 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 899 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 900 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 901 #define MVPP2_RXD_HWF_SYNC BIT(21) 902 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 903 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 904 #define MVPP2_RXD_L4_TCP BIT(25) 905 #define MVPP2_RXD_L4_UDP BIT(26) 906 #define MVPP2_RXD_L3_IP4 BIT(28) 907 #define MVPP2_RXD_L3_IP6 BIT(30) 908 #define MVPP2_RXD_BUF_HDR BIT(31) 909 910 /* HW TX descriptor for PPv2.1 */ 911 struct mvpp21_tx_desc { 912 __le32 command; /* Options used by HW for packet transmitting.*/ 913 u8 packet_offset; /* the offset from the buffer beginning */ 914 u8 phys_txq; /* destination queue ID */ 915 __le16 data_size; /* data size of transmitted packet in bytes */ 916 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 917 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 918 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 919 __le32 reserved2; /* reserved (for future use) */ 920 }; 921 922 /* HW RX descriptor for PPv2.1 */ 923 struct mvpp21_rx_desc { 924 __le32 status; /* info about received packet */ 925 __le16 reserved1; /* parser_info (for future use, PnC) */ 926 __le16 data_size; /* size of received packet in bytes */ 927 __le32 buf_dma_addr; /* physical address of the buffer */ 928 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 929 __le16 reserved2; /* gem_port_id (for future use, PON) */ 930 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 931 u8 reserved4; /* bm_qset (for future use, BM) */ 932 u8 reserved5; 933 __le16 reserved6; /* classify_info (for future use, PnC) */ 934 __le32 reserved7; /* flow_id (for future use, PnC) */ 935 __le32 reserved8; 936 }; 937 938 /* HW TX descriptor for PPv2.2 */ 939 struct mvpp22_tx_desc { 940 __le32 command; 941 u8 packet_offset; 942 u8 phys_txq; 943 __le16 data_size; 944 __le64 reserved1; 945 __le64 buf_dma_addr_ptp; 946 __le64 buf_cookie_misc; 947 }; 948 949 /* HW RX descriptor for PPv2.2 */ 950 struct mvpp22_rx_desc { 951 __le32 status; 952 __le16 reserved1; 953 __le16 data_size; 954 __le32 reserved2; 955 __le32 reserved3; 956 __le64 buf_dma_addr_key_hash; 957 __le64 buf_cookie_misc; 958 }; 959 960 /* Opaque type used by the driver to manipulate the HW TX and RX 961 * descriptors 962 */ 963 struct mvpp2_tx_desc { 964 union { 965 struct mvpp21_tx_desc pp21; 966 struct mvpp22_tx_desc pp22; 967 }; 968 }; 969 970 struct mvpp2_rx_desc { 971 union { 972 struct mvpp21_rx_desc pp21; 973 struct mvpp22_rx_desc pp22; 974 }; 975 }; 976 977 struct mvpp2_txq_pcpu_buf { 978 /* Transmitted SKB */ 979 struct sk_buff *skb; 980 981 /* Physical address of transmitted buffer */ 982 dma_addr_t dma; 983 984 /* Size transmitted */ 985 size_t size; 986 }; 987 988 /* Per-CPU Tx queue control */ 989 struct mvpp2_txq_pcpu { 990 unsigned int thread; 991 992 /* Number of Tx DMA descriptors in the descriptor ring */ 993 int size; 994 995 /* Number of currently used Tx DMA descriptor in the 996 * descriptor ring 997 */ 998 int count; 999 1000 int wake_threshold; 1001 int stop_threshold; 1002 1003 /* Number of Tx DMA descriptors reserved for each CPU */ 1004 int reserved_num; 1005 1006 /* Infos about transmitted buffers */ 1007 struct mvpp2_txq_pcpu_buf *buffs; 1008 1009 /* Index of last TX DMA descriptor that was inserted */ 1010 int txq_put_index; 1011 1012 /* Index of the TX DMA descriptor to be cleaned up */ 1013 int txq_get_index; 1014 1015 /* DMA buffer for TSO headers */ 1016 char *tso_headers; 1017 dma_addr_t tso_headers_dma; 1018 }; 1019 1020 struct mvpp2_tx_queue { 1021 /* Physical number of this Tx queue */ 1022 u8 id; 1023 1024 /* Logical number of this Tx queue */ 1025 u8 log_id; 1026 1027 /* Number of Tx DMA descriptors in the descriptor ring */ 1028 int size; 1029 1030 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 1031 int count; 1032 1033 /* Per-CPU control of physical Tx queues */ 1034 struct mvpp2_txq_pcpu __percpu *pcpu; 1035 1036 u32 done_pkts_coal; 1037 1038 /* Virtual address of thex Tx DMA descriptors array */ 1039 struct mvpp2_tx_desc *descs; 1040 1041 /* DMA address of the Tx DMA descriptors array */ 1042 dma_addr_t descs_dma; 1043 1044 /* Index of the last Tx DMA descriptor */ 1045 int last_desc; 1046 1047 /* Index of the next Tx DMA descriptor to process */ 1048 int next_desc_to_proc; 1049 }; 1050 1051 struct mvpp2_rx_queue { 1052 /* RX queue number, in the range 0-31 for physical RXQs */ 1053 u8 id; 1054 1055 /* Num of rx descriptors in the rx descriptor ring */ 1056 int size; 1057 1058 u32 pkts_coal; 1059 u32 time_coal; 1060 1061 /* Virtual address of the RX DMA descriptors array */ 1062 struct mvpp2_rx_desc *descs; 1063 1064 /* DMA address of the RX DMA descriptors array */ 1065 dma_addr_t descs_dma; 1066 1067 /* Index of the last RX DMA descriptor */ 1068 int last_desc; 1069 1070 /* Index of the next RX DMA descriptor to process */ 1071 int next_desc_to_proc; 1072 1073 /* ID of port to which physical RXQ is mapped */ 1074 int port; 1075 1076 /* Port's logic RXQ number to which physical RXQ is mapped */ 1077 int logic_rxq; 1078 }; 1079 1080 struct mvpp2_bm_pool { 1081 /* Pool number in the range 0-7 */ 1082 int id; 1083 1084 /* Buffer Pointers Pool External (BPPE) size */ 1085 int size; 1086 /* BPPE size in bytes */ 1087 int size_bytes; 1088 /* Number of buffers for this pool */ 1089 int buf_num; 1090 /* Pool buffer size */ 1091 int buf_size; 1092 /* Packet size */ 1093 int pkt_size; 1094 int frag_size; 1095 1096 /* BPPE virtual base address */ 1097 u32 *virt_addr; 1098 /* BPPE DMA base address */ 1099 dma_addr_t dma_addr; 1100 1101 /* Ports using BM pool */ 1102 u32 port_map; 1103 }; 1104 1105 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1106 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1107 (addr) < (txq_pcpu)->tso_headers_dma + \ 1108 (txq_pcpu)->size * TSO_HEADER_SIZE) 1109 1110 #define MVPP2_DRIVER_NAME "mvpp2" 1111 #define MVPP2_DRIVER_VERSION "1.0" 1112 1113 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1114 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1115 1116 void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); 1117 1118 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); 1119 1120 #endif 1121