1 /* 2 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Marcin Wojtas <mw@semihalf.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 #ifndef _MVPP2_H_ 13 #define _MVPP2_H_ 14 15 #include <linux/kernel.h> 16 #include <linux/netdevice.h> 17 #include <linux/phy.h> 18 #include <linux/phylink.h> 19 20 /* Fifo Registers */ 21 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 22 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 23 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 24 #define MVPP2_RX_FIFO_INIT_REG 0x64 25 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 26 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 27 28 /* RX DMA Top Registers */ 29 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 30 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 31 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 32 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 33 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 34 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 35 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 36 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 37 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 38 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 39 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 40 #define MVPP2_RXQ_POOL_LONG_OFFS 24 41 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 42 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 43 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 44 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 45 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 46 47 /* Top Registers */ 48 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 49 #define MVPP2_DSA_EXTENDED BIT(5) 50 51 /* Parser Registers */ 52 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 53 #define MVPP2_PRS_PORT_LU_MAX 0xf 54 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 55 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 56 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 57 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 58 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 59 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 60 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 61 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 62 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 63 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 64 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 65 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 66 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 67 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 68 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 69 70 /* RSS Registers */ 71 #define MVPP22_RSS_INDEX 0x1500 72 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 73 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 74 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 75 #define MVPP22_RSS_TABLE_ENTRY 0x1508 76 #define MVPP22_RSS_TABLE 0x1510 77 #define MVPP22_RSS_TABLE_POINTER(p) (p) 78 #define MVPP22_RSS_WIDTH 0x150c 79 80 /* Classifier Registers */ 81 #define MVPP2_CLS_MODE_REG 0x1800 82 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 83 #define MVPP2_CLS_PORT_WAY_REG 0x1810 84 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 85 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 86 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 87 #define MVPP2_CLS_LKP_TBL_REG 0x1818 88 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 89 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 90 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 91 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 92 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 93 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 94 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 95 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 96 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 97 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 98 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 99 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 100 101 /* Descriptor Manager Top Registers */ 102 #define MVPP2_RXQ_NUM_REG 0x2040 103 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 104 #define MVPP22_DESC_ADDR_OFFS 8 105 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 106 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 107 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 108 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 109 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 110 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 111 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 112 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 113 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 114 #define MVPP2_RXQ_THRESH_REG 0x204c 115 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 116 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 117 #define MVPP2_RXQ_INDEX_REG 0x2050 118 #define MVPP2_TXQ_NUM_REG 0x2080 119 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 120 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 121 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 122 #define MVPP2_TXQ_THRESH_REG 0x2094 123 #define MVPP2_TXQ_THRESH_OFFSET 16 124 #define MVPP2_TXQ_THRESH_MASK 0x3fff 125 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 126 #define MVPP2_TXQ_INDEX_REG 0x2098 127 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 128 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 129 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 130 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 131 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 132 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 133 #define MVPP2_TXQ_PENDING_REG 0x20a0 134 #define MVPP2_TXQ_PENDING_MASK 0x3fff 135 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 136 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 137 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 138 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 139 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 140 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 141 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 142 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 143 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 144 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 145 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 146 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 147 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 148 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 149 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 150 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 151 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 152 153 /* MBUS bridge registers */ 154 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 155 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 156 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 157 #define MVPP2_BASE_ADDR_ENABLE 0x4060 158 159 /* AXI Bridge Registers */ 160 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 161 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 162 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 163 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 164 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 165 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 166 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 167 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 168 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 169 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 170 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 171 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 172 173 /* Values for AXI Bridge registers */ 174 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 175 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 176 177 #define MVPP22_AXI_CODE_CACHE_OFFS 0 178 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 179 180 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 181 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 182 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 183 184 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 185 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 186 187 /* Interrupt Cause and Mask registers */ 188 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 189 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 190 191 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 192 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 193 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 194 195 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 196 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 197 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 198 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 199 200 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 201 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 202 203 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 204 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 205 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 206 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 207 208 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 209 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 210 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 211 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 212 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 213 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 214 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 215 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 216 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 217 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 218 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 219 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 220 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 221 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 222 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 223 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 224 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 225 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 226 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 227 228 /* Buffer Manager registers */ 229 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 230 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 231 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 232 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 233 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 234 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 235 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 236 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 237 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 238 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 239 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 240 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 241 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 242 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 243 #define MVPP2_BM_START_MASK BIT(0) 244 #define MVPP2_BM_STOP_MASK BIT(1) 245 #define MVPP2_BM_STATE_MASK BIT(4) 246 #define MVPP2_BM_LOW_THRESH_OFFS 8 247 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 248 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 249 MVPP2_BM_LOW_THRESH_OFFS) 250 #define MVPP2_BM_HIGH_THRESH_OFFS 16 251 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 252 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 253 MVPP2_BM_HIGH_THRESH_OFFS) 254 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 255 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 256 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 257 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 258 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 259 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 260 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 261 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 262 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 263 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 264 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 265 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 266 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 267 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 268 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 269 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 270 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 271 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 272 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 273 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 274 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 275 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 276 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 277 278 /* TX Scheduler registers */ 279 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 280 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 281 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 282 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 283 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 284 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 285 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 286 #define MVPP2_TXP_MTU_MAX 0x7FFFF 287 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 288 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 289 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 290 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 291 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 292 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 293 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 294 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 295 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 296 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 297 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 298 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 299 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 300 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 301 302 /* TX general registers */ 303 #define MVPP2_TX_SNOOP_REG 0x8800 304 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 305 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 306 307 /* LMS registers */ 308 #define MVPP2_SRC_ADDR_MIDDLE 0x24 309 #define MVPP2_SRC_ADDR_HIGH 0x28 310 #define MVPP2_PHY_AN_CFG0_REG 0x34 311 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 312 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 313 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 314 315 /* Per-port registers */ 316 #define MVPP2_GMAC_CTRL_0_REG 0x0 317 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 318 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 319 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 320 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 321 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 322 #define MVPP2_GMAC_CTRL_1_REG 0x4 323 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 324 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 325 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 326 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 327 #define MVPP2_GMAC_SA_LOW_OFFS 7 328 #define MVPP2_GMAC_CTRL_2_REG 0x8 329 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 330 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 331 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 332 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 333 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 334 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 335 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 336 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 337 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 338 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 339 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 340 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 341 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 342 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 343 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 344 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 345 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 346 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 347 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 348 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 349 #define MVPP2_GMAC_STATUS0 0x10 350 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 351 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 352 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 353 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 354 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6) 355 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7) 356 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 357 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 358 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 359 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 360 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 361 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 362 #define MVPP22_GMAC_INT_STAT 0x20 363 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 364 #define MVPP22_GMAC_INT_MASK 0x24 365 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 366 #define MVPP22_GMAC_CTRL_4_REG 0x90 367 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 368 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 369 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 370 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 371 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 372 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 373 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 374 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 375 376 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 377 * relative to port->base. 378 */ 379 #define MVPP22_XLG_CTRL0_REG 0x100 380 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 381 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 382 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 383 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 384 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 385 #define MVPP22_XLG_CTRL1_REG 0x104 386 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 387 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 388 #define MVPP22_XLG_STATUS 0x10c 389 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 390 #define MVPP22_XLG_INT_STAT 0x114 391 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 392 #define MVPP22_XLG_INT_MASK 0x118 393 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 394 #define MVPP22_XLG_CTRL3_REG 0x11c 395 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 396 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 397 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 398 #define MVPP22_XLG_EXT_INT_MASK 0x15c 399 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 400 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 401 #define MVPP22_XLG_CTRL4_REG 0x184 402 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 403 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 404 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 405 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 406 407 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 408 #define MVPP22_SMI_MISC_CFG_REG 0x1204 409 #define MVPP22_SMI_POLLING_EN BIT(10) 410 411 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 412 413 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 414 415 /* Descriptor ring Macros */ 416 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 417 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 418 419 /* XPCS registers. PPv2.2 only */ 420 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 421 #define MVPP22_MPCS_CTRL 0x14 422 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 423 #define MVPP22_MPCS_CLK_RESET 0x14c 424 #define MAC_CLK_RESET_SD_TX BIT(0) 425 #define MAC_CLK_RESET_SD_RX BIT(1) 426 #define MAC_CLK_RESET_MAC BIT(2) 427 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 428 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 429 430 /* XPCS registers. PPv2.2 only */ 431 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 432 #define MVPP22_XPCS_CFG0 0x0 433 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 434 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 435 436 /* System controller registers. Accessed through a regmap. */ 437 #define GENCONF_SOFT_RESET1 0x1108 438 #define GENCONF_SOFT_RESET1_GOP BIT(6) 439 #define GENCONF_PORT_CTRL0 0x1110 440 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 441 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 442 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 443 #define GENCONF_PORT_CTRL1 0x1114 444 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 445 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 446 #define GENCONF_CTRL0 0x1120 447 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 448 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 449 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 450 451 /* Various constants */ 452 453 /* Coalescing */ 454 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 455 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 456 #define MVPP2_TXDONE_COAL_USEC 1000 457 #define MVPP2_RX_COAL_PKTS 32 458 #define MVPP2_RX_COAL_USEC 64 459 460 /* The two bytes Marvell header. Either contains a special value used 461 * by Marvell switches when a specific hardware mode is enabled (not 462 * supported by this driver) or is filled automatically by zeroes on 463 * the RX side. Those two bytes being at the front of the Ethernet 464 * header, they allow to have the IP header aligned on a 4 bytes 465 * boundary automatically: the hardware skips those two bytes on its 466 * own. 467 */ 468 #define MVPP2_MH_SIZE 2 469 #define MVPP2_ETH_TYPE_LEN 2 470 #define MVPP2_PPPOE_HDR_SIZE 8 471 #define MVPP2_VLAN_TAG_LEN 4 472 #define MVPP2_VLAN_TAG_EDSA_LEN 8 473 474 /* Lbtd 802.3 type */ 475 #define MVPP2_IP_LBDT_TYPE 0xfffa 476 477 #define MVPP2_TX_CSUM_MAX_SIZE 9800 478 479 /* Timeout constants */ 480 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 481 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 482 483 #define MVPP2_TX_MTU_MAX 0x7ffff 484 485 /* Maximum number of T-CONTs of PON port */ 486 #define MVPP2_MAX_TCONT 16 487 488 /* Maximum number of supported ports */ 489 #define MVPP2_MAX_PORTS 4 490 491 /* Maximum number of TXQs used by single port */ 492 #define MVPP2_MAX_TXQ 8 493 494 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 495 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 496 * multiply this value by two to count the maximum number of skb descs needed. 497 */ 498 #define MVPP2_MAX_TSO_SEGS 300 499 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 500 501 /* Dfault number of RXQs in use */ 502 #define MVPP2_DEFAULT_RXQ 4 503 504 /* Max number of Rx descriptors */ 505 #define MVPP2_MAX_RXD_MAX 1024 506 #define MVPP2_MAX_RXD_DFLT 128 507 508 /* Max number of Tx descriptors */ 509 #define MVPP2_MAX_TXD_MAX 2048 510 #define MVPP2_MAX_TXD_DFLT 1024 511 512 /* Amount of Tx descriptors that can be reserved at once by CPU */ 513 #define MVPP2_CPU_DESC_CHUNK 64 514 515 /* Max number of Tx descriptors in each aggregated queue */ 516 #define MVPP2_AGGR_TXQ_SIZE 256 517 518 /* Descriptor aligned size */ 519 #define MVPP2_DESC_ALIGNED_SIZE 32 520 521 /* Descriptor alignment mask */ 522 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 523 524 /* RX FIFO constants */ 525 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 526 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 527 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 528 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 529 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 530 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 531 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 532 533 /* TX FIFO constants */ 534 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 535 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 536 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 537 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 538 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 539 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 540 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 541 542 /* RX buffer constants */ 543 #define MVPP2_SKB_SHINFO_SIZE \ 544 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 545 546 #define MVPP2_RX_PKT_SIZE(mtu) \ 547 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 548 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 549 550 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 551 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 552 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 553 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) 554 555 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 556 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 557 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 558 559 /* IPv6 max L3 address size */ 560 #define MVPP2_MAX_L3_ADDR_SIZE 16 561 562 /* Port flags */ 563 #define MVPP2_F_LOOPBACK BIT(0) 564 565 /* Marvell tag types */ 566 enum mvpp2_tag_type { 567 MVPP2_TAG_TYPE_NONE = 0, 568 MVPP2_TAG_TYPE_MH = 1, 569 MVPP2_TAG_TYPE_DSA = 2, 570 MVPP2_TAG_TYPE_EDSA = 3, 571 MVPP2_TAG_TYPE_VLAN = 4, 572 MVPP2_TAG_TYPE_LAST = 5 573 }; 574 575 /* L2 cast enum */ 576 enum mvpp2_prs_l2_cast { 577 MVPP2_PRS_L2_UNI_CAST, 578 MVPP2_PRS_L2_MULTI_CAST, 579 }; 580 581 /* L3 cast enum */ 582 enum mvpp2_prs_l3_cast { 583 MVPP2_PRS_L3_UNI_CAST, 584 MVPP2_PRS_L3_MULTI_CAST, 585 MVPP2_PRS_L3_BROAD_CAST 586 }; 587 588 /* BM constants */ 589 #define MVPP2_BM_JUMBO_BUF_NUM 512 590 #define MVPP2_BM_LONG_BUF_NUM 1024 591 #define MVPP2_BM_SHORT_BUF_NUM 2048 592 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 593 #define MVPP2_BM_POOL_PTR_ALIGN 128 594 595 /* BM cookie (32 bits) definition */ 596 #define MVPP2_BM_COOKIE_POOL_OFFS 8 597 #define MVPP2_BM_COOKIE_CPU_OFFS 24 598 599 #define MVPP2_BM_SHORT_FRAME_SIZE 512 600 #define MVPP2_BM_LONG_FRAME_SIZE 2048 601 #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 602 /* BM short pool packet size 603 * These value assure that for SWF the total number 604 * of bytes allocated for each buffer will be 512 605 */ 606 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 607 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 608 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 609 610 #define MVPP21_ADDR_SPACE_SZ 0 611 #define MVPP22_ADDR_SPACE_SZ SZ_64K 612 613 #define MVPP2_MAX_THREADS 8 614 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 615 616 /* GMAC MIB Counters register definitions */ 617 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 618 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 619 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 620 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 621 622 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 623 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 624 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 625 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 626 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 627 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 628 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 629 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 630 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 631 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 632 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 633 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 634 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 635 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 636 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 637 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 638 #define MVPP2_MIB_FC_SENT 0x54 639 #define MVPP2_MIB_FC_RCVD 0x58 640 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 641 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 642 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 643 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 644 #define MVPP2_MIB_JABBER_RCVD 0x6c 645 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 646 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 647 #define MVPP2_MIB_COLLISION 0x78 648 #define MVPP2_MIB_LATE_COLLISION 0x7c 649 650 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 651 652 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 653 654 /* Definitions */ 655 656 /* Shared Packet Processor resources */ 657 struct mvpp2 { 658 /* Shared registers' base addresses */ 659 void __iomem *lms_base; 660 void __iomem *iface_base; 661 662 /* On PPv2.2, each "software thread" can access the base 663 * register through a separate address space, each 64 KB apart 664 * from each other. Typically, such address spaces will be 665 * used per CPU. 666 */ 667 void __iomem *swth_base[MVPP2_MAX_THREADS]; 668 669 /* On PPv2.2, some port control registers are located into the system 670 * controller space. These registers are accessible through a regmap. 671 */ 672 struct regmap *sysctrl_base; 673 674 /* Common clocks */ 675 struct clk *pp_clk; 676 struct clk *gop_clk; 677 struct clk *mg_clk; 678 struct clk *mg_core_clk; 679 struct clk *axi_clk; 680 681 /* List of pointers to port structures */ 682 int port_count; 683 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 684 685 /* Aggregated TXQs */ 686 struct mvpp2_tx_queue *aggr_txqs; 687 688 /* BM pools */ 689 struct mvpp2_bm_pool *bm_pools; 690 691 /* PRS shadow table */ 692 struct mvpp2_prs_shadow *prs_shadow; 693 /* PRS auxiliary table for double vlan entries control */ 694 bool *prs_double_vlans; 695 696 /* Tclk value */ 697 u32 tclk; 698 699 /* HW version */ 700 enum { MVPP21, MVPP22 } hw_version; 701 702 /* Maximum number of RXQs per port */ 703 unsigned int max_port_rxqs; 704 705 /* Workqueue to gather hardware statistics */ 706 char queue_name[30]; 707 struct workqueue_struct *stats_queue; 708 }; 709 710 struct mvpp2_pcpu_stats { 711 struct u64_stats_sync syncp; 712 u64 rx_packets; 713 u64 rx_bytes; 714 u64 tx_packets; 715 u64 tx_bytes; 716 }; 717 718 /* Per-CPU port control */ 719 struct mvpp2_port_pcpu { 720 struct hrtimer tx_done_timer; 721 bool timer_scheduled; 722 /* Tasklet for egress finalization */ 723 struct tasklet_struct tx_done_tasklet; 724 }; 725 726 struct mvpp2_queue_vector { 727 int irq; 728 struct napi_struct napi; 729 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 730 int sw_thread_id; 731 u16 sw_thread_mask; 732 int first_rxq; 733 int nrxqs; 734 u32 pending_cause_rx; 735 struct mvpp2_port *port; 736 }; 737 738 struct mvpp2_port { 739 u8 id; 740 741 /* Index of the port from the "group of ports" complex point 742 * of view 743 */ 744 int gop_id; 745 746 int link_irq; 747 748 struct mvpp2 *priv; 749 750 /* Firmware node associated to the port */ 751 struct fwnode_handle *fwnode; 752 753 /* Is a PHY always connected to the port */ 754 bool has_phy; 755 756 /* Per-port registers' base address */ 757 void __iomem *base; 758 void __iomem *stats_base; 759 760 struct mvpp2_rx_queue **rxqs; 761 unsigned int nrxqs; 762 struct mvpp2_tx_queue **txqs; 763 unsigned int ntxqs; 764 struct net_device *dev; 765 766 int pkt_size; 767 768 /* Per-CPU port control */ 769 struct mvpp2_port_pcpu __percpu *pcpu; 770 771 /* Flags */ 772 unsigned long flags; 773 774 u16 tx_ring_size; 775 u16 rx_ring_size; 776 struct mvpp2_pcpu_stats __percpu *stats; 777 u64 *ethtool_stats; 778 779 /* Per-port work and its lock to gather hardware statistics */ 780 struct mutex gather_stats_lock; 781 struct delayed_work stats_work; 782 783 struct device_node *of_node; 784 785 phy_interface_t phy_interface; 786 struct phylink *phylink; 787 struct phy *comphy; 788 789 struct mvpp2_bm_pool *pool_long; 790 struct mvpp2_bm_pool *pool_short; 791 792 /* Index of first port's physical RXQ */ 793 u8 first_rxq; 794 795 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 796 unsigned int nqvecs; 797 bool has_tx_irqs; 798 799 u32 tx_time_coal; 800 }; 801 802 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 803 * layout of the transmit and reception DMA descriptors, and their 804 * layout is therefore defined by the hardware design 805 */ 806 807 #define MVPP2_TXD_L3_OFF_SHIFT 0 808 #define MVPP2_TXD_IP_HLEN_SHIFT 8 809 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 810 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 811 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 812 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 813 #define MVPP2_TXD_L4_UDP BIT(24) 814 #define MVPP2_TXD_L3_IP6 BIT(26) 815 #define MVPP2_TXD_L_DESC BIT(28) 816 #define MVPP2_TXD_F_DESC BIT(29) 817 818 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 819 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 820 #define MVPP2_RXD_ERR_CRC 0x0 821 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 822 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 823 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 824 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 825 #define MVPP2_RXD_HWF_SYNC BIT(21) 826 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 827 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 828 #define MVPP2_RXD_L4_TCP BIT(25) 829 #define MVPP2_RXD_L4_UDP BIT(26) 830 #define MVPP2_RXD_L3_IP4 BIT(28) 831 #define MVPP2_RXD_L3_IP6 BIT(30) 832 #define MVPP2_RXD_BUF_HDR BIT(31) 833 834 /* HW TX descriptor for PPv2.1 */ 835 struct mvpp21_tx_desc { 836 __le32 command; /* Options used by HW for packet transmitting.*/ 837 u8 packet_offset; /* the offset from the buffer beginning */ 838 u8 phys_txq; /* destination queue ID */ 839 __le16 data_size; /* data size of transmitted packet in bytes */ 840 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 841 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 842 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 843 __le32 reserved2; /* reserved (for future use) */ 844 }; 845 846 /* HW RX descriptor for PPv2.1 */ 847 struct mvpp21_rx_desc { 848 __le32 status; /* info about received packet */ 849 __le16 reserved1; /* parser_info (for future use, PnC) */ 850 __le16 data_size; /* size of received packet in bytes */ 851 __le32 buf_dma_addr; /* physical address of the buffer */ 852 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 853 __le16 reserved2; /* gem_port_id (for future use, PON) */ 854 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 855 u8 reserved4; /* bm_qset (for future use, BM) */ 856 u8 reserved5; 857 __le16 reserved6; /* classify_info (for future use, PnC) */ 858 __le32 reserved7; /* flow_id (for future use, PnC) */ 859 __le32 reserved8; 860 }; 861 862 /* HW TX descriptor for PPv2.2 */ 863 struct mvpp22_tx_desc { 864 __le32 command; 865 u8 packet_offset; 866 u8 phys_txq; 867 __le16 data_size; 868 __le64 reserved1; 869 __le64 buf_dma_addr_ptp; 870 __le64 buf_cookie_misc; 871 }; 872 873 /* HW RX descriptor for PPv2.2 */ 874 struct mvpp22_rx_desc { 875 __le32 status; 876 __le16 reserved1; 877 __le16 data_size; 878 __le32 reserved2; 879 __le32 reserved3; 880 __le64 buf_dma_addr_key_hash; 881 __le64 buf_cookie_misc; 882 }; 883 884 /* Opaque type used by the driver to manipulate the HW TX and RX 885 * descriptors 886 */ 887 struct mvpp2_tx_desc { 888 union { 889 struct mvpp21_tx_desc pp21; 890 struct mvpp22_tx_desc pp22; 891 }; 892 }; 893 894 struct mvpp2_rx_desc { 895 union { 896 struct mvpp21_rx_desc pp21; 897 struct mvpp22_rx_desc pp22; 898 }; 899 }; 900 901 struct mvpp2_txq_pcpu_buf { 902 /* Transmitted SKB */ 903 struct sk_buff *skb; 904 905 /* Physical address of transmitted buffer */ 906 dma_addr_t dma; 907 908 /* Size transmitted */ 909 size_t size; 910 }; 911 912 /* Per-CPU Tx queue control */ 913 struct mvpp2_txq_pcpu { 914 int cpu; 915 916 /* Number of Tx DMA descriptors in the descriptor ring */ 917 int size; 918 919 /* Number of currently used Tx DMA descriptor in the 920 * descriptor ring 921 */ 922 int count; 923 924 int wake_threshold; 925 int stop_threshold; 926 927 /* Number of Tx DMA descriptors reserved for each CPU */ 928 int reserved_num; 929 930 /* Infos about transmitted buffers */ 931 struct mvpp2_txq_pcpu_buf *buffs; 932 933 /* Index of last TX DMA descriptor that was inserted */ 934 int txq_put_index; 935 936 /* Index of the TX DMA descriptor to be cleaned up */ 937 int txq_get_index; 938 939 /* DMA buffer for TSO headers */ 940 char *tso_headers; 941 dma_addr_t tso_headers_dma; 942 }; 943 944 struct mvpp2_tx_queue { 945 /* Physical number of this Tx queue */ 946 u8 id; 947 948 /* Logical number of this Tx queue */ 949 u8 log_id; 950 951 /* Number of Tx DMA descriptors in the descriptor ring */ 952 int size; 953 954 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 955 int count; 956 957 /* Per-CPU control of physical Tx queues */ 958 struct mvpp2_txq_pcpu __percpu *pcpu; 959 960 u32 done_pkts_coal; 961 962 /* Virtual address of thex Tx DMA descriptors array */ 963 struct mvpp2_tx_desc *descs; 964 965 /* DMA address of the Tx DMA descriptors array */ 966 dma_addr_t descs_dma; 967 968 /* Index of the last Tx DMA descriptor */ 969 int last_desc; 970 971 /* Index of the next Tx DMA descriptor to process */ 972 int next_desc_to_proc; 973 }; 974 975 struct mvpp2_rx_queue { 976 /* RX queue number, in the range 0-31 for physical RXQs */ 977 u8 id; 978 979 /* Num of rx descriptors in the rx descriptor ring */ 980 int size; 981 982 u32 pkts_coal; 983 u32 time_coal; 984 985 /* Virtual address of the RX DMA descriptors array */ 986 struct mvpp2_rx_desc *descs; 987 988 /* DMA address of the RX DMA descriptors array */ 989 dma_addr_t descs_dma; 990 991 /* Index of the last RX DMA descriptor */ 992 int last_desc; 993 994 /* Index of the next RX DMA descriptor to process */ 995 int next_desc_to_proc; 996 997 /* ID of port to which physical RXQ is mapped */ 998 int port; 999 1000 /* Port's logic RXQ number to which physical RXQ is mapped */ 1001 int logic_rxq; 1002 }; 1003 1004 struct mvpp2_bm_pool { 1005 /* Pool number in the range 0-7 */ 1006 int id; 1007 1008 /* Buffer Pointers Pool External (BPPE) size */ 1009 int size; 1010 /* BPPE size in bytes */ 1011 int size_bytes; 1012 /* Number of buffers for this pool */ 1013 int buf_num; 1014 /* Pool buffer size */ 1015 int buf_size; 1016 /* Packet size */ 1017 int pkt_size; 1018 int frag_size; 1019 1020 /* BPPE virtual base address */ 1021 u32 *virt_addr; 1022 /* BPPE DMA base address */ 1023 dma_addr_t dma_addr; 1024 1025 /* Ports using BM pool */ 1026 u32 port_map; 1027 }; 1028 1029 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1030 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1031 (addr) < (txq_pcpu)->tso_headers_dma + \ 1032 (txq_pcpu)->size * TSO_HEADER_SIZE) 1033 1034 #define MVPP2_DRIVER_NAME "mvpp2" 1035 #define MVPP2_DRIVER_VERSION "1.0" 1036 1037 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1038 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1039 1040 u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset); 1041 1042 void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data); 1043 u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset); 1044 1045 void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, u32 offset, 1046 u32 data); 1047 1048 #endif 1049