1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 5 * 6 * Based on the 64360 driver from: 7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 8 * Rabeeh Khoury <rabeeh@marvell.com> 9 * 10 * Copyright (C) 2003 PMC-Sierra, Inc., 11 * written by Manish Lachwani 12 * 13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 14 * 15 * Copyright (C) 2004-2006 MontaVista Software, Inc. 16 * Dale Farnsworth <dale@farnsworth.org> 17 * 18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 19 * <sjhill@realitydiluted.com> 20 * 21 * Copyright (C) 2007-2008 Marvell Semiconductor 22 * Lennert Buytenhek <buytenh@marvell.com> 23 * 24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 25 */ 26 27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29 #include <linux/init.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/in.h> 32 #include <linux/ip.h> 33 #include <net/tso.h> 34 #include <linux/tcp.h> 35 #include <linux/udp.h> 36 #include <linux/etherdevice.h> 37 #include <linux/delay.h> 38 #include <linux/ethtool.h> 39 #include <linux/platform_device.h> 40 #include <linux/module.h> 41 #include <linux/kernel.h> 42 #include <linux/spinlock.h> 43 #include <linux/workqueue.h> 44 #include <linux/phy.h> 45 #include <linux/mv643xx_eth.h> 46 #include <linux/io.h> 47 #include <linux/interrupt.h> 48 #include <linux/types.h> 49 #include <linux/slab.h> 50 #include <linux/clk.h> 51 #include <linux/of.h> 52 #include <linux/of_irq.h> 53 #include <linux/of_net.h> 54 #include <linux/of_mdio.h> 55 56 static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 57 static char mv643xx_eth_driver_version[] = "1.4"; 58 59 60 /* 61 * Registers shared between all ports. 62 */ 63 #define PHY_ADDR 0x0000 64 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 65 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 66 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 67 #define WINDOW_BAR_ENABLE 0x0290 68 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 69 70 /* 71 * Main per-port registers. These live at offset 0x0400 for 72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 73 */ 74 #define PORT_CONFIG 0x0000 75 #define UNICAST_PROMISCUOUS_MODE 0x00000001 76 #define PORT_CONFIG_EXT 0x0004 77 #define MAC_ADDR_LOW 0x0014 78 #define MAC_ADDR_HIGH 0x0018 79 #define SDMA_CONFIG 0x001c 80 #define TX_BURST_SIZE_16_64BIT 0x01000000 81 #define TX_BURST_SIZE_4_64BIT 0x00800000 82 #define BLM_TX_NO_SWAP 0x00000020 83 #define BLM_RX_NO_SWAP 0x00000010 84 #define RX_BURST_SIZE_16_64BIT 0x00000008 85 #define RX_BURST_SIZE_4_64BIT 0x00000004 86 #define PORT_SERIAL_CONTROL 0x003c 87 #define SET_MII_SPEED_TO_100 0x01000000 88 #define SET_GMII_SPEED_TO_1000 0x00800000 89 #define SET_FULL_DUPLEX_MODE 0x00200000 90 #define MAX_RX_PACKET_9700BYTE 0x000a0000 91 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 92 #define DO_NOT_FORCE_LINK_FAIL 0x00000400 93 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 94 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 95 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 96 #define FORCE_LINK_PASS 0x00000002 97 #define SERIAL_PORT_ENABLE 0x00000001 98 #define PORT_STATUS 0x0044 99 #define TX_FIFO_EMPTY 0x00000400 100 #define TX_IN_PROGRESS 0x00000080 101 #define PORT_SPEED_MASK 0x00000030 102 #define PORT_SPEED_1000 0x00000010 103 #define PORT_SPEED_100 0x00000020 104 #define PORT_SPEED_10 0x00000000 105 #define FLOW_CONTROL_ENABLED 0x00000008 106 #define FULL_DUPLEX 0x00000004 107 #define LINK_UP 0x00000002 108 #define TXQ_COMMAND 0x0048 109 #define TXQ_FIX_PRIO_CONF 0x004c 110 #define PORT_SERIAL_CONTROL1 0x004c 111 #define RGMII_EN 0x00000008 112 #define CLK125_BYPASS_EN 0x00000010 113 #define TX_BW_RATE 0x0050 114 #define TX_BW_MTU 0x0058 115 #define TX_BW_BURST 0x005c 116 #define INT_CAUSE 0x0060 117 #define INT_TX_END 0x07f80000 118 #define INT_TX_END_0 0x00080000 119 #define INT_RX 0x000003fc 120 #define INT_RX_0 0x00000004 121 #define INT_EXT 0x00000002 122 #define INT_CAUSE_EXT 0x0064 123 #define INT_EXT_LINK_PHY 0x00110000 124 #define INT_EXT_TX 0x000000ff 125 #define INT_MASK 0x0068 126 #define INT_MASK_EXT 0x006c 127 #define TX_FIFO_URGENT_THRESHOLD 0x0074 128 #define RX_DISCARD_FRAME_CNT 0x0084 129 #define RX_OVERRUN_FRAME_CNT 0x0088 130 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 131 #define TX_BW_RATE_MOVED 0x00e0 132 #define TX_BW_MTU_MOVED 0x00e8 133 #define TX_BW_BURST_MOVED 0x00ec 134 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 135 #define RXQ_COMMAND 0x0280 136 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 137 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 138 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 139 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 140 141 /* 142 * Misc per-port registers. 143 */ 144 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 145 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 146 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 147 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 148 149 150 /* 151 * SDMA configuration register default value. 152 */ 153 #if defined(__BIG_ENDIAN) 154 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 155 (RX_BURST_SIZE_4_64BIT | \ 156 TX_BURST_SIZE_4_64BIT) 157 #elif defined(__LITTLE_ENDIAN) 158 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 159 (RX_BURST_SIZE_4_64BIT | \ 160 BLM_RX_NO_SWAP | \ 161 BLM_TX_NO_SWAP | \ 162 TX_BURST_SIZE_4_64BIT) 163 #else 164 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 165 #endif 166 167 168 /* 169 * Misc definitions. 170 */ 171 #define DEFAULT_RX_QUEUE_SIZE 128 172 #define DEFAULT_TX_QUEUE_SIZE 512 173 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 174 175 /* Max number of allowed TCP segments for software TSO */ 176 #define MV643XX_MAX_TSO_SEGS 100 177 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 178 179 #define IS_TSO_HEADER(txq, addr) \ 180 ((addr >= txq->tso_hdrs_dma) && \ 181 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 182 183 #define DESC_DMA_MAP_SINGLE 0 184 #define DESC_DMA_MAP_PAGE 1 185 186 /* 187 * RX/TX descriptors. 188 */ 189 #if defined(__BIG_ENDIAN) 190 struct rx_desc { 191 u16 byte_cnt; /* Descriptor buffer byte count */ 192 u16 buf_size; /* Buffer size */ 193 u32 cmd_sts; /* Descriptor command status */ 194 u32 next_desc_ptr; /* Next descriptor pointer */ 195 u32 buf_ptr; /* Descriptor buffer pointer */ 196 }; 197 198 struct tx_desc { 199 u16 byte_cnt; /* buffer byte count */ 200 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u32 cmd_sts; /* Command/status field */ 202 u32 next_desc_ptr; /* Pointer to next descriptor */ 203 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 204 }; 205 #elif defined(__LITTLE_ENDIAN) 206 struct rx_desc { 207 u32 cmd_sts; /* Descriptor command status */ 208 u16 buf_size; /* Buffer size */ 209 u16 byte_cnt; /* Descriptor buffer byte count */ 210 u32 buf_ptr; /* Descriptor buffer pointer */ 211 u32 next_desc_ptr; /* Next descriptor pointer */ 212 }; 213 214 struct tx_desc { 215 u32 cmd_sts; /* Command/status field */ 216 u16 l4i_chk; /* CPU provided TCP checksum */ 217 u16 byte_cnt; /* buffer byte count */ 218 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 219 u32 next_desc_ptr; /* Pointer to next descriptor */ 220 }; 221 #else 222 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 223 #endif 224 225 /* RX & TX descriptor command */ 226 #define BUFFER_OWNED_BY_DMA 0x80000000 227 228 /* RX & TX descriptor status */ 229 #define ERROR_SUMMARY 0x00000001 230 231 /* RX descriptor status */ 232 #define LAYER_4_CHECKSUM_OK 0x40000000 233 #define RX_ENABLE_INTERRUPT 0x20000000 234 #define RX_FIRST_DESC 0x08000000 235 #define RX_LAST_DESC 0x04000000 236 #define RX_IP_HDR_OK 0x02000000 237 #define RX_PKT_IS_IPV4 0x01000000 238 #define RX_PKT_IS_ETHERNETV2 0x00800000 239 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 240 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 241 #define RX_PKT_IS_VLAN_TAGGED 0x00080000 242 243 /* TX descriptor command */ 244 #define TX_ENABLE_INTERRUPT 0x00800000 245 #define GEN_CRC 0x00400000 246 #define TX_FIRST_DESC 0x00200000 247 #define TX_LAST_DESC 0x00100000 248 #define ZERO_PADDING 0x00080000 249 #define GEN_IP_V4_CHECKSUM 0x00040000 250 #define GEN_TCP_UDP_CHECKSUM 0x00020000 251 #define UDP_FRAME 0x00010000 252 #define MAC_HDR_EXTRA_4_BYTES 0x00008000 253 #define GEN_TCP_UDP_CHK_FULL 0x00000400 254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200 255 256 #define TX_IHL_SHIFT 11 257 258 259 /* global *******************************************************************/ 260 struct mv643xx_eth_shared_private { 261 /* 262 * Ethernet controller base address. 263 */ 264 void __iomem *base; 265 266 /* 267 * Per-port MBUS window access register value. 268 */ 269 u32 win_protect; 270 271 /* 272 * Hardware-specific parameters. 273 */ 274 int extended_rx_coal_limit; 275 int tx_bw_control; 276 int tx_csum_limit; 277 struct clk *clk; 278 }; 279 280 #define TX_BW_CONTROL_ABSENT 0 281 #define TX_BW_CONTROL_OLD_LAYOUT 1 282 #define TX_BW_CONTROL_NEW_LAYOUT 2 283 284 static int mv643xx_eth_open(struct net_device *dev); 285 static int mv643xx_eth_stop(struct net_device *dev); 286 287 288 /* per-port *****************************************************************/ 289 struct mib_counters { 290 u64 good_octets_received; 291 u32 bad_octets_received; 292 u32 internal_mac_transmit_err; 293 u32 good_frames_received; 294 u32 bad_frames_received; 295 u32 broadcast_frames_received; 296 u32 multicast_frames_received; 297 u32 frames_64_octets; 298 u32 frames_65_to_127_octets; 299 u32 frames_128_to_255_octets; 300 u32 frames_256_to_511_octets; 301 u32 frames_512_to_1023_octets; 302 u32 frames_1024_to_max_octets; 303 u64 good_octets_sent; 304 u32 good_frames_sent; 305 u32 excessive_collision; 306 u32 multicast_frames_sent; 307 u32 broadcast_frames_sent; 308 u32 unrec_mac_control_received; 309 u32 fc_sent; 310 u32 good_fc_received; 311 u32 bad_fc_received; 312 u32 undersize_received; 313 u32 fragments_received; 314 u32 oversize_received; 315 u32 jabber_received; 316 u32 mac_receive_error; 317 u32 bad_crc_event; 318 u32 collision; 319 u32 late_collision; 320 /* Non MIB hardware counters */ 321 u32 rx_discard; 322 u32 rx_overrun; 323 }; 324 325 struct rx_queue { 326 int index; 327 328 int rx_ring_size; 329 330 int rx_desc_count; 331 int rx_curr_desc; 332 int rx_used_desc; 333 334 struct rx_desc *rx_desc_area; 335 dma_addr_t rx_desc_dma; 336 int rx_desc_area_size; 337 struct sk_buff **rx_skb; 338 }; 339 340 struct tx_queue { 341 int index; 342 343 int tx_ring_size; 344 345 int tx_desc_count; 346 int tx_curr_desc; 347 int tx_used_desc; 348 349 int tx_stop_threshold; 350 int tx_wake_threshold; 351 352 char *tso_hdrs; 353 dma_addr_t tso_hdrs_dma; 354 355 struct tx_desc *tx_desc_area; 356 char *tx_desc_mapping; /* array to track the type of the dma mapping */ 357 dma_addr_t tx_desc_dma; 358 int tx_desc_area_size; 359 360 struct sk_buff_head tx_skb; 361 362 unsigned long tx_packets; 363 unsigned long tx_bytes; 364 unsigned long tx_dropped; 365 }; 366 367 struct mv643xx_eth_private { 368 struct mv643xx_eth_shared_private *shared; 369 void __iomem *base; 370 int port_num; 371 372 struct net_device *dev; 373 374 struct timer_list mib_counters_timer; 375 spinlock_t mib_counters_lock; 376 struct mib_counters mib_counters; 377 378 struct work_struct tx_timeout_task; 379 380 struct napi_struct napi; 381 u32 int_mask; 382 u8 oom; 383 u8 work_link; 384 u8 work_tx; 385 u8 work_tx_end; 386 u8 work_rx; 387 u8 work_rx_refill; 388 389 int skb_size; 390 391 /* 392 * RX state. 393 */ 394 int rx_ring_size; 395 unsigned long rx_desc_sram_addr; 396 int rx_desc_sram_size; 397 int rxq_count; 398 struct timer_list rx_oom; 399 struct rx_queue rxq[8]; 400 401 /* 402 * TX state. 403 */ 404 int tx_ring_size; 405 unsigned long tx_desc_sram_addr; 406 int tx_desc_sram_size; 407 int txq_count; 408 struct tx_queue txq[8]; 409 410 /* 411 * Hardware-specific parameters. 412 */ 413 struct clk *clk; 414 unsigned int t_clk; 415 }; 416 417 418 /* port register accessors **************************************************/ 419 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 420 { 421 return readl(mp->shared->base + offset); 422 } 423 424 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 425 { 426 return readl(mp->base + offset); 427 } 428 429 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 430 { 431 writel(data, mp->shared->base + offset); 432 } 433 434 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 435 { 436 writel(data, mp->base + offset); 437 } 438 439 440 /* rxq/txq helper functions *************************************************/ 441 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 442 { 443 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 444 } 445 446 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 447 { 448 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 449 } 450 451 static void rxq_enable(struct rx_queue *rxq) 452 { 453 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 454 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 455 } 456 457 static void rxq_disable(struct rx_queue *rxq) 458 { 459 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 460 u8 mask = 1 << rxq->index; 461 462 wrlp(mp, RXQ_COMMAND, mask << 8); 463 while (rdlp(mp, RXQ_COMMAND) & mask) 464 udelay(10); 465 } 466 467 static void txq_reset_hw_ptr(struct tx_queue *txq) 468 { 469 struct mv643xx_eth_private *mp = txq_to_mp(txq); 470 u32 addr; 471 472 addr = (u32)txq->tx_desc_dma; 473 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 474 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 475 } 476 477 static void txq_enable(struct tx_queue *txq) 478 { 479 struct mv643xx_eth_private *mp = txq_to_mp(txq); 480 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 481 } 482 483 static void txq_disable(struct tx_queue *txq) 484 { 485 struct mv643xx_eth_private *mp = txq_to_mp(txq); 486 u8 mask = 1 << txq->index; 487 488 wrlp(mp, TXQ_COMMAND, mask << 8); 489 while (rdlp(mp, TXQ_COMMAND) & mask) 490 udelay(10); 491 } 492 493 static void txq_maybe_wake(struct tx_queue *txq) 494 { 495 struct mv643xx_eth_private *mp = txq_to_mp(txq); 496 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 497 498 if (netif_tx_queue_stopped(nq)) { 499 __netif_tx_lock(nq, smp_processor_id()); 500 if (txq->tx_desc_count <= txq->tx_wake_threshold) 501 netif_tx_wake_queue(nq); 502 __netif_tx_unlock(nq); 503 } 504 } 505 506 static int rxq_process(struct rx_queue *rxq, int budget) 507 { 508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 509 struct net_device_stats *stats = &mp->dev->stats; 510 int rx; 511 512 rx = 0; 513 while (rx < budget && rxq->rx_desc_count) { 514 struct rx_desc *rx_desc; 515 unsigned int cmd_sts; 516 struct sk_buff *skb; 517 u16 byte_cnt; 518 519 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 520 521 cmd_sts = rx_desc->cmd_sts; 522 if (cmd_sts & BUFFER_OWNED_BY_DMA) 523 break; 524 rmb(); 525 526 skb = rxq->rx_skb[rxq->rx_curr_desc]; 527 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 528 529 rxq->rx_curr_desc++; 530 if (rxq->rx_curr_desc == rxq->rx_ring_size) 531 rxq->rx_curr_desc = 0; 532 533 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 534 rx_desc->buf_size, DMA_FROM_DEVICE); 535 rxq->rx_desc_count--; 536 rx++; 537 538 mp->work_rx_refill |= 1 << rxq->index; 539 540 byte_cnt = rx_desc->byte_cnt; 541 542 /* 543 * Update statistics. 544 * 545 * Note that the descriptor byte count includes 2 dummy 546 * bytes automatically inserted by the hardware at the 547 * start of the packet (which we don't count), and a 4 548 * byte CRC at the end of the packet (which we do count). 549 */ 550 stats->rx_packets++; 551 stats->rx_bytes += byte_cnt - 2; 552 553 /* 554 * In case we received a packet without first / last bits 555 * on, or the error summary bit is set, the packet needs 556 * to be dropped. 557 */ 558 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 559 != (RX_FIRST_DESC | RX_LAST_DESC)) 560 goto err; 561 562 /* 563 * The -4 is for the CRC in the trailer of the 564 * received packet 565 */ 566 skb_put(skb, byte_cnt - 2 - 4); 567 568 if (cmd_sts & LAYER_4_CHECKSUM_OK) 569 skb->ip_summed = CHECKSUM_UNNECESSARY; 570 skb->protocol = eth_type_trans(skb, mp->dev); 571 572 napi_gro_receive(&mp->napi, skb); 573 574 continue; 575 576 err: 577 stats->rx_dropped++; 578 579 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 580 (RX_FIRST_DESC | RX_LAST_DESC)) { 581 if (net_ratelimit()) 582 netdev_err(mp->dev, 583 "received packet spanning multiple descriptors\n"); 584 } 585 586 if (cmd_sts & ERROR_SUMMARY) 587 stats->rx_errors++; 588 589 dev_kfree_skb(skb); 590 } 591 592 if (rx < budget) 593 mp->work_rx &= ~(1 << rxq->index); 594 595 return rx; 596 } 597 598 static int rxq_refill(struct rx_queue *rxq, int budget) 599 { 600 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 601 int refilled; 602 603 refilled = 0; 604 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 605 struct sk_buff *skb; 606 int rx; 607 struct rx_desc *rx_desc; 608 int size; 609 610 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 611 612 if (skb == NULL) { 613 mp->oom = 1; 614 goto oom; 615 } 616 617 if (SKB_DMA_REALIGN) 618 skb_reserve(skb, SKB_DMA_REALIGN); 619 620 refilled++; 621 rxq->rx_desc_count++; 622 623 rx = rxq->rx_used_desc++; 624 if (rxq->rx_used_desc == rxq->rx_ring_size) 625 rxq->rx_used_desc = 0; 626 627 rx_desc = rxq->rx_desc_area + rx; 628 629 size = skb_end_pointer(skb) - skb->data; 630 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 631 skb->data, size, 632 DMA_FROM_DEVICE); 633 rx_desc->buf_size = size; 634 rxq->rx_skb[rx] = skb; 635 wmb(); 636 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 637 wmb(); 638 639 /* 640 * The hardware automatically prepends 2 bytes of 641 * dummy data to each received packet, so that the 642 * IP header ends up 16-byte aligned. 643 */ 644 skb_reserve(skb, 2); 645 } 646 647 if (refilled < budget) 648 mp->work_rx_refill &= ~(1 << rxq->index); 649 650 oom: 651 return refilled; 652 } 653 654 655 /* tx ***********************************************************************/ 656 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 657 { 658 int frag; 659 660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 661 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 662 663 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7) 664 return 1; 665 } 666 667 return 0; 668 } 669 670 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, 671 u16 *l4i_chk, u32 *command, int length) 672 { 673 int ret; 674 u32 cmd = 0; 675 676 if (skb->ip_summed == CHECKSUM_PARTIAL) { 677 int hdr_len; 678 int tag_bytes; 679 680 BUG_ON(skb->protocol != htons(ETH_P_IP) && 681 skb->protocol != htons(ETH_P_8021Q)); 682 683 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 684 tag_bytes = hdr_len - ETH_HLEN; 685 686 if (length - hdr_len > mp->shared->tx_csum_limit || 687 unlikely(tag_bytes & ~12)) { 688 ret = skb_checksum_help(skb); 689 if (!ret) 690 goto no_csum; 691 return ret; 692 } 693 694 if (tag_bytes & 4) 695 cmd |= MAC_HDR_EXTRA_4_BYTES; 696 if (tag_bytes & 8) 697 cmd |= MAC_HDR_EXTRA_8_BYTES; 698 699 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | 700 GEN_IP_V4_CHECKSUM | 701 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 702 703 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL 704 * it seems we don't need to pass the initial checksum. 705 */ 706 switch (ip_hdr(skb)->protocol) { 707 case IPPROTO_UDP: 708 cmd |= UDP_FRAME; 709 *l4i_chk = 0; 710 break; 711 case IPPROTO_TCP: 712 *l4i_chk = 0; 713 break; 714 default: 715 WARN(1, "protocol not supported"); 716 } 717 } else { 718 no_csum: 719 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 720 cmd |= 5 << TX_IHL_SHIFT; 721 } 722 *command = cmd; 723 return 0; 724 } 725 726 static inline int 727 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, 728 struct sk_buff *skb, char *data, int length, 729 bool last_tcp, bool is_last) 730 { 731 int tx_index; 732 u32 cmd_sts; 733 struct tx_desc *desc; 734 735 tx_index = txq->tx_curr_desc++; 736 if (txq->tx_curr_desc == txq->tx_ring_size) 737 txq->tx_curr_desc = 0; 738 desc = &txq->tx_desc_area[tx_index]; 739 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 740 741 desc->l4i_chk = 0; 742 desc->byte_cnt = length; 743 744 if (length <= 8 && (uintptr_t)data & 0x7) { 745 /* Copy unaligned small data fragment to TSO header data area */ 746 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE, 747 data, length); 748 desc->buf_ptr = txq->tso_hdrs_dma 749 + tx_index * TSO_HEADER_SIZE; 750 } else { 751 /* Alignment is okay, map buffer and hand off to hardware */ 752 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 753 desc->buf_ptr = dma_map_single(dev->dev.parent, data, 754 length, DMA_TO_DEVICE); 755 if (unlikely(dma_mapping_error(dev->dev.parent, 756 desc->buf_ptr))) { 757 WARN(1, "dma_map_single failed!\n"); 758 return -ENOMEM; 759 } 760 } 761 762 cmd_sts = BUFFER_OWNED_BY_DMA; 763 if (last_tcp) { 764 /* last descriptor in the TCP packet */ 765 cmd_sts |= ZERO_PADDING | TX_LAST_DESC; 766 /* last descriptor in SKB */ 767 if (is_last) 768 cmd_sts |= TX_ENABLE_INTERRUPT; 769 } 770 desc->cmd_sts = cmd_sts; 771 return 0; 772 } 773 774 static inline void 775 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length, 776 u32 *first_cmd_sts, bool first_desc) 777 { 778 struct mv643xx_eth_private *mp = txq_to_mp(txq); 779 int hdr_len = skb_tcp_all_headers(skb); 780 int tx_index; 781 struct tx_desc *desc; 782 int ret; 783 u32 cmd_csum = 0; 784 u16 l4i_chk = 0; 785 u32 cmd_sts; 786 787 tx_index = txq->tx_curr_desc; 788 desc = &txq->tx_desc_area[tx_index]; 789 790 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); 791 if (ret) 792 WARN(1, "failed to prepare checksum!"); 793 794 /* Should we set this? Can't use the value from skb_tx_csum() 795 * as it's not the correct initial L4 checksum to use. 796 */ 797 desc->l4i_chk = 0; 798 799 desc->byte_cnt = hdr_len; 800 desc->buf_ptr = txq->tso_hdrs_dma + 801 txq->tx_curr_desc * TSO_HEADER_SIZE; 802 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | 803 GEN_CRC; 804 805 /* Defer updating the first command descriptor until all 806 * following descriptors have been written. 807 */ 808 if (first_desc) 809 *first_cmd_sts = cmd_sts; 810 else 811 desc->cmd_sts = cmd_sts; 812 813 txq->tx_curr_desc++; 814 if (txq->tx_curr_desc == txq->tx_ring_size) 815 txq->tx_curr_desc = 0; 816 } 817 818 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, 819 struct net_device *dev) 820 { 821 struct mv643xx_eth_private *mp = txq_to_mp(txq); 822 int hdr_len, total_len, data_left, ret; 823 int desc_count = 0; 824 struct tso_t tso; 825 struct tx_desc *first_tx_desc; 826 u32 first_cmd_sts = 0; 827 828 /* Count needed descriptors */ 829 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { 830 netdev_dbg(dev, "not enough descriptors for TSO!\n"); 831 return -EBUSY; 832 } 833 834 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc]; 835 836 /* Initialize the TSO handler, and prepare the first payload */ 837 hdr_len = tso_start(skb, &tso); 838 839 total_len = skb->len - hdr_len; 840 while (total_len > 0) { 841 bool first_desc = (desc_count == 0); 842 char *hdr; 843 844 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 845 total_len -= data_left; 846 desc_count++; 847 848 /* prepare packet headers: MAC + IP + TCP */ 849 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; 850 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 851 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts, 852 first_desc); 853 854 while (data_left > 0) { 855 int size; 856 desc_count++; 857 858 size = min_t(int, tso.size, data_left); 859 ret = txq_put_data_tso(dev, txq, skb, tso.data, size, 860 size == data_left, 861 total_len == 0); 862 if (ret) 863 goto err_release; 864 data_left -= size; 865 tso_build_data(skb, &tso, size); 866 } 867 } 868 869 __skb_queue_tail(&txq->tx_skb, skb); 870 skb_tx_timestamp(skb); 871 872 /* ensure all other descriptors are written before first cmd_sts */ 873 wmb(); 874 first_tx_desc->cmd_sts = first_cmd_sts; 875 876 /* clear TX_END status */ 877 mp->work_tx_end &= ~(1 << txq->index); 878 879 /* ensure all descriptors are written before poking hardware */ 880 wmb(); 881 txq_enable(txq); 882 txq->tx_desc_count += desc_count; 883 return 0; 884 err_release: 885 /* TODO: Release all used data descriptors; header descriptors must not 886 * be DMA-unmapped. 887 */ 888 return ret; 889 } 890 891 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 892 { 893 struct mv643xx_eth_private *mp = txq_to_mp(txq); 894 int nr_frags = skb_shinfo(skb)->nr_frags; 895 int frag; 896 897 for (frag = 0; frag < nr_frags; frag++) { 898 skb_frag_t *this_frag; 899 int tx_index; 900 struct tx_desc *desc; 901 902 this_frag = &skb_shinfo(skb)->frags[frag]; 903 tx_index = txq->tx_curr_desc++; 904 if (txq->tx_curr_desc == txq->tx_ring_size) 905 txq->tx_curr_desc = 0; 906 desc = &txq->tx_desc_area[tx_index]; 907 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE; 908 909 /* 910 * The last fragment will generate an interrupt 911 * which will free the skb on TX completion. 912 */ 913 if (frag == nr_frags - 1) { 914 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 915 ZERO_PADDING | TX_LAST_DESC | 916 TX_ENABLE_INTERRUPT; 917 } else { 918 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 919 } 920 921 desc->l4i_chk = 0; 922 desc->byte_cnt = skb_frag_size(this_frag); 923 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 924 this_frag, 0, desc->byte_cnt, 925 DMA_TO_DEVICE); 926 } 927 } 928 929 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, 930 struct net_device *dev) 931 { 932 struct mv643xx_eth_private *mp = txq_to_mp(txq); 933 int nr_frags = skb_shinfo(skb)->nr_frags; 934 int tx_index; 935 struct tx_desc *desc; 936 u32 cmd_sts; 937 u16 l4i_chk; 938 int length, ret; 939 940 cmd_sts = 0; 941 l4i_chk = 0; 942 943 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 944 if (net_ratelimit()) 945 netdev_err(dev, "tx queue full?!\n"); 946 return -EBUSY; 947 } 948 949 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); 950 if (ret) 951 return ret; 952 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 953 954 tx_index = txq->tx_curr_desc++; 955 if (txq->tx_curr_desc == txq->tx_ring_size) 956 txq->tx_curr_desc = 0; 957 desc = &txq->tx_desc_area[tx_index]; 958 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 959 960 if (nr_frags) { 961 txq_submit_frag_skb(txq, skb); 962 length = skb_headlen(skb); 963 } else { 964 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 965 length = skb->len; 966 } 967 968 desc->l4i_chk = l4i_chk; 969 desc->byte_cnt = length; 970 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 971 length, DMA_TO_DEVICE); 972 973 __skb_queue_tail(&txq->tx_skb, skb); 974 975 skb_tx_timestamp(skb); 976 977 /* ensure all other descriptors are written before first cmd_sts */ 978 wmb(); 979 desc->cmd_sts = cmd_sts; 980 981 /* clear TX_END status */ 982 mp->work_tx_end &= ~(1 << txq->index); 983 984 /* ensure all descriptors are written before poking hardware */ 985 wmb(); 986 txq_enable(txq); 987 988 txq->tx_desc_count += nr_frags + 1; 989 990 return 0; 991 } 992 993 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 994 { 995 struct mv643xx_eth_private *mp = netdev_priv(dev); 996 int length, queue, ret; 997 struct tx_queue *txq; 998 struct netdev_queue *nq; 999 1000 queue = skb_get_queue_mapping(skb); 1001 txq = mp->txq + queue; 1002 nq = netdev_get_tx_queue(dev, queue); 1003 1004 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1005 netdev_printk(KERN_DEBUG, dev, 1006 "failed to linearize skb with tiny unaligned fragment\n"); 1007 return NETDEV_TX_BUSY; 1008 } 1009 1010 length = skb->len; 1011 1012 if (skb_is_gso(skb)) 1013 ret = txq_submit_tso(txq, skb, dev); 1014 else 1015 ret = txq_submit_skb(txq, skb, dev); 1016 if (!ret) { 1017 txq->tx_bytes += length; 1018 txq->tx_packets++; 1019 1020 if (txq->tx_desc_count >= txq->tx_stop_threshold) 1021 netif_tx_stop_queue(nq); 1022 } else { 1023 txq->tx_dropped++; 1024 dev_kfree_skb_any(skb); 1025 } 1026 1027 return NETDEV_TX_OK; 1028 } 1029 1030 1031 /* tx napi ******************************************************************/ 1032 static void txq_kick(struct tx_queue *txq) 1033 { 1034 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1035 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1036 u32 hw_desc_ptr; 1037 u32 expected_ptr; 1038 1039 __netif_tx_lock(nq, smp_processor_id()); 1040 1041 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 1042 goto out; 1043 1044 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 1045 expected_ptr = (u32)txq->tx_desc_dma + 1046 txq->tx_curr_desc * sizeof(struct tx_desc); 1047 1048 if (hw_desc_ptr != expected_ptr) 1049 txq_enable(txq); 1050 1051 out: 1052 __netif_tx_unlock(nq); 1053 1054 mp->work_tx_end &= ~(1 << txq->index); 1055 } 1056 1057 static int txq_reclaim(struct tx_queue *txq, int budget, int force) 1058 { 1059 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1060 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1061 int reclaimed; 1062 1063 __netif_tx_lock_bh(nq); 1064 1065 reclaimed = 0; 1066 while (reclaimed < budget && txq->tx_desc_count > 0) { 1067 int tx_index; 1068 struct tx_desc *desc; 1069 u32 cmd_sts; 1070 char desc_dma_map; 1071 1072 tx_index = txq->tx_used_desc; 1073 desc = &txq->tx_desc_area[tx_index]; 1074 desc_dma_map = txq->tx_desc_mapping[tx_index]; 1075 1076 cmd_sts = desc->cmd_sts; 1077 1078 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 1079 if (!force) 1080 break; 1081 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 1082 } 1083 1084 txq->tx_used_desc = tx_index + 1; 1085 if (txq->tx_used_desc == txq->tx_ring_size) 1086 txq->tx_used_desc = 0; 1087 1088 reclaimed++; 1089 txq->tx_desc_count--; 1090 1091 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) { 1092 1093 if (desc_dma_map == DESC_DMA_MAP_PAGE) 1094 dma_unmap_page(mp->dev->dev.parent, 1095 desc->buf_ptr, 1096 desc->byte_cnt, 1097 DMA_TO_DEVICE); 1098 else 1099 dma_unmap_single(mp->dev->dev.parent, 1100 desc->buf_ptr, 1101 desc->byte_cnt, 1102 DMA_TO_DEVICE); 1103 } 1104 1105 if (cmd_sts & TX_ENABLE_INTERRUPT) { 1106 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb); 1107 1108 if (!WARN_ON(!skb)) 1109 dev_consume_skb_any(skb); 1110 } 1111 1112 if (cmd_sts & ERROR_SUMMARY) { 1113 netdev_info(mp->dev, "tx error\n"); 1114 mp->dev->stats.tx_errors++; 1115 } 1116 1117 } 1118 1119 __netif_tx_unlock_bh(nq); 1120 1121 if (reclaimed < budget) 1122 mp->work_tx &= ~(1 << txq->index); 1123 1124 return reclaimed; 1125 } 1126 1127 1128 /* tx rate control **********************************************************/ 1129 /* 1130 * Set total maximum TX rate (shared by all TX queues for this port) 1131 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1132 */ 1133 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1134 { 1135 int token_rate; 1136 int mtu; 1137 int bucket_size; 1138 1139 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1140 if (token_rate > 1023) 1141 token_rate = 1023; 1142 1143 mtu = (mp->dev->mtu + 255) >> 8; 1144 if (mtu > 63) 1145 mtu = 63; 1146 1147 bucket_size = (burst + 255) >> 8; 1148 if (bucket_size > 65535) 1149 bucket_size = 65535; 1150 1151 switch (mp->shared->tx_bw_control) { 1152 case TX_BW_CONTROL_OLD_LAYOUT: 1153 wrlp(mp, TX_BW_RATE, token_rate); 1154 wrlp(mp, TX_BW_MTU, mtu); 1155 wrlp(mp, TX_BW_BURST, bucket_size); 1156 break; 1157 case TX_BW_CONTROL_NEW_LAYOUT: 1158 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1159 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1160 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1161 break; 1162 } 1163 } 1164 1165 static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1166 { 1167 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1168 int token_rate; 1169 int bucket_size; 1170 1171 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1172 if (token_rate > 1023) 1173 token_rate = 1023; 1174 1175 bucket_size = (burst + 255) >> 8; 1176 if (bucket_size > 65535) 1177 bucket_size = 65535; 1178 1179 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1180 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1181 } 1182 1183 static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1184 { 1185 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1186 int off; 1187 u32 val; 1188 1189 /* 1190 * Turn on fixed priority mode. 1191 */ 1192 off = 0; 1193 switch (mp->shared->tx_bw_control) { 1194 case TX_BW_CONTROL_OLD_LAYOUT: 1195 off = TXQ_FIX_PRIO_CONF; 1196 break; 1197 case TX_BW_CONTROL_NEW_LAYOUT: 1198 off = TXQ_FIX_PRIO_CONF_MOVED; 1199 break; 1200 } 1201 1202 if (off) { 1203 val = rdlp(mp, off); 1204 val |= 1 << txq->index; 1205 wrlp(mp, off, val); 1206 } 1207 } 1208 1209 1210 /* mii management interface *************************************************/ 1211 static void mv643xx_eth_adjust_link(struct net_device *dev) 1212 { 1213 struct mv643xx_eth_private *mp = netdev_priv(dev); 1214 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1215 u32 autoneg_disable = FORCE_LINK_PASS | 1216 DISABLE_AUTO_NEG_SPEED_GMII | 1217 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1218 DISABLE_AUTO_NEG_FOR_DUPLEX; 1219 1220 if (dev->phydev->autoneg == AUTONEG_ENABLE) { 1221 /* enable auto negotiation */ 1222 pscr &= ~autoneg_disable; 1223 goto out_write; 1224 } 1225 1226 pscr |= autoneg_disable; 1227 1228 if (dev->phydev->speed == SPEED_1000) { 1229 /* force gigabit, half duplex not supported */ 1230 pscr |= SET_GMII_SPEED_TO_1000; 1231 pscr |= SET_FULL_DUPLEX_MODE; 1232 goto out_write; 1233 } 1234 1235 pscr &= ~SET_GMII_SPEED_TO_1000; 1236 1237 if (dev->phydev->speed == SPEED_100) 1238 pscr |= SET_MII_SPEED_TO_100; 1239 else 1240 pscr &= ~SET_MII_SPEED_TO_100; 1241 1242 if (dev->phydev->duplex == DUPLEX_FULL) 1243 pscr |= SET_FULL_DUPLEX_MODE; 1244 else 1245 pscr &= ~SET_FULL_DUPLEX_MODE; 1246 1247 out_write: 1248 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1249 } 1250 1251 /* statistics ***************************************************************/ 1252 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1253 { 1254 struct mv643xx_eth_private *mp = netdev_priv(dev); 1255 struct net_device_stats *stats = &dev->stats; 1256 unsigned long tx_packets = 0; 1257 unsigned long tx_bytes = 0; 1258 unsigned long tx_dropped = 0; 1259 int i; 1260 1261 for (i = 0; i < mp->txq_count; i++) { 1262 struct tx_queue *txq = mp->txq + i; 1263 1264 tx_packets += txq->tx_packets; 1265 tx_bytes += txq->tx_bytes; 1266 tx_dropped += txq->tx_dropped; 1267 } 1268 1269 stats->tx_packets = tx_packets; 1270 stats->tx_bytes = tx_bytes; 1271 stats->tx_dropped = tx_dropped; 1272 1273 return stats; 1274 } 1275 1276 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1277 { 1278 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1279 } 1280 1281 static void mib_counters_clear(struct mv643xx_eth_private *mp) 1282 { 1283 int i; 1284 1285 for (i = 0; i < 0x80; i += 4) 1286 mib_read(mp, i); 1287 1288 /* Clear non MIB hw counters also */ 1289 rdlp(mp, RX_DISCARD_FRAME_CNT); 1290 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1291 } 1292 1293 static void mib_counters_update(struct mv643xx_eth_private *mp) 1294 { 1295 struct mib_counters *p = &mp->mib_counters; 1296 1297 spin_lock_bh(&mp->mib_counters_lock); 1298 p->good_octets_received += mib_read(mp, 0x00); 1299 p->bad_octets_received += mib_read(mp, 0x08); 1300 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1301 p->good_frames_received += mib_read(mp, 0x10); 1302 p->bad_frames_received += mib_read(mp, 0x14); 1303 p->broadcast_frames_received += mib_read(mp, 0x18); 1304 p->multicast_frames_received += mib_read(mp, 0x1c); 1305 p->frames_64_octets += mib_read(mp, 0x20); 1306 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1307 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1308 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1309 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1310 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1311 p->good_octets_sent += mib_read(mp, 0x38); 1312 p->good_frames_sent += mib_read(mp, 0x40); 1313 p->excessive_collision += mib_read(mp, 0x44); 1314 p->multicast_frames_sent += mib_read(mp, 0x48); 1315 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1316 p->unrec_mac_control_received += mib_read(mp, 0x50); 1317 p->fc_sent += mib_read(mp, 0x54); 1318 p->good_fc_received += mib_read(mp, 0x58); 1319 p->bad_fc_received += mib_read(mp, 0x5c); 1320 p->undersize_received += mib_read(mp, 0x60); 1321 p->fragments_received += mib_read(mp, 0x64); 1322 p->oversize_received += mib_read(mp, 0x68); 1323 p->jabber_received += mib_read(mp, 0x6c); 1324 p->mac_receive_error += mib_read(mp, 0x70); 1325 p->bad_crc_event += mib_read(mp, 0x74); 1326 p->collision += mib_read(mp, 0x78); 1327 p->late_collision += mib_read(mp, 0x7c); 1328 /* Non MIB hardware counters */ 1329 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1330 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1331 spin_unlock_bh(&mp->mib_counters_lock); 1332 } 1333 1334 static void mib_counters_timer_wrapper(struct timer_list *t) 1335 { 1336 struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer); 1337 mib_counters_update(mp); 1338 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1339 } 1340 1341 1342 /* interrupt coalescing *****************************************************/ 1343 /* 1344 * Hardware coalescing parameters are set in units of 64 t_clk 1345 * cycles. I.e.: 1346 * 1347 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1348 * 1349 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1350 * 1351 * In the ->set*() methods, we round the computed register value 1352 * to the nearest integer. 1353 */ 1354 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1355 { 1356 u32 val = rdlp(mp, SDMA_CONFIG); 1357 u64 temp; 1358 1359 if (mp->shared->extended_rx_coal_limit) 1360 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1361 else 1362 temp = (val & 0x003fff00) >> 8; 1363 1364 temp *= 64000000; 1365 temp += mp->t_clk / 2; 1366 do_div(temp, mp->t_clk); 1367 1368 return (unsigned int)temp; 1369 } 1370 1371 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1372 { 1373 u64 temp; 1374 u32 val; 1375 1376 temp = (u64)usec * mp->t_clk; 1377 temp += 31999999; 1378 do_div(temp, 64000000); 1379 1380 val = rdlp(mp, SDMA_CONFIG); 1381 if (mp->shared->extended_rx_coal_limit) { 1382 if (temp > 0xffff) 1383 temp = 0xffff; 1384 val &= ~0x023fff80; 1385 val |= (temp & 0x8000) << 10; 1386 val |= (temp & 0x7fff) << 7; 1387 } else { 1388 if (temp > 0x3fff) 1389 temp = 0x3fff; 1390 val &= ~0x003fff00; 1391 val |= (temp & 0x3fff) << 8; 1392 } 1393 wrlp(mp, SDMA_CONFIG, val); 1394 } 1395 1396 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1397 { 1398 u64 temp; 1399 1400 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1401 temp *= 64000000; 1402 temp += mp->t_clk / 2; 1403 do_div(temp, mp->t_clk); 1404 1405 return (unsigned int)temp; 1406 } 1407 1408 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1409 { 1410 u64 temp; 1411 1412 temp = (u64)usec * mp->t_clk; 1413 temp += 31999999; 1414 do_div(temp, 64000000); 1415 1416 if (temp > 0x3fff) 1417 temp = 0x3fff; 1418 1419 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1420 } 1421 1422 1423 /* ethtool ******************************************************************/ 1424 struct mv643xx_eth_stats { 1425 char stat_string[ETH_GSTRING_LEN]; 1426 int sizeof_stat; 1427 int netdev_off; 1428 int mp_off; 1429 }; 1430 1431 #define SSTAT(m) \ 1432 { #m, sizeof_field(struct net_device_stats, m), \ 1433 offsetof(struct net_device, stats.m), -1 } 1434 1435 #define MIBSTAT(m) \ 1436 { #m, sizeof_field(struct mib_counters, m), \ 1437 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1438 1439 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1440 SSTAT(rx_packets), 1441 SSTAT(tx_packets), 1442 SSTAT(rx_bytes), 1443 SSTAT(tx_bytes), 1444 SSTAT(rx_errors), 1445 SSTAT(tx_errors), 1446 SSTAT(rx_dropped), 1447 SSTAT(tx_dropped), 1448 MIBSTAT(good_octets_received), 1449 MIBSTAT(bad_octets_received), 1450 MIBSTAT(internal_mac_transmit_err), 1451 MIBSTAT(good_frames_received), 1452 MIBSTAT(bad_frames_received), 1453 MIBSTAT(broadcast_frames_received), 1454 MIBSTAT(multicast_frames_received), 1455 MIBSTAT(frames_64_octets), 1456 MIBSTAT(frames_65_to_127_octets), 1457 MIBSTAT(frames_128_to_255_octets), 1458 MIBSTAT(frames_256_to_511_octets), 1459 MIBSTAT(frames_512_to_1023_octets), 1460 MIBSTAT(frames_1024_to_max_octets), 1461 MIBSTAT(good_octets_sent), 1462 MIBSTAT(good_frames_sent), 1463 MIBSTAT(excessive_collision), 1464 MIBSTAT(multicast_frames_sent), 1465 MIBSTAT(broadcast_frames_sent), 1466 MIBSTAT(unrec_mac_control_received), 1467 MIBSTAT(fc_sent), 1468 MIBSTAT(good_fc_received), 1469 MIBSTAT(bad_fc_received), 1470 MIBSTAT(undersize_received), 1471 MIBSTAT(fragments_received), 1472 MIBSTAT(oversize_received), 1473 MIBSTAT(jabber_received), 1474 MIBSTAT(mac_receive_error), 1475 MIBSTAT(bad_crc_event), 1476 MIBSTAT(collision), 1477 MIBSTAT(late_collision), 1478 MIBSTAT(rx_discard), 1479 MIBSTAT(rx_overrun), 1480 }; 1481 1482 static int 1483 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp, 1484 struct ethtool_link_ksettings *cmd) 1485 { 1486 struct net_device *dev = mp->dev; 1487 1488 phy_ethtool_ksettings_get(dev->phydev, cmd); 1489 1490 /* 1491 * The MAC does not support 1000baseT_Half. 1492 */ 1493 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1494 cmd->link_modes.supported); 1495 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1496 cmd->link_modes.advertising); 1497 1498 return 0; 1499 } 1500 1501 static int 1502 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp, 1503 struct ethtool_link_ksettings *cmd) 1504 { 1505 u32 port_status; 1506 u32 supported, advertising; 1507 1508 port_status = rdlp(mp, PORT_STATUS); 1509 1510 supported = SUPPORTED_MII; 1511 advertising = ADVERTISED_MII; 1512 switch (port_status & PORT_SPEED_MASK) { 1513 case PORT_SPEED_10: 1514 cmd->base.speed = SPEED_10; 1515 break; 1516 case PORT_SPEED_100: 1517 cmd->base.speed = SPEED_100; 1518 break; 1519 case PORT_SPEED_1000: 1520 cmd->base.speed = SPEED_1000; 1521 break; 1522 default: 1523 cmd->base.speed = -1; 1524 break; 1525 } 1526 cmd->base.duplex = (port_status & FULL_DUPLEX) ? 1527 DUPLEX_FULL : DUPLEX_HALF; 1528 cmd->base.port = PORT_MII; 1529 cmd->base.phy_address = 0; 1530 cmd->base.autoneg = AUTONEG_DISABLE; 1531 1532 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1533 supported); 1534 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1535 advertising); 1536 1537 return 0; 1538 } 1539 1540 static void 1541 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1542 { 1543 wol->supported = 0; 1544 wol->wolopts = 0; 1545 if (dev->phydev) 1546 phy_ethtool_get_wol(dev->phydev, wol); 1547 } 1548 1549 static int 1550 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1551 { 1552 int err; 1553 1554 if (!dev->phydev) 1555 return -EOPNOTSUPP; 1556 1557 err = phy_ethtool_set_wol(dev->phydev, wol); 1558 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1559 * this debugging hint is useful to have. 1560 */ 1561 if (err == -EOPNOTSUPP) 1562 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1563 return err; 1564 } 1565 1566 static int 1567 mv643xx_eth_get_link_ksettings(struct net_device *dev, 1568 struct ethtool_link_ksettings *cmd) 1569 { 1570 struct mv643xx_eth_private *mp = netdev_priv(dev); 1571 1572 if (dev->phydev) 1573 return mv643xx_eth_get_link_ksettings_phy(mp, cmd); 1574 else 1575 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd); 1576 } 1577 1578 static int 1579 mv643xx_eth_set_link_ksettings(struct net_device *dev, 1580 const struct ethtool_link_ksettings *cmd) 1581 { 1582 struct ethtool_link_ksettings c = *cmd; 1583 u32 advertising; 1584 int ret; 1585 1586 if (!dev->phydev) 1587 return -EINVAL; 1588 1589 /* 1590 * The MAC does not support 1000baseT_Half. 1591 */ 1592 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1593 c.link_modes.advertising); 1594 advertising &= ~ADVERTISED_1000baseT_Half; 1595 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising, 1596 advertising); 1597 1598 ret = phy_ethtool_ksettings_set(dev->phydev, &c); 1599 if (!ret) 1600 mv643xx_eth_adjust_link(dev); 1601 return ret; 1602 } 1603 1604 static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1605 struct ethtool_drvinfo *drvinfo) 1606 { 1607 strscpy(drvinfo->driver, mv643xx_eth_driver_name, 1608 sizeof(drvinfo->driver)); 1609 strscpy(drvinfo->version, mv643xx_eth_driver_version, 1610 sizeof(drvinfo->version)); 1611 strscpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1612 strscpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1613 } 1614 1615 static int mv643xx_eth_get_coalesce(struct net_device *dev, 1616 struct ethtool_coalesce *ec, 1617 struct kernel_ethtool_coalesce *kernel_coal, 1618 struct netlink_ext_ack *extack) 1619 { 1620 struct mv643xx_eth_private *mp = netdev_priv(dev); 1621 1622 ec->rx_coalesce_usecs = get_rx_coal(mp); 1623 ec->tx_coalesce_usecs = get_tx_coal(mp); 1624 1625 return 0; 1626 } 1627 1628 static int mv643xx_eth_set_coalesce(struct net_device *dev, 1629 struct ethtool_coalesce *ec, 1630 struct kernel_ethtool_coalesce *kernel_coal, 1631 struct netlink_ext_ack *extack) 1632 { 1633 struct mv643xx_eth_private *mp = netdev_priv(dev); 1634 1635 set_rx_coal(mp, ec->rx_coalesce_usecs); 1636 set_tx_coal(mp, ec->tx_coalesce_usecs); 1637 1638 return 0; 1639 } 1640 1641 static void 1642 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er, 1643 struct kernel_ethtool_ringparam *kernel_er, 1644 struct netlink_ext_ack *extack) 1645 { 1646 struct mv643xx_eth_private *mp = netdev_priv(dev); 1647 1648 er->rx_max_pending = 4096; 1649 er->tx_max_pending = 4096; 1650 1651 er->rx_pending = mp->rx_ring_size; 1652 er->tx_pending = mp->tx_ring_size; 1653 } 1654 1655 static int 1656 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er, 1657 struct kernel_ethtool_ringparam *kernel_er, 1658 struct netlink_ext_ack *extack) 1659 { 1660 struct mv643xx_eth_private *mp = netdev_priv(dev); 1661 1662 if (er->rx_mini_pending || er->rx_jumbo_pending) 1663 return -EINVAL; 1664 1665 mp->rx_ring_size = min(er->rx_pending, 4096U); 1666 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, 1667 MV643XX_MAX_SKB_DESCS * 2, 4096); 1668 if (mp->tx_ring_size != er->tx_pending) 1669 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 1670 mp->tx_ring_size, er->tx_pending); 1671 1672 if (netif_running(dev)) { 1673 mv643xx_eth_stop(dev); 1674 if (mv643xx_eth_open(dev)) { 1675 netdev_err(dev, 1676 "fatal error on re-opening device after ring param change\n"); 1677 return -ENOMEM; 1678 } 1679 } 1680 1681 return 0; 1682 } 1683 1684 1685 static int 1686 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1687 { 1688 struct mv643xx_eth_private *mp = netdev_priv(dev); 1689 bool rx_csum = features & NETIF_F_RXCSUM; 1690 1691 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1692 1693 return 0; 1694 } 1695 1696 static void mv643xx_eth_get_strings(struct net_device *dev, 1697 uint32_t stringset, uint8_t *data) 1698 { 1699 int i; 1700 1701 if (stringset == ETH_SS_STATS) 1702 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) 1703 ethtool_puts(&data, mv643xx_eth_stats[i].stat_string); 1704 } 1705 1706 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1707 struct ethtool_stats *stats, 1708 uint64_t *data) 1709 { 1710 struct mv643xx_eth_private *mp = netdev_priv(dev); 1711 int i; 1712 1713 mv643xx_eth_get_stats(dev); 1714 mib_counters_update(mp); 1715 1716 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1717 const struct mv643xx_eth_stats *stat; 1718 void *p; 1719 1720 stat = mv643xx_eth_stats + i; 1721 1722 if (stat->netdev_off >= 0) 1723 p = ((void *)mp->dev) + stat->netdev_off; 1724 else 1725 p = ((void *)mp) + stat->mp_off; 1726 1727 data[i] = (stat->sizeof_stat == 8) ? 1728 *(uint64_t *)p : *(uint32_t *)p; 1729 } 1730 } 1731 1732 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1733 { 1734 if (sset == ETH_SS_STATS) 1735 return ARRAY_SIZE(mv643xx_eth_stats); 1736 1737 return -EOPNOTSUPP; 1738 } 1739 1740 static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1741 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 1742 .get_drvinfo = mv643xx_eth_get_drvinfo, 1743 .nway_reset = phy_ethtool_nway_reset, 1744 .get_link = ethtool_op_get_link, 1745 .get_coalesce = mv643xx_eth_get_coalesce, 1746 .set_coalesce = mv643xx_eth_set_coalesce, 1747 .get_ringparam = mv643xx_eth_get_ringparam, 1748 .set_ringparam = mv643xx_eth_set_ringparam, 1749 .get_strings = mv643xx_eth_get_strings, 1750 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1751 .get_sset_count = mv643xx_eth_get_sset_count, 1752 .get_ts_info = ethtool_op_get_ts_info, 1753 .get_wol = mv643xx_eth_get_wol, 1754 .set_wol = mv643xx_eth_set_wol, 1755 .get_link_ksettings = mv643xx_eth_get_link_ksettings, 1756 .set_link_ksettings = mv643xx_eth_set_link_ksettings, 1757 }; 1758 1759 1760 /* address handling *********************************************************/ 1761 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1762 { 1763 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1764 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1765 1766 addr[0] = (mac_h >> 24) & 0xff; 1767 addr[1] = (mac_h >> 16) & 0xff; 1768 addr[2] = (mac_h >> 8) & 0xff; 1769 addr[3] = mac_h & 0xff; 1770 addr[4] = (mac_l >> 8) & 0xff; 1771 addr[5] = mac_l & 0xff; 1772 } 1773 1774 static void uc_addr_set(struct mv643xx_eth_private *mp, const u8 *addr) 1775 { 1776 wrlp(mp, MAC_ADDR_HIGH, 1777 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1778 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1779 } 1780 1781 static u32 uc_addr_filter_mask(struct net_device *dev) 1782 { 1783 struct netdev_hw_addr *ha; 1784 u32 nibbles; 1785 1786 if (dev->flags & IFF_PROMISC) 1787 return 0; 1788 1789 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1790 netdev_for_each_uc_addr(ha, dev) { 1791 if (memcmp(dev->dev_addr, ha->addr, 5)) 1792 return 0; 1793 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1794 return 0; 1795 1796 nibbles |= 1 << (ha->addr[5] & 0x0f); 1797 } 1798 1799 return nibbles; 1800 } 1801 1802 static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1803 { 1804 struct mv643xx_eth_private *mp = netdev_priv(dev); 1805 u32 port_config; 1806 u32 nibbles; 1807 int i; 1808 1809 uc_addr_set(mp, dev->dev_addr); 1810 1811 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1812 1813 nibbles = uc_addr_filter_mask(dev); 1814 if (!nibbles) { 1815 port_config |= UNICAST_PROMISCUOUS_MODE; 1816 nibbles = 0xffff; 1817 } 1818 1819 for (i = 0; i < 16; i += 4) { 1820 int off = UNICAST_TABLE(mp->port_num) + i; 1821 u32 v; 1822 1823 v = 0; 1824 if (nibbles & 1) 1825 v |= 0x00000001; 1826 if (nibbles & 2) 1827 v |= 0x00000100; 1828 if (nibbles & 4) 1829 v |= 0x00010000; 1830 if (nibbles & 8) 1831 v |= 0x01000000; 1832 nibbles >>= 4; 1833 1834 wrl(mp, off, v); 1835 } 1836 1837 wrlp(mp, PORT_CONFIG, port_config); 1838 } 1839 1840 static int addr_crc(unsigned char *addr) 1841 { 1842 int crc = 0; 1843 int i; 1844 1845 for (i = 0; i < 6; i++) { 1846 int j; 1847 1848 crc = (crc ^ addr[i]) << 8; 1849 for (j = 7; j >= 0; j--) { 1850 if (crc & (0x100 << j)) 1851 crc ^= 0x107 << j; 1852 } 1853 } 1854 1855 return crc; 1856 } 1857 1858 static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1859 { 1860 struct mv643xx_eth_private *mp = netdev_priv(dev); 1861 u32 *mc_spec; 1862 u32 *mc_other; 1863 struct netdev_hw_addr *ha; 1864 int i; 1865 1866 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 1867 goto promiscuous; 1868 1869 /* Allocate both mc_spec and mc_other tables */ 1870 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC); 1871 if (!mc_spec) 1872 goto promiscuous; 1873 mc_other = &mc_spec[64]; 1874 1875 netdev_for_each_mc_addr(ha, dev) { 1876 u8 *a = ha->addr; 1877 u32 *table; 1878 u8 entry; 1879 1880 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1881 table = mc_spec; 1882 entry = a[5]; 1883 } else { 1884 table = mc_other; 1885 entry = addr_crc(a); 1886 } 1887 1888 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1889 } 1890 1891 for (i = 0; i < 64; i++) { 1892 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1893 mc_spec[i]); 1894 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1895 mc_other[i]); 1896 } 1897 1898 kfree(mc_spec); 1899 return; 1900 1901 promiscuous: 1902 for (i = 0; i < 64; i++) { 1903 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1904 0x01010101u); 1905 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1906 0x01010101u); 1907 } 1908 } 1909 1910 static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1911 { 1912 mv643xx_eth_program_unicast_filter(dev); 1913 mv643xx_eth_program_multicast_filter(dev); 1914 } 1915 1916 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1917 { 1918 struct sockaddr *sa = addr; 1919 1920 if (!is_valid_ether_addr(sa->sa_data)) 1921 return -EADDRNOTAVAIL; 1922 1923 eth_hw_addr_set(dev, sa->sa_data); 1924 1925 netif_addr_lock_bh(dev); 1926 mv643xx_eth_program_unicast_filter(dev); 1927 netif_addr_unlock_bh(dev); 1928 1929 return 0; 1930 } 1931 1932 1933 /* rx/tx queue initialisation ***********************************************/ 1934 static int rxq_init(struct mv643xx_eth_private *mp, int index) 1935 { 1936 struct rx_queue *rxq = mp->rxq + index; 1937 struct rx_desc *rx_desc; 1938 int size; 1939 int i; 1940 1941 rxq->index = index; 1942 1943 rxq->rx_ring_size = mp->rx_ring_size; 1944 1945 rxq->rx_desc_count = 0; 1946 rxq->rx_curr_desc = 0; 1947 rxq->rx_used_desc = 0; 1948 1949 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1950 1951 if (index == 0 && size <= mp->rx_desc_sram_size) { 1952 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1953 mp->rx_desc_sram_size); 1954 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1955 } else { 1956 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1957 size, &rxq->rx_desc_dma, 1958 GFP_KERNEL); 1959 } 1960 1961 if (rxq->rx_desc_area == NULL) { 1962 netdev_err(mp->dev, 1963 "can't allocate rx ring (%d bytes)\n", size); 1964 goto out; 1965 } 1966 memset(rxq->rx_desc_area, 0, size); 1967 1968 rxq->rx_desc_area_size = size; 1969 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1970 GFP_KERNEL); 1971 if (rxq->rx_skb == NULL) 1972 goto out_free; 1973 1974 rx_desc = rxq->rx_desc_area; 1975 for (i = 0; i < rxq->rx_ring_size; i++) { 1976 int nexti; 1977 1978 nexti = i + 1; 1979 if (nexti == rxq->rx_ring_size) 1980 nexti = 0; 1981 1982 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1983 nexti * sizeof(struct rx_desc); 1984 } 1985 1986 return 0; 1987 1988 1989 out_free: 1990 if (index == 0 && size <= mp->rx_desc_sram_size) 1991 iounmap(rxq->rx_desc_area); 1992 else 1993 dma_free_coherent(mp->dev->dev.parent, size, 1994 rxq->rx_desc_area, 1995 rxq->rx_desc_dma); 1996 1997 out: 1998 return -ENOMEM; 1999 } 2000 2001 static void rxq_deinit(struct rx_queue *rxq) 2002 { 2003 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 2004 int i; 2005 2006 rxq_disable(rxq); 2007 2008 for (i = 0; i < rxq->rx_ring_size; i++) { 2009 if (rxq->rx_skb[i]) { 2010 dev_consume_skb_any(rxq->rx_skb[i]); 2011 rxq->rx_desc_count--; 2012 } 2013 } 2014 2015 if (rxq->rx_desc_count) { 2016 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 2017 rxq->rx_desc_count); 2018 } 2019 2020 if (rxq->index == 0 && 2021 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 2022 iounmap(rxq->rx_desc_area); 2023 else 2024 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 2025 rxq->rx_desc_area, rxq->rx_desc_dma); 2026 2027 kfree(rxq->rx_skb); 2028 } 2029 2030 static int txq_init(struct mv643xx_eth_private *mp, int index) 2031 { 2032 struct tx_queue *txq = mp->txq + index; 2033 struct tx_desc *tx_desc; 2034 int size; 2035 int ret; 2036 int i; 2037 2038 txq->index = index; 2039 2040 txq->tx_ring_size = mp->tx_ring_size; 2041 2042 /* A queue must always have room for at least one skb. 2043 * Therefore, stop the queue when the free entries reaches 2044 * the maximum number of descriptors per skb. 2045 */ 2046 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; 2047 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 2048 2049 txq->tx_desc_count = 0; 2050 txq->tx_curr_desc = 0; 2051 txq->tx_used_desc = 0; 2052 2053 size = txq->tx_ring_size * sizeof(struct tx_desc); 2054 2055 if (index == 0 && size <= mp->tx_desc_sram_size) { 2056 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 2057 mp->tx_desc_sram_size); 2058 txq->tx_desc_dma = mp->tx_desc_sram_addr; 2059 } else { 2060 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 2061 size, &txq->tx_desc_dma, 2062 GFP_KERNEL); 2063 } 2064 2065 if (txq->tx_desc_area == NULL) { 2066 netdev_err(mp->dev, 2067 "can't allocate tx ring (%d bytes)\n", size); 2068 return -ENOMEM; 2069 } 2070 memset(txq->tx_desc_area, 0, size); 2071 2072 txq->tx_desc_area_size = size; 2073 2074 tx_desc = txq->tx_desc_area; 2075 for (i = 0; i < txq->tx_ring_size; i++) { 2076 struct tx_desc *txd = tx_desc + i; 2077 int nexti; 2078 2079 nexti = i + 1; 2080 if (nexti == txq->tx_ring_size) 2081 nexti = 0; 2082 2083 txd->cmd_sts = 0; 2084 txd->next_desc_ptr = txq->tx_desc_dma + 2085 nexti * sizeof(struct tx_desc); 2086 } 2087 2088 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char), 2089 GFP_KERNEL); 2090 if (!txq->tx_desc_mapping) { 2091 ret = -ENOMEM; 2092 goto err_free_desc_area; 2093 } 2094 2095 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 2096 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, 2097 txq->tx_ring_size * TSO_HEADER_SIZE, 2098 &txq->tso_hdrs_dma, GFP_KERNEL); 2099 if (txq->tso_hdrs == NULL) { 2100 ret = -ENOMEM; 2101 goto err_free_desc_mapping; 2102 } 2103 skb_queue_head_init(&txq->tx_skb); 2104 2105 return 0; 2106 2107 err_free_desc_mapping: 2108 kfree(txq->tx_desc_mapping); 2109 err_free_desc_area: 2110 if (index == 0 && size <= mp->tx_desc_sram_size) 2111 iounmap(txq->tx_desc_area); 2112 else 2113 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2114 txq->tx_desc_area, txq->tx_desc_dma); 2115 return ret; 2116 } 2117 2118 static void txq_deinit(struct tx_queue *txq) 2119 { 2120 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2121 2122 txq_disable(txq); 2123 txq_reclaim(txq, txq->tx_ring_size, 1); 2124 2125 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2126 2127 if (txq->index == 0 && 2128 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2129 iounmap(txq->tx_desc_area); 2130 else 2131 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2132 txq->tx_desc_area, txq->tx_desc_dma); 2133 kfree(txq->tx_desc_mapping); 2134 2135 if (txq->tso_hdrs) 2136 dma_free_coherent(mp->dev->dev.parent, 2137 txq->tx_ring_size * TSO_HEADER_SIZE, 2138 txq->tso_hdrs, txq->tso_hdrs_dma); 2139 } 2140 2141 2142 /* netdev ops and related ***************************************************/ 2143 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2144 { 2145 u32 int_cause; 2146 u32 int_cause_ext; 2147 2148 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2149 if (int_cause == 0) 2150 return 0; 2151 2152 int_cause_ext = 0; 2153 if (int_cause & INT_EXT) { 2154 int_cause &= ~INT_EXT; 2155 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2156 } 2157 2158 if (int_cause) { 2159 wrlp(mp, INT_CAUSE, ~int_cause); 2160 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2161 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2162 mp->work_rx |= (int_cause & INT_RX) >> 2; 2163 } 2164 2165 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2166 if (int_cause_ext) { 2167 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2168 if (int_cause_ext & INT_EXT_LINK_PHY) 2169 mp->work_link = 1; 2170 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2171 } 2172 2173 return 1; 2174 } 2175 2176 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2177 { 2178 struct net_device *dev = (struct net_device *)dev_id; 2179 struct mv643xx_eth_private *mp = netdev_priv(dev); 2180 2181 if (unlikely(!mv643xx_eth_collect_events(mp))) 2182 return IRQ_NONE; 2183 2184 wrlp(mp, INT_MASK, 0); 2185 napi_schedule(&mp->napi); 2186 2187 return IRQ_HANDLED; 2188 } 2189 2190 static void handle_link_event(struct mv643xx_eth_private *mp) 2191 { 2192 struct net_device *dev = mp->dev; 2193 u32 port_status; 2194 int speed; 2195 int duplex; 2196 int fc; 2197 2198 port_status = rdlp(mp, PORT_STATUS); 2199 if (!(port_status & LINK_UP)) { 2200 if (netif_carrier_ok(dev)) { 2201 int i; 2202 2203 netdev_info(dev, "link down\n"); 2204 2205 netif_carrier_off(dev); 2206 2207 for (i = 0; i < mp->txq_count; i++) { 2208 struct tx_queue *txq = mp->txq + i; 2209 2210 txq_reclaim(txq, txq->tx_ring_size, 1); 2211 txq_reset_hw_ptr(txq); 2212 } 2213 } 2214 return; 2215 } 2216 2217 switch (port_status & PORT_SPEED_MASK) { 2218 case PORT_SPEED_10: 2219 speed = 10; 2220 break; 2221 case PORT_SPEED_100: 2222 speed = 100; 2223 break; 2224 case PORT_SPEED_1000: 2225 speed = 1000; 2226 break; 2227 default: 2228 speed = -1; 2229 break; 2230 } 2231 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2232 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2233 2234 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2235 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2236 2237 if (!netif_carrier_ok(dev)) 2238 netif_carrier_on(dev); 2239 } 2240 2241 static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2242 { 2243 struct mv643xx_eth_private *mp; 2244 int work_done; 2245 2246 mp = container_of(napi, struct mv643xx_eth_private, napi); 2247 2248 if (unlikely(mp->oom)) { 2249 mp->oom = 0; 2250 del_timer(&mp->rx_oom); 2251 } 2252 2253 work_done = 0; 2254 while (work_done < budget) { 2255 u8 queue_mask; 2256 int queue; 2257 int work_tbd; 2258 2259 if (mp->work_link) { 2260 mp->work_link = 0; 2261 handle_link_event(mp); 2262 work_done++; 2263 continue; 2264 } 2265 2266 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2267 if (likely(!mp->oom)) 2268 queue_mask |= mp->work_rx_refill; 2269 2270 if (!queue_mask) { 2271 if (mv643xx_eth_collect_events(mp)) 2272 continue; 2273 break; 2274 } 2275 2276 queue = fls(queue_mask) - 1; 2277 queue_mask = 1 << queue; 2278 2279 work_tbd = budget - work_done; 2280 if (work_tbd > 16) 2281 work_tbd = 16; 2282 2283 if (mp->work_tx_end & queue_mask) { 2284 txq_kick(mp->txq + queue); 2285 } else if (mp->work_tx & queue_mask) { 2286 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2287 txq_maybe_wake(mp->txq + queue); 2288 } else if (mp->work_rx & queue_mask) { 2289 work_done += rxq_process(mp->rxq + queue, work_tbd); 2290 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2291 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2292 } else { 2293 BUG(); 2294 } 2295 } 2296 2297 if (work_done < budget) { 2298 if (mp->oom) 2299 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2300 napi_complete_done(napi, work_done); 2301 wrlp(mp, INT_MASK, mp->int_mask); 2302 } 2303 2304 return work_done; 2305 } 2306 2307 static inline void oom_timer_wrapper(struct timer_list *t) 2308 { 2309 struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom); 2310 2311 napi_schedule(&mp->napi); 2312 } 2313 2314 static void port_start(struct mv643xx_eth_private *mp) 2315 { 2316 struct net_device *dev = mp->dev; 2317 u32 pscr; 2318 int i; 2319 2320 /* 2321 * Perform PHY reset, if there is a PHY. 2322 */ 2323 if (dev->phydev) { 2324 struct ethtool_link_ksettings cmd; 2325 2326 mv643xx_eth_get_link_ksettings(dev, &cmd); 2327 phy_init_hw(dev->phydev); 2328 mv643xx_eth_set_link_ksettings( 2329 dev, (const struct ethtool_link_ksettings *)&cmd); 2330 phy_start(dev->phydev); 2331 } 2332 2333 /* 2334 * Configure basic link parameters. 2335 */ 2336 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2337 2338 pscr |= SERIAL_PORT_ENABLE; 2339 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2340 2341 pscr |= DO_NOT_FORCE_LINK_FAIL; 2342 if (!dev->phydev) 2343 pscr |= FORCE_LINK_PASS; 2344 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2345 2346 /* 2347 * Configure TX path and queues. 2348 */ 2349 tx_set_rate(mp, 1000000000, 16777216); 2350 for (i = 0; i < mp->txq_count; i++) { 2351 struct tx_queue *txq = mp->txq + i; 2352 2353 txq_reset_hw_ptr(txq); 2354 txq_set_rate(txq, 1000000000, 16777216); 2355 txq_set_fixed_prio_mode(txq); 2356 } 2357 2358 /* 2359 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2360 * frames to RX queue #0, and include the pseudo-header when 2361 * calculating receive checksums. 2362 */ 2363 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2364 2365 /* 2366 * Treat BPDUs as normal multicasts, and disable partition mode. 2367 */ 2368 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2369 2370 /* 2371 * Add configured unicast addresses to address filter table. 2372 */ 2373 mv643xx_eth_program_unicast_filter(mp->dev); 2374 2375 /* 2376 * Enable the receive queues. 2377 */ 2378 for (i = 0; i < mp->rxq_count; i++) { 2379 struct rx_queue *rxq = mp->rxq + i; 2380 u32 addr; 2381 2382 addr = (u32)rxq->rx_desc_dma; 2383 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2384 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2385 2386 rxq_enable(rxq); 2387 } 2388 } 2389 2390 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2391 { 2392 int skb_size; 2393 2394 /* 2395 * Reserve 2+14 bytes for an ethernet header (the hardware 2396 * automatically prepends 2 bytes of dummy data to each 2397 * received packet), 16 bytes for up to four VLAN tags, and 2398 * 4 bytes for the trailing FCS -- 36 bytes total. 2399 */ 2400 skb_size = mp->dev->mtu + 36; 2401 2402 /* 2403 * Make sure that the skb size is a multiple of 8 bytes, as 2404 * the lower three bits of the receive descriptor's buffer 2405 * size field are ignored by the hardware. 2406 */ 2407 mp->skb_size = (skb_size + 7) & ~7; 2408 2409 /* 2410 * If NET_SKB_PAD is smaller than a cache line, 2411 * netdev_alloc_skb() will cause skb->data to be misaligned 2412 * to a cache line boundary. If this is the case, include 2413 * some extra space to allow re-aligning the data area. 2414 */ 2415 mp->skb_size += SKB_DMA_REALIGN; 2416 } 2417 2418 static int mv643xx_eth_open(struct net_device *dev) 2419 { 2420 struct mv643xx_eth_private *mp = netdev_priv(dev); 2421 int err; 2422 int i; 2423 2424 wrlp(mp, INT_CAUSE, 0); 2425 wrlp(mp, INT_CAUSE_EXT, 0); 2426 rdlp(mp, INT_CAUSE_EXT); 2427 2428 err = request_irq(dev->irq, mv643xx_eth_irq, 2429 IRQF_SHARED, dev->name, dev); 2430 if (err) { 2431 netdev_err(dev, "can't assign irq\n"); 2432 return -EAGAIN; 2433 } 2434 2435 mv643xx_eth_recalc_skb_size(mp); 2436 2437 napi_enable(&mp->napi); 2438 2439 mp->int_mask = INT_EXT; 2440 2441 for (i = 0; i < mp->rxq_count; i++) { 2442 err = rxq_init(mp, i); 2443 if (err) { 2444 while (--i >= 0) 2445 rxq_deinit(mp->rxq + i); 2446 goto out; 2447 } 2448 2449 rxq_refill(mp->rxq + i, INT_MAX); 2450 mp->int_mask |= INT_RX_0 << i; 2451 } 2452 2453 if (mp->oom) { 2454 mp->rx_oom.expires = jiffies + (HZ / 10); 2455 add_timer(&mp->rx_oom); 2456 } 2457 2458 for (i = 0; i < mp->txq_count; i++) { 2459 err = txq_init(mp, i); 2460 if (err) { 2461 while (--i >= 0) 2462 txq_deinit(mp->txq + i); 2463 goto out_free; 2464 } 2465 mp->int_mask |= INT_TX_END_0 << i; 2466 } 2467 2468 add_timer(&mp->mib_counters_timer); 2469 port_start(mp); 2470 2471 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2472 wrlp(mp, INT_MASK, mp->int_mask); 2473 2474 return 0; 2475 2476 2477 out_free: 2478 for (i = 0; i < mp->rxq_count; i++) 2479 rxq_deinit(mp->rxq + i); 2480 out: 2481 napi_disable(&mp->napi); 2482 free_irq(dev->irq, dev); 2483 2484 return err; 2485 } 2486 2487 static void port_reset(struct mv643xx_eth_private *mp) 2488 { 2489 unsigned int data; 2490 int i; 2491 2492 for (i = 0; i < mp->rxq_count; i++) 2493 rxq_disable(mp->rxq + i); 2494 for (i = 0; i < mp->txq_count; i++) 2495 txq_disable(mp->txq + i); 2496 2497 while (1) { 2498 u32 ps = rdlp(mp, PORT_STATUS); 2499 2500 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2501 break; 2502 udelay(10); 2503 } 2504 2505 /* Reset the Enable bit in the Configuration Register */ 2506 data = rdlp(mp, PORT_SERIAL_CONTROL); 2507 data &= ~(SERIAL_PORT_ENABLE | 2508 DO_NOT_FORCE_LINK_FAIL | 2509 FORCE_LINK_PASS); 2510 wrlp(mp, PORT_SERIAL_CONTROL, data); 2511 } 2512 2513 static int mv643xx_eth_stop(struct net_device *dev) 2514 { 2515 struct mv643xx_eth_private *mp = netdev_priv(dev); 2516 int i; 2517 2518 wrlp(mp, INT_MASK_EXT, 0x00000000); 2519 wrlp(mp, INT_MASK, 0x00000000); 2520 rdlp(mp, INT_MASK); 2521 2522 napi_disable(&mp->napi); 2523 2524 del_timer_sync(&mp->rx_oom); 2525 2526 netif_carrier_off(dev); 2527 if (dev->phydev) 2528 phy_stop(dev->phydev); 2529 free_irq(dev->irq, dev); 2530 2531 port_reset(mp); 2532 mv643xx_eth_get_stats(dev); 2533 mib_counters_update(mp); 2534 del_timer_sync(&mp->mib_counters_timer); 2535 2536 for (i = 0; i < mp->rxq_count; i++) 2537 rxq_deinit(mp->rxq + i); 2538 for (i = 0; i < mp->txq_count; i++) 2539 txq_deinit(mp->txq + i); 2540 2541 return 0; 2542 } 2543 2544 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2545 { 2546 int ret; 2547 2548 if (!dev->phydev) 2549 return -ENOTSUPP; 2550 2551 ret = phy_mii_ioctl(dev->phydev, ifr, cmd); 2552 if (!ret) 2553 mv643xx_eth_adjust_link(dev); 2554 return ret; 2555 } 2556 2557 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2558 { 2559 struct mv643xx_eth_private *mp = netdev_priv(dev); 2560 2561 WRITE_ONCE(dev->mtu, new_mtu); 2562 mv643xx_eth_recalc_skb_size(mp); 2563 tx_set_rate(mp, 1000000000, 16777216); 2564 2565 if (!netif_running(dev)) 2566 return 0; 2567 2568 /* 2569 * Stop and then re-open the interface. This will allocate RX 2570 * skbs of the new MTU. 2571 * There is a possible danger that the open will not succeed, 2572 * due to memory being full. 2573 */ 2574 mv643xx_eth_stop(dev); 2575 if (mv643xx_eth_open(dev)) { 2576 netdev_err(dev, 2577 "fatal error on re-opening device after MTU change\n"); 2578 } 2579 2580 return 0; 2581 } 2582 2583 static void tx_timeout_task(struct work_struct *ugly) 2584 { 2585 struct mv643xx_eth_private *mp; 2586 2587 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2588 if (netif_running(mp->dev)) { 2589 netif_tx_stop_all_queues(mp->dev); 2590 port_reset(mp); 2591 port_start(mp); 2592 netif_tx_wake_all_queues(mp->dev); 2593 } 2594 } 2595 2596 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue) 2597 { 2598 struct mv643xx_eth_private *mp = netdev_priv(dev); 2599 2600 netdev_info(dev, "tx timeout\n"); 2601 2602 schedule_work(&mp->tx_timeout_task); 2603 } 2604 2605 #ifdef CONFIG_NET_POLL_CONTROLLER 2606 static void mv643xx_eth_netpoll(struct net_device *dev) 2607 { 2608 struct mv643xx_eth_private *mp = netdev_priv(dev); 2609 2610 wrlp(mp, INT_MASK, 0x00000000); 2611 rdlp(mp, INT_MASK); 2612 2613 mv643xx_eth_irq(dev->irq, dev); 2614 2615 wrlp(mp, INT_MASK, mp->int_mask); 2616 } 2617 #endif 2618 2619 2620 /* platform glue ************************************************************/ 2621 static void 2622 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2623 const struct mbus_dram_target_info *dram) 2624 { 2625 void __iomem *base = msp->base; 2626 u32 win_enable; 2627 u32 win_protect; 2628 int i; 2629 2630 for (i = 0; i < 6; i++) { 2631 writel(0, base + WINDOW_BASE(i)); 2632 writel(0, base + WINDOW_SIZE(i)); 2633 if (i < 4) 2634 writel(0, base + WINDOW_REMAP_HIGH(i)); 2635 } 2636 2637 win_enable = 0x3f; 2638 win_protect = 0; 2639 2640 for (i = 0; i < dram->num_cs; i++) { 2641 const struct mbus_dram_window *cs = dram->cs + i; 2642 2643 writel((cs->base & 0xffff0000) | 2644 (cs->mbus_attr << 8) | 2645 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2646 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2647 2648 win_enable &= ~(1 << i); 2649 win_protect |= 3 << (2 * i); 2650 } 2651 2652 writel(win_enable, base + WINDOW_BAR_ENABLE); 2653 msp->win_protect = win_protect; 2654 } 2655 2656 static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2657 { 2658 /* 2659 * Check whether we have a 14-bit coal limit field in bits 2660 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2661 * SDMA config register. 2662 */ 2663 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2664 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2665 msp->extended_rx_coal_limit = 1; 2666 else 2667 msp->extended_rx_coal_limit = 0; 2668 2669 /* 2670 * Check whether the MAC supports TX rate control, and if 2671 * yes, whether its associated registers are in the old or 2672 * the new place. 2673 */ 2674 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2675 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2676 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2677 } else { 2678 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2679 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2680 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2681 else 2682 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2683 } 2684 } 2685 2686 #if defined(CONFIG_OF) 2687 static const struct of_device_id mv643xx_eth_shared_ids[] = { 2688 { .compatible = "marvell,orion-eth", }, 2689 { .compatible = "marvell,kirkwood-eth", }, 2690 { } 2691 }; 2692 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2693 #endif 2694 2695 #ifdef CONFIG_OF_IRQ 2696 #define mv643xx_eth_property(_np, _name, _v) \ 2697 do { \ 2698 u32 tmp; \ 2699 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2700 _v = tmp; \ 2701 } while (0) 2702 2703 static struct platform_device *port_platdev[3]; 2704 2705 static void mv643xx_eth_shared_of_remove(void) 2706 { 2707 int n; 2708 2709 for (n = 0; n < 3; n++) { 2710 platform_device_del(port_platdev[n]); 2711 port_platdev[n] = NULL; 2712 } 2713 } 2714 2715 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2716 struct device_node *pnp) 2717 { 2718 struct platform_device *ppdev; 2719 struct mv643xx_eth_platform_data ppd; 2720 struct resource res; 2721 int ret; 2722 int dev_num = 0; 2723 2724 memset(&ppd, 0, sizeof(ppd)); 2725 ppd.shared = pdev; 2726 2727 memset(&res, 0, sizeof(res)); 2728 if (of_irq_to_resource(pnp, 0, &res) <= 0) { 2729 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp); 2730 return -EINVAL; 2731 } 2732 2733 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2734 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp); 2735 return -EINVAL; 2736 } 2737 2738 if (ppd.port_number >= 3) { 2739 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp); 2740 return -EINVAL; 2741 } 2742 2743 while (dev_num < 3 && port_platdev[dev_num]) 2744 dev_num++; 2745 2746 if (dev_num == 3) { 2747 dev_err(&pdev->dev, "too many ports registered\n"); 2748 return -EINVAL; 2749 } 2750 2751 ret = of_get_mac_address(pnp, ppd.mac_addr); 2752 if (ret == -EPROBE_DEFER) 2753 return ret; 2754 2755 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2756 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2757 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2758 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2759 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2760 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2761 2762 of_get_phy_mode(pnp, &ppd.interface); 2763 2764 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2765 if (!ppd.phy_node) { 2766 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2767 of_property_read_u32(pnp, "speed", &ppd.speed); 2768 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2769 } 2770 2771 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2772 if (!ppdev) 2773 return -ENOMEM; 2774 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2775 ppdev->dev.of_node = pnp; 2776 2777 ret = platform_device_add_resources(ppdev, &res, 1); 2778 if (ret) 2779 goto port_err; 2780 2781 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2782 if (ret) 2783 goto port_err; 2784 2785 ret = platform_device_add(ppdev); 2786 if (ret) 2787 goto port_err; 2788 2789 port_platdev[dev_num] = ppdev; 2790 2791 return 0; 2792 2793 port_err: 2794 platform_device_put(ppdev); 2795 return ret; 2796 } 2797 2798 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2799 { 2800 struct mv643xx_eth_shared_platform_data *pd; 2801 struct device_node *np = pdev->dev.of_node; 2802 int ret; 2803 2804 /* bail out if not registered from DT */ 2805 if (!np) 2806 return 0; 2807 2808 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2809 if (!pd) 2810 return -ENOMEM; 2811 pdev->dev.platform_data = pd; 2812 2813 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2814 2815 for_each_available_child_of_node_scoped(np, pnp) { 2816 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2817 if (ret) { 2818 mv643xx_eth_shared_of_remove(); 2819 return ret; 2820 } 2821 } 2822 return 0; 2823 } 2824 2825 #else 2826 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2827 { 2828 return 0; 2829 } 2830 2831 static inline void mv643xx_eth_shared_of_remove(void) 2832 { 2833 } 2834 #endif 2835 2836 static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2837 { 2838 static int mv643xx_eth_version_printed; 2839 struct mv643xx_eth_shared_platform_data *pd; 2840 struct mv643xx_eth_shared_private *msp; 2841 const struct mbus_dram_target_info *dram; 2842 int ret; 2843 2844 if (!mv643xx_eth_version_printed++) 2845 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2846 mv643xx_eth_driver_version); 2847 2848 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2849 if (msp == NULL) 2850 return -ENOMEM; 2851 platform_set_drvdata(pdev, msp); 2852 2853 msp->base = devm_platform_ioremap_resource(pdev, 0); 2854 if (IS_ERR(msp->base)) 2855 return PTR_ERR(msp->base); 2856 2857 msp->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 2858 if (IS_ERR(msp->clk)) 2859 return PTR_ERR(msp->clk); 2860 2861 /* 2862 * (Re-)program MBUS remapping windows if we are asked to. 2863 */ 2864 dram = mv_mbus_dram_info(); 2865 if (dram) 2866 mv643xx_eth_conf_mbus_windows(msp, dram); 2867 2868 ret = mv643xx_eth_shared_of_probe(pdev); 2869 if (ret) 2870 return ret; 2871 pd = dev_get_platdata(&pdev->dev); 2872 2873 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2874 pd->tx_csum_limit : 9 * 1024; 2875 infer_hw_params(msp); 2876 2877 return 0; 2878 } 2879 2880 static void mv643xx_eth_shared_remove(struct platform_device *pdev) 2881 { 2882 mv643xx_eth_shared_of_remove(); 2883 } 2884 2885 static struct platform_driver mv643xx_eth_shared_driver = { 2886 .probe = mv643xx_eth_shared_probe, 2887 .remove = mv643xx_eth_shared_remove, 2888 .driver = { 2889 .name = MV643XX_ETH_SHARED_NAME, 2890 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2891 }, 2892 }; 2893 2894 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2895 { 2896 int addr_shift = 5 * mp->port_num; 2897 u32 data; 2898 2899 data = rdl(mp, PHY_ADDR); 2900 data &= ~(0x1f << addr_shift); 2901 data |= (phy_addr & 0x1f) << addr_shift; 2902 wrl(mp, PHY_ADDR, data); 2903 } 2904 2905 static int phy_addr_get(struct mv643xx_eth_private *mp) 2906 { 2907 unsigned int data; 2908 2909 data = rdl(mp, PHY_ADDR); 2910 2911 return (data >> (5 * mp->port_num)) & 0x1f; 2912 } 2913 2914 static void set_params(struct mv643xx_eth_private *mp, 2915 struct mv643xx_eth_platform_data *pd) 2916 { 2917 struct net_device *dev = mp->dev; 2918 unsigned int tx_ring_size; 2919 2920 if (is_valid_ether_addr(pd->mac_addr)) { 2921 eth_hw_addr_set(dev, pd->mac_addr); 2922 } else { 2923 u8 addr[ETH_ALEN]; 2924 2925 uc_addr_get(mp, addr); 2926 eth_hw_addr_set(dev, addr); 2927 } 2928 2929 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2930 if (pd->rx_queue_size) 2931 mp->rx_ring_size = pd->rx_queue_size; 2932 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2933 mp->rx_desc_sram_size = pd->rx_sram_size; 2934 2935 mp->rxq_count = pd->rx_queue_count ? : 1; 2936 2937 tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2938 if (pd->tx_queue_size) 2939 tx_ring_size = pd->tx_queue_size; 2940 2941 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, 2942 MV643XX_MAX_SKB_DESCS * 2, 4096); 2943 if (mp->tx_ring_size != tx_ring_size) 2944 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 2945 mp->tx_ring_size, tx_ring_size); 2946 2947 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2948 mp->tx_desc_sram_size = pd->tx_sram_size; 2949 2950 mp->txq_count = pd->tx_queue_count ? : 1; 2951 } 2952 2953 static int get_phy_mode(struct mv643xx_eth_private *mp) 2954 { 2955 struct device *dev = mp->dev->dev.parent; 2956 phy_interface_t iface; 2957 int err; 2958 2959 if (dev->of_node) 2960 err = of_get_phy_mode(dev->of_node, &iface); 2961 2962 /* Historical default if unspecified. We could also read/write 2963 * the interface state in the PSC1 2964 */ 2965 if (!dev->of_node || err) 2966 iface = PHY_INTERFACE_MODE_GMII; 2967 return iface; 2968 } 2969 2970 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2971 int phy_addr) 2972 { 2973 struct phy_device *phydev; 2974 int start; 2975 int num; 2976 int i; 2977 char phy_id[MII_BUS_ID_SIZE + 3]; 2978 2979 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2980 start = phy_addr_get(mp) & 0x1f; 2981 num = 32; 2982 } else { 2983 start = phy_addr & 0x1f; 2984 num = 1; 2985 } 2986 2987 /* Attempt to connect to the PHY using orion-mdio */ 2988 phydev = ERR_PTR(-ENODEV); 2989 for (i = 0; i < num; i++) { 2990 int addr = (start + i) & 0x1f; 2991 2992 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2993 "orion-mdio-mii", addr); 2994 2995 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 2996 get_phy_mode(mp)); 2997 if (!IS_ERR(phydev)) { 2998 phy_addr_set(mp, addr); 2999 break; 3000 } 3001 } 3002 3003 return phydev; 3004 } 3005 3006 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 3007 { 3008 struct net_device *dev = mp->dev; 3009 struct phy_device *phy = dev->phydev; 3010 3011 if (speed == 0) { 3012 phy->autoneg = AUTONEG_ENABLE; 3013 phy->speed = 0; 3014 phy->duplex = 0; 3015 linkmode_copy(phy->advertising, phy->supported); 3016 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3017 phy->advertising); 3018 } else { 3019 phy->autoneg = AUTONEG_DISABLE; 3020 linkmode_zero(phy->advertising); 3021 phy->speed = speed; 3022 phy->duplex = duplex; 3023 } 3024 phy_start_aneg(phy); 3025 } 3026 3027 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 3028 { 3029 struct net_device *dev = mp->dev; 3030 u32 pscr; 3031 3032 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 3033 if (pscr & SERIAL_PORT_ENABLE) { 3034 pscr &= ~SERIAL_PORT_ENABLE; 3035 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3036 } 3037 3038 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 3039 if (!dev->phydev) { 3040 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 3041 if (speed == SPEED_1000) 3042 pscr |= SET_GMII_SPEED_TO_1000; 3043 else if (speed == SPEED_100) 3044 pscr |= SET_MII_SPEED_TO_100; 3045 3046 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 3047 3048 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 3049 if (duplex == DUPLEX_FULL) 3050 pscr |= SET_FULL_DUPLEX_MODE; 3051 } 3052 3053 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3054 } 3055 3056 static const struct net_device_ops mv643xx_eth_netdev_ops = { 3057 .ndo_open = mv643xx_eth_open, 3058 .ndo_stop = mv643xx_eth_stop, 3059 .ndo_start_xmit = mv643xx_eth_xmit, 3060 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 3061 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 3062 .ndo_validate_addr = eth_validate_addr, 3063 .ndo_eth_ioctl = mv643xx_eth_ioctl, 3064 .ndo_change_mtu = mv643xx_eth_change_mtu, 3065 .ndo_set_features = mv643xx_eth_set_features, 3066 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 3067 .ndo_get_stats = mv643xx_eth_get_stats, 3068 #ifdef CONFIG_NET_POLL_CONTROLLER 3069 .ndo_poll_controller = mv643xx_eth_netpoll, 3070 #endif 3071 }; 3072 3073 static int mv643xx_eth_probe(struct platform_device *pdev) 3074 { 3075 struct mv643xx_eth_platform_data *pd; 3076 struct mv643xx_eth_private *mp; 3077 struct net_device *dev; 3078 struct phy_device *phydev = NULL; 3079 u32 psc1r; 3080 int err, irq; 3081 3082 pd = dev_get_platdata(&pdev->dev); 3083 if (pd == NULL) { 3084 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 3085 return -ENODEV; 3086 } 3087 3088 if (pd->shared == NULL) { 3089 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 3090 return -ENODEV; 3091 } 3092 3093 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 3094 if (!dev) 3095 return -ENOMEM; 3096 3097 SET_NETDEV_DEV(dev, &pdev->dev); 3098 mp = netdev_priv(dev); 3099 platform_set_drvdata(pdev, mp); 3100 3101 mp->shared = platform_get_drvdata(pd->shared); 3102 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 3103 mp->port_num = pd->port_number; 3104 3105 mp->dev = dev; 3106 3107 if (of_device_is_compatible(pdev->dev.of_node, 3108 "marvell,kirkwood-eth-port")) { 3109 psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); 3110 3111 /* Kirkwood resets some registers on gated clocks. Especially 3112 * CLK125_BYPASS_EN must be cleared but is not available on 3113 * all other SoCs/System Controllers using this driver. 3114 */ 3115 psc1r &= ~CLK125_BYPASS_EN; 3116 3117 /* On Kirkwood with two Ethernet controllers, if both of them 3118 * have RGMII_EN disabled, the first controller will be in GMII 3119 * mode and the second one is effectively disabled, instead of 3120 * two MII interfaces. 3121 * 3122 * To enable GMII in the first controller, the second one must 3123 * also be configured (and may be enabled) with RGMII_EN 3124 * disabled too, even though it cannot be used at all. 3125 */ 3126 switch (pd->interface) { 3127 /* Use internal to denote second controller being disabled */ 3128 case PHY_INTERFACE_MODE_INTERNAL: 3129 case PHY_INTERFACE_MODE_MII: 3130 case PHY_INTERFACE_MODE_GMII: 3131 psc1r &= ~RGMII_EN; 3132 break; 3133 case PHY_INTERFACE_MODE_RGMII: 3134 case PHY_INTERFACE_MODE_RGMII_ID: 3135 case PHY_INTERFACE_MODE_RGMII_RXID: 3136 case PHY_INTERFACE_MODE_RGMII_TXID: 3137 psc1r |= RGMII_EN; 3138 break; 3139 default: 3140 /* Unknown; don't touch */ 3141 break; 3142 } 3143 3144 wrlp(mp, PORT_SERIAL_CONTROL1, psc1r); 3145 } 3146 3147 /* 3148 * Start with a default rate, and if there is a clock, allow 3149 * it to override the default. 3150 */ 3151 mp->t_clk = 133000000; 3152 mp->clk = devm_clk_get(&pdev->dev, NULL); 3153 if (!IS_ERR(mp->clk)) { 3154 clk_prepare_enable(mp->clk); 3155 mp->t_clk = clk_get_rate(mp->clk); 3156 } else if (!IS_ERR(mp->shared->clk)) { 3157 mp->t_clk = clk_get_rate(mp->shared->clk); 3158 } 3159 3160 set_params(mp, pd); 3161 netif_set_real_num_tx_queues(dev, mp->txq_count); 3162 netif_set_real_num_rx_queues(dev, mp->rxq_count); 3163 3164 err = 0; 3165 if (pd->phy_node) { 3166 phydev = of_phy_connect(mp->dev, pd->phy_node, 3167 mv643xx_eth_adjust_link, 0, 3168 get_phy_mode(mp)); 3169 if (!phydev) 3170 err = -ENODEV; 3171 else 3172 phy_addr_set(mp, phydev->mdio.addr); 3173 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 3174 phydev = phy_scan(mp, pd->phy_addr); 3175 3176 if (IS_ERR(phydev)) 3177 err = PTR_ERR(phydev); 3178 else 3179 phy_init(mp, pd->speed, pd->duplex); 3180 } 3181 if (err == -ENODEV) { 3182 err = -EPROBE_DEFER; 3183 goto out; 3184 } 3185 if (err) 3186 goto out; 3187 3188 dev->ethtool_ops = &mv643xx_eth_ethtool_ops; 3189 3190 init_pscr(mp, pd->speed, pd->duplex); 3191 3192 3193 mib_counters_clear(mp); 3194 3195 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0); 3196 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 3197 3198 spin_lock_init(&mp->mib_counters_lock); 3199 3200 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 3201 3202 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll); 3203 3204 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0); 3205 3206 3207 irq = platform_get_irq(pdev, 0); 3208 if (WARN_ON(irq < 0)) { 3209 err = irq; 3210 goto out; 3211 } 3212 dev->irq = irq; 3213 3214 dev->netdev_ops = &mv643xx_eth_netdev_ops; 3215 3216 dev->watchdog_timeo = 2 * HZ; 3217 dev->base_addr = 0; 3218 3219 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3220 dev->vlan_features = dev->features; 3221 3222 dev->features |= NETIF_F_RXCSUM; 3223 dev->hw_features = dev->features; 3224 3225 dev->priv_flags |= IFF_UNICAST_FLT; 3226 netif_set_tso_max_segs(dev, MV643XX_MAX_TSO_SEGS); 3227 3228 /* MTU range: 64 - 9500 */ 3229 dev->min_mtu = 64; 3230 dev->max_mtu = 9500; 3231 3232 if (mp->shared->win_protect) 3233 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 3234 3235 netif_carrier_off(dev); 3236 3237 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 3238 3239 set_rx_coal(mp, 250); 3240 set_tx_coal(mp, 0); 3241 3242 err = register_netdev(dev); 3243 if (err) 3244 goto out; 3245 3246 netdev_notice(dev, "port %d with MAC address %pM\n", 3247 mp->port_num, dev->dev_addr); 3248 3249 if (mp->tx_desc_sram_size > 0) 3250 netdev_notice(dev, "configured with sram\n"); 3251 3252 return 0; 3253 3254 out: 3255 if (!IS_ERR(mp->clk)) 3256 clk_disable_unprepare(mp->clk); 3257 free_netdev(dev); 3258 3259 return err; 3260 } 3261 3262 static void mv643xx_eth_remove(struct platform_device *pdev) 3263 { 3264 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3265 struct net_device *dev = mp->dev; 3266 3267 unregister_netdev(mp->dev); 3268 if (dev->phydev) 3269 phy_disconnect(dev->phydev); 3270 cancel_work_sync(&mp->tx_timeout_task); 3271 3272 if (!IS_ERR(mp->clk)) 3273 clk_disable_unprepare(mp->clk); 3274 3275 free_netdev(mp->dev); 3276 } 3277 3278 static void mv643xx_eth_shutdown(struct platform_device *pdev) 3279 { 3280 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3281 3282 /* Mask all interrupts on ethernet port */ 3283 wrlp(mp, INT_MASK, 0); 3284 rdlp(mp, INT_MASK); 3285 3286 if (netif_running(mp->dev)) 3287 port_reset(mp); 3288 } 3289 3290 static struct platform_driver mv643xx_eth_driver = { 3291 .probe = mv643xx_eth_probe, 3292 .remove = mv643xx_eth_remove, 3293 .shutdown = mv643xx_eth_shutdown, 3294 .driver = { 3295 .name = MV643XX_ETH_NAME, 3296 }, 3297 }; 3298 3299 static struct platform_driver * const drivers[] = { 3300 &mv643xx_eth_shared_driver, 3301 &mv643xx_eth_driver, 3302 }; 3303 3304 static int __init mv643xx_eth_init_module(void) 3305 { 3306 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 3307 } 3308 module_init(mv643xx_eth_init_module); 3309 3310 static void __exit mv643xx_eth_cleanup_module(void) 3311 { 3312 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 3313 } 3314 module_exit(mv643xx_eth_cleanup_module); 3315 3316 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3317 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3318 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3319 MODULE_LICENSE("GPL"); 3320 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3321 MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3322