1 /* 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 4 * 5 * Based on the 64360 driver from: 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 7 * Rabeeh Khoury <rabeeh@marvell.com> 8 * 9 * Copyright (C) 2003 PMC-Sierra, Inc., 10 * written by Manish Lachwani 11 * 12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 13 * 14 * Copyright (C) 2004-2006 MontaVista Software, Inc. 15 * Dale Farnsworth <dale@farnsworth.org> 16 * 17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 18 * <sjhill@realitydiluted.com> 19 * 20 * Copyright (C) 2007-2008 Marvell Semiconductor 21 * Lennert Buytenhek <buytenh@marvell.com> 22 * 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 24 * 25 * This program is free software; you can redistribute it and/or 26 * modify it under the terms of the GNU General Public License 27 * as published by the Free Software Foundation; either version 2 28 * of the License, or (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, see <http://www.gnu.org/licenses/>. 37 */ 38 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 40 41 #include <linux/init.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/in.h> 44 #include <linux/ip.h> 45 #include <net/tso.h> 46 #include <linux/tcp.h> 47 #include <linux/udp.h> 48 #include <linux/etherdevice.h> 49 #include <linux/delay.h> 50 #include <linux/ethtool.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/kernel.h> 54 #include <linux/spinlock.h> 55 #include <linux/workqueue.h> 56 #include <linux/phy.h> 57 #include <linux/mv643xx_eth.h> 58 #include <linux/io.h> 59 #include <linux/interrupt.h> 60 #include <linux/types.h> 61 #include <linux/slab.h> 62 #include <linux/clk.h> 63 #include <linux/of.h> 64 #include <linux/of_irq.h> 65 #include <linux/of_net.h> 66 #include <linux/of_mdio.h> 67 68 static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 69 static char mv643xx_eth_driver_version[] = "1.4"; 70 71 72 /* 73 * Registers shared between all ports. 74 */ 75 #define PHY_ADDR 0x0000 76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 79 #define WINDOW_BAR_ENABLE 0x0290 80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 81 82 /* 83 * Main per-port registers. These live at offset 0x0400 for 84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 85 */ 86 #define PORT_CONFIG 0x0000 87 #define UNICAST_PROMISCUOUS_MODE 0x00000001 88 #define PORT_CONFIG_EXT 0x0004 89 #define MAC_ADDR_LOW 0x0014 90 #define MAC_ADDR_HIGH 0x0018 91 #define SDMA_CONFIG 0x001c 92 #define TX_BURST_SIZE_16_64BIT 0x01000000 93 #define TX_BURST_SIZE_4_64BIT 0x00800000 94 #define BLM_TX_NO_SWAP 0x00000020 95 #define BLM_RX_NO_SWAP 0x00000010 96 #define RX_BURST_SIZE_16_64BIT 0x00000008 97 #define RX_BURST_SIZE_4_64BIT 0x00000004 98 #define PORT_SERIAL_CONTROL 0x003c 99 #define SET_MII_SPEED_TO_100 0x01000000 100 #define SET_GMII_SPEED_TO_1000 0x00800000 101 #define SET_FULL_DUPLEX_MODE 0x00200000 102 #define MAX_RX_PACKET_9700BYTE 0x000a0000 103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400 105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 108 #define FORCE_LINK_PASS 0x00000002 109 #define SERIAL_PORT_ENABLE 0x00000001 110 #define PORT_STATUS 0x0044 111 #define TX_FIFO_EMPTY 0x00000400 112 #define TX_IN_PROGRESS 0x00000080 113 #define PORT_SPEED_MASK 0x00000030 114 #define PORT_SPEED_1000 0x00000010 115 #define PORT_SPEED_100 0x00000020 116 #define PORT_SPEED_10 0x00000000 117 #define FLOW_CONTROL_ENABLED 0x00000008 118 #define FULL_DUPLEX 0x00000004 119 #define LINK_UP 0x00000002 120 #define TXQ_COMMAND 0x0048 121 #define TXQ_FIX_PRIO_CONF 0x004c 122 #define PORT_SERIAL_CONTROL1 0x004c 123 #define CLK125_BYPASS_EN 0x00000010 124 #define TX_BW_RATE 0x0050 125 #define TX_BW_MTU 0x0058 126 #define TX_BW_BURST 0x005c 127 #define INT_CAUSE 0x0060 128 #define INT_TX_END 0x07f80000 129 #define INT_TX_END_0 0x00080000 130 #define INT_RX 0x000003fc 131 #define INT_RX_0 0x00000004 132 #define INT_EXT 0x00000002 133 #define INT_CAUSE_EXT 0x0064 134 #define INT_EXT_LINK_PHY 0x00110000 135 #define INT_EXT_TX 0x000000ff 136 #define INT_MASK 0x0068 137 #define INT_MASK_EXT 0x006c 138 #define TX_FIFO_URGENT_THRESHOLD 0x0074 139 #define RX_DISCARD_FRAME_CNT 0x0084 140 #define RX_OVERRUN_FRAME_CNT 0x0088 141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 142 #define TX_BW_RATE_MOVED 0x00e0 143 #define TX_BW_MTU_MOVED 0x00e8 144 #define TX_BW_BURST_MOVED 0x00ec 145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 146 #define RXQ_COMMAND 0x0280 147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 151 152 /* 153 * Misc per-port registers. 154 */ 155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 159 160 161 /* 162 * SDMA configuration register default value. 163 */ 164 #if defined(__BIG_ENDIAN) 165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 166 (RX_BURST_SIZE_4_64BIT | \ 167 TX_BURST_SIZE_4_64BIT) 168 #elif defined(__LITTLE_ENDIAN) 169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 170 (RX_BURST_SIZE_4_64BIT | \ 171 BLM_RX_NO_SWAP | \ 172 BLM_TX_NO_SWAP | \ 173 TX_BURST_SIZE_4_64BIT) 174 #else 175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 176 #endif 177 178 179 /* 180 * Misc definitions. 181 */ 182 #define DEFAULT_RX_QUEUE_SIZE 128 183 #define DEFAULT_TX_QUEUE_SIZE 512 184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 185 186 #define TSO_HEADER_SIZE 128 187 188 /* Max number of allowed TCP segments for software TSO */ 189 #define MV643XX_MAX_TSO_SEGS 100 190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 191 192 #define IS_TSO_HEADER(txq, addr) \ 193 ((addr >= txq->tso_hdrs_dma) && \ 194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 195 /* 196 * RX/TX descriptors. 197 */ 198 #if defined(__BIG_ENDIAN) 199 struct rx_desc { 200 u16 byte_cnt; /* Descriptor buffer byte count */ 201 u16 buf_size; /* Buffer size */ 202 u32 cmd_sts; /* Descriptor command status */ 203 u32 next_desc_ptr; /* Next descriptor pointer */ 204 u32 buf_ptr; /* Descriptor buffer pointer */ 205 }; 206 207 struct tx_desc { 208 u16 byte_cnt; /* buffer byte count */ 209 u16 l4i_chk; /* CPU provided TCP checksum */ 210 u32 cmd_sts; /* Command/status field */ 211 u32 next_desc_ptr; /* Pointer to next descriptor */ 212 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 213 }; 214 #elif defined(__LITTLE_ENDIAN) 215 struct rx_desc { 216 u32 cmd_sts; /* Descriptor command status */ 217 u16 buf_size; /* Buffer size */ 218 u16 byte_cnt; /* Descriptor buffer byte count */ 219 u32 buf_ptr; /* Descriptor buffer pointer */ 220 u32 next_desc_ptr; /* Next descriptor pointer */ 221 }; 222 223 struct tx_desc { 224 u32 cmd_sts; /* Command/status field */ 225 u16 l4i_chk; /* CPU provided TCP checksum */ 226 u16 byte_cnt; /* buffer byte count */ 227 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 228 u32 next_desc_ptr; /* Pointer to next descriptor */ 229 }; 230 #else 231 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 232 #endif 233 234 /* RX & TX descriptor command */ 235 #define BUFFER_OWNED_BY_DMA 0x80000000 236 237 /* RX & TX descriptor status */ 238 #define ERROR_SUMMARY 0x00000001 239 240 /* RX descriptor status */ 241 #define LAYER_4_CHECKSUM_OK 0x40000000 242 #define RX_ENABLE_INTERRUPT 0x20000000 243 #define RX_FIRST_DESC 0x08000000 244 #define RX_LAST_DESC 0x04000000 245 #define RX_IP_HDR_OK 0x02000000 246 #define RX_PKT_IS_IPV4 0x01000000 247 #define RX_PKT_IS_ETHERNETV2 0x00800000 248 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 249 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 250 #define RX_PKT_IS_VLAN_TAGGED 0x00080000 251 252 /* TX descriptor command */ 253 #define TX_ENABLE_INTERRUPT 0x00800000 254 #define GEN_CRC 0x00400000 255 #define TX_FIRST_DESC 0x00200000 256 #define TX_LAST_DESC 0x00100000 257 #define ZERO_PADDING 0x00080000 258 #define GEN_IP_V4_CHECKSUM 0x00040000 259 #define GEN_TCP_UDP_CHECKSUM 0x00020000 260 #define UDP_FRAME 0x00010000 261 #define MAC_HDR_EXTRA_4_BYTES 0x00008000 262 #define GEN_TCP_UDP_CHK_FULL 0x00000400 263 #define MAC_HDR_EXTRA_8_BYTES 0x00000200 264 265 #define TX_IHL_SHIFT 11 266 267 268 /* global *******************************************************************/ 269 struct mv643xx_eth_shared_private { 270 /* 271 * Ethernet controller base address. 272 */ 273 void __iomem *base; 274 275 /* 276 * Per-port MBUS window access register value. 277 */ 278 u32 win_protect; 279 280 /* 281 * Hardware-specific parameters. 282 */ 283 int extended_rx_coal_limit; 284 int tx_bw_control; 285 int tx_csum_limit; 286 struct clk *clk; 287 }; 288 289 #define TX_BW_CONTROL_ABSENT 0 290 #define TX_BW_CONTROL_OLD_LAYOUT 1 291 #define TX_BW_CONTROL_NEW_LAYOUT 2 292 293 static int mv643xx_eth_open(struct net_device *dev); 294 static int mv643xx_eth_stop(struct net_device *dev); 295 296 297 /* per-port *****************************************************************/ 298 struct mib_counters { 299 u64 good_octets_received; 300 u32 bad_octets_received; 301 u32 internal_mac_transmit_err; 302 u32 good_frames_received; 303 u32 bad_frames_received; 304 u32 broadcast_frames_received; 305 u32 multicast_frames_received; 306 u32 frames_64_octets; 307 u32 frames_65_to_127_octets; 308 u32 frames_128_to_255_octets; 309 u32 frames_256_to_511_octets; 310 u32 frames_512_to_1023_octets; 311 u32 frames_1024_to_max_octets; 312 u64 good_octets_sent; 313 u32 good_frames_sent; 314 u32 excessive_collision; 315 u32 multicast_frames_sent; 316 u32 broadcast_frames_sent; 317 u32 unrec_mac_control_received; 318 u32 fc_sent; 319 u32 good_fc_received; 320 u32 bad_fc_received; 321 u32 undersize_received; 322 u32 fragments_received; 323 u32 oversize_received; 324 u32 jabber_received; 325 u32 mac_receive_error; 326 u32 bad_crc_event; 327 u32 collision; 328 u32 late_collision; 329 /* Non MIB hardware counters */ 330 u32 rx_discard; 331 u32 rx_overrun; 332 }; 333 334 struct rx_queue { 335 int index; 336 337 int rx_ring_size; 338 339 int rx_desc_count; 340 int rx_curr_desc; 341 int rx_used_desc; 342 343 struct rx_desc *rx_desc_area; 344 dma_addr_t rx_desc_dma; 345 int rx_desc_area_size; 346 struct sk_buff **rx_skb; 347 }; 348 349 struct tx_queue { 350 int index; 351 352 int tx_ring_size; 353 354 int tx_desc_count; 355 int tx_curr_desc; 356 int tx_used_desc; 357 358 int tx_stop_threshold; 359 int tx_wake_threshold; 360 361 char *tso_hdrs; 362 dma_addr_t tso_hdrs_dma; 363 364 struct tx_desc *tx_desc_area; 365 dma_addr_t tx_desc_dma; 366 int tx_desc_area_size; 367 368 struct sk_buff_head tx_skb; 369 370 unsigned long tx_packets; 371 unsigned long tx_bytes; 372 unsigned long tx_dropped; 373 }; 374 375 struct mv643xx_eth_private { 376 struct mv643xx_eth_shared_private *shared; 377 void __iomem *base; 378 int port_num; 379 380 struct net_device *dev; 381 382 struct phy_device *phy; 383 384 struct timer_list mib_counters_timer; 385 spinlock_t mib_counters_lock; 386 struct mib_counters mib_counters; 387 388 struct work_struct tx_timeout_task; 389 390 struct napi_struct napi; 391 u32 int_mask; 392 u8 oom; 393 u8 work_link; 394 u8 work_tx; 395 u8 work_tx_end; 396 u8 work_rx; 397 u8 work_rx_refill; 398 399 int skb_size; 400 401 /* 402 * RX state. 403 */ 404 int rx_ring_size; 405 unsigned long rx_desc_sram_addr; 406 int rx_desc_sram_size; 407 int rxq_count; 408 struct timer_list rx_oom; 409 struct rx_queue rxq[8]; 410 411 /* 412 * TX state. 413 */ 414 int tx_ring_size; 415 unsigned long tx_desc_sram_addr; 416 int tx_desc_sram_size; 417 int txq_count; 418 struct tx_queue txq[8]; 419 420 /* 421 * Hardware-specific parameters. 422 */ 423 struct clk *clk; 424 unsigned int t_clk; 425 }; 426 427 428 /* port register accessors **************************************************/ 429 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 430 { 431 return readl(mp->shared->base + offset); 432 } 433 434 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 435 { 436 return readl(mp->base + offset); 437 } 438 439 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 440 { 441 writel(data, mp->shared->base + offset); 442 } 443 444 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 445 { 446 writel(data, mp->base + offset); 447 } 448 449 450 /* rxq/txq helper functions *************************************************/ 451 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 452 { 453 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 454 } 455 456 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 457 { 458 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 459 } 460 461 static void rxq_enable(struct rx_queue *rxq) 462 { 463 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 464 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 465 } 466 467 static void rxq_disable(struct rx_queue *rxq) 468 { 469 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 470 u8 mask = 1 << rxq->index; 471 472 wrlp(mp, RXQ_COMMAND, mask << 8); 473 while (rdlp(mp, RXQ_COMMAND) & mask) 474 udelay(10); 475 } 476 477 static void txq_reset_hw_ptr(struct tx_queue *txq) 478 { 479 struct mv643xx_eth_private *mp = txq_to_mp(txq); 480 u32 addr; 481 482 addr = (u32)txq->tx_desc_dma; 483 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 484 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 485 } 486 487 static void txq_enable(struct tx_queue *txq) 488 { 489 struct mv643xx_eth_private *mp = txq_to_mp(txq); 490 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 491 } 492 493 static void txq_disable(struct tx_queue *txq) 494 { 495 struct mv643xx_eth_private *mp = txq_to_mp(txq); 496 u8 mask = 1 << txq->index; 497 498 wrlp(mp, TXQ_COMMAND, mask << 8); 499 while (rdlp(mp, TXQ_COMMAND) & mask) 500 udelay(10); 501 } 502 503 static void txq_maybe_wake(struct tx_queue *txq) 504 { 505 struct mv643xx_eth_private *mp = txq_to_mp(txq); 506 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 507 508 if (netif_tx_queue_stopped(nq)) { 509 __netif_tx_lock(nq, smp_processor_id()); 510 if (txq->tx_desc_count <= txq->tx_wake_threshold) 511 netif_tx_wake_queue(nq); 512 __netif_tx_unlock(nq); 513 } 514 } 515 516 static int rxq_process(struct rx_queue *rxq, int budget) 517 { 518 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 519 struct net_device_stats *stats = &mp->dev->stats; 520 int rx; 521 522 rx = 0; 523 while (rx < budget && rxq->rx_desc_count) { 524 struct rx_desc *rx_desc; 525 unsigned int cmd_sts; 526 struct sk_buff *skb; 527 u16 byte_cnt; 528 529 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 530 531 cmd_sts = rx_desc->cmd_sts; 532 if (cmd_sts & BUFFER_OWNED_BY_DMA) 533 break; 534 rmb(); 535 536 skb = rxq->rx_skb[rxq->rx_curr_desc]; 537 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 538 539 rxq->rx_curr_desc++; 540 if (rxq->rx_curr_desc == rxq->rx_ring_size) 541 rxq->rx_curr_desc = 0; 542 543 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 544 rx_desc->buf_size, DMA_FROM_DEVICE); 545 rxq->rx_desc_count--; 546 rx++; 547 548 mp->work_rx_refill |= 1 << rxq->index; 549 550 byte_cnt = rx_desc->byte_cnt; 551 552 /* 553 * Update statistics. 554 * 555 * Note that the descriptor byte count includes 2 dummy 556 * bytes automatically inserted by the hardware at the 557 * start of the packet (which we don't count), and a 4 558 * byte CRC at the end of the packet (which we do count). 559 */ 560 stats->rx_packets++; 561 stats->rx_bytes += byte_cnt - 2; 562 563 /* 564 * In case we received a packet without first / last bits 565 * on, or the error summary bit is set, the packet needs 566 * to be dropped. 567 */ 568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 569 != (RX_FIRST_DESC | RX_LAST_DESC)) 570 goto err; 571 572 /* 573 * The -4 is for the CRC in the trailer of the 574 * received packet 575 */ 576 skb_put(skb, byte_cnt - 2 - 4); 577 578 if (cmd_sts & LAYER_4_CHECKSUM_OK) 579 skb->ip_summed = CHECKSUM_UNNECESSARY; 580 skb->protocol = eth_type_trans(skb, mp->dev); 581 582 napi_gro_receive(&mp->napi, skb); 583 584 continue; 585 586 err: 587 stats->rx_dropped++; 588 589 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 590 (RX_FIRST_DESC | RX_LAST_DESC)) { 591 if (net_ratelimit()) 592 netdev_err(mp->dev, 593 "received packet spanning multiple descriptors\n"); 594 } 595 596 if (cmd_sts & ERROR_SUMMARY) 597 stats->rx_errors++; 598 599 dev_kfree_skb(skb); 600 } 601 602 if (rx < budget) 603 mp->work_rx &= ~(1 << rxq->index); 604 605 return rx; 606 } 607 608 static int rxq_refill(struct rx_queue *rxq, int budget) 609 { 610 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 611 int refilled; 612 613 refilled = 0; 614 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 615 struct sk_buff *skb; 616 int rx; 617 struct rx_desc *rx_desc; 618 int size; 619 620 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 621 622 if (skb == NULL) { 623 mp->oom = 1; 624 goto oom; 625 } 626 627 if (SKB_DMA_REALIGN) 628 skb_reserve(skb, SKB_DMA_REALIGN); 629 630 refilled++; 631 rxq->rx_desc_count++; 632 633 rx = rxq->rx_used_desc++; 634 if (rxq->rx_used_desc == rxq->rx_ring_size) 635 rxq->rx_used_desc = 0; 636 637 rx_desc = rxq->rx_desc_area + rx; 638 639 size = skb_end_pointer(skb) - skb->data; 640 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 641 skb->data, size, 642 DMA_FROM_DEVICE); 643 rx_desc->buf_size = size; 644 rxq->rx_skb[rx] = skb; 645 wmb(); 646 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 647 wmb(); 648 649 /* 650 * The hardware automatically prepends 2 bytes of 651 * dummy data to each received packet, so that the 652 * IP header ends up 16-byte aligned. 653 */ 654 skb_reserve(skb, 2); 655 } 656 657 if (refilled < budget) 658 mp->work_rx_refill &= ~(1 << rxq->index); 659 660 oom: 661 return refilled; 662 } 663 664 665 /* tx ***********************************************************************/ 666 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 667 { 668 int frag; 669 670 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 671 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 672 673 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7) 674 return 1; 675 } 676 677 return 0; 678 } 679 680 static inline __be16 sum16_as_be(__sum16 sum) 681 { 682 return (__force __be16)sum; 683 } 684 685 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, 686 u16 *l4i_chk, u32 *command, int length) 687 { 688 int ret; 689 u32 cmd = 0; 690 691 if (skb->ip_summed == CHECKSUM_PARTIAL) { 692 int hdr_len; 693 int tag_bytes; 694 695 BUG_ON(skb->protocol != htons(ETH_P_IP) && 696 skb->protocol != htons(ETH_P_8021Q)); 697 698 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 699 tag_bytes = hdr_len - ETH_HLEN; 700 701 if (length - hdr_len > mp->shared->tx_csum_limit || 702 unlikely(tag_bytes & ~12)) { 703 ret = skb_checksum_help(skb); 704 if (!ret) 705 goto no_csum; 706 return ret; 707 } 708 709 if (tag_bytes & 4) 710 cmd |= MAC_HDR_EXTRA_4_BYTES; 711 if (tag_bytes & 8) 712 cmd |= MAC_HDR_EXTRA_8_BYTES; 713 714 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | 715 GEN_IP_V4_CHECKSUM | 716 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 717 718 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL 719 * it seems we don't need to pass the initial checksum. */ 720 switch (ip_hdr(skb)->protocol) { 721 case IPPROTO_UDP: 722 cmd |= UDP_FRAME; 723 *l4i_chk = 0; 724 break; 725 case IPPROTO_TCP: 726 *l4i_chk = 0; 727 break; 728 default: 729 WARN(1, "protocol not supported"); 730 } 731 } else { 732 no_csum: 733 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 734 cmd |= 5 << TX_IHL_SHIFT; 735 } 736 *command = cmd; 737 return 0; 738 } 739 740 static inline int 741 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, 742 struct sk_buff *skb, char *data, int length, 743 bool last_tcp, bool is_last) 744 { 745 int tx_index; 746 u32 cmd_sts; 747 struct tx_desc *desc; 748 749 tx_index = txq->tx_curr_desc++; 750 if (txq->tx_curr_desc == txq->tx_ring_size) 751 txq->tx_curr_desc = 0; 752 desc = &txq->tx_desc_area[tx_index]; 753 754 desc->l4i_chk = 0; 755 desc->byte_cnt = length; 756 desc->buf_ptr = dma_map_single(dev->dev.parent, data, 757 length, DMA_TO_DEVICE); 758 if (unlikely(dma_mapping_error(dev->dev.parent, desc->buf_ptr))) { 759 WARN(1, "dma_map_single failed!\n"); 760 return -ENOMEM; 761 } 762 763 cmd_sts = BUFFER_OWNED_BY_DMA; 764 if (last_tcp) { 765 /* last descriptor in the TCP packet */ 766 cmd_sts |= ZERO_PADDING | TX_LAST_DESC; 767 /* last descriptor in SKB */ 768 if (is_last) 769 cmd_sts |= TX_ENABLE_INTERRUPT; 770 } 771 desc->cmd_sts = cmd_sts; 772 return 0; 773 } 774 775 static inline void 776 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length) 777 { 778 struct mv643xx_eth_private *mp = txq_to_mp(txq); 779 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 780 int tx_index; 781 struct tx_desc *desc; 782 int ret; 783 u32 cmd_csum = 0; 784 u16 l4i_chk = 0; 785 786 tx_index = txq->tx_curr_desc; 787 desc = &txq->tx_desc_area[tx_index]; 788 789 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); 790 if (ret) 791 WARN(1, "failed to prepare checksum!"); 792 793 /* Should we set this? Can't use the value from skb_tx_csum() 794 * as it's not the correct initial L4 checksum to use. */ 795 desc->l4i_chk = 0; 796 797 desc->byte_cnt = hdr_len; 798 desc->buf_ptr = txq->tso_hdrs_dma + 799 txq->tx_curr_desc * TSO_HEADER_SIZE; 800 desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | 801 GEN_CRC; 802 803 txq->tx_curr_desc++; 804 if (txq->tx_curr_desc == txq->tx_ring_size) 805 txq->tx_curr_desc = 0; 806 } 807 808 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, 809 struct net_device *dev) 810 { 811 struct mv643xx_eth_private *mp = txq_to_mp(txq); 812 int total_len, data_left, ret; 813 int desc_count = 0; 814 struct tso_t tso; 815 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 816 817 /* Count needed descriptors */ 818 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { 819 netdev_dbg(dev, "not enough descriptors for TSO!\n"); 820 return -EBUSY; 821 } 822 823 /* Initialize the TSO handler, and prepare the first payload */ 824 tso_start(skb, &tso); 825 826 total_len = skb->len - hdr_len; 827 while (total_len > 0) { 828 char *hdr; 829 830 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 831 total_len -= data_left; 832 desc_count++; 833 834 /* prepare packet headers: MAC + IP + TCP */ 835 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; 836 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 837 txq_put_hdr_tso(skb, txq, data_left); 838 839 while (data_left > 0) { 840 int size; 841 desc_count++; 842 843 size = min_t(int, tso.size, data_left); 844 ret = txq_put_data_tso(dev, txq, skb, tso.data, size, 845 size == data_left, 846 total_len == 0); 847 if (ret) 848 goto err_release; 849 data_left -= size; 850 tso_build_data(skb, &tso, size); 851 } 852 } 853 854 __skb_queue_tail(&txq->tx_skb, skb); 855 skb_tx_timestamp(skb); 856 857 /* clear TX_END status */ 858 mp->work_tx_end &= ~(1 << txq->index); 859 860 /* ensure all descriptors are written before poking hardware */ 861 wmb(); 862 txq_enable(txq); 863 txq->tx_desc_count += desc_count; 864 return 0; 865 err_release: 866 /* TODO: Release all used data descriptors; header descriptors must not 867 * be DMA-unmapped. 868 */ 869 return ret; 870 } 871 872 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 873 { 874 struct mv643xx_eth_private *mp = txq_to_mp(txq); 875 int nr_frags = skb_shinfo(skb)->nr_frags; 876 int frag; 877 878 for (frag = 0; frag < nr_frags; frag++) { 879 skb_frag_t *this_frag; 880 int tx_index; 881 struct tx_desc *desc; 882 void *addr; 883 884 this_frag = &skb_shinfo(skb)->frags[frag]; 885 addr = page_address(this_frag->page.p) + this_frag->page_offset; 886 tx_index = txq->tx_curr_desc++; 887 if (txq->tx_curr_desc == txq->tx_ring_size) 888 txq->tx_curr_desc = 0; 889 desc = &txq->tx_desc_area[tx_index]; 890 891 /* 892 * The last fragment will generate an interrupt 893 * which will free the skb on TX completion. 894 */ 895 if (frag == nr_frags - 1) { 896 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 897 ZERO_PADDING | TX_LAST_DESC | 898 TX_ENABLE_INTERRUPT; 899 } else { 900 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 901 } 902 903 desc->l4i_chk = 0; 904 desc->byte_cnt = skb_frag_size(this_frag); 905 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, addr, 906 desc->byte_cnt, DMA_TO_DEVICE); 907 } 908 } 909 910 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, 911 struct net_device *dev) 912 { 913 struct mv643xx_eth_private *mp = txq_to_mp(txq); 914 int nr_frags = skb_shinfo(skb)->nr_frags; 915 int tx_index; 916 struct tx_desc *desc; 917 u32 cmd_sts; 918 u16 l4i_chk; 919 int length, ret; 920 921 cmd_sts = 0; 922 l4i_chk = 0; 923 924 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 925 if (net_ratelimit()) 926 netdev_err(dev, "tx queue full?!\n"); 927 return -EBUSY; 928 } 929 930 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); 931 if (ret) 932 return ret; 933 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 934 935 tx_index = txq->tx_curr_desc++; 936 if (txq->tx_curr_desc == txq->tx_ring_size) 937 txq->tx_curr_desc = 0; 938 desc = &txq->tx_desc_area[tx_index]; 939 940 if (nr_frags) { 941 txq_submit_frag_skb(txq, skb); 942 length = skb_headlen(skb); 943 } else { 944 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 945 length = skb->len; 946 } 947 948 desc->l4i_chk = l4i_chk; 949 desc->byte_cnt = length; 950 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 951 length, DMA_TO_DEVICE); 952 953 __skb_queue_tail(&txq->tx_skb, skb); 954 955 skb_tx_timestamp(skb); 956 957 /* ensure all other descriptors are written before first cmd_sts */ 958 wmb(); 959 desc->cmd_sts = cmd_sts; 960 961 /* clear TX_END status */ 962 mp->work_tx_end &= ~(1 << txq->index); 963 964 /* ensure all descriptors are written before poking hardware */ 965 wmb(); 966 txq_enable(txq); 967 968 txq->tx_desc_count += nr_frags + 1; 969 970 return 0; 971 } 972 973 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 974 { 975 struct mv643xx_eth_private *mp = netdev_priv(dev); 976 int length, queue, ret; 977 struct tx_queue *txq; 978 struct netdev_queue *nq; 979 980 queue = skb_get_queue_mapping(skb); 981 txq = mp->txq + queue; 982 nq = netdev_get_tx_queue(dev, queue); 983 984 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 985 netdev_printk(KERN_DEBUG, dev, 986 "failed to linearize skb with tiny unaligned fragment\n"); 987 return NETDEV_TX_BUSY; 988 } 989 990 length = skb->len; 991 992 if (skb_is_gso(skb)) 993 ret = txq_submit_tso(txq, skb, dev); 994 else 995 ret = txq_submit_skb(txq, skb, dev); 996 if (!ret) { 997 txq->tx_bytes += length; 998 txq->tx_packets++; 999 1000 if (txq->tx_desc_count >= txq->tx_stop_threshold) 1001 netif_tx_stop_queue(nq); 1002 } else { 1003 txq->tx_dropped++; 1004 dev_kfree_skb_any(skb); 1005 } 1006 1007 return NETDEV_TX_OK; 1008 } 1009 1010 1011 /* tx napi ******************************************************************/ 1012 static void txq_kick(struct tx_queue *txq) 1013 { 1014 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1015 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1016 u32 hw_desc_ptr; 1017 u32 expected_ptr; 1018 1019 __netif_tx_lock(nq, smp_processor_id()); 1020 1021 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 1022 goto out; 1023 1024 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 1025 expected_ptr = (u32)txq->tx_desc_dma + 1026 txq->tx_curr_desc * sizeof(struct tx_desc); 1027 1028 if (hw_desc_ptr != expected_ptr) 1029 txq_enable(txq); 1030 1031 out: 1032 __netif_tx_unlock(nq); 1033 1034 mp->work_tx_end &= ~(1 << txq->index); 1035 } 1036 1037 static int txq_reclaim(struct tx_queue *txq, int budget, int force) 1038 { 1039 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1040 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1041 int reclaimed; 1042 1043 __netif_tx_lock_bh(nq); 1044 1045 reclaimed = 0; 1046 while (reclaimed < budget && txq->tx_desc_count > 0) { 1047 int tx_index; 1048 struct tx_desc *desc; 1049 u32 cmd_sts; 1050 struct sk_buff *skb; 1051 1052 tx_index = txq->tx_used_desc; 1053 desc = &txq->tx_desc_area[tx_index]; 1054 cmd_sts = desc->cmd_sts; 1055 1056 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 1057 if (!force) 1058 break; 1059 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 1060 } 1061 1062 txq->tx_used_desc = tx_index + 1; 1063 if (txq->tx_used_desc == txq->tx_ring_size) 1064 txq->tx_used_desc = 0; 1065 1066 reclaimed++; 1067 txq->tx_desc_count--; 1068 1069 skb = NULL; 1070 if (cmd_sts & TX_LAST_DESC) 1071 skb = __skb_dequeue(&txq->tx_skb); 1072 1073 if (cmd_sts & ERROR_SUMMARY) { 1074 netdev_info(mp->dev, "tx error\n"); 1075 mp->dev->stats.tx_errors++; 1076 } 1077 1078 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) 1079 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, 1080 desc->byte_cnt, DMA_TO_DEVICE); 1081 dev_kfree_skb(skb); 1082 } 1083 1084 __netif_tx_unlock_bh(nq); 1085 1086 if (reclaimed < budget) 1087 mp->work_tx &= ~(1 << txq->index); 1088 1089 return reclaimed; 1090 } 1091 1092 1093 /* tx rate control **********************************************************/ 1094 /* 1095 * Set total maximum TX rate (shared by all TX queues for this port) 1096 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1097 */ 1098 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1099 { 1100 int token_rate; 1101 int mtu; 1102 int bucket_size; 1103 1104 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1105 if (token_rate > 1023) 1106 token_rate = 1023; 1107 1108 mtu = (mp->dev->mtu + 255) >> 8; 1109 if (mtu > 63) 1110 mtu = 63; 1111 1112 bucket_size = (burst + 255) >> 8; 1113 if (bucket_size > 65535) 1114 bucket_size = 65535; 1115 1116 switch (mp->shared->tx_bw_control) { 1117 case TX_BW_CONTROL_OLD_LAYOUT: 1118 wrlp(mp, TX_BW_RATE, token_rate); 1119 wrlp(mp, TX_BW_MTU, mtu); 1120 wrlp(mp, TX_BW_BURST, bucket_size); 1121 break; 1122 case TX_BW_CONTROL_NEW_LAYOUT: 1123 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1124 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1125 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1126 break; 1127 } 1128 } 1129 1130 static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1131 { 1132 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1133 int token_rate; 1134 int bucket_size; 1135 1136 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1137 if (token_rate > 1023) 1138 token_rate = 1023; 1139 1140 bucket_size = (burst + 255) >> 8; 1141 if (bucket_size > 65535) 1142 bucket_size = 65535; 1143 1144 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1145 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1146 } 1147 1148 static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1149 { 1150 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1151 int off; 1152 u32 val; 1153 1154 /* 1155 * Turn on fixed priority mode. 1156 */ 1157 off = 0; 1158 switch (mp->shared->tx_bw_control) { 1159 case TX_BW_CONTROL_OLD_LAYOUT: 1160 off = TXQ_FIX_PRIO_CONF; 1161 break; 1162 case TX_BW_CONTROL_NEW_LAYOUT: 1163 off = TXQ_FIX_PRIO_CONF_MOVED; 1164 break; 1165 } 1166 1167 if (off) { 1168 val = rdlp(mp, off); 1169 val |= 1 << txq->index; 1170 wrlp(mp, off, val); 1171 } 1172 } 1173 1174 1175 /* mii management interface *************************************************/ 1176 static void mv643xx_eth_adjust_link(struct net_device *dev) 1177 { 1178 struct mv643xx_eth_private *mp = netdev_priv(dev); 1179 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1180 u32 autoneg_disable = FORCE_LINK_PASS | 1181 DISABLE_AUTO_NEG_SPEED_GMII | 1182 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1183 DISABLE_AUTO_NEG_FOR_DUPLEX; 1184 1185 if (mp->phy->autoneg == AUTONEG_ENABLE) { 1186 /* enable auto negotiation */ 1187 pscr &= ~autoneg_disable; 1188 goto out_write; 1189 } 1190 1191 pscr |= autoneg_disable; 1192 1193 if (mp->phy->speed == SPEED_1000) { 1194 /* force gigabit, half duplex not supported */ 1195 pscr |= SET_GMII_SPEED_TO_1000; 1196 pscr |= SET_FULL_DUPLEX_MODE; 1197 goto out_write; 1198 } 1199 1200 pscr &= ~SET_GMII_SPEED_TO_1000; 1201 1202 if (mp->phy->speed == SPEED_100) 1203 pscr |= SET_MII_SPEED_TO_100; 1204 else 1205 pscr &= ~SET_MII_SPEED_TO_100; 1206 1207 if (mp->phy->duplex == DUPLEX_FULL) 1208 pscr |= SET_FULL_DUPLEX_MODE; 1209 else 1210 pscr &= ~SET_FULL_DUPLEX_MODE; 1211 1212 out_write: 1213 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1214 } 1215 1216 /* statistics ***************************************************************/ 1217 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1218 { 1219 struct mv643xx_eth_private *mp = netdev_priv(dev); 1220 struct net_device_stats *stats = &dev->stats; 1221 unsigned long tx_packets = 0; 1222 unsigned long tx_bytes = 0; 1223 unsigned long tx_dropped = 0; 1224 int i; 1225 1226 for (i = 0; i < mp->txq_count; i++) { 1227 struct tx_queue *txq = mp->txq + i; 1228 1229 tx_packets += txq->tx_packets; 1230 tx_bytes += txq->tx_bytes; 1231 tx_dropped += txq->tx_dropped; 1232 } 1233 1234 stats->tx_packets = tx_packets; 1235 stats->tx_bytes = tx_bytes; 1236 stats->tx_dropped = tx_dropped; 1237 1238 return stats; 1239 } 1240 1241 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1242 { 1243 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1244 } 1245 1246 static void mib_counters_clear(struct mv643xx_eth_private *mp) 1247 { 1248 int i; 1249 1250 for (i = 0; i < 0x80; i += 4) 1251 mib_read(mp, i); 1252 1253 /* Clear non MIB hw counters also */ 1254 rdlp(mp, RX_DISCARD_FRAME_CNT); 1255 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1256 } 1257 1258 static void mib_counters_update(struct mv643xx_eth_private *mp) 1259 { 1260 struct mib_counters *p = &mp->mib_counters; 1261 1262 spin_lock_bh(&mp->mib_counters_lock); 1263 p->good_octets_received += mib_read(mp, 0x00); 1264 p->bad_octets_received += mib_read(mp, 0x08); 1265 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1266 p->good_frames_received += mib_read(mp, 0x10); 1267 p->bad_frames_received += mib_read(mp, 0x14); 1268 p->broadcast_frames_received += mib_read(mp, 0x18); 1269 p->multicast_frames_received += mib_read(mp, 0x1c); 1270 p->frames_64_octets += mib_read(mp, 0x20); 1271 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1272 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1273 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1274 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1275 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1276 p->good_octets_sent += mib_read(mp, 0x38); 1277 p->good_frames_sent += mib_read(mp, 0x40); 1278 p->excessive_collision += mib_read(mp, 0x44); 1279 p->multicast_frames_sent += mib_read(mp, 0x48); 1280 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1281 p->unrec_mac_control_received += mib_read(mp, 0x50); 1282 p->fc_sent += mib_read(mp, 0x54); 1283 p->good_fc_received += mib_read(mp, 0x58); 1284 p->bad_fc_received += mib_read(mp, 0x5c); 1285 p->undersize_received += mib_read(mp, 0x60); 1286 p->fragments_received += mib_read(mp, 0x64); 1287 p->oversize_received += mib_read(mp, 0x68); 1288 p->jabber_received += mib_read(mp, 0x6c); 1289 p->mac_receive_error += mib_read(mp, 0x70); 1290 p->bad_crc_event += mib_read(mp, 0x74); 1291 p->collision += mib_read(mp, 0x78); 1292 p->late_collision += mib_read(mp, 0x7c); 1293 /* Non MIB hardware counters */ 1294 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1295 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1296 spin_unlock_bh(&mp->mib_counters_lock); 1297 } 1298 1299 static void mib_counters_timer_wrapper(unsigned long _mp) 1300 { 1301 struct mv643xx_eth_private *mp = (void *)_mp; 1302 mib_counters_update(mp); 1303 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1304 } 1305 1306 1307 /* interrupt coalescing *****************************************************/ 1308 /* 1309 * Hardware coalescing parameters are set in units of 64 t_clk 1310 * cycles. I.e.: 1311 * 1312 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1313 * 1314 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1315 * 1316 * In the ->set*() methods, we round the computed register value 1317 * to the nearest integer. 1318 */ 1319 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1320 { 1321 u32 val = rdlp(mp, SDMA_CONFIG); 1322 u64 temp; 1323 1324 if (mp->shared->extended_rx_coal_limit) 1325 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1326 else 1327 temp = (val & 0x003fff00) >> 8; 1328 1329 temp *= 64000000; 1330 do_div(temp, mp->t_clk); 1331 1332 return (unsigned int)temp; 1333 } 1334 1335 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1336 { 1337 u64 temp; 1338 u32 val; 1339 1340 temp = (u64)usec * mp->t_clk; 1341 temp += 31999999; 1342 do_div(temp, 64000000); 1343 1344 val = rdlp(mp, SDMA_CONFIG); 1345 if (mp->shared->extended_rx_coal_limit) { 1346 if (temp > 0xffff) 1347 temp = 0xffff; 1348 val &= ~0x023fff80; 1349 val |= (temp & 0x8000) << 10; 1350 val |= (temp & 0x7fff) << 7; 1351 } else { 1352 if (temp > 0x3fff) 1353 temp = 0x3fff; 1354 val &= ~0x003fff00; 1355 val |= (temp & 0x3fff) << 8; 1356 } 1357 wrlp(mp, SDMA_CONFIG, val); 1358 } 1359 1360 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1361 { 1362 u64 temp; 1363 1364 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1365 temp *= 64000000; 1366 do_div(temp, mp->t_clk); 1367 1368 return (unsigned int)temp; 1369 } 1370 1371 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1372 { 1373 u64 temp; 1374 1375 temp = (u64)usec * mp->t_clk; 1376 temp += 31999999; 1377 do_div(temp, 64000000); 1378 1379 if (temp > 0x3fff) 1380 temp = 0x3fff; 1381 1382 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1383 } 1384 1385 1386 /* ethtool ******************************************************************/ 1387 struct mv643xx_eth_stats { 1388 char stat_string[ETH_GSTRING_LEN]; 1389 int sizeof_stat; 1390 int netdev_off; 1391 int mp_off; 1392 }; 1393 1394 #define SSTAT(m) \ 1395 { #m, FIELD_SIZEOF(struct net_device_stats, m), \ 1396 offsetof(struct net_device, stats.m), -1 } 1397 1398 #define MIBSTAT(m) \ 1399 { #m, FIELD_SIZEOF(struct mib_counters, m), \ 1400 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1401 1402 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1403 SSTAT(rx_packets), 1404 SSTAT(tx_packets), 1405 SSTAT(rx_bytes), 1406 SSTAT(tx_bytes), 1407 SSTAT(rx_errors), 1408 SSTAT(tx_errors), 1409 SSTAT(rx_dropped), 1410 SSTAT(tx_dropped), 1411 MIBSTAT(good_octets_received), 1412 MIBSTAT(bad_octets_received), 1413 MIBSTAT(internal_mac_transmit_err), 1414 MIBSTAT(good_frames_received), 1415 MIBSTAT(bad_frames_received), 1416 MIBSTAT(broadcast_frames_received), 1417 MIBSTAT(multicast_frames_received), 1418 MIBSTAT(frames_64_octets), 1419 MIBSTAT(frames_65_to_127_octets), 1420 MIBSTAT(frames_128_to_255_octets), 1421 MIBSTAT(frames_256_to_511_octets), 1422 MIBSTAT(frames_512_to_1023_octets), 1423 MIBSTAT(frames_1024_to_max_octets), 1424 MIBSTAT(good_octets_sent), 1425 MIBSTAT(good_frames_sent), 1426 MIBSTAT(excessive_collision), 1427 MIBSTAT(multicast_frames_sent), 1428 MIBSTAT(broadcast_frames_sent), 1429 MIBSTAT(unrec_mac_control_received), 1430 MIBSTAT(fc_sent), 1431 MIBSTAT(good_fc_received), 1432 MIBSTAT(bad_fc_received), 1433 MIBSTAT(undersize_received), 1434 MIBSTAT(fragments_received), 1435 MIBSTAT(oversize_received), 1436 MIBSTAT(jabber_received), 1437 MIBSTAT(mac_receive_error), 1438 MIBSTAT(bad_crc_event), 1439 MIBSTAT(collision), 1440 MIBSTAT(late_collision), 1441 MIBSTAT(rx_discard), 1442 MIBSTAT(rx_overrun), 1443 }; 1444 1445 static int 1446 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, 1447 struct ethtool_cmd *cmd) 1448 { 1449 int err; 1450 1451 err = phy_read_status(mp->phy); 1452 if (err == 0) 1453 err = phy_ethtool_gset(mp->phy, cmd); 1454 1455 /* 1456 * The MAC does not support 1000baseT_Half. 1457 */ 1458 cmd->supported &= ~SUPPORTED_1000baseT_Half; 1459 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1460 1461 return err; 1462 } 1463 1464 static int 1465 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, 1466 struct ethtool_cmd *cmd) 1467 { 1468 u32 port_status; 1469 1470 port_status = rdlp(mp, PORT_STATUS); 1471 1472 cmd->supported = SUPPORTED_MII; 1473 cmd->advertising = ADVERTISED_MII; 1474 switch (port_status & PORT_SPEED_MASK) { 1475 case PORT_SPEED_10: 1476 ethtool_cmd_speed_set(cmd, SPEED_10); 1477 break; 1478 case PORT_SPEED_100: 1479 ethtool_cmd_speed_set(cmd, SPEED_100); 1480 break; 1481 case PORT_SPEED_1000: 1482 ethtool_cmd_speed_set(cmd, SPEED_1000); 1483 break; 1484 default: 1485 cmd->speed = -1; 1486 break; 1487 } 1488 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; 1489 cmd->port = PORT_MII; 1490 cmd->phy_address = 0; 1491 cmd->transceiver = XCVR_INTERNAL; 1492 cmd->autoneg = AUTONEG_DISABLE; 1493 cmd->maxtxpkt = 1; 1494 cmd->maxrxpkt = 1; 1495 1496 return 0; 1497 } 1498 1499 static void 1500 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1501 { 1502 struct mv643xx_eth_private *mp = netdev_priv(dev); 1503 wol->supported = 0; 1504 wol->wolopts = 0; 1505 if (mp->phy) 1506 phy_ethtool_get_wol(mp->phy, wol); 1507 } 1508 1509 static int 1510 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1511 { 1512 struct mv643xx_eth_private *mp = netdev_priv(dev); 1513 int err; 1514 1515 if (mp->phy == NULL) 1516 return -EOPNOTSUPP; 1517 1518 err = phy_ethtool_set_wol(mp->phy, wol); 1519 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1520 * this debugging hint is useful to have. 1521 */ 1522 if (err == -EOPNOTSUPP) 1523 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1524 return err; 1525 } 1526 1527 static int 1528 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1529 { 1530 struct mv643xx_eth_private *mp = netdev_priv(dev); 1531 1532 if (mp->phy != NULL) 1533 return mv643xx_eth_get_settings_phy(mp, cmd); 1534 else 1535 return mv643xx_eth_get_settings_phyless(mp, cmd); 1536 } 1537 1538 static int 1539 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1540 { 1541 struct mv643xx_eth_private *mp = netdev_priv(dev); 1542 int ret; 1543 1544 if (mp->phy == NULL) 1545 return -EINVAL; 1546 1547 /* 1548 * The MAC does not support 1000baseT_Half. 1549 */ 1550 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1551 1552 ret = phy_ethtool_sset(mp->phy, cmd); 1553 if (!ret) 1554 mv643xx_eth_adjust_link(dev); 1555 return ret; 1556 } 1557 1558 static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1559 struct ethtool_drvinfo *drvinfo) 1560 { 1561 strlcpy(drvinfo->driver, mv643xx_eth_driver_name, 1562 sizeof(drvinfo->driver)); 1563 strlcpy(drvinfo->version, mv643xx_eth_driver_version, 1564 sizeof(drvinfo->version)); 1565 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1566 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1567 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); 1568 } 1569 1570 static int mv643xx_eth_nway_reset(struct net_device *dev) 1571 { 1572 struct mv643xx_eth_private *mp = netdev_priv(dev); 1573 1574 if (mp->phy == NULL) 1575 return -EINVAL; 1576 1577 return genphy_restart_aneg(mp->phy); 1578 } 1579 1580 static int 1581 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1582 { 1583 struct mv643xx_eth_private *mp = netdev_priv(dev); 1584 1585 ec->rx_coalesce_usecs = get_rx_coal(mp); 1586 ec->tx_coalesce_usecs = get_tx_coal(mp); 1587 1588 return 0; 1589 } 1590 1591 static int 1592 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1593 { 1594 struct mv643xx_eth_private *mp = netdev_priv(dev); 1595 1596 set_rx_coal(mp, ec->rx_coalesce_usecs); 1597 set_tx_coal(mp, ec->tx_coalesce_usecs); 1598 1599 return 0; 1600 } 1601 1602 static void 1603 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1604 { 1605 struct mv643xx_eth_private *mp = netdev_priv(dev); 1606 1607 er->rx_max_pending = 4096; 1608 er->tx_max_pending = 4096; 1609 1610 er->rx_pending = mp->rx_ring_size; 1611 er->tx_pending = mp->tx_ring_size; 1612 } 1613 1614 static int 1615 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1616 { 1617 struct mv643xx_eth_private *mp = netdev_priv(dev); 1618 1619 if (er->rx_mini_pending || er->rx_jumbo_pending) 1620 return -EINVAL; 1621 1622 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; 1623 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, 1624 MV643XX_MAX_SKB_DESCS * 2, 4096); 1625 if (mp->tx_ring_size != er->tx_pending) 1626 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 1627 mp->tx_ring_size, er->tx_pending); 1628 1629 if (netif_running(dev)) { 1630 mv643xx_eth_stop(dev); 1631 if (mv643xx_eth_open(dev)) { 1632 netdev_err(dev, 1633 "fatal error on re-opening device after ring param change\n"); 1634 return -ENOMEM; 1635 } 1636 } 1637 1638 return 0; 1639 } 1640 1641 1642 static int 1643 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1644 { 1645 struct mv643xx_eth_private *mp = netdev_priv(dev); 1646 bool rx_csum = features & NETIF_F_RXCSUM; 1647 1648 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1649 1650 return 0; 1651 } 1652 1653 static void mv643xx_eth_get_strings(struct net_device *dev, 1654 uint32_t stringset, uint8_t *data) 1655 { 1656 int i; 1657 1658 if (stringset == ETH_SS_STATS) { 1659 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1660 memcpy(data + i * ETH_GSTRING_LEN, 1661 mv643xx_eth_stats[i].stat_string, 1662 ETH_GSTRING_LEN); 1663 } 1664 } 1665 } 1666 1667 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1668 struct ethtool_stats *stats, 1669 uint64_t *data) 1670 { 1671 struct mv643xx_eth_private *mp = netdev_priv(dev); 1672 int i; 1673 1674 mv643xx_eth_get_stats(dev); 1675 mib_counters_update(mp); 1676 1677 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1678 const struct mv643xx_eth_stats *stat; 1679 void *p; 1680 1681 stat = mv643xx_eth_stats + i; 1682 1683 if (stat->netdev_off >= 0) 1684 p = ((void *)mp->dev) + stat->netdev_off; 1685 else 1686 p = ((void *)mp) + stat->mp_off; 1687 1688 data[i] = (stat->sizeof_stat == 8) ? 1689 *(uint64_t *)p : *(uint32_t *)p; 1690 } 1691 } 1692 1693 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1694 { 1695 if (sset == ETH_SS_STATS) 1696 return ARRAY_SIZE(mv643xx_eth_stats); 1697 1698 return -EOPNOTSUPP; 1699 } 1700 1701 static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1702 .get_settings = mv643xx_eth_get_settings, 1703 .set_settings = mv643xx_eth_set_settings, 1704 .get_drvinfo = mv643xx_eth_get_drvinfo, 1705 .nway_reset = mv643xx_eth_nway_reset, 1706 .get_link = ethtool_op_get_link, 1707 .get_coalesce = mv643xx_eth_get_coalesce, 1708 .set_coalesce = mv643xx_eth_set_coalesce, 1709 .get_ringparam = mv643xx_eth_get_ringparam, 1710 .set_ringparam = mv643xx_eth_set_ringparam, 1711 .get_strings = mv643xx_eth_get_strings, 1712 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1713 .get_sset_count = mv643xx_eth_get_sset_count, 1714 .get_ts_info = ethtool_op_get_ts_info, 1715 .get_wol = mv643xx_eth_get_wol, 1716 .set_wol = mv643xx_eth_set_wol, 1717 }; 1718 1719 1720 /* address handling *********************************************************/ 1721 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1722 { 1723 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1724 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1725 1726 addr[0] = (mac_h >> 24) & 0xff; 1727 addr[1] = (mac_h >> 16) & 0xff; 1728 addr[2] = (mac_h >> 8) & 0xff; 1729 addr[3] = mac_h & 0xff; 1730 addr[4] = (mac_l >> 8) & 0xff; 1731 addr[5] = mac_l & 0xff; 1732 } 1733 1734 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) 1735 { 1736 wrlp(mp, MAC_ADDR_HIGH, 1737 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1738 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1739 } 1740 1741 static u32 uc_addr_filter_mask(struct net_device *dev) 1742 { 1743 struct netdev_hw_addr *ha; 1744 u32 nibbles; 1745 1746 if (dev->flags & IFF_PROMISC) 1747 return 0; 1748 1749 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1750 netdev_for_each_uc_addr(ha, dev) { 1751 if (memcmp(dev->dev_addr, ha->addr, 5)) 1752 return 0; 1753 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1754 return 0; 1755 1756 nibbles |= 1 << (ha->addr[5] & 0x0f); 1757 } 1758 1759 return nibbles; 1760 } 1761 1762 static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1763 { 1764 struct mv643xx_eth_private *mp = netdev_priv(dev); 1765 u32 port_config; 1766 u32 nibbles; 1767 int i; 1768 1769 uc_addr_set(mp, dev->dev_addr); 1770 1771 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1772 1773 nibbles = uc_addr_filter_mask(dev); 1774 if (!nibbles) { 1775 port_config |= UNICAST_PROMISCUOUS_MODE; 1776 nibbles = 0xffff; 1777 } 1778 1779 for (i = 0; i < 16; i += 4) { 1780 int off = UNICAST_TABLE(mp->port_num) + i; 1781 u32 v; 1782 1783 v = 0; 1784 if (nibbles & 1) 1785 v |= 0x00000001; 1786 if (nibbles & 2) 1787 v |= 0x00000100; 1788 if (nibbles & 4) 1789 v |= 0x00010000; 1790 if (nibbles & 8) 1791 v |= 0x01000000; 1792 nibbles >>= 4; 1793 1794 wrl(mp, off, v); 1795 } 1796 1797 wrlp(mp, PORT_CONFIG, port_config); 1798 } 1799 1800 static int addr_crc(unsigned char *addr) 1801 { 1802 int crc = 0; 1803 int i; 1804 1805 for (i = 0; i < 6; i++) { 1806 int j; 1807 1808 crc = (crc ^ addr[i]) << 8; 1809 for (j = 7; j >= 0; j--) { 1810 if (crc & (0x100 << j)) 1811 crc ^= 0x107 << j; 1812 } 1813 } 1814 1815 return crc; 1816 } 1817 1818 static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1819 { 1820 struct mv643xx_eth_private *mp = netdev_priv(dev); 1821 u32 *mc_spec; 1822 u32 *mc_other; 1823 struct netdev_hw_addr *ha; 1824 int i; 1825 1826 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1827 int port_num; 1828 u32 accept; 1829 1830 oom: 1831 port_num = mp->port_num; 1832 accept = 0x01010101; 1833 for (i = 0; i < 0x100; i += 4) { 1834 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); 1835 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); 1836 } 1837 return; 1838 } 1839 1840 mc_spec = kmalloc(0x200, GFP_ATOMIC); 1841 if (mc_spec == NULL) 1842 goto oom; 1843 mc_other = mc_spec + (0x100 >> 2); 1844 1845 memset(mc_spec, 0, 0x100); 1846 memset(mc_other, 0, 0x100); 1847 1848 netdev_for_each_mc_addr(ha, dev) { 1849 u8 *a = ha->addr; 1850 u32 *table; 1851 int entry; 1852 1853 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1854 table = mc_spec; 1855 entry = a[5]; 1856 } else { 1857 table = mc_other; 1858 entry = addr_crc(a); 1859 } 1860 1861 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1862 } 1863 1864 for (i = 0; i < 0x100; i += 4) { 1865 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); 1866 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); 1867 } 1868 1869 kfree(mc_spec); 1870 } 1871 1872 static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1873 { 1874 mv643xx_eth_program_unicast_filter(dev); 1875 mv643xx_eth_program_multicast_filter(dev); 1876 } 1877 1878 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1879 { 1880 struct sockaddr *sa = addr; 1881 1882 if (!is_valid_ether_addr(sa->sa_data)) 1883 return -EADDRNOTAVAIL; 1884 1885 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 1886 1887 netif_addr_lock_bh(dev); 1888 mv643xx_eth_program_unicast_filter(dev); 1889 netif_addr_unlock_bh(dev); 1890 1891 return 0; 1892 } 1893 1894 1895 /* rx/tx queue initialisation ***********************************************/ 1896 static int rxq_init(struct mv643xx_eth_private *mp, int index) 1897 { 1898 struct rx_queue *rxq = mp->rxq + index; 1899 struct rx_desc *rx_desc; 1900 int size; 1901 int i; 1902 1903 rxq->index = index; 1904 1905 rxq->rx_ring_size = mp->rx_ring_size; 1906 1907 rxq->rx_desc_count = 0; 1908 rxq->rx_curr_desc = 0; 1909 rxq->rx_used_desc = 0; 1910 1911 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1912 1913 if (index == 0 && size <= mp->rx_desc_sram_size) { 1914 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1915 mp->rx_desc_sram_size); 1916 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1917 } else { 1918 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1919 size, &rxq->rx_desc_dma, 1920 GFP_KERNEL); 1921 } 1922 1923 if (rxq->rx_desc_area == NULL) { 1924 netdev_err(mp->dev, 1925 "can't allocate rx ring (%d bytes)\n", size); 1926 goto out; 1927 } 1928 memset(rxq->rx_desc_area, 0, size); 1929 1930 rxq->rx_desc_area_size = size; 1931 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1932 GFP_KERNEL); 1933 if (rxq->rx_skb == NULL) 1934 goto out_free; 1935 1936 rx_desc = rxq->rx_desc_area; 1937 for (i = 0; i < rxq->rx_ring_size; i++) { 1938 int nexti; 1939 1940 nexti = i + 1; 1941 if (nexti == rxq->rx_ring_size) 1942 nexti = 0; 1943 1944 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1945 nexti * sizeof(struct rx_desc); 1946 } 1947 1948 return 0; 1949 1950 1951 out_free: 1952 if (index == 0 && size <= mp->rx_desc_sram_size) 1953 iounmap(rxq->rx_desc_area); 1954 else 1955 dma_free_coherent(mp->dev->dev.parent, size, 1956 rxq->rx_desc_area, 1957 rxq->rx_desc_dma); 1958 1959 out: 1960 return -ENOMEM; 1961 } 1962 1963 static void rxq_deinit(struct rx_queue *rxq) 1964 { 1965 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 1966 int i; 1967 1968 rxq_disable(rxq); 1969 1970 for (i = 0; i < rxq->rx_ring_size; i++) { 1971 if (rxq->rx_skb[i]) { 1972 dev_kfree_skb(rxq->rx_skb[i]); 1973 rxq->rx_desc_count--; 1974 } 1975 } 1976 1977 if (rxq->rx_desc_count) { 1978 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 1979 rxq->rx_desc_count); 1980 } 1981 1982 if (rxq->index == 0 && 1983 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 1984 iounmap(rxq->rx_desc_area); 1985 else 1986 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 1987 rxq->rx_desc_area, rxq->rx_desc_dma); 1988 1989 kfree(rxq->rx_skb); 1990 } 1991 1992 static int txq_init(struct mv643xx_eth_private *mp, int index) 1993 { 1994 struct tx_queue *txq = mp->txq + index; 1995 struct tx_desc *tx_desc; 1996 int size; 1997 int i; 1998 1999 txq->index = index; 2000 2001 txq->tx_ring_size = mp->tx_ring_size; 2002 2003 /* A queue must always have room for at least one skb. 2004 * Therefore, stop the queue when the free entries reaches 2005 * the maximum number of descriptors per skb. 2006 */ 2007 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; 2008 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 2009 2010 txq->tx_desc_count = 0; 2011 txq->tx_curr_desc = 0; 2012 txq->tx_used_desc = 0; 2013 2014 size = txq->tx_ring_size * sizeof(struct tx_desc); 2015 2016 if (index == 0 && size <= mp->tx_desc_sram_size) { 2017 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 2018 mp->tx_desc_sram_size); 2019 txq->tx_desc_dma = mp->tx_desc_sram_addr; 2020 } else { 2021 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 2022 size, &txq->tx_desc_dma, 2023 GFP_KERNEL); 2024 } 2025 2026 if (txq->tx_desc_area == NULL) { 2027 netdev_err(mp->dev, 2028 "can't allocate tx ring (%d bytes)\n", size); 2029 return -ENOMEM; 2030 } 2031 memset(txq->tx_desc_area, 0, size); 2032 2033 txq->tx_desc_area_size = size; 2034 2035 tx_desc = txq->tx_desc_area; 2036 for (i = 0; i < txq->tx_ring_size; i++) { 2037 struct tx_desc *txd = tx_desc + i; 2038 int nexti; 2039 2040 nexti = i + 1; 2041 if (nexti == txq->tx_ring_size) 2042 nexti = 0; 2043 2044 txd->cmd_sts = 0; 2045 txd->next_desc_ptr = txq->tx_desc_dma + 2046 nexti * sizeof(struct tx_desc); 2047 } 2048 2049 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 2050 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, 2051 txq->tx_ring_size * TSO_HEADER_SIZE, 2052 &txq->tso_hdrs_dma, GFP_KERNEL); 2053 if (txq->tso_hdrs == NULL) { 2054 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2055 txq->tx_desc_area, txq->tx_desc_dma); 2056 return -ENOMEM; 2057 } 2058 skb_queue_head_init(&txq->tx_skb); 2059 2060 return 0; 2061 } 2062 2063 static void txq_deinit(struct tx_queue *txq) 2064 { 2065 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2066 2067 txq_disable(txq); 2068 txq_reclaim(txq, txq->tx_ring_size, 1); 2069 2070 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2071 2072 if (txq->index == 0 && 2073 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2074 iounmap(txq->tx_desc_area); 2075 else 2076 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2077 txq->tx_desc_area, txq->tx_desc_dma); 2078 if (txq->tso_hdrs) 2079 dma_free_coherent(mp->dev->dev.parent, 2080 txq->tx_ring_size * TSO_HEADER_SIZE, 2081 txq->tso_hdrs, txq->tso_hdrs_dma); 2082 } 2083 2084 2085 /* netdev ops and related ***************************************************/ 2086 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2087 { 2088 u32 int_cause; 2089 u32 int_cause_ext; 2090 2091 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2092 if (int_cause == 0) 2093 return 0; 2094 2095 int_cause_ext = 0; 2096 if (int_cause & INT_EXT) { 2097 int_cause &= ~INT_EXT; 2098 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2099 } 2100 2101 if (int_cause) { 2102 wrlp(mp, INT_CAUSE, ~int_cause); 2103 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2104 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2105 mp->work_rx |= (int_cause & INT_RX) >> 2; 2106 } 2107 2108 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2109 if (int_cause_ext) { 2110 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2111 if (int_cause_ext & INT_EXT_LINK_PHY) 2112 mp->work_link = 1; 2113 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2114 } 2115 2116 return 1; 2117 } 2118 2119 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2120 { 2121 struct net_device *dev = (struct net_device *)dev_id; 2122 struct mv643xx_eth_private *mp = netdev_priv(dev); 2123 2124 if (unlikely(!mv643xx_eth_collect_events(mp))) 2125 return IRQ_NONE; 2126 2127 wrlp(mp, INT_MASK, 0); 2128 napi_schedule(&mp->napi); 2129 2130 return IRQ_HANDLED; 2131 } 2132 2133 static void handle_link_event(struct mv643xx_eth_private *mp) 2134 { 2135 struct net_device *dev = mp->dev; 2136 u32 port_status; 2137 int speed; 2138 int duplex; 2139 int fc; 2140 2141 port_status = rdlp(mp, PORT_STATUS); 2142 if (!(port_status & LINK_UP)) { 2143 if (netif_carrier_ok(dev)) { 2144 int i; 2145 2146 netdev_info(dev, "link down\n"); 2147 2148 netif_carrier_off(dev); 2149 2150 for (i = 0; i < mp->txq_count; i++) { 2151 struct tx_queue *txq = mp->txq + i; 2152 2153 txq_reclaim(txq, txq->tx_ring_size, 1); 2154 txq_reset_hw_ptr(txq); 2155 } 2156 } 2157 return; 2158 } 2159 2160 switch (port_status & PORT_SPEED_MASK) { 2161 case PORT_SPEED_10: 2162 speed = 10; 2163 break; 2164 case PORT_SPEED_100: 2165 speed = 100; 2166 break; 2167 case PORT_SPEED_1000: 2168 speed = 1000; 2169 break; 2170 default: 2171 speed = -1; 2172 break; 2173 } 2174 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2175 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2176 2177 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2178 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2179 2180 if (!netif_carrier_ok(dev)) 2181 netif_carrier_on(dev); 2182 } 2183 2184 static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2185 { 2186 struct mv643xx_eth_private *mp; 2187 int work_done; 2188 2189 mp = container_of(napi, struct mv643xx_eth_private, napi); 2190 2191 if (unlikely(mp->oom)) { 2192 mp->oom = 0; 2193 del_timer(&mp->rx_oom); 2194 } 2195 2196 work_done = 0; 2197 while (work_done < budget) { 2198 u8 queue_mask; 2199 int queue; 2200 int work_tbd; 2201 2202 if (mp->work_link) { 2203 mp->work_link = 0; 2204 handle_link_event(mp); 2205 work_done++; 2206 continue; 2207 } 2208 2209 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2210 if (likely(!mp->oom)) 2211 queue_mask |= mp->work_rx_refill; 2212 2213 if (!queue_mask) { 2214 if (mv643xx_eth_collect_events(mp)) 2215 continue; 2216 break; 2217 } 2218 2219 queue = fls(queue_mask) - 1; 2220 queue_mask = 1 << queue; 2221 2222 work_tbd = budget - work_done; 2223 if (work_tbd > 16) 2224 work_tbd = 16; 2225 2226 if (mp->work_tx_end & queue_mask) { 2227 txq_kick(mp->txq + queue); 2228 } else if (mp->work_tx & queue_mask) { 2229 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2230 txq_maybe_wake(mp->txq + queue); 2231 } else if (mp->work_rx & queue_mask) { 2232 work_done += rxq_process(mp->rxq + queue, work_tbd); 2233 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2234 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2235 } else { 2236 BUG(); 2237 } 2238 } 2239 2240 if (work_done < budget) { 2241 if (mp->oom) 2242 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2243 napi_complete(napi); 2244 wrlp(mp, INT_MASK, mp->int_mask); 2245 } 2246 2247 return work_done; 2248 } 2249 2250 static inline void oom_timer_wrapper(unsigned long data) 2251 { 2252 struct mv643xx_eth_private *mp = (void *)data; 2253 2254 napi_schedule(&mp->napi); 2255 } 2256 2257 static void port_start(struct mv643xx_eth_private *mp) 2258 { 2259 u32 pscr; 2260 int i; 2261 2262 /* 2263 * Perform PHY reset, if there is a PHY. 2264 */ 2265 if (mp->phy != NULL) { 2266 struct ethtool_cmd cmd; 2267 2268 mv643xx_eth_get_settings(mp->dev, &cmd); 2269 phy_init_hw(mp->phy); 2270 mv643xx_eth_set_settings(mp->dev, &cmd); 2271 phy_start(mp->phy); 2272 } 2273 2274 /* 2275 * Configure basic link parameters. 2276 */ 2277 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2278 2279 pscr |= SERIAL_PORT_ENABLE; 2280 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2281 2282 pscr |= DO_NOT_FORCE_LINK_FAIL; 2283 if (mp->phy == NULL) 2284 pscr |= FORCE_LINK_PASS; 2285 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2286 2287 /* 2288 * Configure TX path and queues. 2289 */ 2290 tx_set_rate(mp, 1000000000, 16777216); 2291 for (i = 0; i < mp->txq_count; i++) { 2292 struct tx_queue *txq = mp->txq + i; 2293 2294 txq_reset_hw_ptr(txq); 2295 txq_set_rate(txq, 1000000000, 16777216); 2296 txq_set_fixed_prio_mode(txq); 2297 } 2298 2299 /* 2300 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2301 * frames to RX queue #0, and include the pseudo-header when 2302 * calculating receive checksums. 2303 */ 2304 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2305 2306 /* 2307 * Treat BPDUs as normal multicasts, and disable partition mode. 2308 */ 2309 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2310 2311 /* 2312 * Add configured unicast addresses to address filter table. 2313 */ 2314 mv643xx_eth_program_unicast_filter(mp->dev); 2315 2316 /* 2317 * Enable the receive queues. 2318 */ 2319 for (i = 0; i < mp->rxq_count; i++) { 2320 struct rx_queue *rxq = mp->rxq + i; 2321 u32 addr; 2322 2323 addr = (u32)rxq->rx_desc_dma; 2324 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2325 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2326 2327 rxq_enable(rxq); 2328 } 2329 } 2330 2331 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2332 { 2333 int skb_size; 2334 2335 /* 2336 * Reserve 2+14 bytes for an ethernet header (the hardware 2337 * automatically prepends 2 bytes of dummy data to each 2338 * received packet), 16 bytes for up to four VLAN tags, and 2339 * 4 bytes for the trailing FCS -- 36 bytes total. 2340 */ 2341 skb_size = mp->dev->mtu + 36; 2342 2343 /* 2344 * Make sure that the skb size is a multiple of 8 bytes, as 2345 * the lower three bits of the receive descriptor's buffer 2346 * size field are ignored by the hardware. 2347 */ 2348 mp->skb_size = (skb_size + 7) & ~7; 2349 2350 /* 2351 * If NET_SKB_PAD is smaller than a cache line, 2352 * netdev_alloc_skb() will cause skb->data to be misaligned 2353 * to a cache line boundary. If this is the case, include 2354 * some extra space to allow re-aligning the data area. 2355 */ 2356 mp->skb_size += SKB_DMA_REALIGN; 2357 } 2358 2359 static int mv643xx_eth_open(struct net_device *dev) 2360 { 2361 struct mv643xx_eth_private *mp = netdev_priv(dev); 2362 int err; 2363 int i; 2364 2365 wrlp(mp, INT_CAUSE, 0); 2366 wrlp(mp, INT_CAUSE_EXT, 0); 2367 rdlp(mp, INT_CAUSE_EXT); 2368 2369 err = request_irq(dev->irq, mv643xx_eth_irq, 2370 IRQF_SHARED, dev->name, dev); 2371 if (err) { 2372 netdev_err(dev, "can't assign irq\n"); 2373 return -EAGAIN; 2374 } 2375 2376 mv643xx_eth_recalc_skb_size(mp); 2377 2378 napi_enable(&mp->napi); 2379 2380 mp->int_mask = INT_EXT; 2381 2382 for (i = 0; i < mp->rxq_count; i++) { 2383 err = rxq_init(mp, i); 2384 if (err) { 2385 while (--i >= 0) 2386 rxq_deinit(mp->rxq + i); 2387 goto out; 2388 } 2389 2390 rxq_refill(mp->rxq + i, INT_MAX); 2391 mp->int_mask |= INT_RX_0 << i; 2392 } 2393 2394 if (mp->oom) { 2395 mp->rx_oom.expires = jiffies + (HZ / 10); 2396 add_timer(&mp->rx_oom); 2397 } 2398 2399 for (i = 0; i < mp->txq_count; i++) { 2400 err = txq_init(mp, i); 2401 if (err) { 2402 while (--i >= 0) 2403 txq_deinit(mp->txq + i); 2404 goto out_free; 2405 } 2406 mp->int_mask |= INT_TX_END_0 << i; 2407 } 2408 2409 add_timer(&mp->mib_counters_timer); 2410 port_start(mp); 2411 2412 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2413 wrlp(mp, INT_MASK, mp->int_mask); 2414 2415 return 0; 2416 2417 2418 out_free: 2419 for (i = 0; i < mp->rxq_count; i++) 2420 rxq_deinit(mp->rxq + i); 2421 out: 2422 free_irq(dev->irq, dev); 2423 2424 return err; 2425 } 2426 2427 static void port_reset(struct mv643xx_eth_private *mp) 2428 { 2429 unsigned int data; 2430 int i; 2431 2432 for (i = 0; i < mp->rxq_count; i++) 2433 rxq_disable(mp->rxq + i); 2434 for (i = 0; i < mp->txq_count; i++) 2435 txq_disable(mp->txq + i); 2436 2437 while (1) { 2438 u32 ps = rdlp(mp, PORT_STATUS); 2439 2440 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2441 break; 2442 udelay(10); 2443 } 2444 2445 /* Reset the Enable bit in the Configuration Register */ 2446 data = rdlp(mp, PORT_SERIAL_CONTROL); 2447 data &= ~(SERIAL_PORT_ENABLE | 2448 DO_NOT_FORCE_LINK_FAIL | 2449 FORCE_LINK_PASS); 2450 wrlp(mp, PORT_SERIAL_CONTROL, data); 2451 } 2452 2453 static int mv643xx_eth_stop(struct net_device *dev) 2454 { 2455 struct mv643xx_eth_private *mp = netdev_priv(dev); 2456 int i; 2457 2458 wrlp(mp, INT_MASK_EXT, 0x00000000); 2459 wrlp(mp, INT_MASK, 0x00000000); 2460 rdlp(mp, INT_MASK); 2461 2462 napi_disable(&mp->napi); 2463 2464 del_timer_sync(&mp->rx_oom); 2465 2466 netif_carrier_off(dev); 2467 if (mp->phy) 2468 phy_stop(mp->phy); 2469 free_irq(dev->irq, dev); 2470 2471 port_reset(mp); 2472 mv643xx_eth_get_stats(dev); 2473 mib_counters_update(mp); 2474 del_timer_sync(&mp->mib_counters_timer); 2475 2476 for (i = 0; i < mp->rxq_count; i++) 2477 rxq_deinit(mp->rxq + i); 2478 for (i = 0; i < mp->txq_count; i++) 2479 txq_deinit(mp->txq + i); 2480 2481 return 0; 2482 } 2483 2484 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2485 { 2486 struct mv643xx_eth_private *mp = netdev_priv(dev); 2487 int ret; 2488 2489 if (mp->phy == NULL) 2490 return -ENOTSUPP; 2491 2492 ret = phy_mii_ioctl(mp->phy, ifr, cmd); 2493 if (!ret) 2494 mv643xx_eth_adjust_link(dev); 2495 return ret; 2496 } 2497 2498 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2499 { 2500 struct mv643xx_eth_private *mp = netdev_priv(dev); 2501 2502 if (new_mtu < 64 || new_mtu > 9500) 2503 return -EINVAL; 2504 2505 dev->mtu = new_mtu; 2506 mv643xx_eth_recalc_skb_size(mp); 2507 tx_set_rate(mp, 1000000000, 16777216); 2508 2509 if (!netif_running(dev)) 2510 return 0; 2511 2512 /* 2513 * Stop and then re-open the interface. This will allocate RX 2514 * skbs of the new MTU. 2515 * There is a possible danger that the open will not succeed, 2516 * due to memory being full. 2517 */ 2518 mv643xx_eth_stop(dev); 2519 if (mv643xx_eth_open(dev)) { 2520 netdev_err(dev, 2521 "fatal error on re-opening device after MTU change\n"); 2522 } 2523 2524 return 0; 2525 } 2526 2527 static void tx_timeout_task(struct work_struct *ugly) 2528 { 2529 struct mv643xx_eth_private *mp; 2530 2531 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2532 if (netif_running(mp->dev)) { 2533 netif_tx_stop_all_queues(mp->dev); 2534 port_reset(mp); 2535 port_start(mp); 2536 netif_tx_wake_all_queues(mp->dev); 2537 } 2538 } 2539 2540 static void mv643xx_eth_tx_timeout(struct net_device *dev) 2541 { 2542 struct mv643xx_eth_private *mp = netdev_priv(dev); 2543 2544 netdev_info(dev, "tx timeout\n"); 2545 2546 schedule_work(&mp->tx_timeout_task); 2547 } 2548 2549 #ifdef CONFIG_NET_POLL_CONTROLLER 2550 static void mv643xx_eth_netpoll(struct net_device *dev) 2551 { 2552 struct mv643xx_eth_private *mp = netdev_priv(dev); 2553 2554 wrlp(mp, INT_MASK, 0x00000000); 2555 rdlp(mp, INT_MASK); 2556 2557 mv643xx_eth_irq(dev->irq, dev); 2558 2559 wrlp(mp, INT_MASK, mp->int_mask); 2560 } 2561 #endif 2562 2563 2564 /* platform glue ************************************************************/ 2565 static void 2566 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2567 const struct mbus_dram_target_info *dram) 2568 { 2569 void __iomem *base = msp->base; 2570 u32 win_enable; 2571 u32 win_protect; 2572 int i; 2573 2574 for (i = 0; i < 6; i++) { 2575 writel(0, base + WINDOW_BASE(i)); 2576 writel(0, base + WINDOW_SIZE(i)); 2577 if (i < 4) 2578 writel(0, base + WINDOW_REMAP_HIGH(i)); 2579 } 2580 2581 win_enable = 0x3f; 2582 win_protect = 0; 2583 2584 for (i = 0; i < dram->num_cs; i++) { 2585 const struct mbus_dram_window *cs = dram->cs + i; 2586 2587 writel((cs->base & 0xffff0000) | 2588 (cs->mbus_attr << 8) | 2589 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2590 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2591 2592 win_enable &= ~(1 << i); 2593 win_protect |= 3 << (2 * i); 2594 } 2595 2596 writel(win_enable, base + WINDOW_BAR_ENABLE); 2597 msp->win_protect = win_protect; 2598 } 2599 2600 static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2601 { 2602 /* 2603 * Check whether we have a 14-bit coal limit field in bits 2604 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2605 * SDMA config register. 2606 */ 2607 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2608 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2609 msp->extended_rx_coal_limit = 1; 2610 else 2611 msp->extended_rx_coal_limit = 0; 2612 2613 /* 2614 * Check whether the MAC supports TX rate control, and if 2615 * yes, whether its associated registers are in the old or 2616 * the new place. 2617 */ 2618 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2619 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2620 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2621 } else { 2622 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2623 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2624 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2625 else 2626 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2627 } 2628 } 2629 2630 #if defined(CONFIG_OF) 2631 static const struct of_device_id mv643xx_eth_shared_ids[] = { 2632 { .compatible = "marvell,orion-eth", }, 2633 { .compatible = "marvell,kirkwood-eth", }, 2634 { } 2635 }; 2636 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2637 #endif 2638 2639 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60) 2640 #define mv643xx_eth_property(_np, _name, _v) \ 2641 do { \ 2642 u32 tmp; \ 2643 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2644 _v = tmp; \ 2645 } while (0) 2646 2647 static struct platform_device *port_platdev[3]; 2648 2649 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2650 struct device_node *pnp) 2651 { 2652 struct platform_device *ppdev; 2653 struct mv643xx_eth_platform_data ppd; 2654 struct resource res; 2655 const char *mac_addr; 2656 int ret; 2657 int dev_num = 0; 2658 2659 memset(&ppd, 0, sizeof(ppd)); 2660 ppd.shared = pdev; 2661 2662 memset(&res, 0, sizeof(res)); 2663 if (!of_irq_to_resource(pnp, 0, &res)) { 2664 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name); 2665 return -EINVAL; 2666 } 2667 2668 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2669 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name); 2670 return -EINVAL; 2671 } 2672 2673 if (ppd.port_number >= 3) { 2674 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name); 2675 return -EINVAL; 2676 } 2677 2678 while (dev_num < 3 && port_platdev[dev_num]) 2679 dev_num++; 2680 2681 if (dev_num == 3) { 2682 dev_err(&pdev->dev, "too many ports registered\n"); 2683 return -EINVAL; 2684 } 2685 2686 mac_addr = of_get_mac_address(pnp); 2687 if (mac_addr) 2688 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN); 2689 2690 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2691 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2692 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2693 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2694 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2695 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2696 2697 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2698 if (!ppd.phy_node) { 2699 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2700 of_property_read_u32(pnp, "speed", &ppd.speed); 2701 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2702 } 2703 2704 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2705 if (!ppdev) 2706 return -ENOMEM; 2707 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2708 ppdev->dev.of_node = pnp; 2709 2710 ret = platform_device_add_resources(ppdev, &res, 1); 2711 if (ret) 2712 goto port_err; 2713 2714 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2715 if (ret) 2716 goto port_err; 2717 2718 ret = platform_device_add(ppdev); 2719 if (ret) 2720 goto port_err; 2721 2722 port_platdev[dev_num] = ppdev; 2723 2724 return 0; 2725 2726 port_err: 2727 platform_device_put(ppdev); 2728 return ret; 2729 } 2730 2731 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2732 { 2733 struct mv643xx_eth_shared_platform_data *pd; 2734 struct device_node *pnp, *np = pdev->dev.of_node; 2735 int ret; 2736 2737 /* bail out if not registered from DT */ 2738 if (!np) 2739 return 0; 2740 2741 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2742 if (!pd) 2743 return -ENOMEM; 2744 pdev->dev.platform_data = pd; 2745 2746 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2747 2748 for_each_available_child_of_node(np, pnp) { 2749 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2750 if (ret) 2751 return ret; 2752 } 2753 return 0; 2754 } 2755 2756 static void mv643xx_eth_shared_of_remove(void) 2757 { 2758 int n; 2759 2760 for (n = 0; n < 3; n++) { 2761 platform_device_del(port_platdev[n]); 2762 port_platdev[n] = NULL; 2763 } 2764 } 2765 #else 2766 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2767 { 2768 return 0; 2769 } 2770 2771 static inline void mv643xx_eth_shared_of_remove(void) 2772 { 2773 } 2774 #endif 2775 2776 static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2777 { 2778 static int mv643xx_eth_version_printed; 2779 struct mv643xx_eth_shared_platform_data *pd; 2780 struct mv643xx_eth_shared_private *msp; 2781 const struct mbus_dram_target_info *dram; 2782 struct resource *res; 2783 int ret; 2784 2785 if (!mv643xx_eth_version_printed++) 2786 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2787 mv643xx_eth_driver_version); 2788 2789 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2790 if (res == NULL) 2791 return -EINVAL; 2792 2793 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2794 if (msp == NULL) 2795 return -ENOMEM; 2796 platform_set_drvdata(pdev, msp); 2797 2798 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 2799 if (msp->base == NULL) 2800 return -ENOMEM; 2801 2802 msp->clk = devm_clk_get(&pdev->dev, NULL); 2803 if (!IS_ERR(msp->clk)) 2804 clk_prepare_enable(msp->clk); 2805 2806 /* 2807 * (Re-)program MBUS remapping windows if we are asked to. 2808 */ 2809 dram = mv_mbus_dram_info(); 2810 if (dram) 2811 mv643xx_eth_conf_mbus_windows(msp, dram); 2812 2813 ret = mv643xx_eth_shared_of_probe(pdev); 2814 if (ret) 2815 return ret; 2816 pd = dev_get_platdata(&pdev->dev); 2817 2818 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2819 pd->tx_csum_limit : 9 * 1024; 2820 infer_hw_params(msp); 2821 2822 return 0; 2823 } 2824 2825 static int mv643xx_eth_shared_remove(struct platform_device *pdev) 2826 { 2827 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); 2828 2829 mv643xx_eth_shared_of_remove(); 2830 if (!IS_ERR(msp->clk)) 2831 clk_disable_unprepare(msp->clk); 2832 return 0; 2833 } 2834 2835 static struct platform_driver mv643xx_eth_shared_driver = { 2836 .probe = mv643xx_eth_shared_probe, 2837 .remove = mv643xx_eth_shared_remove, 2838 .driver = { 2839 .name = MV643XX_ETH_SHARED_NAME, 2840 .owner = THIS_MODULE, 2841 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2842 }, 2843 }; 2844 2845 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2846 { 2847 int addr_shift = 5 * mp->port_num; 2848 u32 data; 2849 2850 data = rdl(mp, PHY_ADDR); 2851 data &= ~(0x1f << addr_shift); 2852 data |= (phy_addr & 0x1f) << addr_shift; 2853 wrl(mp, PHY_ADDR, data); 2854 } 2855 2856 static int phy_addr_get(struct mv643xx_eth_private *mp) 2857 { 2858 unsigned int data; 2859 2860 data = rdl(mp, PHY_ADDR); 2861 2862 return (data >> (5 * mp->port_num)) & 0x1f; 2863 } 2864 2865 static void set_params(struct mv643xx_eth_private *mp, 2866 struct mv643xx_eth_platform_data *pd) 2867 { 2868 struct net_device *dev = mp->dev; 2869 unsigned int tx_ring_size; 2870 2871 if (is_valid_ether_addr(pd->mac_addr)) 2872 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 2873 else 2874 uc_addr_get(mp, dev->dev_addr); 2875 2876 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2877 if (pd->rx_queue_size) 2878 mp->rx_ring_size = pd->rx_queue_size; 2879 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2880 mp->rx_desc_sram_size = pd->rx_sram_size; 2881 2882 mp->rxq_count = pd->rx_queue_count ? : 1; 2883 2884 tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2885 if (pd->tx_queue_size) 2886 tx_ring_size = pd->tx_queue_size; 2887 2888 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, 2889 MV643XX_MAX_SKB_DESCS * 2, 4096); 2890 if (mp->tx_ring_size != tx_ring_size) 2891 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 2892 mp->tx_ring_size, tx_ring_size); 2893 2894 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2895 mp->tx_desc_sram_size = pd->tx_sram_size; 2896 2897 mp->txq_count = pd->tx_queue_count ? : 1; 2898 } 2899 2900 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2901 int phy_addr) 2902 { 2903 struct phy_device *phydev; 2904 int start; 2905 int num; 2906 int i; 2907 char phy_id[MII_BUS_ID_SIZE + 3]; 2908 2909 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2910 start = phy_addr_get(mp) & 0x1f; 2911 num = 32; 2912 } else { 2913 start = phy_addr & 0x1f; 2914 num = 1; 2915 } 2916 2917 /* Attempt to connect to the PHY using orion-mdio */ 2918 phydev = ERR_PTR(-ENODEV); 2919 for (i = 0; i < num; i++) { 2920 int addr = (start + i) & 0x1f; 2921 2922 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2923 "orion-mdio-mii", addr); 2924 2925 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 2926 PHY_INTERFACE_MODE_GMII); 2927 if (!IS_ERR(phydev)) { 2928 phy_addr_set(mp, addr); 2929 break; 2930 } 2931 } 2932 2933 return phydev; 2934 } 2935 2936 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 2937 { 2938 struct phy_device *phy = mp->phy; 2939 2940 if (speed == 0) { 2941 phy->autoneg = AUTONEG_ENABLE; 2942 phy->speed = 0; 2943 phy->duplex = 0; 2944 phy->advertising = phy->supported | ADVERTISED_Autoneg; 2945 } else { 2946 phy->autoneg = AUTONEG_DISABLE; 2947 phy->advertising = 0; 2948 phy->speed = speed; 2949 phy->duplex = duplex; 2950 } 2951 phy_start_aneg(phy); 2952 } 2953 2954 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 2955 { 2956 u32 pscr; 2957 2958 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2959 if (pscr & SERIAL_PORT_ENABLE) { 2960 pscr &= ~SERIAL_PORT_ENABLE; 2961 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2962 } 2963 2964 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 2965 if (mp->phy == NULL) { 2966 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 2967 if (speed == SPEED_1000) 2968 pscr |= SET_GMII_SPEED_TO_1000; 2969 else if (speed == SPEED_100) 2970 pscr |= SET_MII_SPEED_TO_100; 2971 2972 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 2973 2974 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 2975 if (duplex == DUPLEX_FULL) 2976 pscr |= SET_FULL_DUPLEX_MODE; 2977 } 2978 2979 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2980 } 2981 2982 static const struct net_device_ops mv643xx_eth_netdev_ops = { 2983 .ndo_open = mv643xx_eth_open, 2984 .ndo_stop = mv643xx_eth_stop, 2985 .ndo_start_xmit = mv643xx_eth_xmit, 2986 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 2987 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 2988 .ndo_validate_addr = eth_validate_addr, 2989 .ndo_do_ioctl = mv643xx_eth_ioctl, 2990 .ndo_change_mtu = mv643xx_eth_change_mtu, 2991 .ndo_set_features = mv643xx_eth_set_features, 2992 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 2993 .ndo_get_stats = mv643xx_eth_get_stats, 2994 #ifdef CONFIG_NET_POLL_CONTROLLER 2995 .ndo_poll_controller = mv643xx_eth_netpoll, 2996 #endif 2997 }; 2998 2999 static int mv643xx_eth_probe(struct platform_device *pdev) 3000 { 3001 struct mv643xx_eth_platform_data *pd; 3002 struct mv643xx_eth_private *mp; 3003 struct net_device *dev; 3004 struct resource *res; 3005 int err; 3006 3007 pd = dev_get_platdata(&pdev->dev); 3008 if (pd == NULL) { 3009 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 3010 return -ENODEV; 3011 } 3012 3013 if (pd->shared == NULL) { 3014 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 3015 return -ENODEV; 3016 } 3017 3018 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 3019 if (!dev) 3020 return -ENOMEM; 3021 3022 mp = netdev_priv(dev); 3023 platform_set_drvdata(pdev, mp); 3024 3025 mp->shared = platform_get_drvdata(pd->shared); 3026 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 3027 mp->port_num = pd->port_number; 3028 3029 mp->dev = dev; 3030 3031 /* Kirkwood resets some registers on gated clocks. Especially 3032 * CLK125_BYPASS_EN must be cleared but is not available on 3033 * all other SoCs/System Controllers using this driver. 3034 */ 3035 if (of_device_is_compatible(pdev->dev.of_node, 3036 "marvell,kirkwood-eth-port")) 3037 wrlp(mp, PORT_SERIAL_CONTROL1, 3038 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); 3039 3040 /* 3041 * Start with a default rate, and if there is a clock, allow 3042 * it to override the default. 3043 */ 3044 mp->t_clk = 133000000; 3045 mp->clk = devm_clk_get(&pdev->dev, NULL); 3046 if (!IS_ERR(mp->clk)) { 3047 clk_prepare_enable(mp->clk); 3048 mp->t_clk = clk_get_rate(mp->clk); 3049 } else if (!IS_ERR(mp->shared->clk)) { 3050 mp->t_clk = clk_get_rate(mp->shared->clk); 3051 } 3052 3053 set_params(mp, pd); 3054 netif_set_real_num_tx_queues(dev, mp->txq_count); 3055 netif_set_real_num_rx_queues(dev, mp->rxq_count); 3056 3057 err = 0; 3058 if (pd->phy_node) { 3059 mp->phy = of_phy_connect(mp->dev, pd->phy_node, 3060 mv643xx_eth_adjust_link, 0, 3061 PHY_INTERFACE_MODE_GMII); 3062 if (!mp->phy) 3063 err = -ENODEV; 3064 else 3065 phy_addr_set(mp, mp->phy->addr); 3066 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 3067 mp->phy = phy_scan(mp, pd->phy_addr); 3068 3069 if (IS_ERR(mp->phy)) 3070 err = PTR_ERR(mp->phy); 3071 else 3072 phy_init(mp, pd->speed, pd->duplex); 3073 } 3074 if (err == -ENODEV) { 3075 err = -EPROBE_DEFER; 3076 goto out; 3077 } 3078 if (err) 3079 goto out; 3080 3081 dev->ethtool_ops = &mv643xx_eth_ethtool_ops; 3082 3083 init_pscr(mp, pd->speed, pd->duplex); 3084 3085 3086 mib_counters_clear(mp); 3087 3088 init_timer(&mp->mib_counters_timer); 3089 mp->mib_counters_timer.data = (unsigned long)mp; 3090 mp->mib_counters_timer.function = mib_counters_timer_wrapper; 3091 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 3092 3093 spin_lock_init(&mp->mib_counters_lock); 3094 3095 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 3096 3097 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT); 3098 3099 init_timer(&mp->rx_oom); 3100 mp->rx_oom.data = (unsigned long)mp; 3101 mp->rx_oom.function = oom_timer_wrapper; 3102 3103 3104 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 3105 BUG_ON(!res); 3106 dev->irq = res->start; 3107 3108 dev->netdev_ops = &mv643xx_eth_netdev_ops; 3109 3110 dev->watchdog_timeo = 2 * HZ; 3111 dev->base_addr = 0; 3112 3113 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3114 dev->vlan_features = dev->features; 3115 3116 dev->features |= NETIF_F_RXCSUM; 3117 dev->hw_features = dev->features; 3118 3119 dev->priv_flags |= IFF_UNICAST_FLT; 3120 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS; 3121 3122 SET_NETDEV_DEV(dev, &pdev->dev); 3123 3124 if (mp->shared->win_protect) 3125 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 3126 3127 netif_carrier_off(dev); 3128 3129 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 3130 3131 set_rx_coal(mp, 250); 3132 set_tx_coal(mp, 0); 3133 3134 err = register_netdev(dev); 3135 if (err) 3136 goto out; 3137 3138 netdev_notice(dev, "port %d with MAC address %pM\n", 3139 mp->port_num, dev->dev_addr); 3140 3141 if (mp->tx_desc_sram_size > 0) 3142 netdev_notice(dev, "configured with sram\n"); 3143 3144 return 0; 3145 3146 out: 3147 if (!IS_ERR(mp->clk)) 3148 clk_disable_unprepare(mp->clk); 3149 free_netdev(dev); 3150 3151 return err; 3152 } 3153 3154 static int mv643xx_eth_remove(struct platform_device *pdev) 3155 { 3156 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3157 3158 unregister_netdev(mp->dev); 3159 if (mp->phy != NULL) 3160 phy_disconnect(mp->phy); 3161 cancel_work_sync(&mp->tx_timeout_task); 3162 3163 if (!IS_ERR(mp->clk)) 3164 clk_disable_unprepare(mp->clk); 3165 3166 free_netdev(mp->dev); 3167 3168 return 0; 3169 } 3170 3171 static void mv643xx_eth_shutdown(struct platform_device *pdev) 3172 { 3173 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3174 3175 /* Mask all interrupts on ethernet port */ 3176 wrlp(mp, INT_MASK, 0); 3177 rdlp(mp, INT_MASK); 3178 3179 if (netif_running(mp->dev)) 3180 port_reset(mp); 3181 } 3182 3183 static struct platform_driver mv643xx_eth_driver = { 3184 .probe = mv643xx_eth_probe, 3185 .remove = mv643xx_eth_remove, 3186 .shutdown = mv643xx_eth_shutdown, 3187 .driver = { 3188 .name = MV643XX_ETH_NAME, 3189 .owner = THIS_MODULE, 3190 }, 3191 }; 3192 3193 static int __init mv643xx_eth_init_module(void) 3194 { 3195 int rc; 3196 3197 rc = platform_driver_register(&mv643xx_eth_shared_driver); 3198 if (!rc) { 3199 rc = platform_driver_register(&mv643xx_eth_driver); 3200 if (rc) 3201 platform_driver_unregister(&mv643xx_eth_shared_driver); 3202 } 3203 3204 return rc; 3205 } 3206 module_init(mv643xx_eth_init_module); 3207 3208 static void __exit mv643xx_eth_cleanup_module(void) 3209 { 3210 platform_driver_unregister(&mv643xx_eth_driver); 3211 platform_driver_unregister(&mv643xx_eth_shared_driver); 3212 } 3213 module_exit(mv643xx_eth_cleanup_module); 3214 3215 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3216 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3217 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3218 MODULE_LICENSE("GPL"); 3219 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3220 MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3221