1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 #ifndef _IXGBEVF_DEFINES_H_ 5 #define _IXGBEVF_DEFINES_H_ 6 7 /* Device IDs */ 8 #define IXGBE_DEV_ID_82599_VF 0x10ED 9 #define IXGBE_DEV_ID_X540_VF 0x1515 10 #define IXGBE_DEV_ID_X550_VF 0x1565 11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 13 14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E 15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530 16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564 17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 18 19 #define IXGBE_DEV_ID_E610_VF 0x57AD 20 #define IXGBE_SUBDEV_ID_E610_VF_HV 0x00FF 21 22 #define IXGBE_VF_IRQ_CLEAR_MASK 7 23 #define IXGBE_VF_MAX_TX_QUEUES 8 24 #define IXGBE_VF_MAX_RX_QUEUES 8 25 26 /* DCB define */ 27 #define IXGBE_VF_MAX_TRAFFIC_CLASS 8 28 29 /* Link speed */ 30 typedef u32 ixgbe_link_speed; 31 #define IXGBE_LINK_SPEED_UNKNOWN 0 32 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 33 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 34 #define IXGBE_LINK_SPEED_100_FULL 0x0008 35 36 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 37 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 38 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 39 #define IXGBE_LINKS_UP 0x40000000 40 #define IXGBE_LINKS_SPEED_82599 0x30000000 41 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 42 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 43 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 44 45 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 46 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 47 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 48 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 49 50 /* Interrupt Vector Allocation Registers */ 51 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 52 53 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 54 55 /* Receive Config masks */ 56 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 57 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 58 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 59 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 60 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 61 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 62 63 /* DCA Control */ 64 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 65 66 /* PSRTYPE bit definitions */ 67 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 68 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 69 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 70 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 71 #define IXGBE_PSRTYPE_L2HDR 0x00001000 72 73 /* SRRCTL bit definitions */ 74 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 75 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 76 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 77 #define IXGBE_SRRCTL_DROP_EN 0x10000000 78 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 79 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 80 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 81 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 82 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 83 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 84 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 85 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 86 87 /* Receive Descriptor bit definitions */ 88 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 89 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 90 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 91 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 92 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 93 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 94 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 95 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 96 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 97 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 98 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 99 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 100 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 101 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 102 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 103 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 104 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 105 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 106 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 107 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 108 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 109 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 110 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 111 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 112 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 113 #define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ 114 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 115 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 116 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 117 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 118 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 119 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 120 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 121 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 122 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 123 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 124 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 125 #define IXGBE_RXD_PRI_SHIFT 13 126 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 127 #define IXGBE_RXD_CFI_SHIFT 12 128 129 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 130 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 131 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 132 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 133 #define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ 134 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 135 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 136 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 137 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 138 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 139 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 140 #define IXGBE_RXDADV_STAT_SECP 0x00020000 /* IPsec/MACsec pkt found */ 141 142 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 143 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 144 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 145 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 146 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 147 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 148 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 149 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 150 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 151 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 152 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 153 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 154 #define IXGBE_RXDADV_SPH 0x8000 155 156 /* RSS Hash results */ 157 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 158 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 159 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 160 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 161 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 162 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 163 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 164 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 165 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 166 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 167 168 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 169 IXGBE_RXD_ERR_CE | \ 170 IXGBE_RXD_ERR_LE | \ 171 IXGBE_RXD_ERR_PE | \ 172 IXGBE_RXD_ERR_OSE | \ 173 IXGBE_RXD_ERR_USE) 174 175 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 176 IXGBE_RXDADV_ERR_CE | \ 177 IXGBE_RXDADV_ERR_LE | \ 178 IXGBE_RXDADV_ERR_PE | \ 179 IXGBE_RXDADV_ERR_OSE | \ 180 IXGBE_RXDADV_ERR_USE) 181 182 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 183 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 184 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 185 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 186 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 187 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 188 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor ext (0 = legacy) */ 189 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 190 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 191 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS) 192 193 /* Transmit Descriptor - Advanced */ 194 union ixgbe_adv_tx_desc { 195 struct { 196 __le64 buffer_addr; /* Address of descriptor's data buf */ 197 __le32 cmd_type_len; 198 __le32 olinfo_status; 199 } read; 200 struct { 201 __le64 rsvd; /* Reserved */ 202 __le32 nxtseq_seed; 203 __le32 status; 204 } wb; 205 }; 206 207 /* Receive Descriptor - Advanced */ 208 union ixgbe_adv_rx_desc { 209 struct { 210 __le64 pkt_addr; /* Packet buffer address */ 211 __le64 hdr_addr; /* Header buffer address */ 212 } read; 213 struct { 214 struct { 215 union { 216 __le32 data; 217 struct { 218 __le16 pkt_info; /* RSS, Pkt type */ 219 __le16 hdr_info; /* Splithdr, hdrlen */ 220 } hs_rss; 221 } lo_dword; 222 union { 223 __le32 rss; /* RSS Hash */ 224 struct { 225 __le16 ip_id; /* IP id */ 226 __le16 csum; /* Packet Checksum */ 227 } csum_ip; 228 } hi_dword; 229 } lower; 230 struct { 231 __le32 status_error; /* ext status/error */ 232 __le16 length; /* Packet length */ 233 __le16 vlan; /* VLAN tag */ 234 } upper; 235 } wb; /* writeback */ 236 }; 237 238 /* Context descriptors */ 239 struct ixgbe_adv_tx_context_desc { 240 __le32 vlan_macip_lens; 241 __le32 fceof_saidx; 242 __le32 type_tucmd_mlhl; 243 __le32 mss_l4len_idx; 244 }; 245 246 /* Adv Transmit Descriptor Config Masks */ 247 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 248 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 249 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 250 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 251 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 252 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 253 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 254 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 255 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 256 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 257 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 258 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 259 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 260 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 261 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 262 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 263 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 /* ESP Encrypt Enable */ 264 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 265 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 266 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 267 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 268 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 269 IXGBE_ADVTXD_POPTS_SHIFT) 270 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 271 IXGBE_ADVTXD_POPTS_SHIFT) 272 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 273 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 274 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 275 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 276 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 277 278 /* Interrupt register bitmasks */ 279 280 #define IXGBE_EITR_CNT_WDIS 0x80000000 281 #define IXGBE_MAX_EITR 0x00000FF8 282 #define IXGBE_MIN_EITR 8 283 284 /* Error Codes */ 285 #define IXGBE_ERR_INVALID_MAC_ADDR -1 286 #define IXGBE_ERR_RESET_FAILED -2 287 #define IXGBE_ERR_INVALID_ARGUMENT -3 288 #define IXGBE_ERR_CONFIG -4 289 #define IXGBE_ERR_MBX -5 290 #define IXGBE_ERR_TIMEOUT -6 291 #define IXGBE_ERR_PARAM -7 292 293 /* Transmit Config masks */ 294 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 295 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 296 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 297 298 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ 299 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ 300 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ 301 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ 302 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 303 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 304 305 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 306 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 307 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 308 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 309 310 #endif /* _IXGBEVF_DEFINES_H_ */ 311