1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 30 { 31 struct ixgbe_mac_info *mac = &hw->mac; 32 struct ixgbe_phy_info *phy = &hw->phy; 33 34 /* Start with X540 invariants, since so simular */ 35 ixgbe_get_invariants_X540(hw); 36 37 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 38 phy->ops.set_phy_power = NULL; 39 40 return 0; 41 } 42 43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 44 * @hw: pointer to hardware structure 45 **/ 46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 47 { 48 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 49 50 if (hw->bus.lan_id) { 51 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 52 esdp |= IXGBE_ESDP_SDP1_DIR; 53 } 54 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 55 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 56 IXGBE_WRITE_FLUSH(hw); 57 } 58 59 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 60 * @hw: pointer to hardware structure 61 * 62 * Returns error code 63 */ 64 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 65 { 66 switch (hw->device_id) { 67 case IXGBE_DEV_ID_X550EM_X_SFP: 68 /* set up for CS4227 usage */ 69 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 70 ixgbe_setup_mux_ctl(hw); 71 72 return ixgbe_identify_module_generic(hw); 73 case IXGBE_DEV_ID_X550EM_X_KX4: 74 hw->phy.type = ixgbe_phy_x550em_kx4; 75 break; 76 case IXGBE_DEV_ID_X550EM_X_KR: 77 hw->phy.type = ixgbe_phy_x550em_kr; 78 break; 79 case IXGBE_DEV_ID_X550EM_X_1G_T: 80 case IXGBE_DEV_ID_X550EM_X_10G_T: 81 return ixgbe_identify_phy_generic(hw); 82 default: 83 break; 84 } 85 return 0; 86 } 87 88 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 89 u32 device_type, u16 *phy_data) 90 { 91 return IXGBE_NOT_IMPLEMENTED; 92 } 93 94 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 95 u32 device_type, u16 phy_data) 96 { 97 return IXGBE_NOT_IMPLEMENTED; 98 } 99 100 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 101 * @hw: pointer to hardware structure 102 * 103 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 104 * ixgbe_hw struct in order to set up EEPROM access. 105 **/ 106 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 107 { 108 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 109 u32 eec; 110 u16 eeprom_size; 111 112 if (eeprom->type == ixgbe_eeprom_uninitialized) { 113 eeprom->semaphore_delay = 10; 114 eeprom->type = ixgbe_flash; 115 116 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 117 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 118 IXGBE_EEC_SIZE_SHIFT); 119 eeprom->word_size = 1 << (eeprom_size + 120 IXGBE_EEPROM_WORD_SIZE_SHIFT); 121 122 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 123 eeprom->type, eeprom->word_size); 124 } 125 126 return 0; 127 } 128 129 /** 130 * ixgbe_iosf_wait - Wait for IOSF command completion 131 * @hw: pointer to hardware structure 132 * @ctrl: pointer to location to receive final IOSF control value 133 * 134 * Return: failing status on timeout 135 * 136 * Note: ctrl can be NULL if the IOSF control register value is not needed 137 */ 138 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 139 { 140 u32 i, command; 141 142 /* Check every 10 usec to see if the address cycle completed. 143 * The SB IOSF BUSY bit will clear when the operation is 144 * complete. 145 */ 146 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 147 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 148 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 149 break; 150 usleep_range(10, 20); 151 } 152 if (ctrl) 153 *ctrl = command; 154 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 155 hw_dbg(hw, "IOSF wait timed out\n"); 156 return IXGBE_ERR_PHY; 157 } 158 159 return 0; 160 } 161 162 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 163 * IOSF device 164 * @hw: pointer to hardware structure 165 * @reg_addr: 32 bit PHY register to write 166 * @device_type: 3 bit device type 167 * @phy_data: Pointer to read data from the register 168 **/ 169 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 170 u32 device_type, u32 *data) 171 { 172 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 173 u32 command, error; 174 s32 ret; 175 176 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 177 if (ret) 178 return ret; 179 180 ret = ixgbe_iosf_wait(hw, NULL); 181 if (ret) 182 goto out; 183 184 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 185 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 186 187 /* Write IOSF control register */ 188 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 189 190 ret = ixgbe_iosf_wait(hw, &command); 191 192 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 193 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 194 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 195 hw_dbg(hw, "Failed to read, error %x\n", error); 196 return IXGBE_ERR_PHY; 197 } 198 199 if (!ret) 200 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 201 202 out: 203 hw->mac.ops.release_swfw_sync(hw, gssr); 204 return ret; 205 } 206 207 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface 208 * command assuming that the semaphore is already obtained. 209 * @hw: pointer to hardware structure 210 * @offset: offset of word in the EEPROM to read 211 * @data: word read from the EEPROM 212 * 213 * Reads a 16 bit word from the EEPROM using the hostif. 214 **/ 215 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 216 u16 *data) 217 { 218 s32 status; 219 struct ixgbe_hic_read_shadow_ram buffer; 220 221 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 222 buffer.hdr.req.buf_lenh = 0; 223 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 224 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 225 226 /* convert offset from words to bytes */ 227 buffer.address = cpu_to_be32(offset * 2); 228 /* one word */ 229 buffer.length = cpu_to_be16(sizeof(u16)); 230 231 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 232 sizeof(buffer), 233 IXGBE_HI_COMMAND_TIMEOUT, false); 234 if (status) 235 return status; 236 237 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 238 FW_NVM_DATA_OFFSET); 239 240 return 0; 241 } 242 243 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 244 * @hw: pointer to hardware structure 245 * @offset: offset of word in the EEPROM to read 246 * @words: number of words 247 * @data: word(s) read from the EEPROM 248 * 249 * Reads a 16 bit word(s) from the EEPROM using the hostif. 250 **/ 251 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 252 u16 offset, u16 words, u16 *data) 253 { 254 struct ixgbe_hic_read_shadow_ram buffer; 255 u32 current_word = 0; 256 u16 words_to_read; 257 s32 status; 258 u32 i; 259 260 /* Take semaphore for the entire operation. */ 261 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 262 if (status) { 263 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 264 return status; 265 } 266 267 while (words) { 268 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 269 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 270 else 271 words_to_read = words; 272 273 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 274 buffer.hdr.req.buf_lenh = 0; 275 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 276 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 277 278 /* convert offset from words to bytes */ 279 buffer.address = cpu_to_be32((offset + current_word) * 2); 280 buffer.length = cpu_to_be16(words_to_read * 2); 281 282 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 283 sizeof(buffer), 284 IXGBE_HI_COMMAND_TIMEOUT, 285 false); 286 if (status) { 287 hw_dbg(hw, "Host interface command failed\n"); 288 goto out; 289 } 290 291 for (i = 0; i < words_to_read; i++) { 292 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 293 2 * i; 294 u32 value = IXGBE_READ_REG(hw, reg); 295 296 data[current_word] = (u16)(value & 0xffff); 297 current_word++; 298 i++; 299 if (i < words_to_read) { 300 value >>= 16; 301 data[current_word] = (u16)(value & 0xffff); 302 current_word++; 303 } 304 } 305 words -= words_to_read; 306 } 307 308 out: 309 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 310 return status; 311 } 312 313 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 314 * @hw: pointer to hardware structure 315 * @ptr: pointer offset in eeprom 316 * @size: size of section pointed by ptr, if 0 first word will be used as size 317 * @csum: address of checksum to update 318 * 319 * Returns error status for any failure 320 **/ 321 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 322 u16 size, u16 *csum, u16 *buffer, 323 u32 buffer_size) 324 { 325 u16 buf[256]; 326 s32 status; 327 u16 length, bufsz, i, start; 328 u16 *local_buffer; 329 330 bufsz = sizeof(buf) / sizeof(buf[0]); 331 332 /* Read a chunk at the pointer location */ 333 if (!buffer) { 334 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 335 if (status) { 336 hw_dbg(hw, "Failed to read EEPROM image\n"); 337 return status; 338 } 339 local_buffer = buf; 340 } else { 341 if (buffer_size < ptr) 342 return IXGBE_ERR_PARAM; 343 local_buffer = &buffer[ptr]; 344 } 345 346 if (size) { 347 start = 0; 348 length = size; 349 } else { 350 start = 1; 351 length = local_buffer[0]; 352 353 /* Skip pointer section if length is invalid. */ 354 if (length == 0xFFFF || length == 0 || 355 (ptr + length) >= hw->eeprom.word_size) 356 return 0; 357 } 358 359 if (buffer && ((u32)start + (u32)length > buffer_size)) 360 return IXGBE_ERR_PARAM; 361 362 for (i = start; length; i++, length--) { 363 if (i == bufsz && !buffer) { 364 ptr += bufsz; 365 i = 0; 366 if (length < bufsz) 367 bufsz = length; 368 369 /* Read a chunk at the pointer location */ 370 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 371 bufsz, buf); 372 if (status) { 373 hw_dbg(hw, "Failed to read EEPROM image\n"); 374 return status; 375 } 376 } 377 *csum += local_buffer[i]; 378 } 379 return 0; 380 } 381 382 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 383 * @hw: pointer to hardware structure 384 * @buffer: pointer to buffer containing calculated checksum 385 * @buffer_size: size of buffer 386 * 387 * Returns a negative error code on error, or the 16-bit checksum 388 **/ 389 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 390 u32 buffer_size) 391 { 392 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 393 u16 *local_buffer; 394 s32 status; 395 u16 checksum = 0; 396 u16 pointer, i, size; 397 398 hw->eeprom.ops.init_params(hw); 399 400 if (!buffer) { 401 /* Read pointer area */ 402 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 403 IXGBE_EEPROM_LAST_WORD + 1, 404 eeprom_ptrs); 405 if (status) { 406 hw_dbg(hw, "Failed to read EEPROM image\n"); 407 return status; 408 } 409 local_buffer = eeprom_ptrs; 410 } else { 411 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 412 return IXGBE_ERR_PARAM; 413 local_buffer = buffer; 414 } 415 416 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 417 * checksum word itself 418 */ 419 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 420 if (i != IXGBE_EEPROM_CHECKSUM) 421 checksum += local_buffer[i]; 422 423 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 424 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 425 */ 426 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 427 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 428 continue; 429 430 pointer = local_buffer[i]; 431 432 /* Skip pointer section if the pointer is invalid. */ 433 if (pointer == 0xFFFF || pointer == 0 || 434 pointer >= hw->eeprom.word_size) 435 continue; 436 437 switch (i) { 438 case IXGBE_PCIE_GENERAL_PTR: 439 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 440 break; 441 case IXGBE_PCIE_CONFIG0_PTR: 442 case IXGBE_PCIE_CONFIG1_PTR: 443 size = IXGBE_PCIE_CONFIG_SIZE; 444 break; 445 default: 446 size = 0; 447 break; 448 } 449 450 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 451 buffer, buffer_size); 452 if (status) 453 return status; 454 } 455 456 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 457 458 return (s32)checksum; 459 } 460 461 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 462 * @hw: pointer to hardware structure 463 * 464 * Returns a negative error code on error, or the 16-bit checksum 465 **/ 466 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 467 { 468 return ixgbe_calc_checksum_X550(hw, NULL, 0); 469 } 470 471 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 472 * @hw: pointer to hardware structure 473 * @offset: offset of word in the EEPROM to read 474 * @data: word read from the EEPROM 475 * 476 * Reads a 16 bit word from the EEPROM using the hostif. 477 **/ 478 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 479 { 480 s32 status = 0; 481 482 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 483 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 484 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 485 } else { 486 status = IXGBE_ERR_SWFW_SYNC; 487 } 488 489 return status; 490 } 491 492 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 493 * @hw: pointer to hardware structure 494 * @checksum_val: calculated checksum 495 * 496 * Performs checksum calculation and validates the EEPROM checksum. If the 497 * caller does not need checksum_val, the value can be NULL. 498 **/ 499 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 500 u16 *checksum_val) 501 { 502 s32 status; 503 u16 checksum; 504 u16 read_checksum = 0; 505 506 /* Read the first word from the EEPROM. If this times out or fails, do 507 * not continue or we could be in for a very long wait while every 508 * EEPROM read fails 509 */ 510 status = hw->eeprom.ops.read(hw, 0, &checksum); 511 if (status) { 512 hw_dbg(hw, "EEPROM read failed\n"); 513 return status; 514 } 515 516 status = hw->eeprom.ops.calc_checksum(hw); 517 if (status < 0) 518 return status; 519 520 checksum = (u16)(status & 0xffff); 521 522 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 523 &read_checksum); 524 if (status) 525 return status; 526 527 /* Verify read checksum from EEPROM is the same as 528 * calculated checksum 529 */ 530 if (read_checksum != checksum) { 531 status = IXGBE_ERR_EEPROM_CHECKSUM; 532 hw_dbg(hw, "Invalid EEPROM checksum"); 533 } 534 535 /* If the user cares, return the calculated checksum */ 536 if (checksum_val) 537 *checksum_val = checksum; 538 539 return status; 540 } 541 542 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 543 * @hw: pointer to hardware structure 544 * @offset: offset of word in the EEPROM to write 545 * @data: word write to the EEPROM 546 * 547 * Write a 16 bit word to the EEPROM using the hostif. 548 **/ 549 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 550 u16 data) 551 { 552 s32 status; 553 struct ixgbe_hic_write_shadow_ram buffer; 554 555 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 556 buffer.hdr.req.buf_lenh = 0; 557 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 558 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 559 560 /* one word */ 561 buffer.length = cpu_to_be16(sizeof(u16)); 562 buffer.data = data; 563 buffer.address = cpu_to_be32(offset * 2); 564 565 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 566 sizeof(buffer), 567 IXGBE_HI_COMMAND_TIMEOUT, false); 568 return status; 569 } 570 571 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 572 * @hw: pointer to hardware structure 573 * @offset: offset of word in the EEPROM to write 574 * @data: word write to the EEPROM 575 * 576 * Write a 16 bit word to the EEPROM using the hostif. 577 **/ 578 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 579 { 580 s32 status = 0; 581 582 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 583 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 584 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 585 } else { 586 hw_dbg(hw, "write ee hostif failed to get semaphore"); 587 status = IXGBE_ERR_SWFW_SYNC; 588 } 589 590 return status; 591 } 592 593 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 594 * @hw: pointer to hardware structure 595 * 596 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 597 **/ 598 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 599 { 600 s32 status = 0; 601 union ixgbe_hic_hdr2 buffer; 602 603 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 604 buffer.req.buf_lenh = 0; 605 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 606 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 607 608 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 609 sizeof(buffer), 610 IXGBE_HI_COMMAND_TIMEOUT, false); 611 return status; 612 } 613 614 /** 615 * ixgbe_get_bus_info_X550em - Set PCI bus info 616 * @hw: pointer to hardware structure 617 * 618 * Sets bus link width and speed to unknown because X550em is 619 * not a PCI device. 620 **/ 621 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 622 { 623 hw->bus.type = ixgbe_bus_type_internal; 624 hw->bus.width = ixgbe_bus_width_unknown; 625 hw->bus.speed = ixgbe_bus_speed_unknown; 626 627 hw->mac.ops.set_lan_id(hw); 628 629 return 0; 630 } 631 632 /** ixgbe_disable_rx_x550 - Disable RX unit 633 * 634 * Enables the Rx DMA unit for x550 635 **/ 636 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 637 { 638 u32 rxctrl, pfdtxgswc; 639 s32 status; 640 struct ixgbe_hic_disable_rxen fw_cmd; 641 642 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 643 if (rxctrl & IXGBE_RXCTRL_RXEN) { 644 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 645 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 646 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 647 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 648 hw->mac.set_lben = true; 649 } else { 650 hw->mac.set_lben = false; 651 } 652 653 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 654 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 655 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 656 fw_cmd.port_number = (u8)hw->bus.lan_id; 657 658 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 659 sizeof(struct ixgbe_hic_disable_rxen), 660 IXGBE_HI_COMMAND_TIMEOUT, true); 661 662 /* If we fail - disable RX using register write */ 663 if (status) { 664 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 665 if (rxctrl & IXGBE_RXCTRL_RXEN) { 666 rxctrl &= ~IXGBE_RXCTRL_RXEN; 667 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 668 } 669 } 670 } 671 } 672 673 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 674 * @hw: pointer to hardware structure 675 * 676 * After writing EEPROM to shadow RAM using EEWR register, software calculates 677 * checksum and updates the EEPROM and instructs the hardware to update 678 * the flash. 679 **/ 680 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 681 { 682 s32 status; 683 u16 checksum = 0; 684 685 /* Read the first word from the EEPROM. If this times out or fails, do 686 * not continue or we could be in for a very long wait while every 687 * EEPROM read fails 688 */ 689 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 690 if (status) { 691 hw_dbg(hw, "EEPROM read failed\n"); 692 return status; 693 } 694 695 status = ixgbe_calc_eeprom_checksum_X550(hw); 696 if (status < 0) 697 return status; 698 699 checksum = (u16)(status & 0xffff); 700 701 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 702 checksum); 703 if (status) 704 return status; 705 706 status = ixgbe_update_flash_X550(hw); 707 708 return status; 709 } 710 711 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 712 * @hw: pointer to hardware structure 713 * @offset: offset of word in the EEPROM to write 714 * @words: number of words 715 * @data: word(s) write to the EEPROM 716 * 717 * 718 * Write a 16 bit word(s) to the EEPROM using the hostif. 719 **/ 720 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 721 u16 offset, u16 words, 722 u16 *data) 723 { 724 s32 status = 0; 725 u32 i = 0; 726 727 /* Take semaphore for the entire operation. */ 728 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 729 if (status) { 730 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 731 return status; 732 } 733 734 for (i = 0; i < words; i++) { 735 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 736 data[i]); 737 if (status) { 738 hw_dbg(hw, "Eeprom buffered write failed\n"); 739 break; 740 } 741 } 742 743 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 744 745 return status; 746 } 747 748 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 749 * IOSF device 750 * 751 * @hw: pointer to hardware structure 752 * @reg_addr: 32 bit PHY register to write 753 * @device_type: 3 bit device type 754 * @data: Data to write to the register 755 **/ 756 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 757 u32 device_type, u32 data) 758 { 759 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 760 u32 command, error; 761 s32 ret; 762 763 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 764 if (ret) 765 return ret; 766 767 ret = ixgbe_iosf_wait(hw, NULL); 768 if (ret) 769 goto out; 770 771 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 772 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 773 774 /* Write IOSF control register */ 775 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 776 777 /* Write IOSF data register */ 778 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 779 780 ret = ixgbe_iosf_wait(hw, &command); 781 782 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 783 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 784 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 785 hw_dbg(hw, "Failed to write, error %x\n", error); 786 return IXGBE_ERR_PHY; 787 } 788 789 out: 790 hw->mac.ops.release_swfw_sync(hw, gssr); 791 return ret; 792 } 793 794 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 795 * @hw: pointer to hardware structure 796 * @speed: the link speed to force 797 * 798 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 799 * internal and external PHY at a specific speed, without autonegotiation. 800 **/ 801 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 802 { 803 s32 status; 804 u32 reg_val; 805 806 /* Disable AN and force speed to 10G Serial. */ 807 status = ixgbe_read_iosf_sb_reg_x550(hw, 808 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 809 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 810 if (status) 811 return status; 812 813 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 814 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 815 816 /* Select forced link speed for internal PHY. */ 817 switch (*speed) { 818 case IXGBE_LINK_SPEED_10GB_FULL: 819 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 820 break; 821 case IXGBE_LINK_SPEED_1GB_FULL: 822 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 823 break; 824 default: 825 /* Other link speeds are not supported by internal KR PHY. */ 826 return IXGBE_ERR_LINK_SETUP; 827 } 828 829 status = ixgbe_write_iosf_sb_reg_x550(hw, 830 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 831 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 832 if (status) 833 return status; 834 835 /* Disable training protocol FSM. */ 836 status = ixgbe_read_iosf_sb_reg_x550(hw, 837 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 838 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 839 if (status) 840 return status; 841 842 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 843 status = ixgbe_write_iosf_sb_reg_x550(hw, 844 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 845 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 846 if (status) 847 return status; 848 849 /* Disable Flex from training TXFFE. */ 850 status = ixgbe_read_iosf_sb_reg_x550(hw, 851 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 852 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 853 if (status) 854 return status; 855 856 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 857 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 858 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 859 status = ixgbe_write_iosf_sb_reg_x550(hw, 860 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 861 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 862 if (status) 863 return status; 864 865 status = ixgbe_read_iosf_sb_reg_x550(hw, 866 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 867 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 868 if (status) 869 return status; 870 871 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 872 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 873 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 874 status = ixgbe_write_iosf_sb_reg_x550(hw, 875 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 876 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 877 if (status) 878 return status; 879 880 /* Enable override for coefficients. */ 881 status = ixgbe_read_iosf_sb_reg_x550(hw, 882 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 883 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 884 if (status) 885 return status; 886 887 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 888 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 889 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 890 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 891 status = ixgbe_write_iosf_sb_reg_x550(hw, 892 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 893 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 894 if (status) 895 return status; 896 897 /* Toggle port SW reset by AN reset. */ 898 status = ixgbe_read_iosf_sb_reg_x550(hw, 899 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 900 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 901 if (status) 902 return status; 903 904 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 905 status = ixgbe_write_iosf_sb_reg_x550(hw, 906 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 907 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 908 909 return status; 910 } 911 912 /** 913 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 914 * @hw: pointer to hardware structure 915 * @speed: new link speed 916 * @autoneg_wait_to_complete: true when waiting for completion is needed 917 * 918 * Setup internal/external PHY link speed based on link speed, then set 919 * external PHY auto advertised link speed. 920 * 921 * Returns error status for any failure 922 **/ 923 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 924 ixgbe_link_speed speed, 925 bool autoneg_wait) 926 { 927 s32 status; 928 ixgbe_link_speed force_speed; 929 930 /* Setup internal/external PHY link speed to iXFI (10G), unless 931 * only 1G is auto advertised then setup KX link. 932 */ 933 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 934 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 935 else 936 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 937 938 /* If internal link mode is XFI, then setup XFI internal link. */ 939 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 940 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 941 942 if (status) 943 return status; 944 } 945 946 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 947 } 948 949 /** ixgbe_check_link_t_X550em - Determine link and speed status 950 * @hw: pointer to hardware structure 951 * @speed: pointer to link speed 952 * @link_up: true when link is up 953 * @link_up_wait_to_complete: bool used to wait for link up or not 954 * 955 * Check that both the MAC and X557 external PHY have link. 956 **/ 957 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 958 ixgbe_link_speed *speed, 959 bool *link_up, 960 bool link_up_wait_to_complete) 961 { 962 u32 status; 963 u16 autoneg_status; 964 965 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 966 return IXGBE_ERR_CONFIG; 967 968 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 969 link_up_wait_to_complete); 970 971 /* If check link fails or MAC link is not up, then return */ 972 if (status || !(*link_up)) 973 return status; 974 975 /* MAC link is up, so check external PHY link. 976 * Read this twice back to back to indicate current status. 977 */ 978 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 980 &autoneg_status); 981 if (status) 982 return status; 983 984 /* If external PHY link is not up, then indicate link not up */ 985 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 986 *link_up = false; 987 988 return 0; 989 } 990 991 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 992 * @hw: pointer to hardware structure 993 **/ 994 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 995 { 996 struct ixgbe_mac_info *mac = &hw->mac; 997 998 switch (mac->ops.get_media_type(hw)) { 999 case ixgbe_media_type_fiber: 1000 /* CS4227 does not support autoneg, so disable the laser control 1001 * functions for SFP+ fiber 1002 */ 1003 mac->ops.disable_tx_laser = NULL; 1004 mac->ops.enable_tx_laser = NULL; 1005 mac->ops.flap_tx_laser = NULL; 1006 break; 1007 case ixgbe_media_type_copper: 1008 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1009 mac->ops.check_link = ixgbe_check_link_t_X550em; 1010 break; 1011 default: 1012 break; 1013 } 1014 } 1015 1016 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 1017 * @hw: pointer to hardware structure 1018 */ 1019 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1020 { 1021 bool setup_linear; 1022 u16 reg_slice, edc_mode; 1023 s32 ret_val; 1024 1025 switch (hw->phy.sfp_type) { 1026 case ixgbe_sfp_type_unknown: 1027 return 0; 1028 case ixgbe_sfp_type_not_present: 1029 return IXGBE_ERR_SFP_NOT_PRESENT; 1030 case ixgbe_sfp_type_da_cu_core0: 1031 case ixgbe_sfp_type_da_cu_core1: 1032 setup_linear = true; 1033 break; 1034 case ixgbe_sfp_type_srlr_core0: 1035 case ixgbe_sfp_type_srlr_core1: 1036 case ixgbe_sfp_type_da_act_lmt_core0: 1037 case ixgbe_sfp_type_da_act_lmt_core1: 1038 case ixgbe_sfp_type_1g_sx_core0: 1039 case ixgbe_sfp_type_1g_sx_core1: 1040 setup_linear = false; 1041 break; 1042 default: 1043 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1044 } 1045 1046 ixgbe_init_mac_link_ops_X550em(hw); 1047 hw->phy.ops.reset = NULL; 1048 1049 /* The CS4227 slice address is the base address + the port-pair reg 1050 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0. 1051 */ 1052 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12); 1053 1054 if (setup_linear) 1055 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1056 else 1057 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1058 1059 /* Configure CS4227 for connection type. */ 1060 ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1061 edc_mode); 1062 1063 if (ret_val) 1064 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice, 1065 edc_mode); 1066 1067 return ret_val; 1068 } 1069 1070 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 1071 * @hw: pointer to hardware structure 1072 * @speed: pointer to link speed 1073 * @autoneg: true when autoneg or autotry is enabled 1074 **/ 1075 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1076 ixgbe_link_speed *speed, 1077 bool *autoneg) 1078 { 1079 /* SFP */ 1080 if (hw->phy.media_type == ixgbe_media_type_fiber) { 1081 /* CS4227 SFP must not enable auto-negotiation */ 1082 *autoneg = false; 1083 1084 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1085 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 1086 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1087 return 0; 1088 } 1089 1090 /* Link capabilities are based on SFP */ 1091 if (hw->phy.multispeed_fiber) 1092 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1093 IXGBE_LINK_SPEED_1GB_FULL; 1094 else 1095 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1096 } else { 1097 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1098 IXGBE_LINK_SPEED_1GB_FULL; 1099 *autoneg = true; 1100 } 1101 return 0; 1102 } 1103 1104 /** 1105 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1106 * @hw: pointer to hardware structure 1107 * @lsc: pointer to boolean flag which indicates whether external Base T 1108 * PHY interrupt is lsc 1109 * 1110 * Determime if external Base T PHY interrupt cause is high temperature 1111 * failure alarm or link status change. 1112 * 1113 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1114 * failure alarm, else return PHY access status. 1115 **/ 1116 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1117 { 1118 u32 status; 1119 u16 reg; 1120 1121 *lsc = false; 1122 1123 /* Vendor alarm triggered */ 1124 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1125 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1126 ®); 1127 1128 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1129 return status; 1130 1131 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1132 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1133 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1134 ®); 1135 1136 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1137 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1138 return status; 1139 1140 /* High temperature failure alarm triggered */ 1141 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1142 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1143 ®); 1144 1145 if (status) 1146 return status; 1147 1148 /* If high temperature failure, then return over temp error and exit */ 1149 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1150 /* power down the PHY in case the PHY FW didn't already */ 1151 ixgbe_set_copper_phy_power(hw, false); 1152 return IXGBE_ERR_OVERTEMP; 1153 } 1154 1155 /* Vendor alarm 2 triggered */ 1156 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1157 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1158 1159 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1160 return status; 1161 1162 /* link connect/disconnect event occurred */ 1163 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1164 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1165 1166 if (status) 1167 return status; 1168 1169 /* Indicate LSC */ 1170 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1171 *lsc = true; 1172 1173 return 0; 1174 } 1175 1176 /** 1177 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1178 * @hw: pointer to hardware structure 1179 * 1180 * Enable link status change and temperature failure alarm for the external 1181 * Base T PHY 1182 * 1183 * Returns PHY access status 1184 **/ 1185 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1186 { 1187 u32 status; 1188 u16 reg; 1189 bool lsc; 1190 1191 /* Clear interrupt flags */ 1192 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1193 1194 /* Enable link status change alarm */ 1195 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1196 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1197 if (status) 1198 return status; 1199 1200 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1201 1202 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1203 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1204 if (status) 1205 return status; 1206 1207 /* Enables high temperature failure alarm */ 1208 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1209 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1210 ®); 1211 if (status) 1212 return status; 1213 1214 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1215 1216 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1217 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1218 reg); 1219 if (status) 1220 return status; 1221 1222 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1223 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1224 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1225 ®); 1226 if (status) 1227 return status; 1228 1229 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1230 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1231 1232 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1233 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1234 reg); 1235 if (status) 1236 return status; 1237 1238 /* Enable chip-wide vendor alarm */ 1239 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1240 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1241 ®); 1242 if (status) 1243 return status; 1244 1245 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1246 1247 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1248 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1249 reg); 1250 1251 return status; 1252 } 1253 1254 /** 1255 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 1256 * @hw: pointer to hardware structure 1257 * 1258 * Handle external Base T PHY interrupt. If high temperature 1259 * failure alarm then return error, else if link status change 1260 * then setup internal/external PHY link 1261 * 1262 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1263 * failure alarm, else return PHY access status. 1264 **/ 1265 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1266 { 1267 struct ixgbe_phy_info *phy = &hw->phy; 1268 bool lsc; 1269 u32 status; 1270 1271 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1272 if (status) 1273 return status; 1274 1275 if (lsc) 1276 return phy->ops.setup_internal_link(hw); 1277 1278 return 0; 1279 } 1280 1281 /** 1282 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1283 * @hw: pointer to hardware structure 1284 * @speed: link speed 1285 * 1286 * Configures the integrated KR PHY. 1287 **/ 1288 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1289 ixgbe_link_speed speed) 1290 { 1291 s32 status; 1292 u32 reg_val; 1293 1294 status = ixgbe_read_iosf_sb_reg_x550(hw, 1295 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1296 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1297 if (status) 1298 return status; 1299 1300 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1301 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 1302 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 1303 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1304 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1305 1306 /* Advertise 10G support. */ 1307 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1308 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1309 1310 /* Advertise 1G support. */ 1311 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1312 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1313 1314 /* Restart auto-negotiation. */ 1315 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1316 status = ixgbe_write_iosf_sb_reg_x550(hw, 1317 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1318 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1319 1320 return status; 1321 } 1322 1323 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 1324 * @hw: pointer to hardware structure 1325 * 1326 * Configures the integrated KX4 PHY. 1327 **/ 1328 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 1329 { 1330 s32 status; 1331 u32 reg_val; 1332 1333 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1334 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 1335 hw->bus.lan_id, ®_val); 1336 if (status) 1337 return status; 1338 1339 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 1340 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 1341 1342 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 1343 1344 /* Advertise 10G support. */ 1345 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1346 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 1347 1348 /* Advertise 1G support. */ 1349 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1350 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 1351 1352 /* Restart auto-negotiation. */ 1353 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 1354 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1355 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 1356 hw->bus.lan_id, reg_val); 1357 1358 return status; 1359 } 1360 1361 /** ixgbe_setup_kr_x550em - Configure the KR PHY. 1362 * @hw: pointer to hardware structure 1363 * 1364 * Configures the integrated KR PHY. 1365 **/ 1366 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1367 { 1368 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1369 } 1370 1371 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1372 * @hw: address of hardware structure 1373 * @link_up: address of boolean to indicate link status 1374 * 1375 * Returns error code if unable to get link status. 1376 **/ 1377 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1378 { 1379 u32 ret; 1380 u16 autoneg_status; 1381 1382 *link_up = false; 1383 1384 /* read this twice back to back to indicate current status */ 1385 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1386 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1387 &autoneg_status); 1388 if (ret) 1389 return ret; 1390 1391 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1392 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1393 &autoneg_status); 1394 if (ret) 1395 return ret; 1396 1397 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1398 1399 return 0; 1400 } 1401 1402 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1403 * @hw: point to hardware structure 1404 * 1405 * Configures the link between the integrated KR PHY and the external X557 PHY 1406 * The driver will call this function when it gets a link status change 1407 * interrupt from the X557 PHY. This function configures the link speed 1408 * between the PHYs to match the link speed of the BASE-T link. 1409 * 1410 * A return of a non-zero value indicates an error, and the base driver should 1411 * not report link up. 1412 **/ 1413 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1414 { 1415 ixgbe_link_speed force_speed; 1416 bool link_up; 1417 u32 status; 1418 u16 speed; 1419 1420 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1421 return IXGBE_ERR_CONFIG; 1422 1423 /* If link is not up, then there is no setup necessary so return */ 1424 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1425 if (status) 1426 return status; 1427 1428 if (!link_up) 1429 return 0; 1430 1431 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1432 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1433 &speed); 1434 if (status) 1435 return status; 1436 1437 /* If link is not still up, then no setup is necessary so return */ 1438 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1439 if (status) 1440 return status; 1441 1442 if (!link_up) 1443 return 0; 1444 1445 /* clear everything but the speed and duplex bits */ 1446 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1447 1448 switch (speed) { 1449 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1450 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1451 break; 1452 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1453 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1454 break; 1455 default: 1456 /* Internal PHY does not support anything else */ 1457 return IXGBE_ERR_INVALID_LINK_SETTINGS; 1458 } 1459 1460 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1461 } 1462 1463 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 1464 * @hw: pointer to hardware structure 1465 **/ 1466 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 1467 { 1468 s32 status; 1469 1470 status = ixgbe_reset_phy_generic(hw); 1471 1472 if (status) 1473 return status; 1474 1475 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 1476 return ixgbe_enable_lasi_ext_t_x550em(hw); 1477 } 1478 1479 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 1480 * @hw: pointer to hardware structure 1481 * @lcd_speed: pointer to lowest common link speed 1482 * 1483 * Determine lowest common link speed with link partner. 1484 **/ 1485 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 1486 ixgbe_link_speed *lcd_speed) 1487 { 1488 u16 an_lp_status; 1489 s32 status; 1490 u16 word = hw->eeprom.ctrl_word_3; 1491 1492 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 1493 1494 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 1495 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1496 &an_lp_status); 1497 if (status) 1498 return status; 1499 1500 /* If link partner advertised 1G, return 1G */ 1501 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 1502 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 1503 return status; 1504 } 1505 1506 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 1507 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 1508 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 1509 return status; 1510 1511 /* Link partner not capable of lower speeds, return 10G */ 1512 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 1513 return status; 1514 } 1515 1516 /** ixgbe_enter_lplu_x550em - Transition to low power states 1517 * @hw: pointer to hardware structure 1518 * 1519 * Configures Low Power Link Up on transition to low power states 1520 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 1521 * the X557 PHY immediately prior to entering LPLU. 1522 **/ 1523 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 1524 { 1525 u16 an_10g_cntl_reg, autoneg_reg, speed; 1526 s32 status; 1527 ixgbe_link_speed lcd_speed; 1528 u32 save_autoneg; 1529 bool link_up; 1530 1531 /* SW LPLU not required on later HW revisions. */ 1532 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) 1533 return 0; 1534 1535 /* If blocked by MNG FW, then don't restart AN */ 1536 if (ixgbe_check_reset_blocked(hw)) 1537 return 0; 1538 1539 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1540 if (status) 1541 return status; 1542 1543 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 1544 &hw->eeprom.ctrl_word_3); 1545 if (status) 1546 return status; 1547 1548 /* If link is down, LPLU disabled in NVM, WoL disabled, or 1549 * manageability disabled, then force link down by entering 1550 * low power mode. 1551 */ 1552 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 1553 !(hw->wol_enabled || ixgbe_mng_present(hw))) 1554 return ixgbe_set_copper_phy_power(hw, false); 1555 1556 /* Determine LCD */ 1557 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 1558 if (status) 1559 return status; 1560 1561 /* If no valid LCD link speed, then force link down and exit. */ 1562 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 1563 return ixgbe_set_copper_phy_power(hw, false); 1564 1565 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1566 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1567 &speed); 1568 if (status) 1569 return status; 1570 1571 /* If no link now, speed is invalid so take link down */ 1572 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1573 if (status) 1574 return ixgbe_set_copper_phy_power(hw, false); 1575 1576 /* clear everything but the speed bits */ 1577 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 1578 1579 /* If current speed is already LCD, then exit. */ 1580 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 1581 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 1582 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 1583 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 1584 return status; 1585 1586 /* Clear AN completed indication */ 1587 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 1588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1589 &autoneg_reg); 1590 if (status) 1591 return status; 1592 1593 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1594 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1595 &an_10g_cntl_reg); 1596 if (status) 1597 return status; 1598 1599 status = hw->phy.ops.read_reg(hw, 1600 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 1601 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1602 &autoneg_reg); 1603 if (status) 1604 return status; 1605 1606 save_autoneg = hw->phy.autoneg_advertised; 1607 1608 /* Setup link at least common link speed */ 1609 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 1610 1611 /* restore autoneg from before setting lplu speed */ 1612 hw->phy.autoneg_advertised = save_autoneg; 1613 1614 return status; 1615 } 1616 1617 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1618 * @hw: pointer to hardware structure 1619 * 1620 * Initialize any function pointers that were not able to be 1621 * set during init_shared_code because the PHY/SFP type was 1622 * not known. Perform the SFP init if necessary. 1623 **/ 1624 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1625 { 1626 struct ixgbe_phy_info *phy = &hw->phy; 1627 ixgbe_link_speed speed; 1628 s32 ret_val; 1629 1630 hw->mac.ops.set_lan_id(hw); 1631 1632 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1633 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1634 ixgbe_setup_mux_ctl(hw); 1635 1636 /* Save NW management interface connected on board. This is used 1637 * to determine internal PHY mode. 1638 */ 1639 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1640 1641 /* If internal PHY mode is KR, then initialize KR link */ 1642 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1643 speed = IXGBE_LINK_SPEED_10GB_FULL | 1644 IXGBE_LINK_SPEED_1GB_FULL; 1645 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1646 } 1647 } 1648 1649 /* Identify the PHY or SFP module */ 1650 ret_val = phy->ops.identify(hw); 1651 1652 /* Setup function pointers based on detected hardware */ 1653 ixgbe_init_mac_link_ops_X550em(hw); 1654 if (phy->sfp_type != ixgbe_sfp_type_unknown) 1655 phy->ops.reset = NULL; 1656 1657 /* Set functions pointers based on phy type */ 1658 switch (hw->phy.type) { 1659 case ixgbe_phy_x550em_kx4: 1660 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 1661 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1662 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1663 break; 1664 case ixgbe_phy_x550em_kr: 1665 phy->ops.setup_link = ixgbe_setup_kr_x550em; 1666 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1667 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1668 break; 1669 case ixgbe_phy_x550em_ext_t: 1670 /* Save NW management interface connected on board. This is used 1671 * to determine internal PHY mode 1672 */ 1673 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1674 1675 /* If internal link mode is XFI, then setup iXFI internal link, 1676 * else setup KR now. 1677 */ 1678 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1679 phy->ops.setup_internal_link = 1680 ixgbe_setup_internal_phy_t_x550em; 1681 } else { 1682 speed = IXGBE_LINK_SPEED_10GB_FULL | 1683 IXGBE_LINK_SPEED_1GB_FULL; 1684 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1685 } 1686 1687 /* setup SW LPLU only for first revision */ 1688 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, 1689 IXGBE_FUSES0_GROUP(0)))) 1690 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1691 1692 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1693 phy->ops.reset = ixgbe_reset_phy_t_X550em; 1694 break; 1695 default: 1696 break; 1697 } 1698 1699 return ret_val; 1700 } 1701 1702 /** ixgbe_get_media_type_X550em - Get media type 1703 * @hw: pointer to hardware structure 1704 * 1705 * Returns the media type (fiber, copper, backplane) 1706 * 1707 */ 1708 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1709 { 1710 enum ixgbe_media_type media_type; 1711 1712 /* Detect if there is a copper PHY attached. */ 1713 switch (hw->device_id) { 1714 case IXGBE_DEV_ID_X550EM_X_KR: 1715 case IXGBE_DEV_ID_X550EM_X_KX4: 1716 media_type = ixgbe_media_type_backplane; 1717 break; 1718 case IXGBE_DEV_ID_X550EM_X_SFP: 1719 media_type = ixgbe_media_type_fiber; 1720 break; 1721 case IXGBE_DEV_ID_X550EM_X_1G_T: 1722 case IXGBE_DEV_ID_X550EM_X_10G_T: 1723 media_type = ixgbe_media_type_copper; 1724 break; 1725 default: 1726 media_type = ixgbe_media_type_unknown; 1727 break; 1728 } 1729 return media_type; 1730 } 1731 1732 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1733 ** @hw: pointer to hardware structure 1734 **/ 1735 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1736 { 1737 s32 status; 1738 u16 reg; 1739 1740 status = hw->phy.ops.read_reg(hw, 1741 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1742 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1743 ®); 1744 if (status) 1745 return status; 1746 1747 /* If PHY FW reset completed bit is set then this is the first 1748 * SW instance after a power on so the PHY FW must be un-stalled. 1749 */ 1750 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1751 status = hw->phy.ops.read_reg(hw, 1752 IXGBE_MDIO_GLOBAL_RES_PR_10, 1753 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1754 ®); 1755 if (status) 1756 return status; 1757 1758 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1759 1760 status = hw->phy.ops.write_reg(hw, 1761 IXGBE_MDIO_GLOBAL_RES_PR_10, 1762 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1763 reg); 1764 if (status) 1765 return status; 1766 } 1767 1768 return status; 1769 } 1770 1771 /** ixgbe_reset_hw_X550em - Perform hardware reset 1772 ** @hw: pointer to hardware structure 1773 ** 1774 ** Resets the hardware by resetting the transmit and receive units, masks 1775 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1776 ** reset. 1777 **/ 1778 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1779 { 1780 ixgbe_link_speed link_speed; 1781 s32 status; 1782 u32 ctrl = 0; 1783 u32 i; 1784 u32 hlreg0; 1785 bool link_up = false; 1786 1787 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1788 status = hw->mac.ops.stop_adapter(hw); 1789 if (status) 1790 return status; 1791 1792 /* flush pending Tx transactions */ 1793 ixgbe_clear_tx_pending(hw); 1794 1795 /* PHY ops must be identified and initialized prior to reset */ 1796 1797 /* Identify PHY and related function pointers */ 1798 status = hw->phy.ops.init(hw); 1799 1800 /* start the external PHY */ 1801 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1802 status = ixgbe_init_ext_t_x550em(hw); 1803 if (status) 1804 return status; 1805 } 1806 1807 /* Setup SFP module if there is one present. */ 1808 if (hw->phy.sfp_setup_needed) { 1809 status = hw->mac.ops.setup_sfp(hw); 1810 hw->phy.sfp_setup_needed = false; 1811 } 1812 1813 /* Reset PHY */ 1814 if (!hw->phy.reset_disable && hw->phy.ops.reset) 1815 hw->phy.ops.reset(hw); 1816 1817 mac_reset_top: 1818 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1819 * If link reset is used when link is up, it might reset the PHY when 1820 * mng is using it. If link is down or the flag to force full link 1821 * reset is set, then perform link reset. 1822 */ 1823 ctrl = IXGBE_CTRL_LNK_RST; 1824 1825 if (!hw->force_full_reset) { 1826 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1827 if (link_up) 1828 ctrl = IXGBE_CTRL_RST; 1829 } 1830 1831 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1832 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1833 IXGBE_WRITE_FLUSH(hw); 1834 1835 /* Poll for reset bit to self-clear meaning reset is complete */ 1836 for (i = 0; i < 10; i++) { 1837 udelay(1); 1838 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1839 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1840 break; 1841 } 1842 1843 if (ctrl & IXGBE_CTRL_RST_MASK) { 1844 status = IXGBE_ERR_RESET_FAILED; 1845 hw_dbg(hw, "Reset polling failed to complete.\n"); 1846 } 1847 1848 msleep(50); 1849 1850 /* Double resets are required for recovery from certain error 1851 * clear the multicast table. Also reset num_rar_entries to 128, 1852 * since we modify this value when programming the SAN MAC address. 1853 */ 1854 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1855 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1856 goto mac_reset_top; 1857 } 1858 1859 /* Store the permanent mac address */ 1860 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1861 1862 /* Store MAC address from RAR0, clear receive address registers, and 1863 * clear the multicast table. Also reset num_rar_entries to 128, 1864 * since we modify this value when programming the SAN MAC address. 1865 */ 1866 hw->mac.num_rar_entries = 128; 1867 hw->mac.ops.init_rx_addrs(hw); 1868 1869 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1870 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1871 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1872 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1873 } 1874 1875 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1876 ixgbe_setup_mux_ctl(hw); 1877 1878 return status; 1879 } 1880 1881 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 1882 * anti-spoofing 1883 * @hw: pointer to hardware structure 1884 * @enable: enable or disable switch for Ethertype anti-spoofing 1885 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1886 **/ 1887 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1888 bool enable, int vf) 1889 { 1890 int vf_target_reg = vf >> 3; 1891 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1892 u32 pfvfspoof; 1893 1894 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1895 if (enable) 1896 pfvfspoof |= (1 << vf_target_shift); 1897 else 1898 pfvfspoof &= ~(1 << vf_target_shift); 1899 1900 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1901 } 1902 1903 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 1904 * @hw: pointer to hardware structure 1905 * @enable: enable or disable source address pruning 1906 * @pool: Rx pool to set source address pruning for 1907 **/ 1908 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 1909 bool enable, 1910 unsigned int pool) 1911 { 1912 u64 pfflp; 1913 1914 /* max rx pool is 63 */ 1915 if (pool > 63) 1916 return; 1917 1918 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1919 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1920 1921 if (enable) 1922 pfflp |= (1ULL << pool); 1923 else 1924 pfflp &= ~(1ULL << pool); 1925 1926 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1927 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1928 } 1929 1930 #define X550_COMMON_MAC \ 1931 .init_hw = &ixgbe_init_hw_generic, \ 1932 .start_hw = &ixgbe_start_hw_X540, \ 1933 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 1934 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 1935 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 1936 .get_device_caps = &ixgbe_get_device_caps_generic, \ 1937 .stop_adapter = &ixgbe_stop_adapter_generic, \ 1938 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 1939 .read_analog_reg8 = NULL, \ 1940 .write_analog_reg8 = NULL, \ 1941 .set_rxpba = &ixgbe_set_rxpba_generic, \ 1942 .check_link = &ixgbe_check_mac_link_generic, \ 1943 .led_on = &ixgbe_led_on_generic, \ 1944 .led_off = &ixgbe_led_off_generic, \ 1945 .blink_led_start = &ixgbe_blink_led_start_X540, \ 1946 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 1947 .set_rar = &ixgbe_set_rar_generic, \ 1948 .clear_rar = &ixgbe_clear_rar_generic, \ 1949 .set_vmdq = &ixgbe_set_vmdq_generic, \ 1950 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 1951 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 1952 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 1953 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 1954 .enable_mc = &ixgbe_enable_mc_generic, \ 1955 .disable_mc = &ixgbe_disable_mc_generic, \ 1956 .clear_vfta = &ixgbe_clear_vfta_generic, \ 1957 .set_vfta = &ixgbe_set_vfta_generic, \ 1958 .fc_enable = &ixgbe_fc_enable_generic, \ 1959 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \ 1960 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 1961 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 1962 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 1963 .set_source_address_pruning = \ 1964 &ixgbe_set_source_address_pruning_X550, \ 1965 .set_ethertype_anti_spoofing = \ 1966 &ixgbe_set_ethertype_anti_spoofing_X550, \ 1967 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \ 1968 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \ 1969 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 1970 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 1971 .get_thermal_sensor_data = NULL, \ 1972 .init_thermal_sensor_thresh = NULL, \ 1973 .prot_autoc_read = &prot_autoc_read_generic, \ 1974 .prot_autoc_write = &prot_autoc_write_generic, \ 1975 .enable_rx = &ixgbe_enable_rx_generic, \ 1976 .disable_rx = &ixgbe_disable_rx_x550, \ 1977 1978 static struct ixgbe_mac_operations mac_ops_X550 = { 1979 X550_COMMON_MAC 1980 .reset_hw = &ixgbe_reset_hw_X540, 1981 .get_media_type = &ixgbe_get_media_type_X540, 1982 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 1983 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 1984 .setup_link = &ixgbe_setup_mac_link_X540, 1985 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 1986 .get_bus_info = &ixgbe_get_bus_info_generic, 1987 .setup_sfp = NULL, 1988 }; 1989 1990 static struct ixgbe_mac_operations mac_ops_X550EM_x = { 1991 X550_COMMON_MAC 1992 .reset_hw = &ixgbe_reset_hw_X550em, 1993 .get_media_type = &ixgbe_get_media_type_X550em, 1994 .get_san_mac_addr = NULL, 1995 .get_wwn_prefix = NULL, 1996 .setup_link = NULL, /* defined later */ 1997 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 1998 .get_bus_info = &ixgbe_get_bus_info_X550em, 1999 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 2000 2001 }; 2002 2003 #define X550_COMMON_EEP \ 2004 .read = &ixgbe_read_ee_hostif_X550, \ 2005 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 2006 .write = &ixgbe_write_ee_hostif_X550, \ 2007 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 2008 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 2009 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 2010 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 2011 2012 static struct ixgbe_eeprom_operations eeprom_ops_X550 = { 2013 X550_COMMON_EEP 2014 .init_params = &ixgbe_init_eeprom_params_X550, 2015 }; 2016 2017 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 2018 X550_COMMON_EEP 2019 .init_params = &ixgbe_init_eeprom_params_X540, 2020 }; 2021 2022 #define X550_COMMON_PHY \ 2023 .identify_sfp = &ixgbe_identify_module_generic, \ 2024 .reset = NULL, \ 2025 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 2026 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 2027 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 2028 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 2029 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 2030 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 2031 .read_reg = &ixgbe_read_phy_reg_generic, \ 2032 .write_reg = &ixgbe_write_phy_reg_generic, \ 2033 .setup_link = &ixgbe_setup_phy_link_generic, \ 2034 .set_phy_power = NULL, \ 2035 .check_overtemp = &ixgbe_tn_check_overtemp, \ 2036 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 2037 2038 static struct ixgbe_phy_operations phy_ops_X550 = { 2039 X550_COMMON_PHY 2040 .init = NULL, 2041 .identify = &ixgbe_identify_phy_generic, 2042 .read_i2c_combined = &ixgbe_read_i2c_combined_generic, 2043 .write_i2c_combined = &ixgbe_write_i2c_combined_generic, 2044 }; 2045 2046 static struct ixgbe_phy_operations phy_ops_X550EM_x = { 2047 X550_COMMON_PHY 2048 .init = &ixgbe_init_phy_ops_X550em, 2049 .identify = &ixgbe_identify_phy_x550em, 2050 }; 2051 2052 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 2053 IXGBE_MVALS_INIT(X550) 2054 }; 2055 2056 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 2057 IXGBE_MVALS_INIT(X550EM_x) 2058 }; 2059 2060 struct ixgbe_info ixgbe_X550_info = { 2061 .mac = ixgbe_mac_X550, 2062 .get_invariants = &ixgbe_get_invariants_X540, 2063 .mac_ops = &mac_ops_X550, 2064 .eeprom_ops = &eeprom_ops_X550, 2065 .phy_ops = &phy_ops_X550, 2066 .mbx_ops = &mbx_ops_generic, 2067 .mvals = ixgbe_mvals_X550, 2068 }; 2069 2070 struct ixgbe_info ixgbe_X550EM_x_info = { 2071 .mac = ixgbe_mac_X550EM_x, 2072 .get_invariants = &ixgbe_get_invariants_X550_x, 2073 .mac_ops = &mac_ops_X550EM_x, 2074 .eeprom_ops = &eeprom_ops_X550EM_x, 2075 .phy_ops = &phy_ops_X550EM_x, 2076 .mbx_ops = &mbx_ops_generic, 2077 .mvals = ixgbe_mvals_X550EM_x, 2078 }; 2079