1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include "ixgbe_x540.h" 5 #include "ixgbe_type.h" 6 #include "ixgbe_common.h" 7 #include "ixgbe_phy.h" 8 9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 14 15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 16 { 17 struct ixgbe_mac_info *mac = &hw->mac; 18 struct ixgbe_phy_info *phy = &hw->phy; 19 struct ixgbe_link_info *link = &hw->link; 20 21 /* Start with X540 invariants, since so simular */ 22 ixgbe_get_invariants_X540(hw); 23 24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 25 phy->ops.set_phy_power = NULL; 26 27 link->addr = IXGBE_CS4227; 28 29 return 0; 30 } 31 32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 33 { 34 struct ixgbe_phy_info *phy = &hw->phy; 35 36 /* Start with X540 invariants, since so similar */ 37 ixgbe_get_invariants_X540(hw); 38 39 phy->ops.set_phy_power = NULL; 40 41 return 0; 42 } 43 44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 45 { 46 struct ixgbe_mac_info *mac = &hw->mac; 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* Start with X540 invariants, since so simular */ 50 ixgbe_get_invariants_X540(hw); 51 52 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 53 phy->ops.set_phy_power = NULL; 54 55 return 0; 56 } 57 58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* Start with X540 invariants, since so similar */ 63 ixgbe_get_invariants_X540(hw); 64 65 phy->ops.set_phy_power = NULL; 66 67 return 0; 68 } 69 70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 71 * @hw: pointer to hardware structure 72 **/ 73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 74 { 75 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 76 77 if (hw->bus.lan_id) { 78 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 79 esdp |= IXGBE_ESDP_SDP1_DIR; 80 } 81 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 82 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 83 IXGBE_WRITE_FLUSH(hw); 84 } 85 86 /** 87 * ixgbe_read_cs4227 - Read CS4227 register 88 * @hw: pointer to hardware structure 89 * @reg: register number to write 90 * @value: pointer to receive value read 91 * 92 * Returns status code 93 */ 94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 95 { 96 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 97 } 98 99 /** 100 * ixgbe_write_cs4227 - Write CS4227 register 101 * @hw: pointer to hardware structure 102 * @reg: register number to write 103 * @value: value to write to register 104 * 105 * Returns status code 106 */ 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 108 { 109 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 110 } 111 112 /** 113 * ixgbe_read_pe - Read register from port expander 114 * @hw: pointer to hardware structure 115 * @reg: register number to read 116 * @value: pointer to receive read value 117 * 118 * Returns status code 119 */ 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 121 { 122 s32 status; 123 124 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 125 if (status) 126 hw_err(hw, "port expander access failed with %d\n", status); 127 return status; 128 } 129 130 /** 131 * ixgbe_write_pe - Write register to port expander 132 * @hw: pointer to hardware structure 133 * @reg: register number to write 134 * @value: value to write 135 * 136 * Returns status code 137 */ 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 139 { 140 s32 status; 141 142 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 143 value); 144 if (status) 145 hw_err(hw, "port expander access failed with %d\n", status); 146 return status; 147 } 148 149 /** 150 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 151 * @hw: pointer to hardware structure 152 * 153 * This function assumes that the caller has acquired the proper semaphore. 154 * Returns error code 155 */ 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 157 { 158 s32 status; 159 u32 retry; 160 u16 value; 161 u8 reg; 162 163 /* Trigger hard reset. */ 164 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 165 if (status) 166 return status; 167 reg |= IXGBE_PE_BIT1; 168 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 169 if (status) 170 return status; 171 172 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 173 if (status) 174 return status; 175 reg &= ~IXGBE_PE_BIT1; 176 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 177 if (status) 178 return status; 179 180 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 181 if (status) 182 return status; 183 reg &= ~IXGBE_PE_BIT1; 184 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 185 if (status) 186 return status; 187 188 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 189 190 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 191 if (status) 192 return status; 193 reg |= IXGBE_PE_BIT1; 194 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 195 if (status) 196 return status; 197 198 /* Wait for the reset to complete. */ 199 msleep(IXGBE_CS4227_RESET_DELAY); 200 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 201 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 202 &value); 203 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 204 break; 205 msleep(IXGBE_CS4227_CHECK_DELAY); 206 } 207 if (retry == IXGBE_CS4227_RETRIES) { 208 hw_err(hw, "CS4227 reset did not complete\n"); 209 return IXGBE_ERR_PHY; 210 } 211 212 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 213 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 214 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 215 return IXGBE_ERR_PHY; 216 } 217 218 return 0; 219 } 220 221 /** 222 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 223 * @hw: pointer to hardware structure 224 */ 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 226 { 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 s32 status; 229 u16 value; 230 u8 retry; 231 232 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 234 if (status) { 235 hw_err(hw, "semaphore failed with %d\n", status); 236 msleep(IXGBE_CS4227_CHECK_DELAY); 237 continue; 238 } 239 240 /* Get status of reset flow. */ 241 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 242 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 243 goto out; 244 245 if (status || value != IXGBE_CS4227_RESET_PENDING) 246 break; 247 248 /* Reset is pending. Wait and check again. */ 249 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 250 msleep(IXGBE_CS4227_CHECK_DELAY); 251 } 252 /* If still pending, assume other instance failed. */ 253 if (retry == IXGBE_CS4227_RETRIES) { 254 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 255 if (status) { 256 hw_err(hw, "semaphore failed with %d\n", status); 257 return; 258 } 259 } 260 261 /* Reset the CS4227. */ 262 status = ixgbe_reset_cs4227(hw); 263 if (status) { 264 hw_err(hw, "CS4227 reset failed: %d", status); 265 goto out; 266 } 267 268 /* Reset takes so long, temporarily release semaphore in case the 269 * other driver instance is waiting for the reset indication. 270 */ 271 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 272 IXGBE_CS4227_RESET_PENDING); 273 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 274 usleep_range(10000, 12000); 275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 276 if (status) { 277 hw_err(hw, "semaphore failed with %d", status); 278 return; 279 } 280 281 /* Record completion for next time. */ 282 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 283 IXGBE_CS4227_RESET_COMPLETE); 284 285 out: 286 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 287 msleep(hw->eeprom.semaphore_delay); 288 } 289 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 291 * @hw: pointer to hardware structure 292 * 293 * Returns error code 294 */ 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 296 { 297 switch (hw->device_id) { 298 case IXGBE_DEV_ID_X550EM_A_SFP: 299 if (hw->bus.lan_id) 300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 301 else 302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 303 return ixgbe_identify_module_generic(hw); 304 case IXGBE_DEV_ID_X550EM_X_SFP: 305 /* set up for CS4227 usage */ 306 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 307 ixgbe_setup_mux_ctl(hw); 308 ixgbe_check_cs4227(hw); 309 /* Fallthrough */ 310 case IXGBE_DEV_ID_X550EM_A_SFP_N: 311 return ixgbe_identify_module_generic(hw); 312 case IXGBE_DEV_ID_X550EM_X_KX4: 313 hw->phy.type = ixgbe_phy_x550em_kx4; 314 break; 315 case IXGBE_DEV_ID_X550EM_X_XFI: 316 hw->phy.type = ixgbe_phy_x550em_xfi; 317 break; 318 case IXGBE_DEV_ID_X550EM_X_KR: 319 case IXGBE_DEV_ID_X550EM_A_KR: 320 case IXGBE_DEV_ID_X550EM_A_KR_L: 321 hw->phy.type = ixgbe_phy_x550em_kr; 322 break; 323 case IXGBE_DEV_ID_X550EM_A_10G_T: 324 if (hw->bus.lan_id) 325 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 326 else 327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 328 /* Fallthrough */ 329 case IXGBE_DEV_ID_X550EM_X_10G_T: 330 return ixgbe_identify_phy_generic(hw); 331 case IXGBE_DEV_ID_X550EM_X_1G_T: 332 hw->phy.type = ixgbe_phy_ext_1g_t; 333 break; 334 case IXGBE_DEV_ID_X550EM_A_1G_T: 335 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 336 hw->phy.type = ixgbe_phy_fw; 337 hw->phy.ops.read_reg = NULL; 338 hw->phy.ops.write_reg = NULL; 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 343 break; 344 default: 345 break; 346 } 347 return 0; 348 } 349 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 device_type, u16 *phy_data) 352 { 353 return IXGBE_NOT_IMPLEMENTED; 354 } 355 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 357 u32 device_type, u16 phy_data) 358 { 359 return IXGBE_NOT_IMPLEMENTED; 360 } 361 362 /** 363 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 364 * @hw: pointer to the hardware structure 365 * @addr: I2C bus address to read from 366 * @reg: I2C device register to read from 367 * @val: pointer to location to receive read value 368 * 369 * Returns an error code on error. 370 **/ 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 372 u16 reg, u16 *val) 373 { 374 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 375 } 376 377 /** 378 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 379 * @hw: pointer to the hardware structure 380 * @addr: I2C bus address to read from 381 * @reg: I2C device register to read from 382 * @val: pointer to location to receive read value 383 * 384 * Returns an error code on error. 385 **/ 386 static s32 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 388 u16 reg, u16 *val) 389 { 390 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 391 } 392 393 /** 394 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 395 * @hw: pointer to the hardware structure 396 * @addr: I2C bus address to write to 397 * @reg: I2C device register to write to 398 * @val: value to write 399 * 400 * Returns an error code on error. 401 **/ 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 403 u8 addr, u16 reg, u16 val) 404 { 405 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 406 } 407 408 /** 409 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 410 * @hw: pointer to the hardware structure 411 * @addr: I2C bus address to write to 412 * @reg: I2C device register to write to 413 * @val: value to write 414 * 415 * Returns an error code on error. 416 **/ 417 static s32 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 419 u8 addr, u16 reg, u16 val) 420 { 421 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 422 } 423 424 /** 425 * ixgbe_fw_phy_activity - Perform an activity on a PHY 426 * @hw: pointer to hardware structure 427 * @activity: activity to perform 428 * @data: Pointer to 4 32-bit words of data 429 */ 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 431 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 432 { 433 union { 434 struct ixgbe_hic_phy_activity_req cmd; 435 struct ixgbe_hic_phy_activity_resp rsp; 436 } hic; 437 u16 retries = FW_PHY_ACT_RETRIES; 438 s32 rc; 439 u32 i; 440 441 do { 442 memset(&hic, 0, sizeof(hic)); 443 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 444 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 445 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 446 hic.cmd.port_number = hw->bus.lan_id; 447 hic.cmd.activity_id = cpu_to_le16(activity); 448 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 449 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 450 451 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 452 IXGBE_HI_COMMAND_TIMEOUT, 453 true); 454 if (rc) 455 return rc; 456 if (hic.rsp.hdr.cmd_or_resp.ret_status == 457 FW_CEM_RESP_STATUS_SUCCESS) { 458 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 459 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 460 return 0; 461 } 462 usleep_range(20, 30); 463 --retries; 464 } while (retries > 0); 465 466 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 467 } 468 469 static const struct { 470 u16 fw_speed; 471 ixgbe_link_speed phy_speed; 472 } ixgbe_fw_map[] = { 473 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 474 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 475 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 476 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 477 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 478 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 479 }; 480 481 /** 482 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 483 * @hw: pointer to hardware structure 484 * 485 * Returns error code 486 */ 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 488 { 489 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 490 u16 phy_speeds; 491 u16 phy_id_lo; 492 s32 rc; 493 u16 i; 494 495 if (hw->phy.id) 496 return 0; 497 498 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 499 if (rc) 500 return rc; 501 502 hw->phy.speeds_supported = 0; 503 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 504 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 505 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 506 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 507 } 508 509 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 510 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 511 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 512 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 513 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 514 return IXGBE_ERR_PHY_ADDR_INVALID; 515 516 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 517 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 518 IXGBE_LINK_SPEED_1GB_FULL; 519 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 520 return 0; 521 } 522 523 /** 524 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 525 * @hw: pointer to hardware structure 526 * 527 * Returns error code 528 */ 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 530 { 531 if (hw->bus.lan_id) 532 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 533 else 534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 535 536 hw->phy.type = ixgbe_phy_fw; 537 hw->phy.ops.read_reg = NULL; 538 hw->phy.ops.write_reg = NULL; 539 return ixgbe_get_phy_id_fw(hw); 540 } 541 542 /** 543 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 544 * @hw: pointer to hardware structure 545 * 546 * Returns error code 547 */ 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 549 { 550 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 551 552 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 553 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 554 } 555 556 /** 557 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 558 * @hw: pointer to hardware structure 559 */ 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 561 { 562 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 563 s32 rc; 564 u16 i; 565 566 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 567 return 0; 568 569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 570 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 571 return IXGBE_ERR_INVALID_LINK_SETTINGS; 572 } 573 574 switch (hw->fc.requested_mode) { 575 case ixgbe_fc_full: 576 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 577 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 578 break; 579 case ixgbe_fc_rx_pause: 580 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 581 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 582 break; 583 case ixgbe_fc_tx_pause: 584 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 585 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 586 break; 587 default: 588 break; 589 } 590 591 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 592 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 593 setup[0] |= ixgbe_fw_map[i].fw_speed; 594 } 595 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 596 597 if (hw->phy.eee_speeds_advertised) 598 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 599 600 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 601 if (rc) 602 return rc; 603 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 604 return IXGBE_ERR_OVERTEMP; 605 return 0; 606 } 607 608 /** 609 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 610 * @hw: pointer to hardware structure 611 * 612 * Called at init time to set up flow control. 613 */ 614 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 615 { 616 if (hw->fc.requested_mode == ixgbe_fc_default) 617 hw->fc.requested_mode = ixgbe_fc_full; 618 619 return ixgbe_setup_fw_link(hw); 620 } 621 622 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 623 * @hw: pointer to hardware structure 624 * 625 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 626 * ixgbe_hw struct in order to set up EEPROM access. 627 **/ 628 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 629 { 630 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 631 u32 eec; 632 u16 eeprom_size; 633 634 if (eeprom->type == ixgbe_eeprom_uninitialized) { 635 eeprom->semaphore_delay = 10; 636 eeprom->type = ixgbe_flash; 637 638 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 639 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 640 IXGBE_EEC_SIZE_SHIFT); 641 eeprom->word_size = BIT(eeprom_size + 642 IXGBE_EEPROM_WORD_SIZE_SHIFT); 643 644 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 645 eeprom->type, eeprom->word_size); 646 } 647 648 return 0; 649 } 650 651 /** 652 * ixgbe_iosf_wait - Wait for IOSF command completion 653 * @hw: pointer to hardware structure 654 * @ctrl: pointer to location to receive final IOSF control value 655 * 656 * Return: failing status on timeout 657 * 658 * Note: ctrl can be NULL if the IOSF control register value is not needed 659 */ 660 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 661 { 662 u32 i, command; 663 664 /* Check every 10 usec to see if the address cycle completed. 665 * The SB IOSF BUSY bit will clear when the operation is 666 * complete. 667 */ 668 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 669 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 670 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 671 break; 672 udelay(10); 673 } 674 if (ctrl) 675 *ctrl = command; 676 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 677 hw_dbg(hw, "IOSF wait timed out\n"); 678 return IXGBE_ERR_PHY; 679 } 680 681 return 0; 682 } 683 684 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 685 * IOSF device 686 * @hw: pointer to hardware structure 687 * @reg_addr: 32 bit PHY register to write 688 * @device_type: 3 bit device type 689 * @phy_data: Pointer to read data from the register 690 **/ 691 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 692 u32 device_type, u32 *data) 693 { 694 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 695 u32 command, error; 696 s32 ret; 697 698 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 699 if (ret) 700 return ret; 701 702 ret = ixgbe_iosf_wait(hw, NULL); 703 if (ret) 704 goto out; 705 706 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 707 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 708 709 /* Write IOSF control register */ 710 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 711 712 ret = ixgbe_iosf_wait(hw, &command); 713 714 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 715 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 716 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 717 hw_dbg(hw, "Failed to read, error %x\n", error); 718 return IXGBE_ERR_PHY; 719 } 720 721 if (!ret) 722 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 723 724 out: 725 hw->mac.ops.release_swfw_sync(hw, gssr); 726 return ret; 727 } 728 729 /** 730 * ixgbe_get_phy_token - Get the token for shared PHY access 731 * @hw: Pointer to hardware structure 732 */ 733 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 734 { 735 struct ixgbe_hic_phy_token_req token_cmd; 736 s32 status; 737 738 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 739 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 740 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 741 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 742 token_cmd.port_number = hw->bus.lan_id; 743 token_cmd.command_type = FW_PHY_TOKEN_REQ; 744 token_cmd.pad = 0; 745 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 746 IXGBE_HI_COMMAND_TIMEOUT, 747 true); 748 if (status) 749 return status; 750 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 751 return 0; 752 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 753 return IXGBE_ERR_FW_RESP_INVALID; 754 755 return IXGBE_ERR_TOKEN_RETRY; 756 } 757 758 /** 759 * ixgbe_put_phy_token - Put the token for shared PHY access 760 * @hw: Pointer to hardware structure 761 */ 762 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 763 { 764 struct ixgbe_hic_phy_token_req token_cmd; 765 s32 status; 766 767 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 768 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 769 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 770 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 771 token_cmd.port_number = hw->bus.lan_id; 772 token_cmd.command_type = FW_PHY_TOKEN_REL; 773 token_cmd.pad = 0; 774 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 775 IXGBE_HI_COMMAND_TIMEOUT, 776 true); 777 if (status) 778 return status; 779 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 780 return 0; 781 return IXGBE_ERR_FW_RESP_INVALID; 782 } 783 784 /** 785 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 786 * @hw: pointer to hardware structure 787 * @reg_addr: 32 bit PHY register to write 788 * @device_type: 3 bit device type 789 * @data: Data to write to the register 790 **/ 791 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 792 __always_unused u32 device_type, 793 u32 data) 794 { 795 struct ixgbe_hic_internal_phy_req write_cmd; 796 797 memset(&write_cmd, 0, sizeof(write_cmd)); 798 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 799 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 800 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 801 write_cmd.port_number = hw->bus.lan_id; 802 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 803 write_cmd.address = cpu_to_be16(reg_addr); 804 write_cmd.write_data = cpu_to_be32(data); 805 806 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 807 IXGBE_HI_COMMAND_TIMEOUT, false); 808 } 809 810 /** 811 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 812 * @hw: pointer to hardware structure 813 * @reg_addr: 32 bit PHY register to write 814 * @device_type: 3 bit device type 815 * @data: Pointer to read data from the register 816 **/ 817 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 818 __always_unused u32 device_type, 819 u32 *data) 820 { 821 union { 822 struct ixgbe_hic_internal_phy_req cmd; 823 struct ixgbe_hic_internal_phy_resp rsp; 824 } hic; 825 s32 status; 826 827 memset(&hic, 0, sizeof(hic)); 828 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 829 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 830 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 831 hic.cmd.port_number = hw->bus.lan_id; 832 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 833 hic.cmd.address = cpu_to_be16(reg_addr); 834 835 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 836 IXGBE_HI_COMMAND_TIMEOUT, true); 837 838 /* Extract the register value from the response. */ 839 *data = be32_to_cpu(hic.rsp.read_data); 840 841 return status; 842 } 843 844 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 845 * @hw: pointer to hardware structure 846 * @offset: offset of word in the EEPROM to read 847 * @words: number of words 848 * @data: word(s) read from the EEPROM 849 * 850 * Reads a 16 bit word(s) from the EEPROM using the hostif. 851 **/ 852 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 853 u16 offset, u16 words, u16 *data) 854 { 855 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 856 struct ixgbe_hic_read_shadow_ram buffer; 857 u32 current_word = 0; 858 u16 words_to_read; 859 s32 status; 860 u32 i; 861 862 /* Take semaphore for the entire operation. */ 863 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 864 if (status) { 865 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 866 return status; 867 } 868 869 while (words) { 870 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 871 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 872 else 873 words_to_read = words; 874 875 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 876 buffer.hdr.req.buf_lenh = 0; 877 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 878 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 879 880 /* convert offset from words to bytes */ 881 buffer.address = cpu_to_be32((offset + current_word) * 2); 882 buffer.length = cpu_to_be16(words_to_read * 2); 883 buffer.pad2 = 0; 884 buffer.pad3 = 0; 885 886 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 887 IXGBE_HI_COMMAND_TIMEOUT); 888 if (status) { 889 hw_dbg(hw, "Host interface command failed\n"); 890 goto out; 891 } 892 893 for (i = 0; i < words_to_read; i++) { 894 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 895 2 * i; 896 u32 value = IXGBE_READ_REG(hw, reg); 897 898 data[current_word] = (u16)(value & 0xffff); 899 current_word++; 900 i++; 901 if (i < words_to_read) { 902 value >>= 16; 903 data[current_word] = (u16)(value & 0xffff); 904 current_word++; 905 } 906 } 907 words -= words_to_read; 908 } 909 910 out: 911 hw->mac.ops.release_swfw_sync(hw, mask); 912 return status; 913 } 914 915 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 916 * @hw: pointer to hardware structure 917 * @ptr: pointer offset in eeprom 918 * @size: size of section pointed by ptr, if 0 first word will be used as size 919 * @csum: address of checksum to update 920 * 921 * Returns error status for any failure 922 **/ 923 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 924 u16 size, u16 *csum, u16 *buffer, 925 u32 buffer_size) 926 { 927 u16 buf[256]; 928 s32 status; 929 u16 length, bufsz, i, start; 930 u16 *local_buffer; 931 932 bufsz = ARRAY_SIZE(buf); 933 934 /* Read a chunk at the pointer location */ 935 if (!buffer) { 936 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 937 if (status) { 938 hw_dbg(hw, "Failed to read EEPROM image\n"); 939 return status; 940 } 941 local_buffer = buf; 942 } else { 943 if (buffer_size < ptr) 944 return IXGBE_ERR_PARAM; 945 local_buffer = &buffer[ptr]; 946 } 947 948 if (size) { 949 start = 0; 950 length = size; 951 } else { 952 start = 1; 953 length = local_buffer[0]; 954 955 /* Skip pointer section if length is invalid. */ 956 if (length == 0xFFFF || length == 0 || 957 (ptr + length) >= hw->eeprom.word_size) 958 return 0; 959 } 960 961 if (buffer && ((u32)start + (u32)length > buffer_size)) 962 return IXGBE_ERR_PARAM; 963 964 for (i = start; length; i++, length--) { 965 if (i == bufsz && !buffer) { 966 ptr += bufsz; 967 i = 0; 968 if (length < bufsz) 969 bufsz = length; 970 971 /* Read a chunk at the pointer location */ 972 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 973 bufsz, buf); 974 if (status) { 975 hw_dbg(hw, "Failed to read EEPROM image\n"); 976 return status; 977 } 978 } 979 *csum += local_buffer[i]; 980 } 981 return 0; 982 } 983 984 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 985 * @hw: pointer to hardware structure 986 * @buffer: pointer to buffer containing calculated checksum 987 * @buffer_size: size of buffer 988 * 989 * Returns a negative error code on error, or the 16-bit checksum 990 **/ 991 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 992 u32 buffer_size) 993 { 994 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 995 u16 *local_buffer; 996 s32 status; 997 u16 checksum = 0; 998 u16 pointer, i, size; 999 1000 hw->eeprom.ops.init_params(hw); 1001 1002 if (!buffer) { 1003 /* Read pointer area */ 1004 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1005 IXGBE_EEPROM_LAST_WORD + 1, 1006 eeprom_ptrs); 1007 if (status) { 1008 hw_dbg(hw, "Failed to read EEPROM image\n"); 1009 return status; 1010 } 1011 local_buffer = eeprom_ptrs; 1012 } else { 1013 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1014 return IXGBE_ERR_PARAM; 1015 local_buffer = buffer; 1016 } 1017 1018 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1019 * checksum word itself 1020 */ 1021 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1022 if (i != IXGBE_EEPROM_CHECKSUM) 1023 checksum += local_buffer[i]; 1024 1025 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1026 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1027 */ 1028 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1029 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1030 continue; 1031 1032 pointer = local_buffer[i]; 1033 1034 /* Skip pointer section if the pointer is invalid. */ 1035 if (pointer == 0xFFFF || pointer == 0 || 1036 pointer >= hw->eeprom.word_size) 1037 continue; 1038 1039 switch (i) { 1040 case IXGBE_PCIE_GENERAL_PTR: 1041 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1042 break; 1043 case IXGBE_PCIE_CONFIG0_PTR: 1044 case IXGBE_PCIE_CONFIG1_PTR: 1045 size = IXGBE_PCIE_CONFIG_SIZE; 1046 break; 1047 default: 1048 size = 0; 1049 break; 1050 } 1051 1052 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1053 buffer, buffer_size); 1054 if (status) 1055 return status; 1056 } 1057 1058 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1059 1060 return (s32)checksum; 1061 } 1062 1063 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1064 * @hw: pointer to hardware structure 1065 * 1066 * Returns a negative error code on error, or the 16-bit checksum 1067 **/ 1068 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1069 { 1070 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1071 } 1072 1073 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1074 * @hw: pointer to hardware structure 1075 * @offset: offset of word in the EEPROM to read 1076 * @data: word read from the EEPROM 1077 * 1078 * Reads a 16 bit word from the EEPROM using the hostif. 1079 **/ 1080 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1081 { 1082 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1083 struct ixgbe_hic_read_shadow_ram buffer; 1084 s32 status; 1085 1086 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1087 buffer.hdr.req.buf_lenh = 0; 1088 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1089 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1090 1091 /* convert offset from words to bytes */ 1092 buffer.address = cpu_to_be32(offset * 2); 1093 /* one word */ 1094 buffer.length = cpu_to_be16(sizeof(u16)); 1095 1096 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1097 if (status) 1098 return status; 1099 1100 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1101 IXGBE_HI_COMMAND_TIMEOUT); 1102 if (!status) { 1103 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1104 FW_NVM_DATA_OFFSET); 1105 } 1106 1107 hw->mac.ops.release_swfw_sync(hw, mask); 1108 return status; 1109 } 1110 1111 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1112 * @hw: pointer to hardware structure 1113 * @checksum_val: calculated checksum 1114 * 1115 * Performs checksum calculation and validates the EEPROM checksum. If the 1116 * caller does not need checksum_val, the value can be NULL. 1117 **/ 1118 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1119 u16 *checksum_val) 1120 { 1121 s32 status; 1122 u16 checksum; 1123 u16 read_checksum = 0; 1124 1125 /* Read the first word from the EEPROM. If this times out or fails, do 1126 * not continue or we could be in for a very long wait while every 1127 * EEPROM read fails 1128 */ 1129 status = hw->eeprom.ops.read(hw, 0, &checksum); 1130 if (status) { 1131 hw_dbg(hw, "EEPROM read failed\n"); 1132 return status; 1133 } 1134 1135 status = hw->eeprom.ops.calc_checksum(hw); 1136 if (status < 0) 1137 return status; 1138 1139 checksum = (u16)(status & 0xffff); 1140 1141 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1142 &read_checksum); 1143 if (status) 1144 return status; 1145 1146 /* Verify read checksum from EEPROM is the same as 1147 * calculated checksum 1148 */ 1149 if (read_checksum != checksum) { 1150 status = IXGBE_ERR_EEPROM_CHECKSUM; 1151 hw_dbg(hw, "Invalid EEPROM checksum"); 1152 } 1153 1154 /* If the user cares, return the calculated checksum */ 1155 if (checksum_val) 1156 *checksum_val = checksum; 1157 1158 return status; 1159 } 1160 1161 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1162 * @hw: pointer to hardware structure 1163 * @offset: offset of word in the EEPROM to write 1164 * @data: word write to the EEPROM 1165 * 1166 * Write a 16 bit word to the EEPROM using the hostif. 1167 **/ 1168 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1169 u16 data) 1170 { 1171 s32 status; 1172 struct ixgbe_hic_write_shadow_ram buffer; 1173 1174 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1175 buffer.hdr.req.buf_lenh = 0; 1176 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1177 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1178 1179 /* one word */ 1180 buffer.length = cpu_to_be16(sizeof(u16)); 1181 buffer.data = data; 1182 buffer.address = cpu_to_be32(offset * 2); 1183 1184 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1185 IXGBE_HI_COMMAND_TIMEOUT, false); 1186 return status; 1187 } 1188 1189 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1190 * @hw: pointer to hardware structure 1191 * @offset: offset of word in the EEPROM to write 1192 * @data: word write to the EEPROM 1193 * 1194 * Write a 16 bit word to the EEPROM using the hostif. 1195 **/ 1196 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1197 { 1198 s32 status = 0; 1199 1200 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1201 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1202 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1203 } else { 1204 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1205 status = IXGBE_ERR_SWFW_SYNC; 1206 } 1207 1208 return status; 1209 } 1210 1211 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1212 * @hw: pointer to hardware structure 1213 * 1214 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1215 **/ 1216 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1217 { 1218 s32 status = 0; 1219 union ixgbe_hic_hdr2 buffer; 1220 1221 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1222 buffer.req.buf_lenh = 0; 1223 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1224 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1225 1226 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1227 IXGBE_HI_COMMAND_TIMEOUT, false); 1228 return status; 1229 } 1230 1231 /** 1232 * ixgbe_get_bus_info_X550em - Set PCI bus info 1233 * @hw: pointer to hardware structure 1234 * 1235 * Sets bus link width and speed to unknown because X550em is 1236 * not a PCI device. 1237 **/ 1238 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1239 { 1240 hw->bus.type = ixgbe_bus_type_internal; 1241 hw->bus.width = ixgbe_bus_width_unknown; 1242 hw->bus.speed = ixgbe_bus_speed_unknown; 1243 1244 hw->mac.ops.set_lan_id(hw); 1245 1246 return 0; 1247 } 1248 1249 /** ixgbe_disable_rx_x550 - Disable RX unit 1250 * 1251 * Enables the Rx DMA unit for x550 1252 **/ 1253 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1254 { 1255 u32 rxctrl, pfdtxgswc; 1256 s32 status; 1257 struct ixgbe_hic_disable_rxen fw_cmd; 1258 1259 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1260 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1261 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1262 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1263 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1264 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1265 hw->mac.set_lben = true; 1266 } else { 1267 hw->mac.set_lben = false; 1268 } 1269 1270 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1271 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1272 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1273 fw_cmd.port_number = hw->bus.lan_id; 1274 1275 status = ixgbe_host_interface_command(hw, &fw_cmd, 1276 sizeof(struct ixgbe_hic_disable_rxen), 1277 IXGBE_HI_COMMAND_TIMEOUT, true); 1278 1279 /* If we fail - disable RX using register write */ 1280 if (status) { 1281 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1282 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1283 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1284 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1285 } 1286 } 1287 } 1288 } 1289 1290 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1291 * @hw: pointer to hardware structure 1292 * 1293 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1294 * checksum and updates the EEPROM and instructs the hardware to update 1295 * the flash. 1296 **/ 1297 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1298 { 1299 s32 status; 1300 u16 checksum = 0; 1301 1302 /* Read the first word from the EEPROM. If this times out or fails, do 1303 * not continue or we could be in for a very long wait while every 1304 * EEPROM read fails 1305 */ 1306 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1307 if (status) { 1308 hw_dbg(hw, "EEPROM read failed\n"); 1309 return status; 1310 } 1311 1312 status = ixgbe_calc_eeprom_checksum_X550(hw); 1313 if (status < 0) 1314 return status; 1315 1316 checksum = (u16)(status & 0xffff); 1317 1318 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1319 checksum); 1320 if (status) 1321 return status; 1322 1323 status = ixgbe_update_flash_X550(hw); 1324 1325 return status; 1326 } 1327 1328 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1329 * @hw: pointer to hardware structure 1330 * @offset: offset of word in the EEPROM to write 1331 * @words: number of words 1332 * @data: word(s) write to the EEPROM 1333 * 1334 * 1335 * Write a 16 bit word(s) to the EEPROM using the hostif. 1336 **/ 1337 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1338 u16 offset, u16 words, 1339 u16 *data) 1340 { 1341 s32 status = 0; 1342 u32 i = 0; 1343 1344 /* Take semaphore for the entire operation. */ 1345 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1346 if (status) { 1347 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1348 return status; 1349 } 1350 1351 for (i = 0; i < words; i++) { 1352 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1353 data[i]); 1354 if (status) { 1355 hw_dbg(hw, "Eeprom buffered write failed\n"); 1356 break; 1357 } 1358 } 1359 1360 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1361 1362 return status; 1363 } 1364 1365 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1366 * IOSF device 1367 * 1368 * @hw: pointer to hardware structure 1369 * @reg_addr: 32 bit PHY register to write 1370 * @device_type: 3 bit device type 1371 * @data: Data to write to the register 1372 **/ 1373 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1374 u32 device_type, u32 data) 1375 { 1376 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1377 u32 command, error; 1378 s32 ret; 1379 1380 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1381 if (ret) 1382 return ret; 1383 1384 ret = ixgbe_iosf_wait(hw, NULL); 1385 if (ret) 1386 goto out; 1387 1388 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1389 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1390 1391 /* Write IOSF control register */ 1392 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1393 1394 /* Write IOSF data register */ 1395 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1396 1397 ret = ixgbe_iosf_wait(hw, &command); 1398 1399 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1400 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1401 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1402 hw_dbg(hw, "Failed to write, error %x\n", error); 1403 return IXGBE_ERR_PHY; 1404 } 1405 1406 out: 1407 hw->mac.ops.release_swfw_sync(hw, gssr); 1408 return ret; 1409 } 1410 1411 /** 1412 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1413 * @hw: pointer to hardware structure 1414 * 1415 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1416 **/ 1417 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1418 { 1419 s32 status; 1420 u32 reg_val; 1421 1422 /* Disable training protocol FSM. */ 1423 status = ixgbe_read_iosf_sb_reg_x550(hw, 1424 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1425 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1426 if (status) 1427 return status; 1428 1429 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1430 status = ixgbe_write_iosf_sb_reg_x550(hw, 1431 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1432 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1433 if (status) 1434 return status; 1435 1436 /* Disable Flex from training TXFFE. */ 1437 status = ixgbe_read_iosf_sb_reg_x550(hw, 1438 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1439 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1440 if (status) 1441 return status; 1442 1443 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1444 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1445 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1446 status = ixgbe_write_iosf_sb_reg_x550(hw, 1447 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1448 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1449 if (status) 1450 return status; 1451 1452 status = ixgbe_read_iosf_sb_reg_x550(hw, 1453 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1454 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1455 if (status) 1456 return status; 1457 1458 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1459 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1461 status = ixgbe_write_iosf_sb_reg_x550(hw, 1462 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1463 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1464 if (status) 1465 return status; 1466 1467 /* Enable override for coefficients. */ 1468 status = ixgbe_read_iosf_sb_reg_x550(hw, 1469 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1470 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1471 if (status) 1472 return status; 1473 1474 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1475 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1476 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1477 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1478 status = ixgbe_write_iosf_sb_reg_x550(hw, 1479 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1480 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1481 return status; 1482 } 1483 1484 /** 1485 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1486 * internal PHY 1487 * @hw: pointer to hardware structure 1488 **/ 1489 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1490 { 1491 s32 status; 1492 u32 link_ctrl; 1493 1494 /* Restart auto-negotiation. */ 1495 status = hw->mac.ops.read_iosf_sb_reg(hw, 1496 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1497 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1498 1499 if (status) { 1500 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1501 return status; 1502 } 1503 1504 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1505 status = hw->mac.ops.write_iosf_sb_reg(hw, 1506 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1507 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1508 1509 if (hw->mac.type == ixgbe_mac_x550em_a) { 1510 u32 flx_mask_st20; 1511 1512 /* Indicate to FW that AN restart has been asserted */ 1513 status = hw->mac.ops.read_iosf_sb_reg(hw, 1514 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1516 1517 if (status) { 1518 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1519 return status; 1520 } 1521 1522 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1523 status = hw->mac.ops.write_iosf_sb_reg(hw, 1524 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1525 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1526 } 1527 1528 return status; 1529 } 1530 1531 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1532 * @hw: pointer to hardware structure 1533 * @speed: the link speed to force 1534 * 1535 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1536 * internal and external PHY at a specific speed, without autonegotiation. 1537 **/ 1538 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1539 { 1540 struct ixgbe_mac_info *mac = &hw->mac; 1541 s32 status; 1542 u32 reg_val; 1543 1544 /* iXFI is only supported with X552 */ 1545 if (mac->type != ixgbe_mac_X550EM_x) 1546 return IXGBE_ERR_LINK_SETUP; 1547 1548 /* Disable AN and force speed to 10G Serial. */ 1549 status = ixgbe_read_iosf_sb_reg_x550(hw, 1550 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1551 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1552 if (status) 1553 return status; 1554 1555 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1556 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1557 1558 /* Select forced link speed for internal PHY. */ 1559 switch (*speed) { 1560 case IXGBE_LINK_SPEED_10GB_FULL: 1561 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1562 break; 1563 case IXGBE_LINK_SPEED_1GB_FULL: 1564 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1565 break; 1566 default: 1567 /* Other link speeds are not supported by internal KR PHY. */ 1568 return IXGBE_ERR_LINK_SETUP; 1569 } 1570 1571 status = ixgbe_write_iosf_sb_reg_x550(hw, 1572 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1573 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1574 if (status) 1575 return status; 1576 1577 /* Additional configuration needed for x550em_x */ 1578 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1579 status = ixgbe_setup_ixfi_x550em_x(hw); 1580 if (status) 1581 return status; 1582 } 1583 1584 /* Toggle port SW reset by AN reset. */ 1585 status = ixgbe_restart_an_internal_phy_x550em(hw); 1586 1587 return status; 1588 } 1589 1590 /** 1591 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1592 * @hw: pointer to hardware structure 1593 * @linear: true if SFP module is linear 1594 */ 1595 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1596 { 1597 switch (hw->phy.sfp_type) { 1598 case ixgbe_sfp_type_not_present: 1599 return IXGBE_ERR_SFP_NOT_PRESENT; 1600 case ixgbe_sfp_type_da_cu_core0: 1601 case ixgbe_sfp_type_da_cu_core1: 1602 *linear = true; 1603 break; 1604 case ixgbe_sfp_type_srlr_core0: 1605 case ixgbe_sfp_type_srlr_core1: 1606 case ixgbe_sfp_type_da_act_lmt_core0: 1607 case ixgbe_sfp_type_da_act_lmt_core1: 1608 case ixgbe_sfp_type_1g_sx_core0: 1609 case ixgbe_sfp_type_1g_sx_core1: 1610 case ixgbe_sfp_type_1g_lx_core0: 1611 case ixgbe_sfp_type_1g_lx_core1: 1612 *linear = false; 1613 break; 1614 case ixgbe_sfp_type_unknown: 1615 case ixgbe_sfp_type_1g_cu_core0: 1616 case ixgbe_sfp_type_1g_cu_core1: 1617 default: 1618 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1619 } 1620 1621 return 0; 1622 } 1623 1624 /** 1625 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1626 * @hw: pointer to hardware structure 1627 * @speed: the link speed to force 1628 * @autoneg_wait_to_complete: unused 1629 * 1630 * Configures the extern PHY and the integrated KR PHY for SFP support. 1631 */ 1632 static s32 1633 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1634 ixgbe_link_speed speed, 1635 __always_unused bool autoneg_wait_to_complete) 1636 { 1637 s32 status; 1638 u16 reg_slice, reg_val; 1639 bool setup_linear = false; 1640 1641 /* Check if SFP module is supported and linear */ 1642 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1643 1644 /* If no SFP module present, then return success. Return success since 1645 * there is no reason to configure CS4227 and SFP not present error is 1646 * not accepted in the setup MAC link flow. 1647 */ 1648 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1649 return 0; 1650 1651 if (status) 1652 return status; 1653 1654 /* Configure internal PHY for KR/KX. */ 1655 ixgbe_setup_kr_speed_x550em(hw, speed); 1656 1657 /* Configure CS4227 LINE side to proper mode. */ 1658 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1659 if (setup_linear) 1660 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1661 else 1662 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1663 1664 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1665 reg_val); 1666 1667 return status; 1668 } 1669 1670 /** 1671 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1672 * @hw: pointer to hardware structure 1673 * @speed: the link speed to force 1674 * 1675 * Configures the integrated PHY for native SFI mode. Used to connect the 1676 * internal PHY directly to an SFP cage, without autonegotiation. 1677 **/ 1678 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1679 { 1680 struct ixgbe_mac_info *mac = &hw->mac; 1681 s32 status; 1682 u32 reg_val; 1683 1684 /* Disable all AN and force speed to 10G Serial. */ 1685 status = mac->ops.read_iosf_sb_reg(hw, 1686 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1687 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1688 if (status) 1689 return status; 1690 1691 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1692 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1693 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1694 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1695 1696 /* Select forced link speed for internal PHY. */ 1697 switch (*speed) { 1698 case IXGBE_LINK_SPEED_10GB_FULL: 1699 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1700 break; 1701 case IXGBE_LINK_SPEED_1GB_FULL: 1702 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1703 break; 1704 default: 1705 /* Other link speeds are not supported by internal PHY. */ 1706 return IXGBE_ERR_LINK_SETUP; 1707 } 1708 1709 status = mac->ops.write_iosf_sb_reg(hw, 1710 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1711 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1712 1713 /* Toggle port SW reset by AN reset. */ 1714 status = ixgbe_restart_an_internal_phy_x550em(hw); 1715 1716 return status; 1717 } 1718 1719 /** 1720 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1721 * @hw: pointer to hardware structure 1722 * @speed: link speed 1723 * @autoneg_wait_to_complete: unused 1724 * 1725 * Configure the the integrated PHY for native SFP support. 1726 */ 1727 static s32 1728 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1729 __always_unused bool autoneg_wait_to_complete) 1730 { 1731 bool setup_linear = false; 1732 u32 reg_phy_int; 1733 s32 ret_val; 1734 1735 /* Check if SFP module is supported and linear */ 1736 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1737 1738 /* If no SFP module present, then return success. Return success since 1739 * SFP not present error is not excepted in the setup MAC link flow. 1740 */ 1741 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1742 return 0; 1743 1744 if (ret_val) 1745 return ret_val; 1746 1747 /* Configure internal PHY for native SFI based on module type */ 1748 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1749 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1750 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1751 if (ret_val) 1752 return ret_val; 1753 1754 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1755 if (!setup_linear) 1756 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1757 1758 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1759 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1760 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1761 if (ret_val) 1762 return ret_val; 1763 1764 /* Setup SFI internal link. */ 1765 return ixgbe_setup_sfi_x550a(hw, &speed); 1766 } 1767 1768 /** 1769 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1770 * @hw: pointer to hardware structure 1771 * @speed: link speed 1772 * @autoneg_wait_to_complete: unused 1773 * 1774 * Configure the the integrated PHY for SFP support. 1775 */ 1776 static s32 1777 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1778 __always_unused bool autoneg_wait_to_complete) 1779 { 1780 u32 reg_slice, slice_offset; 1781 bool setup_linear = false; 1782 u16 reg_phy_ext; 1783 s32 ret_val; 1784 1785 /* Check if SFP module is supported and linear */ 1786 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1787 1788 /* If no SFP module present, then return success. Return success since 1789 * SFP not present error is not excepted in the setup MAC link flow. 1790 */ 1791 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1792 return 0; 1793 1794 if (ret_val) 1795 return ret_val; 1796 1797 /* Configure internal PHY for KR/KX. */ 1798 ixgbe_setup_kr_speed_x550em(hw, speed); 1799 1800 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1801 return IXGBE_ERR_PHY_ADDR_INVALID; 1802 1803 /* Get external PHY SKU id */ 1804 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1805 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1806 if (ret_val) 1807 return ret_val; 1808 1809 /* When configuring quad port CS4223, the MAC instance is part 1810 * of the slice offset. 1811 */ 1812 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1813 slice_offset = (hw->bus.lan_id + 1814 (hw->bus.instance_id << 1)) << 12; 1815 else 1816 slice_offset = hw->bus.lan_id << 12; 1817 1818 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1819 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1820 1821 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1822 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1823 if (ret_val) 1824 return ret_val; 1825 1826 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1827 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1828 1829 if (setup_linear) 1830 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1831 else 1832 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1833 1834 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1835 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1836 if (ret_val) 1837 return ret_val; 1838 1839 /* Flush previous write with a read */ 1840 return hw->phy.ops.read_reg(hw, reg_slice, 1841 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1842 } 1843 1844 /** 1845 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1846 * @hw: pointer to hardware structure 1847 * @speed: new link speed 1848 * @autoneg_wait: true when waiting for completion is needed 1849 * 1850 * Setup internal/external PHY link speed based on link speed, then set 1851 * external PHY auto advertised link speed. 1852 * 1853 * Returns error status for any failure 1854 **/ 1855 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1856 ixgbe_link_speed speed, 1857 bool autoneg_wait) 1858 { 1859 s32 status; 1860 ixgbe_link_speed force_speed; 1861 1862 /* Setup internal/external PHY link speed to iXFI (10G), unless 1863 * only 1G is auto advertised then setup KX link. 1864 */ 1865 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1866 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1867 else 1868 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1869 1870 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1871 */ 1872 if (hw->mac.type == ixgbe_mac_X550EM_x && 1873 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1874 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1875 1876 if (status) 1877 return status; 1878 } 1879 1880 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1881 } 1882 1883 /** ixgbe_check_link_t_X550em - Determine link and speed status 1884 * @hw: pointer to hardware structure 1885 * @speed: pointer to link speed 1886 * @link_up: true when link is up 1887 * @link_up_wait_to_complete: bool used to wait for link up or not 1888 * 1889 * Check that both the MAC and X557 external PHY have link. 1890 **/ 1891 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1892 ixgbe_link_speed *speed, 1893 bool *link_up, 1894 bool link_up_wait_to_complete) 1895 { 1896 u32 status; 1897 u16 i, autoneg_status; 1898 1899 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1900 return IXGBE_ERR_CONFIG; 1901 1902 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1903 link_up_wait_to_complete); 1904 1905 /* If check link fails or MAC link is not up, then return */ 1906 if (status || !(*link_up)) 1907 return status; 1908 1909 /* MAC link is up, so check external PHY link. 1910 * Link status is latching low, and can only be used to detect link 1911 * drop, and not the current status of the link without performing 1912 * back-to-back reads. 1913 */ 1914 for (i = 0; i < 2; i++) { 1915 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1916 &autoneg_status); 1917 1918 if (status) 1919 return status; 1920 } 1921 1922 /* If external PHY link is not up, then indicate link not up */ 1923 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1924 *link_up = false; 1925 1926 return 0; 1927 } 1928 1929 /** 1930 * ixgbe_setup_sgmii - Set up link for sgmii 1931 * @hw: pointer to hardware structure 1932 * @speed: unused 1933 * @autoneg_wait_to_complete: unused 1934 */ 1935 static s32 1936 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1937 __always_unused bool autoneg_wait_to_complete) 1938 { 1939 struct ixgbe_mac_info *mac = &hw->mac; 1940 u32 lval, sval, flx_val; 1941 s32 rc; 1942 1943 rc = mac->ops.read_iosf_sb_reg(hw, 1944 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1945 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1946 if (rc) 1947 return rc; 1948 1949 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1950 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1951 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1952 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1953 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1954 rc = mac->ops.write_iosf_sb_reg(hw, 1955 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1956 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1957 if (rc) 1958 return rc; 1959 1960 rc = mac->ops.read_iosf_sb_reg(hw, 1961 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1962 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1963 if (rc) 1964 return rc; 1965 1966 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1967 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1968 rc = mac->ops.write_iosf_sb_reg(hw, 1969 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1970 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1971 if (rc) 1972 return rc; 1973 1974 rc = mac->ops.read_iosf_sb_reg(hw, 1975 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1976 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1977 if (rc) 1978 return rc; 1979 1980 rc = mac->ops.read_iosf_sb_reg(hw, 1981 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1982 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1983 if (rc) 1984 return rc; 1985 1986 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1987 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1988 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1989 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1990 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1991 1992 rc = mac->ops.write_iosf_sb_reg(hw, 1993 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1994 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1995 if (rc) 1996 return rc; 1997 1998 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1999 return rc; 2000 } 2001 2002 /** 2003 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2004 * @hw: pointer to hardware structure 2005 * @speed: the link speed to force 2006 * @autoneg_wait: true when waiting for completion is needed 2007 */ 2008 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2009 bool autoneg_wait) 2010 { 2011 struct ixgbe_mac_info *mac = &hw->mac; 2012 u32 lval, sval, flx_val; 2013 s32 rc; 2014 2015 rc = mac->ops.read_iosf_sb_reg(hw, 2016 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2017 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2018 if (rc) 2019 return rc; 2020 2021 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2022 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2023 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2024 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2025 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2026 rc = mac->ops.write_iosf_sb_reg(hw, 2027 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2028 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2029 if (rc) 2030 return rc; 2031 2032 rc = mac->ops.read_iosf_sb_reg(hw, 2033 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2034 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2035 if (rc) 2036 return rc; 2037 2038 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2039 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2040 rc = mac->ops.write_iosf_sb_reg(hw, 2041 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2042 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2043 if (rc) 2044 return rc; 2045 2046 rc = mac->ops.write_iosf_sb_reg(hw, 2047 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2048 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2049 if (rc) 2050 return rc; 2051 2052 rc = mac->ops.read_iosf_sb_reg(hw, 2053 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2054 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2055 if (rc) 2056 return rc; 2057 2058 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2059 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2060 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2061 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2062 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2063 2064 rc = mac->ops.write_iosf_sb_reg(hw, 2065 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2066 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2067 if (rc) 2068 return rc; 2069 2070 ixgbe_restart_an_internal_phy_x550em(hw); 2071 2072 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2073 } 2074 2075 /** 2076 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2077 * @hw: pointer to hardware structure 2078 * 2079 * Enable flow control according to IEEE clause 37. 2080 */ 2081 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2082 { 2083 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2084 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2085 ixgbe_link_speed speed; 2086 bool link_up; 2087 2088 /* AN should have completed when the cable was plugged in. 2089 * Look for reasons to bail out. Bail out if: 2090 * - FC autoneg is disabled, or if 2091 * - link is not up. 2092 */ 2093 if (hw->fc.disable_fc_autoneg) 2094 goto out; 2095 2096 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2097 if (!link_up) 2098 goto out; 2099 2100 /* Check if auto-negotiation has completed */ 2101 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2102 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2103 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2104 goto out; 2105 } 2106 2107 /* Negotiate the flow control */ 2108 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2109 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2110 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2111 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2112 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2113 2114 out: 2115 if (!status) { 2116 hw->fc.fc_was_autonegged = true; 2117 } else { 2118 hw->fc.fc_was_autonegged = false; 2119 hw->fc.current_mode = hw->fc.requested_mode; 2120 } 2121 } 2122 2123 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2124 * @hw: pointer to hardware structure 2125 **/ 2126 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2127 { 2128 struct ixgbe_mac_info *mac = &hw->mac; 2129 2130 switch (mac->ops.get_media_type(hw)) { 2131 case ixgbe_media_type_fiber: 2132 mac->ops.setup_fc = NULL; 2133 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2134 break; 2135 case ixgbe_media_type_copper: 2136 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2137 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2138 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2139 break; 2140 } 2141 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2142 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2143 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2144 mac->ops.check_link = ixgbe_check_mac_link_generic; 2145 break; 2146 case ixgbe_media_type_backplane: 2147 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2148 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2149 break; 2150 default: 2151 break; 2152 } 2153 } 2154 2155 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2156 * @hw: pointer to hardware structure 2157 **/ 2158 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2159 { 2160 struct ixgbe_mac_info *mac = &hw->mac; 2161 2162 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2163 2164 switch (mac->ops.get_media_type(hw)) { 2165 case ixgbe_media_type_fiber: 2166 /* CS4227 does not support autoneg, so disable the laser control 2167 * functions for SFP+ fiber 2168 */ 2169 mac->ops.disable_tx_laser = NULL; 2170 mac->ops.enable_tx_laser = NULL; 2171 mac->ops.flap_tx_laser = NULL; 2172 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2173 switch (hw->device_id) { 2174 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2175 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2176 break; 2177 case IXGBE_DEV_ID_X550EM_A_SFP: 2178 mac->ops.setup_mac_link = 2179 ixgbe_setup_mac_link_sfp_x550a; 2180 break; 2181 default: 2182 mac->ops.setup_mac_link = 2183 ixgbe_setup_mac_link_sfp_x550em; 2184 break; 2185 } 2186 mac->ops.set_rate_select_speed = 2187 ixgbe_set_soft_rate_select_speed; 2188 break; 2189 case ixgbe_media_type_copper: 2190 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2191 break; 2192 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2193 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2194 mac->ops.check_link = ixgbe_check_link_t_X550em; 2195 break; 2196 case ixgbe_media_type_backplane: 2197 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2198 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2199 mac->ops.setup_link = ixgbe_setup_sgmii; 2200 break; 2201 default: 2202 break; 2203 } 2204 2205 /* Additional modification for X550em_a devices */ 2206 if (hw->mac.type == ixgbe_mac_x550em_a) 2207 ixgbe_init_mac_link_ops_X550em_a(hw); 2208 } 2209 2210 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2211 * @hw: pointer to hardware structure 2212 */ 2213 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2214 { 2215 s32 status; 2216 bool linear; 2217 2218 /* Check if SFP module is supported */ 2219 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2220 if (status) 2221 return status; 2222 2223 ixgbe_init_mac_link_ops_X550em(hw); 2224 hw->phy.ops.reset = NULL; 2225 2226 return 0; 2227 } 2228 2229 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2230 * @hw: pointer to hardware structure 2231 * @speed: pointer to link speed 2232 * @autoneg: true when autoneg or autotry is enabled 2233 **/ 2234 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2235 ixgbe_link_speed *speed, 2236 bool *autoneg) 2237 { 2238 if (hw->phy.type == ixgbe_phy_fw) { 2239 *autoneg = true; 2240 *speed = hw->phy.speeds_supported; 2241 return 0; 2242 } 2243 2244 /* SFP */ 2245 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2246 /* CS4227 SFP must not enable auto-negotiation */ 2247 *autoneg = false; 2248 2249 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2250 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2251 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2252 return 0; 2253 } 2254 2255 /* Link capabilities are based on SFP */ 2256 if (hw->phy.multispeed_fiber) 2257 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2258 IXGBE_LINK_SPEED_1GB_FULL; 2259 else 2260 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2261 } else { 2262 switch (hw->phy.type) { 2263 case ixgbe_phy_x550em_kx4: 2264 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2265 IXGBE_LINK_SPEED_2_5GB_FULL | 2266 IXGBE_LINK_SPEED_10GB_FULL; 2267 break; 2268 case ixgbe_phy_x550em_xfi: 2269 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2270 IXGBE_LINK_SPEED_10GB_FULL; 2271 break; 2272 case ixgbe_phy_ext_1g_t: 2273 case ixgbe_phy_sgmii: 2274 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2275 break; 2276 case ixgbe_phy_x550em_kr: 2277 if (hw->mac.type == ixgbe_mac_x550em_a) { 2278 /* check different backplane modes */ 2279 if (hw->phy.nw_mng_if_sel & 2280 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2281 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2282 break; 2283 } else if (hw->device_id == 2284 IXGBE_DEV_ID_X550EM_A_KR_L) { 2285 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2286 break; 2287 } 2288 } 2289 /* fall through */ 2290 default: 2291 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2292 IXGBE_LINK_SPEED_1GB_FULL; 2293 break; 2294 } 2295 *autoneg = true; 2296 } 2297 return 0; 2298 } 2299 2300 /** 2301 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2302 * @hw: pointer to hardware structure 2303 * @lsc: pointer to boolean flag which indicates whether external Base T 2304 * PHY interrupt is lsc 2305 * 2306 * Determime if external Base T PHY interrupt cause is high temperature 2307 * failure alarm or link status change. 2308 * 2309 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2310 * failure alarm, else return PHY access status. 2311 **/ 2312 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2313 { 2314 u32 status; 2315 u16 reg; 2316 2317 *lsc = false; 2318 2319 /* Vendor alarm triggered */ 2320 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2321 MDIO_MMD_VEND1, 2322 ®); 2323 2324 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2325 return status; 2326 2327 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2328 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2329 MDIO_MMD_VEND1, 2330 ®); 2331 2332 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2333 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2334 return status; 2335 2336 /* Global alarm triggered */ 2337 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2338 MDIO_MMD_VEND1, 2339 ®); 2340 2341 if (status) 2342 return status; 2343 2344 /* If high temperature failure, then return over temp error and exit */ 2345 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2346 /* power down the PHY in case the PHY FW didn't already */ 2347 ixgbe_set_copper_phy_power(hw, false); 2348 return IXGBE_ERR_OVERTEMP; 2349 } 2350 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2351 /* device fault alarm triggered */ 2352 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2353 MDIO_MMD_VEND1, 2354 ®); 2355 if (status) 2356 return status; 2357 2358 /* if device fault was due to high temp alarm handle and exit */ 2359 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2360 /* power down the PHY in case the PHY FW didn't */ 2361 ixgbe_set_copper_phy_power(hw, false); 2362 return IXGBE_ERR_OVERTEMP; 2363 } 2364 } 2365 2366 /* Vendor alarm 2 triggered */ 2367 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2368 MDIO_MMD_AN, ®); 2369 2370 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2371 return status; 2372 2373 /* link connect/disconnect event occurred */ 2374 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2375 MDIO_MMD_AN, ®); 2376 2377 if (status) 2378 return status; 2379 2380 /* Indicate LSC */ 2381 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2382 *lsc = true; 2383 2384 return 0; 2385 } 2386 2387 /** 2388 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2389 * @hw: pointer to hardware structure 2390 * 2391 * Enable link status change and temperature failure alarm for the external 2392 * Base T PHY 2393 * 2394 * Returns PHY access status 2395 **/ 2396 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2397 { 2398 u32 status; 2399 u16 reg; 2400 bool lsc; 2401 2402 /* Clear interrupt flags */ 2403 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2404 2405 /* Enable link status change alarm */ 2406 2407 /* Enable the LASI interrupts on X552 devices to receive notifications 2408 * of the link configurations of the external PHY and correspondingly 2409 * support the configuration of the internal iXFI link, since iXFI does 2410 * not support auto-negotiation. This is not required for X553 devices 2411 * having KR support, which performs auto-negotiations and which is used 2412 * as the internal link to the external PHY. Hence adding a check here 2413 * to avoid enabling LASI interrupts for X553 devices. 2414 */ 2415 if (hw->mac.type != ixgbe_mac_x550em_a) { 2416 status = hw->phy.ops.read_reg(hw, 2417 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2418 MDIO_MMD_AN, ®); 2419 if (status) 2420 return status; 2421 2422 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2423 2424 status = hw->phy.ops.write_reg(hw, 2425 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2426 MDIO_MMD_AN, reg); 2427 if (status) 2428 return status; 2429 } 2430 2431 /* Enable high temperature failure and global fault alarms */ 2432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2433 MDIO_MMD_VEND1, 2434 ®); 2435 if (status) 2436 return status; 2437 2438 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2439 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2440 2441 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2442 MDIO_MMD_VEND1, 2443 reg); 2444 if (status) 2445 return status; 2446 2447 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2448 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2449 MDIO_MMD_VEND1, 2450 ®); 2451 if (status) 2452 return status; 2453 2454 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2455 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2456 2457 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2458 MDIO_MMD_VEND1, 2459 reg); 2460 if (status) 2461 return status; 2462 2463 /* Enable chip-wide vendor alarm */ 2464 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2465 MDIO_MMD_VEND1, 2466 ®); 2467 if (status) 2468 return status; 2469 2470 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2471 2472 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2473 MDIO_MMD_VEND1, 2474 reg); 2475 2476 return status; 2477 } 2478 2479 /** 2480 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2481 * @hw: pointer to hardware structure 2482 * 2483 * Handle external Base T PHY interrupt. If high temperature 2484 * failure alarm then return error, else if link status change 2485 * then setup internal/external PHY link 2486 * 2487 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2488 * failure alarm, else return PHY access status. 2489 **/ 2490 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2491 { 2492 struct ixgbe_phy_info *phy = &hw->phy; 2493 bool lsc; 2494 u32 status; 2495 2496 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2497 if (status) 2498 return status; 2499 2500 if (lsc && phy->ops.setup_internal_link) 2501 return phy->ops.setup_internal_link(hw); 2502 2503 return 0; 2504 } 2505 2506 /** 2507 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2508 * @hw: pointer to hardware structure 2509 * @speed: link speed 2510 * 2511 * Configures the integrated KR PHY. 2512 **/ 2513 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2514 ixgbe_link_speed speed) 2515 { 2516 s32 status; 2517 u32 reg_val; 2518 2519 status = hw->mac.ops.read_iosf_sb_reg(hw, 2520 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2521 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2522 if (status) 2523 return status; 2524 2525 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2526 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2527 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2528 2529 /* Advertise 10G support. */ 2530 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2531 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2532 2533 /* Advertise 1G support. */ 2534 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2535 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2536 2537 status = hw->mac.ops.write_iosf_sb_reg(hw, 2538 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2539 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2540 2541 if (hw->mac.type == ixgbe_mac_x550em_a) { 2542 /* Set lane mode to KR auto negotiation */ 2543 status = hw->mac.ops.read_iosf_sb_reg(hw, 2544 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2545 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2546 2547 if (status) 2548 return status; 2549 2550 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2551 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2552 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2553 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2554 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2555 2556 status = hw->mac.ops.write_iosf_sb_reg(hw, 2557 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2558 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2559 } 2560 2561 return ixgbe_restart_an_internal_phy_x550em(hw); 2562 } 2563 2564 /** 2565 * ixgbe_setup_kr_x550em - Configure the KR PHY 2566 * @hw: pointer to hardware structure 2567 **/ 2568 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2569 { 2570 /* leave link alone for 2.5G */ 2571 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2572 return 0; 2573 2574 if (ixgbe_check_reset_blocked(hw)) 2575 return 0; 2576 2577 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2578 } 2579 2580 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2581 * @hw: address of hardware structure 2582 * @link_up: address of boolean to indicate link status 2583 * 2584 * Returns error code if unable to get link status. 2585 **/ 2586 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2587 { 2588 u32 ret; 2589 u16 autoneg_status; 2590 2591 *link_up = false; 2592 2593 /* read this twice back to back to indicate current status */ 2594 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2595 &autoneg_status); 2596 if (ret) 2597 return ret; 2598 2599 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2600 &autoneg_status); 2601 if (ret) 2602 return ret; 2603 2604 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2605 2606 return 0; 2607 } 2608 2609 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2610 * @hw: point to hardware structure 2611 * 2612 * Configures the link between the integrated KR PHY and the external X557 PHY 2613 * The driver will call this function when it gets a link status change 2614 * interrupt from the X557 PHY. This function configures the link speed 2615 * between the PHYs to match the link speed of the BASE-T link. 2616 * 2617 * A return of a non-zero value indicates an error, and the base driver should 2618 * not report link up. 2619 **/ 2620 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2621 { 2622 ixgbe_link_speed force_speed; 2623 bool link_up; 2624 u32 status; 2625 u16 speed; 2626 2627 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2628 return IXGBE_ERR_CONFIG; 2629 2630 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2631 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2632 speed = IXGBE_LINK_SPEED_10GB_FULL | 2633 IXGBE_LINK_SPEED_1GB_FULL; 2634 return ixgbe_setup_kr_speed_x550em(hw, speed); 2635 } 2636 2637 /* If link is not up, then there is no setup necessary so return */ 2638 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2639 if (status) 2640 return status; 2641 2642 if (!link_up) 2643 return 0; 2644 2645 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2646 MDIO_MMD_AN, 2647 &speed); 2648 if (status) 2649 return status; 2650 2651 /* If link is not still up, then no setup is necessary so return */ 2652 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2653 if (status) 2654 return status; 2655 2656 if (!link_up) 2657 return 0; 2658 2659 /* clear everything but the speed and duplex bits */ 2660 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2661 2662 switch (speed) { 2663 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2664 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2665 break; 2666 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2667 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2668 break; 2669 default: 2670 /* Internal PHY does not support anything else */ 2671 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2672 } 2673 2674 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2675 } 2676 2677 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2678 * @hw: pointer to hardware structure 2679 **/ 2680 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2681 { 2682 s32 status; 2683 2684 status = ixgbe_reset_phy_generic(hw); 2685 2686 if (status) 2687 return status; 2688 2689 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2690 return ixgbe_enable_lasi_ext_t_x550em(hw); 2691 } 2692 2693 /** 2694 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2695 * @hw: pointer to hardware structure 2696 * @led_idx: led number to turn on 2697 **/ 2698 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2699 { 2700 u16 phy_data; 2701 2702 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2703 return IXGBE_ERR_PARAM; 2704 2705 /* To turn on the LED, set mode to ON. */ 2706 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2707 MDIO_MMD_VEND1, &phy_data); 2708 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2709 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2710 MDIO_MMD_VEND1, phy_data); 2711 2712 return 0; 2713 } 2714 2715 /** 2716 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2717 * @hw: pointer to hardware structure 2718 * @led_idx: led number to turn off 2719 **/ 2720 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2721 { 2722 u16 phy_data; 2723 2724 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2725 return IXGBE_ERR_PARAM; 2726 2727 /* To turn on the LED, set mode to ON. */ 2728 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2729 MDIO_MMD_VEND1, &phy_data); 2730 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2731 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2732 MDIO_MMD_VEND1, phy_data); 2733 2734 return 0; 2735 } 2736 2737 /** 2738 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2739 * @hw: pointer to the HW structure 2740 * @maj: driver version major number 2741 * @min: driver version minor number 2742 * @build: driver version build number 2743 * @sub: driver version sub build number 2744 * @len: length of driver_ver string 2745 * @driver_ver: driver string 2746 * 2747 * Sends driver version number to firmware through the manageability 2748 * block. On success return 0 2749 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2750 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2751 **/ 2752 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2753 u8 build, u8 sub, u16 len, 2754 const char *driver_ver) 2755 { 2756 struct ixgbe_hic_drv_info2 fw_cmd; 2757 s32 ret_val; 2758 int i; 2759 2760 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2761 return IXGBE_ERR_INVALID_ARGUMENT; 2762 2763 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2764 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2765 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2766 fw_cmd.port_num = (u8)hw->bus.func; 2767 fw_cmd.ver_maj = maj; 2768 fw_cmd.ver_min = min; 2769 fw_cmd.ver_build = build; 2770 fw_cmd.ver_sub = sub; 2771 fw_cmd.hdr.checksum = 0; 2772 memcpy(fw_cmd.driver_string, driver_ver, len); 2773 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2774 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2775 2776 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2777 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2778 sizeof(fw_cmd), 2779 IXGBE_HI_COMMAND_TIMEOUT, 2780 true); 2781 if (ret_val) 2782 continue; 2783 2784 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2785 FW_CEM_RESP_STATUS_SUCCESS) 2786 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2787 return 0; 2788 } 2789 2790 return ret_val; 2791 } 2792 2793 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2794 * @hw: pointer to hardware structure 2795 * @lcd_speed: pointer to lowest common link speed 2796 * 2797 * Determine lowest common link speed with link partner. 2798 **/ 2799 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2800 ixgbe_link_speed *lcd_speed) 2801 { 2802 u16 an_lp_status; 2803 s32 status; 2804 u16 word = hw->eeprom.ctrl_word_3; 2805 2806 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2807 2808 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2809 MDIO_MMD_AN, 2810 &an_lp_status); 2811 if (status) 2812 return status; 2813 2814 /* If link partner advertised 1G, return 1G */ 2815 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2816 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2817 return status; 2818 } 2819 2820 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2821 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2822 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2823 return status; 2824 2825 /* Link partner not capable of lower speeds, return 10G */ 2826 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2827 return status; 2828 } 2829 2830 /** 2831 * ixgbe_setup_fc_x550em - Set up flow control 2832 * @hw: pointer to hardware structure 2833 */ 2834 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2835 { 2836 bool pause, asm_dir; 2837 u32 reg_val; 2838 s32 rc = 0; 2839 2840 /* Validate the requested mode */ 2841 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2842 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2843 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2844 } 2845 2846 /* 10gig parts do not have a word in the EEPROM to determine the 2847 * default flow control setting, so we explicitly set it to full. 2848 */ 2849 if (hw->fc.requested_mode == ixgbe_fc_default) 2850 hw->fc.requested_mode = ixgbe_fc_full; 2851 2852 /* Determine PAUSE and ASM_DIR bits. */ 2853 switch (hw->fc.requested_mode) { 2854 case ixgbe_fc_none: 2855 pause = false; 2856 asm_dir = false; 2857 break; 2858 case ixgbe_fc_tx_pause: 2859 pause = false; 2860 asm_dir = true; 2861 break; 2862 case ixgbe_fc_rx_pause: 2863 /* Rx Flow control is enabled and Tx Flow control is 2864 * disabled by software override. Since there really 2865 * isn't a way to advertise that we are capable of RX 2866 * Pause ONLY, we will advertise that we support both 2867 * symmetric and asymmetric Rx PAUSE, as such we fall 2868 * through to the fc_full statement. Later, we will 2869 * disable the adapter's ability to send PAUSE frames. 2870 */ 2871 /* Fallthrough */ 2872 case ixgbe_fc_full: 2873 pause = true; 2874 asm_dir = true; 2875 break; 2876 default: 2877 hw_err(hw, "Flow control param set incorrectly\n"); 2878 return IXGBE_ERR_CONFIG; 2879 } 2880 2881 switch (hw->device_id) { 2882 case IXGBE_DEV_ID_X550EM_X_KR: 2883 case IXGBE_DEV_ID_X550EM_A_KR: 2884 case IXGBE_DEV_ID_X550EM_A_KR_L: 2885 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2886 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2887 IXGBE_SB_IOSF_TARGET_KR_PHY, 2888 ®_val); 2889 if (rc) 2890 return rc; 2891 2892 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2893 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2894 if (pause) 2895 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2896 if (asm_dir) 2897 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2898 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2899 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2900 IXGBE_SB_IOSF_TARGET_KR_PHY, 2901 reg_val); 2902 2903 /* This device does not fully support AN. */ 2904 hw->fc.disable_fc_autoneg = true; 2905 break; 2906 case IXGBE_DEV_ID_X550EM_X_XFI: 2907 hw->fc.disable_fc_autoneg = true; 2908 break; 2909 default: 2910 break; 2911 } 2912 return rc; 2913 } 2914 2915 /** 2916 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2917 * @hw: pointer to hardware structure 2918 **/ 2919 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2920 { 2921 u32 link_s1, lp_an_page_low, an_cntl_1; 2922 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2923 ixgbe_link_speed speed; 2924 bool link_up; 2925 2926 /* AN should have completed when the cable was plugged in. 2927 * Look for reasons to bail out. Bail out if: 2928 * - FC autoneg is disabled, or if 2929 * - link is not up. 2930 */ 2931 if (hw->fc.disable_fc_autoneg) { 2932 hw_err(hw, "Flow control autoneg is disabled"); 2933 goto out; 2934 } 2935 2936 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2937 if (!link_up) { 2938 hw_err(hw, "The link is down"); 2939 goto out; 2940 } 2941 2942 /* Check at auto-negotiation has completed */ 2943 status = hw->mac.ops.read_iosf_sb_reg(hw, 2944 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2945 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2946 2947 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2948 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2949 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2950 goto out; 2951 } 2952 2953 /* Read the 10g AN autoc and LP ability registers and resolve 2954 * local flow control settings accordingly 2955 */ 2956 status = hw->mac.ops.read_iosf_sb_reg(hw, 2957 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2958 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2959 2960 if (status) { 2961 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2962 goto out; 2963 } 2964 2965 status = hw->mac.ops.read_iosf_sb_reg(hw, 2966 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2967 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2968 2969 if (status) { 2970 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2971 goto out; 2972 } 2973 2974 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2975 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2976 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2977 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2978 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2979 2980 out: 2981 if (!status) { 2982 hw->fc.fc_was_autonegged = true; 2983 } else { 2984 hw->fc.fc_was_autonegged = false; 2985 hw->fc.current_mode = hw->fc.requested_mode; 2986 } 2987 } 2988 2989 /** 2990 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 2991 * @hw: pointer to hardware structure 2992 **/ 2993 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 2994 { 2995 hw->fc.fc_was_autonegged = false; 2996 hw->fc.current_mode = hw->fc.requested_mode; 2997 } 2998 2999 /** ixgbe_enter_lplu_x550em - Transition to low power states 3000 * @hw: pointer to hardware structure 3001 * 3002 * Configures Low Power Link Up on transition to low power states 3003 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3004 * the X557 PHY immediately prior to entering LPLU. 3005 **/ 3006 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3007 { 3008 u16 an_10g_cntl_reg, autoneg_reg, speed; 3009 s32 status; 3010 ixgbe_link_speed lcd_speed; 3011 u32 save_autoneg; 3012 bool link_up; 3013 3014 /* If blocked by MNG FW, then don't restart AN */ 3015 if (ixgbe_check_reset_blocked(hw)) 3016 return 0; 3017 3018 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3019 if (status) 3020 return status; 3021 3022 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3023 &hw->eeprom.ctrl_word_3); 3024 if (status) 3025 return status; 3026 3027 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3028 * manageability disabled, then force link down by entering 3029 * low power mode. 3030 */ 3031 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3032 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3033 return ixgbe_set_copper_phy_power(hw, false); 3034 3035 /* Determine LCD */ 3036 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3037 if (status) 3038 return status; 3039 3040 /* If no valid LCD link speed, then force link down and exit. */ 3041 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3042 return ixgbe_set_copper_phy_power(hw, false); 3043 3044 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3045 MDIO_MMD_AN, 3046 &speed); 3047 if (status) 3048 return status; 3049 3050 /* If no link now, speed is invalid so take link down */ 3051 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3052 if (status) 3053 return ixgbe_set_copper_phy_power(hw, false); 3054 3055 /* clear everything but the speed bits */ 3056 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3057 3058 /* If current speed is already LCD, then exit. */ 3059 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3060 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3061 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3062 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3063 return status; 3064 3065 /* Clear AN completed indication */ 3066 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3067 MDIO_MMD_AN, 3068 &autoneg_reg); 3069 if (status) 3070 return status; 3071 3072 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3073 MDIO_MMD_AN, 3074 &an_10g_cntl_reg); 3075 if (status) 3076 return status; 3077 3078 status = hw->phy.ops.read_reg(hw, 3079 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3080 MDIO_MMD_AN, 3081 &autoneg_reg); 3082 if (status) 3083 return status; 3084 3085 save_autoneg = hw->phy.autoneg_advertised; 3086 3087 /* Setup link at least common link speed */ 3088 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3089 3090 /* restore autoneg from before setting lplu speed */ 3091 hw->phy.autoneg_advertised = save_autoneg; 3092 3093 return status; 3094 } 3095 3096 /** 3097 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3098 * @hw: pointer to hardware structure 3099 */ 3100 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3101 { 3102 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3103 s32 rc; 3104 3105 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3106 return 0; 3107 3108 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3109 if (rc) 3110 return rc; 3111 memset(store, 0, sizeof(store)); 3112 3113 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3114 if (rc) 3115 return rc; 3116 3117 return ixgbe_setup_fw_link(hw); 3118 } 3119 3120 /** 3121 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3122 * @hw: pointer to hardware structure 3123 */ 3124 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3125 { 3126 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3127 s32 rc; 3128 3129 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3130 if (rc) 3131 return rc; 3132 3133 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3134 ixgbe_shutdown_fw_phy(hw); 3135 return IXGBE_ERR_OVERTEMP; 3136 } 3137 return 0; 3138 } 3139 3140 /** 3141 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3142 * @hw: pointer to hardware structure 3143 * 3144 * Read NW_MNG_IF_SEL register and save field values. 3145 */ 3146 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3147 { 3148 /* Save NW management interface connected on board. This is used 3149 * to determine internal PHY mode. 3150 */ 3151 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3152 3153 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3154 * PHY address. This register field was has only been used for X552. 3155 */ 3156 if (hw->mac.type == ixgbe_mac_x550em_a && 3157 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3158 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3159 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3160 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3161 } 3162 } 3163 3164 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3165 * @hw: pointer to hardware structure 3166 * 3167 * Initialize any function pointers that were not able to be 3168 * set during init_shared_code because the PHY/SFP type was 3169 * not known. Perform the SFP init if necessary. 3170 **/ 3171 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3172 { 3173 struct ixgbe_phy_info *phy = &hw->phy; 3174 s32 ret_val; 3175 3176 hw->mac.ops.set_lan_id(hw); 3177 3178 ixgbe_read_mng_if_sel_x550em(hw); 3179 3180 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3181 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3182 ixgbe_setup_mux_ctl(hw); 3183 } 3184 3185 /* Identify the PHY or SFP module */ 3186 ret_val = phy->ops.identify(hw); 3187 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 3188 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 3189 return ret_val; 3190 3191 /* Setup function pointers based on detected hardware */ 3192 ixgbe_init_mac_link_ops_X550em(hw); 3193 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3194 phy->ops.reset = NULL; 3195 3196 /* Set functions pointers based on phy type */ 3197 switch (hw->phy.type) { 3198 case ixgbe_phy_x550em_kx4: 3199 phy->ops.setup_link = NULL; 3200 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3201 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3202 break; 3203 case ixgbe_phy_x550em_kr: 3204 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3205 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3206 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3207 break; 3208 case ixgbe_phy_x550em_xfi: 3209 /* link is managed by HW */ 3210 phy->ops.setup_link = NULL; 3211 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3212 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3213 break; 3214 case ixgbe_phy_x550em_ext_t: 3215 /* Save NW management interface connected on board. This is used 3216 * to determine internal PHY mode 3217 */ 3218 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3219 3220 /* If internal link mode is XFI, then setup iXFI internal link, 3221 * else setup KR now. 3222 */ 3223 phy->ops.setup_internal_link = 3224 ixgbe_setup_internal_phy_t_x550em; 3225 3226 /* setup SW LPLU only for first revision */ 3227 if (hw->mac.type == ixgbe_mac_X550EM_x && 3228 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3229 IXGBE_FUSES0_REV_MASK)) 3230 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3231 3232 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3233 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3234 break; 3235 case ixgbe_phy_sgmii: 3236 phy->ops.setup_link = NULL; 3237 break; 3238 case ixgbe_phy_fw: 3239 phy->ops.setup_link = ixgbe_setup_fw_link; 3240 phy->ops.reset = ixgbe_reset_phy_fw; 3241 break; 3242 case ixgbe_phy_ext_1g_t: 3243 phy->ops.setup_link = NULL; 3244 phy->ops.read_reg = NULL; 3245 phy->ops.write_reg = NULL; 3246 phy->ops.reset = NULL; 3247 break; 3248 default: 3249 break; 3250 } 3251 3252 return ret_val; 3253 } 3254 3255 /** ixgbe_get_media_type_X550em - Get media type 3256 * @hw: pointer to hardware structure 3257 * 3258 * Returns the media type (fiber, copper, backplane) 3259 * 3260 */ 3261 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3262 { 3263 enum ixgbe_media_type media_type; 3264 3265 /* Detect if there is a copper PHY attached. */ 3266 switch (hw->device_id) { 3267 case IXGBE_DEV_ID_X550EM_A_SGMII: 3268 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3269 hw->phy.type = ixgbe_phy_sgmii; 3270 /* Fallthrough */ 3271 case IXGBE_DEV_ID_X550EM_X_KR: 3272 case IXGBE_DEV_ID_X550EM_X_KX4: 3273 case IXGBE_DEV_ID_X550EM_X_XFI: 3274 case IXGBE_DEV_ID_X550EM_A_KR: 3275 case IXGBE_DEV_ID_X550EM_A_KR_L: 3276 media_type = ixgbe_media_type_backplane; 3277 break; 3278 case IXGBE_DEV_ID_X550EM_X_SFP: 3279 case IXGBE_DEV_ID_X550EM_A_SFP: 3280 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3281 media_type = ixgbe_media_type_fiber; 3282 break; 3283 case IXGBE_DEV_ID_X550EM_X_1G_T: 3284 case IXGBE_DEV_ID_X550EM_X_10G_T: 3285 case IXGBE_DEV_ID_X550EM_A_10G_T: 3286 case IXGBE_DEV_ID_X550EM_A_1G_T: 3287 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3288 media_type = ixgbe_media_type_copper; 3289 break; 3290 default: 3291 media_type = ixgbe_media_type_unknown; 3292 break; 3293 } 3294 return media_type; 3295 } 3296 3297 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3298 ** @hw: pointer to hardware structure 3299 **/ 3300 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3301 { 3302 s32 status; 3303 u16 reg; 3304 3305 status = hw->phy.ops.read_reg(hw, 3306 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3307 MDIO_MMD_PMAPMD, 3308 ®); 3309 if (status) 3310 return status; 3311 3312 /* If PHY FW reset completed bit is set then this is the first 3313 * SW instance after a power on so the PHY FW must be un-stalled. 3314 */ 3315 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3316 status = hw->phy.ops.read_reg(hw, 3317 IXGBE_MDIO_GLOBAL_RES_PR_10, 3318 MDIO_MMD_VEND1, 3319 ®); 3320 if (status) 3321 return status; 3322 3323 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3324 3325 status = hw->phy.ops.write_reg(hw, 3326 IXGBE_MDIO_GLOBAL_RES_PR_10, 3327 MDIO_MMD_VEND1, 3328 reg); 3329 if (status) 3330 return status; 3331 } 3332 3333 return status; 3334 } 3335 3336 /** 3337 * ixgbe_set_mdio_speed - Set MDIO clock speed 3338 * @hw: pointer to hardware structure 3339 */ 3340 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3341 { 3342 u32 hlreg0; 3343 3344 switch (hw->device_id) { 3345 case IXGBE_DEV_ID_X550EM_X_10G_T: 3346 case IXGBE_DEV_ID_X550EM_A_SGMII: 3347 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3348 case IXGBE_DEV_ID_X550EM_A_10G_T: 3349 case IXGBE_DEV_ID_X550EM_A_SFP: 3350 /* Config MDIO clock speed before the first MDIO PHY access */ 3351 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3352 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3353 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3354 break; 3355 case IXGBE_DEV_ID_X550EM_A_1G_T: 3356 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3357 /* Select fast MDIO clock speed for these devices */ 3358 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3359 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3360 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3361 break; 3362 default: 3363 break; 3364 } 3365 } 3366 3367 /** ixgbe_reset_hw_X550em - Perform hardware reset 3368 ** @hw: pointer to hardware structure 3369 ** 3370 ** Resets the hardware by resetting the transmit and receive units, masks 3371 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3372 ** reset. 3373 **/ 3374 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3375 { 3376 ixgbe_link_speed link_speed; 3377 s32 status; 3378 u32 ctrl = 0; 3379 u32 i; 3380 bool link_up = false; 3381 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3382 3383 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3384 status = hw->mac.ops.stop_adapter(hw); 3385 if (status) 3386 return status; 3387 3388 /* flush pending Tx transactions */ 3389 ixgbe_clear_tx_pending(hw); 3390 3391 /* PHY ops must be identified and initialized prior to reset */ 3392 status = hw->phy.ops.init(hw); 3393 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 3394 status == IXGBE_ERR_PHY_ADDR_INVALID) 3395 return status; 3396 3397 /* start the external PHY */ 3398 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3399 status = ixgbe_init_ext_t_x550em(hw); 3400 if (status) 3401 return status; 3402 } 3403 3404 /* Setup SFP module if there is one present. */ 3405 if (hw->phy.sfp_setup_needed) { 3406 status = hw->mac.ops.setup_sfp(hw); 3407 hw->phy.sfp_setup_needed = false; 3408 } 3409 3410 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 3411 return status; 3412 3413 /* Reset PHY */ 3414 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3415 hw->phy.ops.reset(hw); 3416 3417 mac_reset_top: 3418 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3419 * If link reset is used when link is up, it might reset the PHY when 3420 * mng is using it. If link is down or the flag to force full link 3421 * reset is set, then perform link reset. 3422 */ 3423 ctrl = IXGBE_CTRL_LNK_RST; 3424 3425 if (!hw->force_full_reset) { 3426 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3427 if (link_up) 3428 ctrl = IXGBE_CTRL_RST; 3429 } 3430 3431 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3432 if (status) { 3433 hw_dbg(hw, "semaphore failed with %d", status); 3434 return IXGBE_ERR_SWFW_SYNC; 3435 } 3436 3437 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3438 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3439 IXGBE_WRITE_FLUSH(hw); 3440 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3441 usleep_range(1000, 1200); 3442 3443 /* Poll for reset bit to self-clear meaning reset is complete */ 3444 for (i = 0; i < 10; i++) { 3445 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3446 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3447 break; 3448 udelay(1); 3449 } 3450 3451 if (ctrl & IXGBE_CTRL_RST_MASK) { 3452 status = IXGBE_ERR_RESET_FAILED; 3453 hw_dbg(hw, "Reset polling failed to complete.\n"); 3454 } 3455 3456 msleep(50); 3457 3458 /* Double resets are required for recovery from certain error 3459 * clear the multicast table. Also reset num_rar_entries to 128, 3460 * since we modify this value when programming the SAN MAC address. 3461 */ 3462 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3463 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3464 goto mac_reset_top; 3465 } 3466 3467 /* Store the permanent mac address */ 3468 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3469 3470 /* Store MAC address from RAR0, clear receive address registers, and 3471 * clear the multicast table. Also reset num_rar_entries to 128, 3472 * since we modify this value when programming the SAN MAC address. 3473 */ 3474 hw->mac.num_rar_entries = 128; 3475 hw->mac.ops.init_rx_addrs(hw); 3476 3477 ixgbe_set_mdio_speed(hw); 3478 3479 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3480 ixgbe_setup_mux_ctl(hw); 3481 3482 return status; 3483 } 3484 3485 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3486 * anti-spoofing 3487 * @hw: pointer to hardware structure 3488 * @enable: enable or disable switch for Ethertype anti-spoofing 3489 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3490 **/ 3491 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3492 bool enable, int vf) 3493 { 3494 int vf_target_reg = vf >> 3; 3495 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3496 u32 pfvfspoof; 3497 3498 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3499 if (enable) 3500 pfvfspoof |= BIT(vf_target_shift); 3501 else 3502 pfvfspoof &= ~BIT(vf_target_shift); 3503 3504 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3505 } 3506 3507 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3508 * @hw: pointer to hardware structure 3509 * @enable: enable or disable source address pruning 3510 * @pool: Rx pool to set source address pruning for 3511 **/ 3512 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3513 bool enable, 3514 unsigned int pool) 3515 { 3516 u64 pfflp; 3517 3518 /* max rx pool is 63 */ 3519 if (pool > 63) 3520 return; 3521 3522 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3523 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3524 3525 if (enable) 3526 pfflp |= (1ULL << pool); 3527 else 3528 pfflp &= ~(1ULL << pool); 3529 3530 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3531 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3532 } 3533 3534 /** 3535 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3536 * @hw: pointer to hardware structure 3537 * 3538 * Called at init time to set up flow control. 3539 **/ 3540 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3541 { 3542 s32 status = 0; 3543 u32 an_cntl = 0; 3544 3545 /* Validate the requested mode */ 3546 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3547 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3548 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3549 } 3550 3551 if (hw->fc.requested_mode == ixgbe_fc_default) 3552 hw->fc.requested_mode = ixgbe_fc_full; 3553 3554 /* Set up the 1G and 10G flow control advertisement registers so the 3555 * HW will be able to do FC autoneg once the cable is plugged in. If 3556 * we link at 10G, the 1G advertisement is harmless and vice versa. 3557 */ 3558 status = hw->mac.ops.read_iosf_sb_reg(hw, 3559 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3560 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3561 3562 if (status) { 3563 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3564 return status; 3565 } 3566 3567 /* The possible values of fc.requested_mode are: 3568 * 0: Flow control is completely disabled 3569 * 1: Rx flow control is enabled (we can receive pause frames, 3570 * but not send pause frames). 3571 * 2: Tx flow control is enabled (we can send pause frames but 3572 * we do not support receiving pause frames). 3573 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3574 * other: Invalid. 3575 */ 3576 switch (hw->fc.requested_mode) { 3577 case ixgbe_fc_none: 3578 /* Flow control completely disabled by software override. */ 3579 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3580 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3581 break; 3582 case ixgbe_fc_tx_pause: 3583 /* Tx Flow control is enabled, and Rx Flow control is 3584 * disabled by software override. 3585 */ 3586 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3587 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3588 break; 3589 case ixgbe_fc_rx_pause: 3590 /* Rx Flow control is enabled and Tx Flow control is 3591 * disabled by software override. Since there really 3592 * isn't a way to advertise that we are capable of RX 3593 * Pause ONLY, we will advertise that we support both 3594 * symmetric and asymmetric Rx PAUSE, as such we fall 3595 * through to the fc_full statement. Later, we will 3596 * disable the adapter's ability to send PAUSE frames. 3597 */ 3598 case ixgbe_fc_full: 3599 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3600 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3601 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3602 break; 3603 default: 3604 hw_err(hw, "Flow control param set incorrectly\n"); 3605 return IXGBE_ERR_CONFIG; 3606 } 3607 3608 status = hw->mac.ops.write_iosf_sb_reg(hw, 3609 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3610 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3611 3612 /* Restart auto-negotiation. */ 3613 status = ixgbe_restart_an_internal_phy_x550em(hw); 3614 3615 return status; 3616 } 3617 3618 /** 3619 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3620 * @hw: pointer to hardware structure 3621 * @state: set mux if 1, clear if 0 3622 */ 3623 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3624 { 3625 u32 esdp; 3626 3627 if (!hw->bus.lan_id) 3628 return; 3629 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3630 if (state) 3631 esdp |= IXGBE_ESDP_SDP1; 3632 else 3633 esdp &= ~IXGBE_ESDP_SDP1; 3634 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3635 IXGBE_WRITE_FLUSH(hw); 3636 } 3637 3638 /** 3639 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3640 * @hw: pointer to hardware structure 3641 * @mask: Mask to specify which semaphore to acquire 3642 * 3643 * Acquires the SWFW semaphore and sets the I2C MUX 3644 */ 3645 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3646 { 3647 s32 status; 3648 3649 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3650 if (status) 3651 return status; 3652 3653 if (mask & IXGBE_GSSR_I2C_MASK) 3654 ixgbe_set_mux(hw, 1); 3655 3656 return 0; 3657 } 3658 3659 /** 3660 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3661 * @hw: pointer to hardware structure 3662 * @mask: Mask to specify which semaphore to release 3663 * 3664 * Releases the SWFW semaphore and sets the I2C MUX 3665 */ 3666 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3667 { 3668 if (mask & IXGBE_GSSR_I2C_MASK) 3669 ixgbe_set_mux(hw, 0); 3670 3671 ixgbe_release_swfw_sync_X540(hw, mask); 3672 } 3673 3674 /** 3675 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3676 * @hw: pointer to hardware structure 3677 * @mask: Mask to specify which semaphore to acquire 3678 * 3679 * Acquires the SWFW semaphore and get the shared PHY token as needed 3680 */ 3681 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3682 { 3683 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3684 int retries = FW_PHY_TOKEN_RETRIES; 3685 s32 status; 3686 3687 while (--retries) { 3688 status = 0; 3689 if (hmask) 3690 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3691 if (status) 3692 return status; 3693 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3694 return 0; 3695 3696 status = ixgbe_get_phy_token(hw); 3697 if (!status) 3698 return 0; 3699 if (hmask) 3700 ixgbe_release_swfw_sync_X540(hw, hmask); 3701 if (status != IXGBE_ERR_TOKEN_RETRY) 3702 return status; 3703 msleep(FW_PHY_TOKEN_DELAY); 3704 } 3705 3706 return status; 3707 } 3708 3709 /** 3710 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3711 * @hw: pointer to hardware structure 3712 * @mask: Mask to specify which semaphore to release 3713 * 3714 * Release the SWFW semaphore and puts the shared PHY token as needed 3715 */ 3716 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3717 { 3718 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3719 3720 if (mask & IXGBE_GSSR_TOKEN_SM) 3721 ixgbe_put_phy_token(hw); 3722 3723 if (hmask) 3724 ixgbe_release_swfw_sync_X540(hw, hmask); 3725 } 3726 3727 /** 3728 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3729 * @hw: pointer to hardware structure 3730 * @reg_addr: 32 bit address of PHY register to read 3731 * @device_type: 5 bit device type 3732 * @phy_data: Pointer to read data from PHY register 3733 * 3734 * Reads a value from a specified PHY register using the SWFW lock and PHY 3735 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3736 * instances. 3737 */ 3738 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3739 u32 device_type, u16 *phy_data) 3740 { 3741 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3742 s32 status; 3743 3744 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3745 return IXGBE_ERR_SWFW_SYNC; 3746 3747 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3748 3749 hw->mac.ops.release_swfw_sync(hw, mask); 3750 3751 return status; 3752 } 3753 3754 /** 3755 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3756 * @hw: pointer to hardware structure 3757 * @reg_addr: 32 bit PHY register to write 3758 * @device_type: 5 bit device type 3759 * @phy_data: Data to write to the PHY register 3760 * 3761 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3762 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3763 */ 3764 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3765 u32 device_type, u16 phy_data) 3766 { 3767 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3768 s32 status; 3769 3770 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3771 return IXGBE_ERR_SWFW_SYNC; 3772 3773 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3774 hw->mac.ops.release_swfw_sync(hw, mask); 3775 3776 return status; 3777 } 3778 3779 #define X550_COMMON_MAC \ 3780 .init_hw = &ixgbe_init_hw_generic, \ 3781 .start_hw = &ixgbe_start_hw_X540, \ 3782 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3783 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3784 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3785 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3786 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3787 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3788 .read_analog_reg8 = NULL, \ 3789 .write_analog_reg8 = NULL, \ 3790 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3791 .check_link = &ixgbe_check_mac_link_generic, \ 3792 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3793 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3794 .set_rar = &ixgbe_set_rar_generic, \ 3795 .clear_rar = &ixgbe_clear_rar_generic, \ 3796 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3797 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3798 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3799 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3800 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3801 .enable_mc = &ixgbe_enable_mc_generic, \ 3802 .disable_mc = &ixgbe_disable_mc_generic, \ 3803 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3804 .set_vfta = &ixgbe_set_vfta_generic, \ 3805 .fc_enable = &ixgbe_fc_enable_generic, \ 3806 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3807 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3808 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3809 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3810 .set_source_address_pruning = \ 3811 &ixgbe_set_source_address_pruning_X550, \ 3812 .set_ethertype_anti_spoofing = \ 3813 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3814 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3815 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3816 .get_thermal_sensor_data = NULL, \ 3817 .init_thermal_sensor_thresh = NULL, \ 3818 .enable_rx = &ixgbe_enable_rx_generic, \ 3819 .disable_rx = &ixgbe_disable_rx_x550, \ 3820 3821 static const struct ixgbe_mac_operations mac_ops_X550 = { 3822 X550_COMMON_MAC 3823 .led_on = ixgbe_led_on_generic, 3824 .led_off = ixgbe_led_off_generic, 3825 .init_led_link_act = ixgbe_init_led_link_act_generic, 3826 .reset_hw = &ixgbe_reset_hw_X540, 3827 .get_media_type = &ixgbe_get_media_type_X540, 3828 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3829 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3830 .setup_link = &ixgbe_setup_mac_link_X540, 3831 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3832 .get_bus_info = &ixgbe_get_bus_info_generic, 3833 .setup_sfp = NULL, 3834 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3835 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3836 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3837 .prot_autoc_read = prot_autoc_read_generic, 3838 .prot_autoc_write = prot_autoc_write_generic, 3839 .setup_fc = ixgbe_setup_fc_generic, 3840 .fc_autoneg = ixgbe_fc_autoneg, 3841 }; 3842 3843 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3844 X550_COMMON_MAC 3845 .led_on = ixgbe_led_on_t_x550em, 3846 .led_off = ixgbe_led_off_t_x550em, 3847 .init_led_link_act = ixgbe_init_led_link_act_generic, 3848 .reset_hw = &ixgbe_reset_hw_X550em, 3849 .get_media_type = &ixgbe_get_media_type_X550em, 3850 .get_san_mac_addr = NULL, 3851 .get_wwn_prefix = NULL, 3852 .setup_link = &ixgbe_setup_mac_link_X540, 3853 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3854 .get_bus_info = &ixgbe_get_bus_info_X550em, 3855 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3856 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3857 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3858 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3859 .setup_fc = NULL, /* defined later */ 3860 .fc_autoneg = ixgbe_fc_autoneg, 3861 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3862 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3863 }; 3864 3865 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3866 X550_COMMON_MAC 3867 .led_on = NULL, 3868 .led_off = NULL, 3869 .init_led_link_act = NULL, 3870 .reset_hw = &ixgbe_reset_hw_X550em, 3871 .get_media_type = &ixgbe_get_media_type_X550em, 3872 .get_san_mac_addr = NULL, 3873 .get_wwn_prefix = NULL, 3874 .setup_link = &ixgbe_setup_mac_link_X540, 3875 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3876 .get_bus_info = &ixgbe_get_bus_info_X550em, 3877 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3878 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3879 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3880 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3881 .setup_fc = NULL, 3882 .fc_autoneg = ixgbe_fc_autoneg, 3883 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3884 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3885 }; 3886 3887 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3888 X550_COMMON_MAC 3889 .led_on = ixgbe_led_on_t_x550em, 3890 .led_off = ixgbe_led_off_t_x550em, 3891 .init_led_link_act = ixgbe_init_led_link_act_generic, 3892 .reset_hw = ixgbe_reset_hw_X550em, 3893 .get_media_type = ixgbe_get_media_type_X550em, 3894 .get_san_mac_addr = NULL, 3895 .get_wwn_prefix = NULL, 3896 .setup_link = &ixgbe_setup_mac_link_X540, 3897 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3898 .get_bus_info = ixgbe_get_bus_info_X550em, 3899 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3900 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3901 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3902 .setup_fc = ixgbe_setup_fc_x550em, 3903 .fc_autoneg = ixgbe_fc_autoneg, 3904 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3905 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3906 }; 3907 3908 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3909 X550_COMMON_MAC 3910 .led_on = ixgbe_led_on_generic, 3911 .led_off = ixgbe_led_off_generic, 3912 .init_led_link_act = ixgbe_init_led_link_act_generic, 3913 .reset_hw = ixgbe_reset_hw_X550em, 3914 .get_media_type = ixgbe_get_media_type_X550em, 3915 .get_san_mac_addr = NULL, 3916 .get_wwn_prefix = NULL, 3917 .setup_link = NULL, /* defined later */ 3918 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3919 .get_bus_info = ixgbe_get_bus_info_X550em, 3920 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3921 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3922 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3923 .setup_fc = ixgbe_setup_fc_x550em, 3924 .fc_autoneg = ixgbe_fc_autoneg, 3925 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3926 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3927 }; 3928 3929 #define X550_COMMON_EEP \ 3930 .read = &ixgbe_read_ee_hostif_X550, \ 3931 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3932 .write = &ixgbe_write_ee_hostif_X550, \ 3933 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3934 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3935 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3936 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3937 3938 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3939 X550_COMMON_EEP 3940 .init_params = &ixgbe_init_eeprom_params_X550, 3941 }; 3942 3943 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3944 X550_COMMON_EEP 3945 .init_params = &ixgbe_init_eeprom_params_X540, 3946 }; 3947 3948 #define X550_COMMON_PHY \ 3949 .identify_sfp = &ixgbe_identify_module_generic, \ 3950 .reset = NULL, \ 3951 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3952 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3953 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3954 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3955 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3956 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3957 .setup_link = &ixgbe_setup_phy_link_generic, \ 3958 .set_phy_power = NULL, 3959 3960 static const struct ixgbe_phy_operations phy_ops_X550 = { 3961 X550_COMMON_PHY 3962 .check_overtemp = &ixgbe_tn_check_overtemp, 3963 .init = NULL, 3964 .identify = &ixgbe_identify_phy_generic, 3965 .read_reg = &ixgbe_read_phy_reg_generic, 3966 .write_reg = &ixgbe_write_phy_reg_generic, 3967 }; 3968 3969 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3970 X550_COMMON_PHY 3971 .check_overtemp = &ixgbe_tn_check_overtemp, 3972 .init = &ixgbe_init_phy_ops_X550em, 3973 .identify = &ixgbe_identify_phy_x550em, 3974 .read_reg = &ixgbe_read_phy_reg_generic, 3975 .write_reg = &ixgbe_write_phy_reg_generic, 3976 }; 3977 3978 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3979 X550_COMMON_PHY 3980 .check_overtemp = NULL, 3981 .init = ixgbe_init_phy_ops_X550em, 3982 .identify = ixgbe_identify_phy_x550em, 3983 .read_reg = NULL, 3984 .write_reg = NULL, 3985 .read_reg_mdi = NULL, 3986 .write_reg_mdi = NULL, 3987 }; 3988 3989 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3990 X550_COMMON_PHY 3991 .check_overtemp = &ixgbe_tn_check_overtemp, 3992 .init = &ixgbe_init_phy_ops_X550em, 3993 .identify = &ixgbe_identify_phy_x550em, 3994 .read_reg = &ixgbe_read_phy_reg_x550a, 3995 .write_reg = &ixgbe_write_phy_reg_x550a, 3996 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 3997 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 3998 }; 3999 4000 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4001 X550_COMMON_PHY 4002 .check_overtemp = ixgbe_check_overtemp_fw, 4003 .init = ixgbe_init_phy_ops_X550em, 4004 .identify = ixgbe_identify_phy_fw, 4005 .read_reg = NULL, 4006 .write_reg = NULL, 4007 .read_reg_mdi = NULL, 4008 .write_reg_mdi = NULL, 4009 }; 4010 4011 static const struct ixgbe_link_operations link_ops_x550em_x = { 4012 .read_link = &ixgbe_read_i2c_combined_generic, 4013 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4014 .write_link = &ixgbe_write_i2c_combined_generic, 4015 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4016 }; 4017 4018 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4019 IXGBE_MVALS_INIT(X550) 4020 }; 4021 4022 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4023 IXGBE_MVALS_INIT(X550EM_x) 4024 }; 4025 4026 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4027 IXGBE_MVALS_INIT(X550EM_a) 4028 }; 4029 4030 const struct ixgbe_info ixgbe_X550_info = { 4031 .mac = ixgbe_mac_X550, 4032 .get_invariants = &ixgbe_get_invariants_X540, 4033 .mac_ops = &mac_ops_X550, 4034 .eeprom_ops = &eeprom_ops_X550, 4035 .phy_ops = &phy_ops_X550, 4036 .mbx_ops = &mbx_ops_generic, 4037 .mvals = ixgbe_mvals_X550, 4038 }; 4039 4040 const struct ixgbe_info ixgbe_X550EM_x_info = { 4041 .mac = ixgbe_mac_X550EM_x, 4042 .get_invariants = &ixgbe_get_invariants_X550_x, 4043 .mac_ops = &mac_ops_X550EM_x, 4044 .eeprom_ops = &eeprom_ops_X550EM_x, 4045 .phy_ops = &phy_ops_X550EM_x, 4046 .mbx_ops = &mbx_ops_generic, 4047 .mvals = ixgbe_mvals_X550EM_x, 4048 .link_ops = &link_ops_x550em_x, 4049 }; 4050 4051 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4052 .mac = ixgbe_mac_X550EM_x, 4053 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4054 .mac_ops = &mac_ops_X550EM_x_fw, 4055 .eeprom_ops = &eeprom_ops_X550EM_x, 4056 .phy_ops = &phy_ops_x550em_x_fw, 4057 .mbx_ops = &mbx_ops_generic, 4058 .mvals = ixgbe_mvals_X550EM_x, 4059 }; 4060 4061 const struct ixgbe_info ixgbe_x550em_a_info = { 4062 .mac = ixgbe_mac_x550em_a, 4063 .get_invariants = &ixgbe_get_invariants_X550_a, 4064 .mac_ops = &mac_ops_x550em_a, 4065 .eeprom_ops = &eeprom_ops_X550EM_x, 4066 .phy_ops = &phy_ops_x550em_a, 4067 .mbx_ops = &mbx_ops_generic, 4068 .mvals = ixgbe_mvals_x550em_a, 4069 }; 4070 4071 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4072 .mac = ixgbe_mac_x550em_a, 4073 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4074 .mac_ops = &mac_ops_x550em_a_fw, 4075 .eeprom_ops = &eeprom_ops_X550EM_x, 4076 .phy_ops = &phy_ops_x550em_a_fw, 4077 .mbx_ops = &mbx_ops_generic, 4078 .mvals = ixgbe_mvals_x550em_a, 4079 }; 4080