1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include "ixgbe_x540.h" 5 #include "ixgbe_type.h" 6 #include "ixgbe_common.h" 7 #include "ixgbe_phy.h" 8 9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 14 15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 16 { 17 struct ixgbe_mac_info *mac = &hw->mac; 18 struct ixgbe_phy_info *phy = &hw->phy; 19 struct ixgbe_link_info *link = &hw->link; 20 21 /* Start with X540 invariants, since so simular */ 22 ixgbe_get_invariants_X540(hw); 23 24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 25 phy->ops.set_phy_power = NULL; 26 27 link->addr = IXGBE_CS4227; 28 29 return 0; 30 } 31 32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 33 { 34 struct ixgbe_phy_info *phy = &hw->phy; 35 36 /* Start with X540 invariants, since so similar */ 37 ixgbe_get_invariants_X540(hw); 38 39 phy->ops.set_phy_power = NULL; 40 41 return 0; 42 } 43 44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 45 { 46 struct ixgbe_mac_info *mac = &hw->mac; 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* Start with X540 invariants, since so simular */ 50 ixgbe_get_invariants_X540(hw); 51 52 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 53 phy->ops.set_phy_power = NULL; 54 55 return 0; 56 } 57 58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* Start with X540 invariants, since so similar */ 63 ixgbe_get_invariants_X540(hw); 64 65 phy->ops.set_phy_power = NULL; 66 67 return 0; 68 } 69 70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 71 * @hw: pointer to hardware structure 72 **/ 73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 74 { 75 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 76 77 if (hw->bus.lan_id) { 78 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 79 esdp |= IXGBE_ESDP_SDP1_DIR; 80 } 81 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 82 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 83 IXGBE_WRITE_FLUSH(hw); 84 } 85 86 /** 87 * ixgbe_read_cs4227 - Read CS4227 register 88 * @hw: pointer to hardware structure 89 * @reg: register number to write 90 * @value: pointer to receive value read 91 * 92 * Returns status code 93 */ 94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 95 { 96 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 97 } 98 99 /** 100 * ixgbe_write_cs4227 - Write CS4227 register 101 * @hw: pointer to hardware structure 102 * @reg: register number to write 103 * @value: value to write to register 104 * 105 * Returns status code 106 */ 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 108 { 109 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 110 } 111 112 /** 113 * ixgbe_read_pe - Read register from port expander 114 * @hw: pointer to hardware structure 115 * @reg: register number to read 116 * @value: pointer to receive read value 117 * 118 * Returns status code 119 */ 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 121 { 122 s32 status; 123 124 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 125 if (status) 126 hw_err(hw, "port expander access failed with %d\n", status); 127 return status; 128 } 129 130 /** 131 * ixgbe_write_pe - Write register to port expander 132 * @hw: pointer to hardware structure 133 * @reg: register number to write 134 * @value: value to write 135 * 136 * Returns status code 137 */ 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 139 { 140 s32 status; 141 142 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 143 value); 144 if (status) 145 hw_err(hw, "port expander access failed with %d\n", status); 146 return status; 147 } 148 149 /** 150 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 151 * @hw: pointer to hardware structure 152 * 153 * This function assumes that the caller has acquired the proper semaphore. 154 * Returns error code 155 */ 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 157 { 158 s32 status; 159 u32 retry; 160 u16 value; 161 u8 reg; 162 163 /* Trigger hard reset. */ 164 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 165 if (status) 166 return status; 167 reg |= IXGBE_PE_BIT1; 168 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 169 if (status) 170 return status; 171 172 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 173 if (status) 174 return status; 175 reg &= ~IXGBE_PE_BIT1; 176 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 177 if (status) 178 return status; 179 180 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 181 if (status) 182 return status; 183 reg &= ~IXGBE_PE_BIT1; 184 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 185 if (status) 186 return status; 187 188 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 189 190 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 191 if (status) 192 return status; 193 reg |= IXGBE_PE_BIT1; 194 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 195 if (status) 196 return status; 197 198 /* Wait for the reset to complete. */ 199 msleep(IXGBE_CS4227_RESET_DELAY); 200 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 201 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 202 &value); 203 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 204 break; 205 msleep(IXGBE_CS4227_CHECK_DELAY); 206 } 207 if (retry == IXGBE_CS4227_RETRIES) { 208 hw_err(hw, "CS4227 reset did not complete\n"); 209 return -EIO; 210 } 211 212 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 213 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 214 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 215 return -EIO; 216 } 217 218 return 0; 219 } 220 221 /** 222 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 223 * @hw: pointer to hardware structure 224 */ 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 226 { 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 s32 status; 229 u16 value; 230 u8 retry; 231 232 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 234 if (status) { 235 hw_err(hw, "semaphore failed with %d\n", status); 236 msleep(IXGBE_CS4227_CHECK_DELAY); 237 continue; 238 } 239 240 /* Get status of reset flow. */ 241 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 242 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 243 goto out; 244 245 if (status || value != IXGBE_CS4227_RESET_PENDING) 246 break; 247 248 /* Reset is pending. Wait and check again. */ 249 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 250 msleep(IXGBE_CS4227_CHECK_DELAY); 251 } 252 /* If still pending, assume other instance failed. */ 253 if (retry == IXGBE_CS4227_RETRIES) { 254 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 255 if (status) { 256 hw_err(hw, "semaphore failed with %d\n", status); 257 return; 258 } 259 } 260 261 /* Reset the CS4227. */ 262 status = ixgbe_reset_cs4227(hw); 263 if (status) { 264 hw_err(hw, "CS4227 reset failed: %d", status); 265 goto out; 266 } 267 268 /* Reset takes so long, temporarily release semaphore in case the 269 * other driver instance is waiting for the reset indication. 270 */ 271 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 272 IXGBE_CS4227_RESET_PENDING); 273 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 274 usleep_range(10000, 12000); 275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 276 if (status) { 277 hw_err(hw, "semaphore failed with %d", status); 278 return; 279 } 280 281 /* Record completion for next time. */ 282 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 283 IXGBE_CS4227_RESET_COMPLETE); 284 285 out: 286 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 287 msleep(hw->eeprom.semaphore_delay); 288 } 289 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 291 * @hw: pointer to hardware structure 292 * 293 * Returns error code 294 */ 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 296 { 297 switch (hw->device_id) { 298 case IXGBE_DEV_ID_X550EM_A_SFP: 299 if (hw->bus.lan_id) 300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 301 else 302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 303 return ixgbe_identify_module_generic(hw); 304 case IXGBE_DEV_ID_X550EM_X_SFP: 305 /* set up for CS4227 usage */ 306 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 307 ixgbe_setup_mux_ctl(hw); 308 ixgbe_check_cs4227(hw); 309 fallthrough; 310 case IXGBE_DEV_ID_X550EM_A_SFP_N: 311 return ixgbe_identify_module_generic(hw); 312 case IXGBE_DEV_ID_X550EM_X_KX4: 313 hw->phy.type = ixgbe_phy_x550em_kx4; 314 break; 315 case IXGBE_DEV_ID_X550EM_X_XFI: 316 hw->phy.type = ixgbe_phy_x550em_xfi; 317 break; 318 case IXGBE_DEV_ID_X550EM_X_KR: 319 case IXGBE_DEV_ID_X550EM_A_KR: 320 case IXGBE_DEV_ID_X550EM_A_KR_L: 321 hw->phy.type = ixgbe_phy_x550em_kr; 322 break; 323 case IXGBE_DEV_ID_X550EM_A_10G_T: 324 if (hw->bus.lan_id) 325 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 326 else 327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 328 fallthrough; 329 case IXGBE_DEV_ID_X550EM_X_10G_T: 330 return ixgbe_identify_phy_generic(hw); 331 case IXGBE_DEV_ID_X550EM_X_1G_T: 332 hw->phy.type = ixgbe_phy_ext_1g_t; 333 break; 334 case IXGBE_DEV_ID_X550EM_A_1G_T: 335 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 336 hw->phy.type = ixgbe_phy_fw; 337 hw->phy.ops.read_reg = NULL; 338 hw->phy.ops.write_reg = NULL; 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 343 break; 344 default: 345 break; 346 } 347 return 0; 348 } 349 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 device_type, u16 *phy_data) 352 { 353 return -EOPNOTSUPP; 354 } 355 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 357 u32 device_type, u16 phy_data) 358 { 359 return -EOPNOTSUPP; 360 } 361 362 /** 363 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 364 * @hw: pointer to the hardware structure 365 * @addr: I2C bus address to read from 366 * @reg: I2C device register to read from 367 * @val: pointer to location to receive read value 368 * 369 * Returns an error code on error. 370 **/ 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 372 u16 reg, u16 *val) 373 { 374 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 375 } 376 377 /** 378 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 379 * @hw: pointer to the hardware structure 380 * @addr: I2C bus address to read from 381 * @reg: I2C device register to read from 382 * @val: pointer to location to receive read value 383 * 384 * Returns an error code on error. 385 **/ 386 static s32 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 388 u16 reg, u16 *val) 389 { 390 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 391 } 392 393 /** 394 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 395 * @hw: pointer to the hardware structure 396 * @addr: I2C bus address to write to 397 * @reg: I2C device register to write to 398 * @val: value to write 399 * 400 * Returns an error code on error. 401 **/ 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 403 u8 addr, u16 reg, u16 val) 404 { 405 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 406 } 407 408 /** 409 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 410 * @hw: pointer to the hardware structure 411 * @addr: I2C bus address to write to 412 * @reg: I2C device register to write to 413 * @val: value to write 414 * 415 * Returns an error code on error. 416 **/ 417 static s32 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 419 u8 addr, u16 reg, u16 val) 420 { 421 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 422 } 423 424 /** 425 * ixgbe_fw_phy_activity - Perform an activity on a PHY 426 * @hw: pointer to hardware structure 427 * @activity: activity to perform 428 * @data: Pointer to 4 32-bit words of data 429 */ 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 431 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 432 { 433 union { 434 struct ixgbe_hic_phy_activity_req cmd; 435 struct ixgbe_hic_phy_activity_resp rsp; 436 } hic; 437 u16 retries = FW_PHY_ACT_RETRIES; 438 s32 rc; 439 u32 i; 440 441 do { 442 memset(&hic, 0, sizeof(hic)); 443 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 444 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 445 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 446 hic.cmd.port_number = hw->bus.lan_id; 447 hic.cmd.activity_id = cpu_to_le16(activity); 448 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 449 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 450 451 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 452 IXGBE_HI_COMMAND_TIMEOUT, 453 true); 454 if (rc) 455 return rc; 456 if (hic.rsp.hdr.cmd_or_resp.ret_status == 457 FW_CEM_RESP_STATUS_SUCCESS) { 458 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 459 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 460 return 0; 461 } 462 usleep_range(20, 30); 463 --retries; 464 } while (retries > 0); 465 466 return -EIO; 467 } 468 469 static const struct { 470 u16 fw_speed; 471 ixgbe_link_speed phy_speed; 472 } ixgbe_fw_map[] = { 473 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 474 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 475 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 476 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 477 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 478 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 479 }; 480 481 /** 482 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 483 * @hw: pointer to hardware structure 484 * 485 * Returns error code 486 */ 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 488 { 489 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 490 u16 phy_speeds; 491 u16 phy_id_lo; 492 s32 rc; 493 u16 i; 494 495 if (hw->phy.id) 496 return 0; 497 498 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 499 if (rc) 500 return rc; 501 502 hw->phy.speeds_supported = 0; 503 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 504 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 505 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 506 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 507 } 508 509 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 510 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 511 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 512 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 513 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 514 return -EFAULT; 515 516 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 517 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 518 IXGBE_LINK_SPEED_1GB_FULL; 519 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 520 return 0; 521 } 522 523 /** 524 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 525 * @hw: pointer to hardware structure 526 * 527 * Returns error code 528 */ 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 530 { 531 if (hw->bus.lan_id) 532 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 533 else 534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 535 536 hw->phy.type = ixgbe_phy_fw; 537 hw->phy.ops.read_reg = NULL; 538 hw->phy.ops.write_reg = NULL; 539 return ixgbe_get_phy_id_fw(hw); 540 } 541 542 /** 543 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 544 * @hw: pointer to hardware structure 545 * 546 * Returns error code 547 */ 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 549 { 550 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 551 552 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 553 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 554 } 555 556 /** 557 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 558 * @hw: pointer to hardware structure 559 */ 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 561 { 562 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 563 s32 rc; 564 u16 i; 565 566 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 567 return 0; 568 569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 570 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 571 return -EINVAL; 572 } 573 574 switch (hw->fc.requested_mode) { 575 case ixgbe_fc_full: 576 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 577 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 578 break; 579 case ixgbe_fc_rx_pause: 580 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 581 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 582 break; 583 case ixgbe_fc_tx_pause: 584 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 585 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 586 break; 587 default: 588 break; 589 } 590 591 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 592 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 593 setup[0] |= ixgbe_fw_map[i].fw_speed; 594 } 595 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 596 597 if (hw->phy.eee_speeds_advertised) 598 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 599 600 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 601 if (rc) 602 return rc; 603 604 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 605 return -EIO; 606 607 return 0; 608 } 609 610 /** 611 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 612 * @hw: pointer to hardware structure 613 * 614 * Called at init time to set up flow control. 615 */ 616 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 617 { 618 if (hw->fc.requested_mode == ixgbe_fc_default) 619 hw->fc.requested_mode = ixgbe_fc_full; 620 621 return ixgbe_setup_fw_link(hw); 622 } 623 624 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 625 * @hw: pointer to hardware structure 626 * 627 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 628 * ixgbe_hw struct in order to set up EEPROM access. 629 **/ 630 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 631 { 632 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 633 634 if (eeprom->type == ixgbe_eeprom_uninitialized) { 635 u16 eeprom_size; 636 u32 eec; 637 638 eeprom->semaphore_delay = 10; 639 eeprom->type = ixgbe_flash; 640 641 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 642 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 643 eeprom->word_size = BIT(eeprom_size + 644 IXGBE_EEPROM_WORD_SIZE_SHIFT); 645 646 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 647 eeprom->type, eeprom->word_size); 648 } 649 650 return 0; 651 } 652 653 /** 654 * ixgbe_iosf_wait - Wait for IOSF command completion 655 * @hw: pointer to hardware structure 656 * @ctrl: pointer to location to receive final IOSF control value 657 * 658 * Return: failing status on timeout 659 * 660 * Note: ctrl can be NULL if the IOSF control register value is not needed 661 */ 662 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 663 { 664 u32 i, command; 665 666 /* Check every 10 usec to see if the address cycle completed. 667 * The SB IOSF BUSY bit will clear when the operation is 668 * complete. 669 */ 670 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 671 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 672 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 673 break; 674 udelay(10); 675 } 676 if (ctrl) 677 *ctrl = command; 678 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 679 hw_dbg(hw, "IOSF wait timed out\n"); 680 return -EIO; 681 } 682 683 return 0; 684 } 685 686 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 687 * IOSF device 688 * @hw: pointer to hardware structure 689 * @reg_addr: 32 bit PHY register to write 690 * @device_type: 3 bit device type 691 * @phy_data: Pointer to read data from the register 692 **/ 693 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 694 u32 device_type, u32 *data) 695 { 696 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 697 u32 command, error; 698 s32 ret; 699 700 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 701 if (ret) 702 return ret; 703 704 ret = ixgbe_iosf_wait(hw, NULL); 705 if (ret) 706 goto out; 707 708 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 709 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 710 711 /* Write IOSF control register */ 712 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 713 714 ret = ixgbe_iosf_wait(hw, &command); 715 716 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 717 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 718 hw_dbg(hw, "Failed to read, error %x\n", error); 719 return -EIO; 720 } 721 722 if (!ret) 723 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 724 725 out: 726 hw->mac.ops.release_swfw_sync(hw, gssr); 727 return ret; 728 } 729 730 /** 731 * ixgbe_get_phy_token - Get the token for shared PHY access 732 * @hw: Pointer to hardware structure 733 */ 734 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 735 { 736 struct ixgbe_hic_phy_token_req token_cmd; 737 s32 status; 738 739 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 740 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 741 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 742 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 743 token_cmd.port_number = hw->bus.lan_id; 744 token_cmd.command_type = FW_PHY_TOKEN_REQ; 745 token_cmd.pad = 0; 746 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 747 IXGBE_HI_COMMAND_TIMEOUT, 748 true); 749 if (status) 750 return status; 751 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 752 return 0; 753 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 754 return -EIO; 755 756 return -EAGAIN; 757 } 758 759 /** 760 * ixgbe_put_phy_token - Put the token for shared PHY access 761 * @hw: Pointer to hardware structure 762 */ 763 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 764 { 765 struct ixgbe_hic_phy_token_req token_cmd; 766 s32 status; 767 768 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 769 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 770 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 771 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 772 token_cmd.port_number = hw->bus.lan_id; 773 token_cmd.command_type = FW_PHY_TOKEN_REL; 774 token_cmd.pad = 0; 775 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 776 IXGBE_HI_COMMAND_TIMEOUT, 777 true); 778 if (status) 779 return status; 780 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 781 return 0; 782 return -EIO; 783 } 784 785 /** 786 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 787 * @hw: pointer to hardware structure 788 * @reg_addr: 32 bit PHY register to write 789 * @device_type: 3 bit device type 790 * @data: Data to write to the register 791 **/ 792 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 793 __always_unused u32 device_type, 794 u32 data) 795 { 796 struct ixgbe_hic_internal_phy_req write_cmd; 797 798 memset(&write_cmd, 0, sizeof(write_cmd)); 799 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 800 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 801 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 802 write_cmd.port_number = hw->bus.lan_id; 803 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 804 write_cmd.address = cpu_to_be16(reg_addr); 805 write_cmd.write_data = cpu_to_be32(data); 806 807 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 808 IXGBE_HI_COMMAND_TIMEOUT, false); 809 } 810 811 /** 812 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 813 * @hw: pointer to hardware structure 814 * @reg_addr: 32 bit PHY register to write 815 * @device_type: 3 bit device type 816 * @data: Pointer to read data from the register 817 **/ 818 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 819 __always_unused u32 device_type, 820 u32 *data) 821 { 822 union { 823 struct ixgbe_hic_internal_phy_req cmd; 824 struct ixgbe_hic_internal_phy_resp rsp; 825 } hic; 826 s32 status; 827 828 memset(&hic, 0, sizeof(hic)); 829 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 830 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 831 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 832 hic.cmd.port_number = hw->bus.lan_id; 833 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 834 hic.cmd.address = cpu_to_be16(reg_addr); 835 836 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 837 IXGBE_HI_COMMAND_TIMEOUT, true); 838 839 /* Extract the register value from the response. */ 840 *data = be32_to_cpu(hic.rsp.read_data); 841 842 return status; 843 } 844 845 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 846 * @hw: pointer to hardware structure 847 * @offset: offset of word in the EEPROM to read 848 * @words: number of words 849 * @data: word(s) read from the EEPROM 850 * 851 * Reads a 16 bit word(s) from the EEPROM using the hostif. 852 **/ 853 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 854 u16 offset, u16 words, u16 *data) 855 { 856 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 857 struct ixgbe_hic_read_shadow_ram buffer; 858 u32 current_word = 0; 859 u16 words_to_read; 860 s32 status; 861 u32 i; 862 863 /* Take semaphore for the entire operation. */ 864 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 865 if (status) { 866 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 867 return status; 868 } 869 870 while (words) { 871 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 872 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 873 else 874 words_to_read = words; 875 876 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 877 buffer.hdr.req.buf_lenh = 0; 878 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 879 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 880 881 /* convert offset from words to bytes */ 882 buffer.address = (__force u32)cpu_to_be32((offset + 883 current_word) * 2); 884 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 885 buffer.pad2 = 0; 886 buffer.pad3 = 0; 887 888 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 889 IXGBE_HI_COMMAND_TIMEOUT); 890 if (status) { 891 hw_dbg(hw, "Host interface command failed\n"); 892 goto out; 893 } 894 895 for (i = 0; i < words_to_read; i++) { 896 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 897 2 * i; 898 u32 value = IXGBE_READ_REG(hw, reg); 899 900 data[current_word] = (u16)(value & 0xffff); 901 current_word++; 902 i++; 903 if (i < words_to_read) { 904 value >>= 16; 905 data[current_word] = (u16)(value & 0xffff); 906 current_word++; 907 } 908 } 909 words -= words_to_read; 910 } 911 912 out: 913 hw->mac.ops.release_swfw_sync(hw, mask); 914 return status; 915 } 916 917 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 918 * @hw: pointer to hardware structure 919 * @ptr: pointer offset in eeprom 920 * @size: size of section pointed by ptr, if 0 first word will be used as size 921 * @csum: address of checksum to update 922 * 923 * Returns error status for any failure 924 **/ 925 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 926 u16 size, u16 *csum, u16 *buffer, 927 u32 buffer_size) 928 { 929 u16 buf[256]; 930 s32 status; 931 u16 length, bufsz, i, start; 932 u16 *local_buffer; 933 934 bufsz = ARRAY_SIZE(buf); 935 936 /* Read a chunk at the pointer location */ 937 if (!buffer) { 938 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 939 if (status) { 940 hw_dbg(hw, "Failed to read EEPROM image\n"); 941 return status; 942 } 943 local_buffer = buf; 944 } else { 945 if (buffer_size < ptr) 946 return -EINVAL; 947 local_buffer = &buffer[ptr]; 948 } 949 950 if (size) { 951 start = 0; 952 length = size; 953 } else { 954 start = 1; 955 length = local_buffer[0]; 956 957 /* Skip pointer section if length is invalid. */ 958 if (length == 0xFFFF || length == 0 || 959 (ptr + length) >= hw->eeprom.word_size) 960 return 0; 961 } 962 963 if (buffer && ((u32)start + (u32)length > buffer_size)) 964 return -EINVAL; 965 966 for (i = start; length; i++, length--) { 967 if (i == bufsz && !buffer) { 968 ptr += bufsz; 969 i = 0; 970 if (length < bufsz) 971 bufsz = length; 972 973 /* Read a chunk at the pointer location */ 974 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 975 bufsz, buf); 976 if (status) { 977 hw_dbg(hw, "Failed to read EEPROM image\n"); 978 return status; 979 } 980 } 981 *csum += local_buffer[i]; 982 } 983 return 0; 984 } 985 986 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 987 * @hw: pointer to hardware structure 988 * @buffer: pointer to buffer containing calculated checksum 989 * @buffer_size: size of buffer 990 * 991 * Returns a negative error code on error, or the 16-bit checksum 992 **/ 993 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 994 u32 buffer_size) 995 { 996 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 997 u16 *local_buffer; 998 s32 status; 999 u16 checksum = 0; 1000 u16 pointer, i, size; 1001 1002 hw->eeprom.ops.init_params(hw); 1003 1004 if (!buffer) { 1005 /* Read pointer area */ 1006 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1007 IXGBE_EEPROM_LAST_WORD + 1, 1008 eeprom_ptrs); 1009 if (status) { 1010 hw_dbg(hw, "Failed to read EEPROM image\n"); 1011 return status; 1012 } 1013 local_buffer = eeprom_ptrs; 1014 } else { 1015 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1016 return -EINVAL; 1017 local_buffer = buffer; 1018 } 1019 1020 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1021 * checksum word itself 1022 */ 1023 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1024 if (i != IXGBE_EEPROM_CHECKSUM) 1025 checksum += local_buffer[i]; 1026 1027 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1028 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1029 */ 1030 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1031 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1032 continue; 1033 1034 pointer = local_buffer[i]; 1035 1036 /* Skip pointer section if the pointer is invalid. */ 1037 if (pointer == 0xFFFF || pointer == 0 || 1038 pointer >= hw->eeprom.word_size) 1039 continue; 1040 1041 switch (i) { 1042 case IXGBE_PCIE_GENERAL_PTR: 1043 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1044 break; 1045 case IXGBE_PCIE_CONFIG0_PTR: 1046 case IXGBE_PCIE_CONFIG1_PTR: 1047 size = IXGBE_PCIE_CONFIG_SIZE; 1048 break; 1049 default: 1050 size = 0; 1051 break; 1052 } 1053 1054 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1055 buffer, buffer_size); 1056 if (status) 1057 return status; 1058 } 1059 1060 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1061 1062 return (s32)checksum; 1063 } 1064 1065 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1066 * @hw: pointer to hardware structure 1067 * 1068 * Returns a negative error code on error, or the 16-bit checksum 1069 **/ 1070 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1071 { 1072 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1073 } 1074 1075 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1076 * @hw: pointer to hardware structure 1077 * @offset: offset of word in the EEPROM to read 1078 * @data: word read from the EEPROM 1079 * 1080 * Reads a 16 bit word from the EEPROM using the hostif. 1081 **/ 1082 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1083 { 1084 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1085 struct ixgbe_hic_read_shadow_ram buffer; 1086 s32 status; 1087 1088 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1089 buffer.hdr.req.buf_lenh = 0; 1090 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1091 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1092 1093 /* convert offset from words to bytes */ 1094 buffer.address = (__force u32)cpu_to_be32(offset * 2); 1095 /* one word */ 1096 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 1097 1098 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1099 if (status) 1100 return status; 1101 1102 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1103 IXGBE_HI_COMMAND_TIMEOUT); 1104 if (!status) { 1105 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1106 FW_NVM_DATA_OFFSET); 1107 } 1108 1109 hw->mac.ops.release_swfw_sync(hw, mask); 1110 return status; 1111 } 1112 1113 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1114 * @hw: pointer to hardware structure 1115 * @checksum_val: calculated checksum 1116 * 1117 * Performs checksum calculation and validates the EEPROM checksum. If the 1118 * caller does not need checksum_val, the value can be NULL. 1119 **/ 1120 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1121 u16 *checksum_val) 1122 { 1123 s32 status; 1124 u16 checksum; 1125 u16 read_checksum = 0; 1126 1127 /* Read the first word from the EEPROM. If this times out or fails, do 1128 * not continue or we could be in for a very long wait while every 1129 * EEPROM read fails 1130 */ 1131 status = hw->eeprom.ops.read(hw, 0, &checksum); 1132 if (status) { 1133 hw_dbg(hw, "EEPROM read failed\n"); 1134 return status; 1135 } 1136 1137 status = hw->eeprom.ops.calc_checksum(hw); 1138 if (status < 0) 1139 return status; 1140 1141 checksum = (u16)(status & 0xffff); 1142 1143 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1144 &read_checksum); 1145 if (status) 1146 return status; 1147 1148 /* Verify read checksum from EEPROM is the same as 1149 * calculated checksum 1150 */ 1151 if (read_checksum != checksum) { 1152 status = -EIO; 1153 hw_dbg(hw, "Invalid EEPROM checksum"); 1154 } 1155 1156 /* If the user cares, return the calculated checksum */ 1157 if (checksum_val) 1158 *checksum_val = checksum; 1159 1160 return status; 1161 } 1162 1163 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1164 * @hw: pointer to hardware structure 1165 * @offset: offset of word in the EEPROM to write 1166 * @data: word write to the EEPROM 1167 * 1168 * Write a 16 bit word to the EEPROM using the hostif. 1169 **/ 1170 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1171 u16 data) 1172 { 1173 s32 status; 1174 struct ixgbe_hic_write_shadow_ram buffer; 1175 1176 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1177 buffer.hdr.req.buf_lenh = 0; 1178 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1179 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1180 1181 /* one word */ 1182 buffer.length = cpu_to_be16(sizeof(u16)); 1183 buffer.data = data; 1184 buffer.address = cpu_to_be32(offset * 2); 1185 1186 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1187 IXGBE_HI_COMMAND_TIMEOUT, false); 1188 return status; 1189 } 1190 1191 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1192 * @hw: pointer to hardware structure 1193 * @offset: offset of word in the EEPROM to write 1194 * @data: word write to the EEPROM 1195 * 1196 * Write a 16 bit word to the EEPROM using the hostif. 1197 **/ 1198 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1199 { 1200 s32 status = 0; 1201 1202 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1203 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1204 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1205 } else { 1206 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1207 status = -EBUSY; 1208 } 1209 1210 return status; 1211 } 1212 1213 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1214 * @hw: pointer to hardware structure 1215 * 1216 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1217 **/ 1218 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1219 { 1220 s32 status = 0; 1221 union ixgbe_hic_hdr2 buffer; 1222 1223 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1224 buffer.req.buf_lenh = 0; 1225 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1226 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1227 1228 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1229 IXGBE_HI_COMMAND_TIMEOUT, false); 1230 return status; 1231 } 1232 1233 /** 1234 * ixgbe_get_bus_info_X550em - Set PCI bus info 1235 * @hw: pointer to hardware structure 1236 * 1237 * Sets bus link width and speed to unknown because X550em is 1238 * not a PCI device. 1239 **/ 1240 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1241 { 1242 hw->bus.type = ixgbe_bus_type_internal; 1243 hw->bus.width = ixgbe_bus_width_unknown; 1244 hw->bus.speed = ixgbe_bus_speed_unknown; 1245 1246 hw->mac.ops.set_lan_id(hw); 1247 1248 return 0; 1249 } 1250 1251 /** 1252 * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode 1253 * @hw: pointer t hardware structure 1254 * 1255 * Returns true if in FW NVM recovery mode. 1256 */ 1257 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw) 1258 { 1259 u32 fwsm; 1260 1261 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 1262 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE); 1263 } 1264 1265 /** ixgbe_disable_rx_x550 - Disable RX unit 1266 * 1267 * Enables the Rx DMA unit for x550 1268 **/ 1269 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1270 { 1271 u32 rxctrl, pfdtxgswc; 1272 s32 status; 1273 struct ixgbe_hic_disable_rxen fw_cmd; 1274 1275 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1276 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1277 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1278 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1279 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1280 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1281 hw->mac.set_lben = true; 1282 } else { 1283 hw->mac.set_lben = false; 1284 } 1285 1286 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1287 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1288 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1289 fw_cmd.port_number = hw->bus.lan_id; 1290 1291 status = ixgbe_host_interface_command(hw, &fw_cmd, 1292 sizeof(struct ixgbe_hic_disable_rxen), 1293 IXGBE_HI_COMMAND_TIMEOUT, true); 1294 1295 /* If we fail - disable RX using register write */ 1296 if (status) { 1297 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1298 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1299 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1300 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1301 } 1302 } 1303 } 1304 } 1305 1306 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1307 * @hw: pointer to hardware structure 1308 * 1309 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1310 * checksum and updates the EEPROM and instructs the hardware to update 1311 * the flash. 1312 **/ 1313 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1314 { 1315 s32 status; 1316 u16 checksum = 0; 1317 1318 /* Read the first word from the EEPROM. If this times out or fails, do 1319 * not continue or we could be in for a very long wait while every 1320 * EEPROM read fails 1321 */ 1322 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1323 if (status) { 1324 hw_dbg(hw, "EEPROM read failed\n"); 1325 return status; 1326 } 1327 1328 status = ixgbe_calc_eeprom_checksum_X550(hw); 1329 if (status < 0) 1330 return status; 1331 1332 checksum = (u16)(status & 0xffff); 1333 1334 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1335 checksum); 1336 if (status) 1337 return status; 1338 1339 status = ixgbe_update_flash_X550(hw); 1340 1341 return status; 1342 } 1343 1344 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1345 * @hw: pointer to hardware structure 1346 * @offset: offset of word in the EEPROM to write 1347 * @words: number of words 1348 * @data: word(s) write to the EEPROM 1349 * 1350 * 1351 * Write a 16 bit word(s) to the EEPROM using the hostif. 1352 **/ 1353 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1354 u16 offset, u16 words, 1355 u16 *data) 1356 { 1357 s32 status = 0; 1358 u32 i = 0; 1359 1360 /* Take semaphore for the entire operation. */ 1361 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1362 if (status) { 1363 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1364 return status; 1365 } 1366 1367 for (i = 0; i < words; i++) { 1368 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1369 data[i]); 1370 if (status) { 1371 hw_dbg(hw, "Eeprom buffered write failed\n"); 1372 break; 1373 } 1374 } 1375 1376 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1377 1378 return status; 1379 } 1380 1381 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1382 * IOSF device 1383 * 1384 * @hw: pointer to hardware structure 1385 * @reg_addr: 32 bit PHY register to write 1386 * @device_type: 3 bit device type 1387 * @data: Data to write to the register 1388 **/ 1389 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1390 u32 device_type, u32 data) 1391 { 1392 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1393 u32 command, error; 1394 s32 ret; 1395 1396 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1397 if (ret) 1398 return ret; 1399 1400 ret = ixgbe_iosf_wait(hw, NULL); 1401 if (ret) 1402 goto out; 1403 1404 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1405 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1406 1407 /* Write IOSF control register */ 1408 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1409 1410 /* Write IOSF data register */ 1411 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1412 1413 ret = ixgbe_iosf_wait(hw, &command); 1414 1415 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1416 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 1417 hw_dbg(hw, "Failed to write, error %x\n", error); 1418 return -EIO; 1419 } 1420 1421 out: 1422 hw->mac.ops.release_swfw_sync(hw, gssr); 1423 return ret; 1424 } 1425 1426 /** 1427 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1428 * @hw: pointer to hardware structure 1429 * 1430 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1431 **/ 1432 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1433 { 1434 s32 status; 1435 u32 reg_val; 1436 1437 /* Disable training protocol FSM. */ 1438 status = ixgbe_read_iosf_sb_reg_x550(hw, 1439 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1440 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1441 if (status) 1442 return status; 1443 1444 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1445 status = ixgbe_write_iosf_sb_reg_x550(hw, 1446 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1447 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1448 if (status) 1449 return status; 1450 1451 /* Disable Flex from training TXFFE. */ 1452 status = ixgbe_read_iosf_sb_reg_x550(hw, 1453 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1454 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1455 if (status) 1456 return status; 1457 1458 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1459 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1461 status = ixgbe_write_iosf_sb_reg_x550(hw, 1462 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1463 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1464 if (status) 1465 return status; 1466 1467 status = ixgbe_read_iosf_sb_reg_x550(hw, 1468 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1469 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1470 if (status) 1471 return status; 1472 1473 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1474 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1476 status = ixgbe_write_iosf_sb_reg_x550(hw, 1477 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1478 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1479 if (status) 1480 return status; 1481 1482 /* Enable override for coefficients. */ 1483 status = ixgbe_read_iosf_sb_reg_x550(hw, 1484 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1485 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1486 if (status) 1487 return status; 1488 1489 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1490 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1491 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1493 status = ixgbe_write_iosf_sb_reg_x550(hw, 1494 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1495 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1496 return status; 1497 } 1498 1499 /** 1500 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1501 * internal PHY 1502 * @hw: pointer to hardware structure 1503 **/ 1504 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1505 { 1506 s32 status; 1507 u32 link_ctrl; 1508 1509 /* Restart auto-negotiation. */ 1510 status = hw->mac.ops.read_iosf_sb_reg(hw, 1511 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1512 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1513 1514 if (status) { 1515 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1516 return status; 1517 } 1518 1519 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1520 status = hw->mac.ops.write_iosf_sb_reg(hw, 1521 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1522 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1523 1524 if (hw->mac.type == ixgbe_mac_x550em_a) { 1525 u32 flx_mask_st20; 1526 1527 /* Indicate to FW that AN restart has been asserted */ 1528 status = hw->mac.ops.read_iosf_sb_reg(hw, 1529 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1530 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1531 1532 if (status) { 1533 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1534 return status; 1535 } 1536 1537 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1538 status = hw->mac.ops.write_iosf_sb_reg(hw, 1539 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1540 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1541 } 1542 1543 return status; 1544 } 1545 1546 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1547 * @hw: pointer to hardware structure 1548 * @speed: the link speed to force 1549 * 1550 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1551 * internal and external PHY at a specific speed, without autonegotiation. 1552 **/ 1553 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1554 { 1555 struct ixgbe_mac_info *mac = &hw->mac; 1556 s32 status; 1557 u32 reg_val; 1558 1559 /* iXFI is only supported with X552 */ 1560 if (mac->type != ixgbe_mac_X550EM_x) 1561 return -EIO; 1562 1563 /* Disable AN and force speed to 10G Serial. */ 1564 status = ixgbe_read_iosf_sb_reg_x550(hw, 1565 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1566 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1567 if (status) 1568 return status; 1569 1570 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1571 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1572 1573 /* Select forced link speed for internal PHY. */ 1574 switch (*speed) { 1575 case IXGBE_LINK_SPEED_10GB_FULL: 1576 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1577 break; 1578 case IXGBE_LINK_SPEED_1GB_FULL: 1579 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1580 break; 1581 default: 1582 /* Other link speeds are not supported by internal KR PHY. */ 1583 return -EINVAL; 1584 } 1585 1586 status = ixgbe_write_iosf_sb_reg_x550(hw, 1587 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1588 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1589 if (status) 1590 return status; 1591 1592 /* Additional configuration needed for x550em_x */ 1593 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1594 status = ixgbe_setup_ixfi_x550em_x(hw); 1595 if (status) 1596 return status; 1597 } 1598 1599 /* Toggle port SW reset by AN reset. */ 1600 status = ixgbe_restart_an_internal_phy_x550em(hw); 1601 1602 return status; 1603 } 1604 1605 /** 1606 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1607 * @hw: pointer to hardware structure 1608 * @linear: true if SFP module is linear 1609 */ 1610 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1611 { 1612 switch (hw->phy.sfp_type) { 1613 case ixgbe_sfp_type_not_present: 1614 return -ENOENT; 1615 case ixgbe_sfp_type_da_cu_core0: 1616 case ixgbe_sfp_type_da_cu_core1: 1617 *linear = true; 1618 break; 1619 case ixgbe_sfp_type_srlr_core0: 1620 case ixgbe_sfp_type_srlr_core1: 1621 case ixgbe_sfp_type_da_act_lmt_core0: 1622 case ixgbe_sfp_type_da_act_lmt_core1: 1623 case ixgbe_sfp_type_1g_sx_core0: 1624 case ixgbe_sfp_type_1g_sx_core1: 1625 case ixgbe_sfp_type_1g_lx_core0: 1626 case ixgbe_sfp_type_1g_lx_core1: 1627 *linear = false; 1628 break; 1629 case ixgbe_sfp_type_unknown: 1630 case ixgbe_sfp_type_1g_cu_core0: 1631 case ixgbe_sfp_type_1g_cu_core1: 1632 default: 1633 return -EOPNOTSUPP; 1634 } 1635 1636 return 0; 1637 } 1638 1639 /** 1640 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1641 * @hw: pointer to hardware structure 1642 * @speed: the link speed to force 1643 * @autoneg_wait_to_complete: unused 1644 * 1645 * Configures the extern PHY and the integrated KR PHY for SFP support. 1646 */ 1647 static s32 1648 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1649 ixgbe_link_speed speed, 1650 __always_unused bool autoneg_wait_to_complete) 1651 { 1652 s32 status; 1653 u16 reg_slice, reg_val; 1654 bool setup_linear = false; 1655 1656 /* Check if SFP module is supported and linear */ 1657 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1658 1659 /* If no SFP module present, then return success. Return success since 1660 * there is no reason to configure CS4227 and SFP not present error is 1661 * not accepted in the setup MAC link flow. 1662 */ 1663 if (status == -ENOENT) 1664 return 0; 1665 1666 if (status) 1667 return status; 1668 1669 /* Configure internal PHY for KR/KX. */ 1670 ixgbe_setup_kr_speed_x550em(hw, speed); 1671 1672 /* Configure CS4227 LINE side to proper mode. */ 1673 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1674 if (setup_linear) 1675 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1676 else 1677 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1678 1679 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1680 reg_val); 1681 1682 return status; 1683 } 1684 1685 /** 1686 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1687 * @hw: pointer to hardware structure 1688 * @speed: the link speed to force 1689 * 1690 * Configures the integrated PHY for native SFI mode. Used to connect the 1691 * internal PHY directly to an SFP cage, without autonegotiation. 1692 **/ 1693 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1694 { 1695 struct ixgbe_mac_info *mac = &hw->mac; 1696 s32 status; 1697 u32 reg_val; 1698 1699 /* Disable all AN and force speed to 10G Serial. */ 1700 status = mac->ops.read_iosf_sb_reg(hw, 1701 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1702 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1703 if (status) 1704 return status; 1705 1706 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1707 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1710 1711 /* Select forced link speed for internal PHY. */ 1712 switch (*speed) { 1713 case IXGBE_LINK_SPEED_10GB_FULL: 1714 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1715 break; 1716 case IXGBE_LINK_SPEED_1GB_FULL: 1717 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1718 break; 1719 default: 1720 /* Other link speeds are not supported by internal PHY. */ 1721 return -EINVAL; 1722 } 1723 1724 (void)mac->ops.write_iosf_sb_reg(hw, 1725 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1726 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1727 1728 /* change mode enforcement rules to hybrid */ 1729 (void)mac->ops.read_iosf_sb_reg(hw, 1730 IXGBE_KRM_FLX_TMRS_CTRL_ST31(hw->bus.lan_id), 1731 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1732 reg_val |= 0x0400; 1733 1734 (void)mac->ops.write_iosf_sb_reg(hw, 1735 IXGBE_KRM_FLX_TMRS_CTRL_ST31(hw->bus.lan_id), 1736 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1737 1738 /* manually control the config */ 1739 (void)mac->ops.read_iosf_sb_reg(hw, 1740 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1741 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1742 reg_val |= 0x20002240; 1743 1744 (void)mac->ops.write_iosf_sb_reg(hw, 1745 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1746 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1747 1748 /* move the AN base page values */ 1749 (void)mac->ops.read_iosf_sb_reg(hw, 1750 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id), 1751 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1752 reg_val |= 0x1; 1753 1754 (void)mac->ops.write_iosf_sb_reg(hw, 1755 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id), 1756 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1757 1758 /* set the AN37 over CB mode */ 1759 (void)mac->ops.read_iosf_sb_reg(hw, 1760 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id), 1761 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1762 reg_val |= 0x20000000; 1763 1764 (void)mac->ops.write_iosf_sb_reg(hw, 1765 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id), 1766 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1767 1768 /* restart AN manually */ 1769 (void)mac->ops.read_iosf_sb_reg(hw, 1770 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1771 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1772 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1773 1774 (void)mac->ops.write_iosf_sb_reg(hw, 1775 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1776 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1777 1778 /* Toggle port SW reset by AN reset. */ 1779 status = ixgbe_restart_an_internal_phy_x550em(hw); 1780 1781 return status; 1782 } 1783 1784 /** 1785 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1786 * @hw: pointer to hardware structure 1787 * @speed: link speed 1788 * @autoneg_wait_to_complete: unused 1789 * 1790 * Configure the integrated PHY for native SFP support. 1791 */ 1792 static s32 1793 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1794 __always_unused bool autoneg_wait_to_complete) 1795 { 1796 bool setup_linear = false; 1797 u32 reg_phy_int; 1798 s32 ret_val; 1799 1800 /* Check if SFP module is supported and linear */ 1801 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1802 1803 /* If no SFP module present, then return success. Return success since 1804 * SFP not present error is not excepted in the setup MAC link flow. 1805 */ 1806 if (ret_val == -ENOENT) 1807 return 0; 1808 1809 if (ret_val) 1810 return ret_val; 1811 1812 /* Configure internal PHY for native SFI based on module type */ 1813 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1814 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1815 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1816 if (ret_val) 1817 return ret_val; 1818 1819 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1820 if (!setup_linear) 1821 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1822 1823 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1824 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1825 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1826 if (ret_val) 1827 return ret_val; 1828 1829 /* Setup SFI internal link. */ 1830 return ixgbe_setup_sfi_x550a(hw, &speed); 1831 } 1832 1833 /** 1834 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1835 * @hw: pointer to hardware structure 1836 * @speed: link speed 1837 * @autoneg_wait_to_complete: unused 1838 * 1839 * Configure the integrated PHY for SFP support. 1840 */ 1841 static s32 1842 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1843 __always_unused bool autoneg_wait_to_complete) 1844 { 1845 u32 reg_slice, slice_offset; 1846 bool setup_linear = false; 1847 u16 reg_phy_ext; 1848 s32 ret_val; 1849 1850 /* Check if SFP module is supported and linear */ 1851 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1852 1853 /* If no SFP module present, then return success. Return success since 1854 * SFP not present error is not excepted in the setup MAC link flow. 1855 */ 1856 if (ret_val == -ENOENT) 1857 return 0; 1858 1859 if (ret_val) 1860 return ret_val; 1861 1862 /* Configure internal PHY for KR/KX. */ 1863 ixgbe_setup_kr_speed_x550em(hw, speed); 1864 1865 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1866 return -EFAULT; 1867 1868 /* Get external PHY SKU id */ 1869 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1870 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1871 if (ret_val) 1872 return ret_val; 1873 1874 /* When configuring quad port CS4223, the MAC instance is part 1875 * of the slice offset. 1876 */ 1877 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1878 slice_offset = (hw->bus.lan_id + 1879 (hw->bus.instance_id << 1)) << 12; 1880 else 1881 slice_offset = hw->bus.lan_id << 12; 1882 1883 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1884 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1885 1886 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1887 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1888 if (ret_val) 1889 return ret_val; 1890 1891 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1892 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1893 1894 if (setup_linear) 1895 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1896 else 1897 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1898 1899 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1900 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1901 if (ret_val) 1902 return ret_val; 1903 1904 /* Flush previous write with a read */ 1905 return hw->phy.ops.read_reg(hw, reg_slice, 1906 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1907 } 1908 1909 /** 1910 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1911 * @hw: pointer to hardware structure 1912 * @speed: new link speed 1913 * @autoneg_wait: true when waiting for completion is needed 1914 * 1915 * Setup internal/external PHY link speed based on link speed, then set 1916 * external PHY auto advertised link speed. 1917 * 1918 * Returns error status for any failure 1919 **/ 1920 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1921 ixgbe_link_speed speed, 1922 bool autoneg_wait) 1923 { 1924 s32 status; 1925 ixgbe_link_speed force_speed; 1926 1927 /* Setup internal/external PHY link speed to iXFI (10G), unless 1928 * only 1G is auto advertised then setup KX link. 1929 */ 1930 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1931 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1932 else 1933 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1934 1935 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1936 */ 1937 if (hw->mac.type == ixgbe_mac_X550EM_x && 1938 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1939 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1940 1941 if (status) 1942 return status; 1943 } 1944 1945 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1946 } 1947 1948 /** ixgbe_check_link_t_X550em - Determine link and speed status 1949 * @hw: pointer to hardware structure 1950 * @speed: pointer to link speed 1951 * @link_up: true when link is up 1952 * @link_up_wait_to_complete: bool used to wait for link up or not 1953 * 1954 * Check that both the MAC and X557 external PHY have link. 1955 **/ 1956 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1957 ixgbe_link_speed *speed, 1958 bool *link_up, 1959 bool link_up_wait_to_complete) 1960 { 1961 u32 status; 1962 u16 i, autoneg_status; 1963 1964 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1965 return -EIO; 1966 1967 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1968 link_up_wait_to_complete); 1969 1970 /* If check link fails or MAC link is not up, then return */ 1971 if (status || !(*link_up)) 1972 return status; 1973 1974 /* MAC link is up, so check external PHY link. 1975 * Link status is latching low, and can only be used to detect link 1976 * drop, and not the current status of the link without performing 1977 * back-to-back reads. 1978 */ 1979 for (i = 0; i < 2; i++) { 1980 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1981 &autoneg_status); 1982 1983 if (status) 1984 return status; 1985 } 1986 1987 /* If external PHY link is not up, then indicate link not up */ 1988 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1989 *link_up = false; 1990 1991 return 0; 1992 } 1993 1994 /** 1995 * ixgbe_setup_sgmii - Set up link for sgmii 1996 * @hw: pointer to hardware structure 1997 * @speed: unused 1998 * @autoneg_wait_to_complete: unused 1999 */ 2000 static s32 2001 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 2002 __always_unused bool autoneg_wait_to_complete) 2003 { 2004 struct ixgbe_mac_info *mac = &hw->mac; 2005 u32 lval, sval, flx_val; 2006 s32 rc; 2007 2008 rc = mac->ops.read_iosf_sb_reg(hw, 2009 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2010 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2011 if (rc) 2012 return rc; 2013 2014 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2015 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2016 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2017 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2018 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2019 rc = mac->ops.write_iosf_sb_reg(hw, 2020 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2021 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2022 if (rc) 2023 return rc; 2024 2025 rc = mac->ops.read_iosf_sb_reg(hw, 2026 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2027 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2028 if (rc) 2029 return rc; 2030 2031 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2032 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2033 rc = mac->ops.write_iosf_sb_reg(hw, 2034 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2035 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2036 if (rc) 2037 return rc; 2038 2039 rc = mac->ops.read_iosf_sb_reg(hw, 2040 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2041 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2042 if (rc) 2043 return rc; 2044 2045 rc = mac->ops.read_iosf_sb_reg(hw, 2046 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2047 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2048 if (rc) 2049 return rc; 2050 2051 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2052 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2053 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2054 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2055 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2056 2057 rc = mac->ops.write_iosf_sb_reg(hw, 2058 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2059 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2060 if (rc) 2061 return rc; 2062 2063 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2064 return rc; 2065 } 2066 2067 /** 2068 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2069 * @hw: pointer to hardware structure 2070 * @speed: the link speed to force 2071 * @autoneg_wait: true when waiting for completion is needed 2072 */ 2073 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2074 bool autoneg_wait) 2075 { 2076 struct ixgbe_mac_info *mac = &hw->mac; 2077 u32 lval, sval, flx_val; 2078 s32 rc; 2079 2080 rc = mac->ops.read_iosf_sb_reg(hw, 2081 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2082 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2083 if (rc) 2084 return rc; 2085 2086 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2087 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2088 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2089 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2090 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2091 rc = mac->ops.write_iosf_sb_reg(hw, 2092 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2093 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2094 if (rc) 2095 return rc; 2096 2097 rc = mac->ops.read_iosf_sb_reg(hw, 2098 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2099 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2100 if (rc) 2101 return rc; 2102 2103 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2104 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2105 rc = mac->ops.write_iosf_sb_reg(hw, 2106 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2107 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2108 if (rc) 2109 return rc; 2110 2111 rc = mac->ops.write_iosf_sb_reg(hw, 2112 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2113 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2114 if (rc) 2115 return rc; 2116 2117 rc = mac->ops.read_iosf_sb_reg(hw, 2118 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2119 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2120 if (rc) 2121 return rc; 2122 2123 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2124 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2125 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2126 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2127 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2128 2129 rc = mac->ops.write_iosf_sb_reg(hw, 2130 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2131 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2132 if (rc) 2133 return rc; 2134 2135 ixgbe_restart_an_internal_phy_x550em(hw); 2136 2137 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2138 } 2139 2140 /** 2141 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2142 * @hw: pointer to hardware structure 2143 * 2144 * Enable flow control according to IEEE clause 37. 2145 */ 2146 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2147 { 2148 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2149 ixgbe_link_speed speed; 2150 s32 status = -EIO; 2151 bool link_up; 2152 2153 /* AN should have completed when the cable was plugged in. 2154 * Look for reasons to bail out. Bail out if: 2155 * - FC autoneg is disabled, or if 2156 * - link is not up. 2157 */ 2158 if (hw->fc.disable_fc_autoneg) 2159 goto out; 2160 2161 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2162 if (!link_up) 2163 goto out; 2164 2165 /* Check if auto-negotiation has completed */ 2166 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2167 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2168 status = -EIO; 2169 goto out; 2170 } 2171 2172 /* Negotiate the flow control */ 2173 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2174 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2175 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2176 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2177 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2178 2179 out: 2180 if (!status) { 2181 hw->fc.fc_was_autonegged = true; 2182 } else { 2183 hw->fc.fc_was_autonegged = false; 2184 hw->fc.current_mode = hw->fc.requested_mode; 2185 } 2186 } 2187 2188 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2189 * @hw: pointer to hardware structure 2190 **/ 2191 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2192 { 2193 struct ixgbe_mac_info *mac = &hw->mac; 2194 2195 switch (mac->ops.get_media_type(hw)) { 2196 case ixgbe_media_type_fiber: 2197 mac->ops.setup_fc = NULL; 2198 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2199 break; 2200 case ixgbe_media_type_copper: 2201 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2202 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2203 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2204 break; 2205 } 2206 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2207 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2208 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2209 mac->ops.check_link = ixgbe_check_mac_link_generic; 2210 break; 2211 case ixgbe_media_type_backplane: 2212 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2213 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2214 break; 2215 default: 2216 break; 2217 } 2218 } 2219 2220 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2221 * @hw: pointer to hardware structure 2222 **/ 2223 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2224 { 2225 struct ixgbe_mac_info *mac = &hw->mac; 2226 2227 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2228 2229 switch (mac->ops.get_media_type(hw)) { 2230 case ixgbe_media_type_fiber: 2231 /* CS4227 does not support autoneg, so disable the laser control 2232 * functions for SFP+ fiber 2233 */ 2234 mac->ops.disable_tx_laser = NULL; 2235 mac->ops.enable_tx_laser = NULL; 2236 mac->ops.flap_tx_laser = NULL; 2237 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2238 switch (hw->device_id) { 2239 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2240 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2241 break; 2242 case IXGBE_DEV_ID_X550EM_A_SFP: 2243 mac->ops.setup_mac_link = 2244 ixgbe_setup_mac_link_sfp_x550a; 2245 break; 2246 default: 2247 mac->ops.setup_mac_link = 2248 ixgbe_setup_mac_link_sfp_x550em; 2249 break; 2250 } 2251 mac->ops.set_rate_select_speed = 2252 ixgbe_set_soft_rate_select_speed; 2253 break; 2254 case ixgbe_media_type_copper: 2255 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2256 break; 2257 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2258 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2259 mac->ops.check_link = ixgbe_check_link_t_X550em; 2260 break; 2261 case ixgbe_media_type_backplane: 2262 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2263 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2264 mac->ops.setup_link = ixgbe_setup_sgmii; 2265 break; 2266 default: 2267 break; 2268 } 2269 2270 /* Additional modification for X550em_a devices */ 2271 if (hw->mac.type == ixgbe_mac_x550em_a) 2272 ixgbe_init_mac_link_ops_X550em_a(hw); 2273 } 2274 2275 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2276 * @hw: pointer to hardware structure 2277 */ 2278 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2279 { 2280 s32 status; 2281 bool linear; 2282 2283 /* Check if SFP module is supported */ 2284 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2285 if (status) 2286 return status; 2287 2288 ixgbe_init_mac_link_ops_X550em(hw); 2289 hw->phy.ops.reset = NULL; 2290 2291 return 0; 2292 } 2293 2294 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2295 * @hw: pointer to hardware structure 2296 * @speed: pointer to link speed 2297 * @autoneg: true when autoneg or autotry is enabled 2298 **/ 2299 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2300 ixgbe_link_speed *speed, 2301 bool *autoneg) 2302 { 2303 if (hw->phy.type == ixgbe_phy_fw) { 2304 *autoneg = true; 2305 *speed = hw->phy.speeds_supported; 2306 return 0; 2307 } 2308 2309 /* SFP */ 2310 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2311 /* CS4227 SFP must not enable auto-negotiation */ 2312 *autoneg = false; 2313 2314 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2315 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 2316 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2317 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2318 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2319 return 0; 2320 } 2321 2322 /* Link capabilities are based on SFP */ 2323 if (hw->phy.multispeed_fiber) 2324 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2325 IXGBE_LINK_SPEED_1GB_FULL; 2326 else 2327 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2328 } else { 2329 switch (hw->phy.type) { 2330 case ixgbe_phy_x550em_kx4: 2331 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2332 IXGBE_LINK_SPEED_2_5GB_FULL | 2333 IXGBE_LINK_SPEED_10GB_FULL; 2334 break; 2335 case ixgbe_phy_x550em_xfi: 2336 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2337 IXGBE_LINK_SPEED_10GB_FULL; 2338 break; 2339 case ixgbe_phy_ext_1g_t: 2340 case ixgbe_phy_sgmii: 2341 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2342 break; 2343 case ixgbe_phy_x550em_kr: 2344 if (hw->mac.type == ixgbe_mac_x550em_a) { 2345 /* check different backplane modes */ 2346 if (hw->phy.nw_mng_if_sel & 2347 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2348 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2349 break; 2350 } else if (hw->device_id == 2351 IXGBE_DEV_ID_X550EM_A_KR_L) { 2352 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2353 break; 2354 } 2355 } 2356 fallthrough; 2357 default: 2358 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2359 IXGBE_LINK_SPEED_1GB_FULL; 2360 break; 2361 } 2362 *autoneg = true; 2363 } 2364 return 0; 2365 } 2366 2367 /** 2368 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2369 * @hw: pointer to hardware structure 2370 * @lsc: pointer to boolean flag which indicates whether external Base T 2371 * PHY interrupt is lsc 2372 * @is_overtemp: indicate whether an overtemp event encountered 2373 * 2374 * Determime if external Base T PHY interrupt cause is high temperature 2375 * failure alarm or link status change. 2376 **/ 2377 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc, 2378 bool *is_overtemp) 2379 { 2380 u32 status; 2381 u16 reg; 2382 2383 *is_overtemp = false; 2384 *lsc = false; 2385 2386 /* Vendor alarm triggered */ 2387 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2388 MDIO_MMD_VEND1, 2389 ®); 2390 2391 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2392 return status; 2393 2394 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2395 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2396 MDIO_MMD_VEND1, 2397 ®); 2398 2399 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2400 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2401 return status; 2402 2403 /* Global alarm triggered */ 2404 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2405 MDIO_MMD_VEND1, 2406 ®); 2407 2408 if (status) 2409 return status; 2410 2411 /* If high temperature failure, then return over temp error and exit */ 2412 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2413 /* power down the PHY in case the PHY FW didn't already */ 2414 ixgbe_set_copper_phy_power(hw, false); 2415 *is_overtemp = true; 2416 return -EIO; 2417 } 2418 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2419 /* device fault alarm triggered */ 2420 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2421 MDIO_MMD_VEND1, 2422 ®); 2423 if (status) 2424 return status; 2425 2426 /* if device fault was due to high temp alarm handle and exit */ 2427 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2428 /* power down the PHY in case the PHY FW didn't */ 2429 ixgbe_set_copper_phy_power(hw, false); 2430 *is_overtemp = true; 2431 return -EIO; 2432 } 2433 } 2434 2435 /* Vendor alarm 2 triggered */ 2436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2437 MDIO_MMD_AN, ®); 2438 2439 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2440 return status; 2441 2442 /* link connect/disconnect event occurred */ 2443 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2444 MDIO_MMD_AN, ®); 2445 2446 if (status) 2447 return status; 2448 2449 /* Indicate LSC */ 2450 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2451 *lsc = true; 2452 2453 return 0; 2454 } 2455 2456 /** 2457 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2458 * @hw: pointer to hardware structure 2459 * 2460 * Enable link status change and temperature failure alarm for the external 2461 * Base T PHY 2462 * 2463 * Returns PHY access status 2464 **/ 2465 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2466 { 2467 bool lsc, overtemp; 2468 u32 status; 2469 u16 reg; 2470 2471 /* Clear interrupt flags */ 2472 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp); 2473 2474 /* Enable link status change alarm */ 2475 2476 /* Enable the LASI interrupts on X552 devices to receive notifications 2477 * of the link configurations of the external PHY and correspondingly 2478 * support the configuration of the internal iXFI link, since iXFI does 2479 * not support auto-negotiation. This is not required for X553 devices 2480 * having KR support, which performs auto-negotiations and which is used 2481 * as the internal link to the external PHY. Hence adding a check here 2482 * to avoid enabling LASI interrupts for X553 devices. 2483 */ 2484 if (hw->mac.type != ixgbe_mac_x550em_a) { 2485 status = hw->phy.ops.read_reg(hw, 2486 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2487 MDIO_MMD_AN, ®); 2488 if (status) 2489 return status; 2490 2491 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2492 2493 status = hw->phy.ops.write_reg(hw, 2494 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2495 MDIO_MMD_AN, reg); 2496 if (status) 2497 return status; 2498 } 2499 2500 /* Enable high temperature failure and global fault alarms */ 2501 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2502 MDIO_MMD_VEND1, 2503 ®); 2504 if (status) 2505 return status; 2506 2507 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2508 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2509 2510 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2511 MDIO_MMD_VEND1, 2512 reg); 2513 if (status) 2514 return status; 2515 2516 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2517 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2518 MDIO_MMD_VEND1, 2519 ®); 2520 if (status) 2521 return status; 2522 2523 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2524 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2525 2526 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2527 MDIO_MMD_VEND1, 2528 reg); 2529 if (status) 2530 return status; 2531 2532 /* Enable chip-wide vendor alarm */ 2533 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2534 MDIO_MMD_VEND1, 2535 ®); 2536 if (status) 2537 return status; 2538 2539 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2540 2541 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2542 MDIO_MMD_VEND1, 2543 reg); 2544 2545 return status; 2546 } 2547 2548 /** 2549 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2550 * @hw: pointer to hardware structure 2551 * @is_overtemp: indicate whether an overtemp event encountered 2552 * 2553 * Handle external Base T PHY interrupt. If high temperature 2554 * failure alarm then return error, else if link status change 2555 * then setup internal/external PHY link 2556 **/ 2557 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw, 2558 bool *is_overtemp) 2559 { 2560 struct ixgbe_phy_info *phy = &hw->phy; 2561 bool lsc; 2562 u32 status; 2563 2564 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp); 2565 if (status) 2566 return status; 2567 2568 if (lsc && phy->ops.setup_internal_link) 2569 return phy->ops.setup_internal_link(hw); 2570 2571 return 0; 2572 } 2573 2574 /** 2575 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2576 * @hw: pointer to hardware structure 2577 * @speed: link speed 2578 * 2579 * Configures the integrated KR PHY. 2580 **/ 2581 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2582 ixgbe_link_speed speed) 2583 { 2584 s32 status; 2585 u32 reg_val; 2586 2587 status = hw->mac.ops.read_iosf_sb_reg(hw, 2588 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2589 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2590 if (status) 2591 return status; 2592 2593 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2594 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2595 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2596 2597 /* Advertise 10G support. */ 2598 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2599 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2600 2601 /* Advertise 1G support. */ 2602 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2603 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2604 2605 status = hw->mac.ops.write_iosf_sb_reg(hw, 2606 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2607 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2608 2609 if (hw->mac.type == ixgbe_mac_x550em_a) { 2610 /* Set lane mode to KR auto negotiation */ 2611 status = hw->mac.ops.read_iosf_sb_reg(hw, 2612 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2613 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2614 2615 if (status) 2616 return status; 2617 2618 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2619 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2620 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2621 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2622 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2623 2624 status = hw->mac.ops.write_iosf_sb_reg(hw, 2625 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2626 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2627 } 2628 2629 return ixgbe_restart_an_internal_phy_x550em(hw); 2630 } 2631 2632 /** 2633 * ixgbe_setup_kr_x550em - Configure the KR PHY 2634 * @hw: pointer to hardware structure 2635 **/ 2636 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2637 { 2638 /* leave link alone for 2.5G */ 2639 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2640 return 0; 2641 2642 if (ixgbe_check_reset_blocked(hw)) 2643 return 0; 2644 2645 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2646 } 2647 2648 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2649 * @hw: address of hardware structure 2650 * @link_up: address of boolean to indicate link status 2651 * 2652 * Returns error code if unable to get link status. 2653 **/ 2654 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2655 { 2656 u32 ret; 2657 u16 autoneg_status; 2658 2659 *link_up = false; 2660 2661 /* read this twice back to back to indicate current status */ 2662 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2663 &autoneg_status); 2664 if (ret) 2665 return ret; 2666 2667 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2668 &autoneg_status); 2669 if (ret) 2670 return ret; 2671 2672 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2673 2674 return 0; 2675 } 2676 2677 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2678 * @hw: point to hardware structure 2679 * 2680 * Configures the link between the integrated KR PHY and the external X557 PHY 2681 * The driver will call this function when it gets a link status change 2682 * interrupt from the X557 PHY. This function configures the link speed 2683 * between the PHYs to match the link speed of the BASE-T link. 2684 * 2685 * A return of a non-zero value indicates an error, and the base driver should 2686 * not report link up. 2687 **/ 2688 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2689 { 2690 ixgbe_link_speed force_speed; 2691 bool link_up; 2692 u32 status; 2693 u16 speed; 2694 2695 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2696 return -EIO; 2697 2698 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2699 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2700 speed = IXGBE_LINK_SPEED_10GB_FULL | 2701 IXGBE_LINK_SPEED_1GB_FULL; 2702 return ixgbe_setup_kr_speed_x550em(hw, speed); 2703 } 2704 2705 /* If link is not up, then there is no setup necessary so return */ 2706 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2707 if (status) 2708 return status; 2709 2710 if (!link_up) 2711 return 0; 2712 2713 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2714 MDIO_MMD_AN, 2715 &speed); 2716 if (status) 2717 return status; 2718 2719 /* If link is not still up, then no setup is necessary so return */ 2720 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2721 if (status) 2722 return status; 2723 2724 if (!link_up) 2725 return 0; 2726 2727 /* clear everything but the speed and duplex bits */ 2728 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2729 2730 switch (speed) { 2731 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2732 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2733 break; 2734 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2735 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2736 break; 2737 default: 2738 /* Internal PHY does not support anything else */ 2739 return -EINVAL; 2740 } 2741 2742 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2743 } 2744 2745 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2746 * @hw: pointer to hardware structure 2747 **/ 2748 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2749 { 2750 s32 status; 2751 2752 status = ixgbe_reset_phy_generic(hw); 2753 2754 if (status) 2755 return status; 2756 2757 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2758 return ixgbe_enable_lasi_ext_t_x550em(hw); 2759 } 2760 2761 /** 2762 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2763 * @hw: pointer to hardware structure 2764 * @led_idx: led number to turn on 2765 **/ 2766 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2767 { 2768 u16 phy_data; 2769 2770 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2771 return -EINVAL; 2772 2773 /* To turn on the LED, set mode to ON. */ 2774 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2775 MDIO_MMD_VEND1, &phy_data); 2776 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2777 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2778 MDIO_MMD_VEND1, phy_data); 2779 2780 return 0; 2781 } 2782 2783 /** 2784 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2785 * @hw: pointer to hardware structure 2786 * @led_idx: led number to turn off 2787 **/ 2788 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2789 { 2790 u16 phy_data; 2791 2792 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2793 return -EINVAL; 2794 2795 /* To turn on the LED, set mode to ON. */ 2796 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2797 MDIO_MMD_VEND1, &phy_data); 2798 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2799 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2800 MDIO_MMD_VEND1, phy_data); 2801 2802 return 0; 2803 } 2804 2805 /** 2806 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2807 * @hw: pointer to the HW structure 2808 * @maj: driver version major number 2809 * @min: driver version minor number 2810 * @build: driver version build number 2811 * @sub: driver version sub build number 2812 * @len: length of driver_ver string 2813 * @driver_ver: driver string 2814 * 2815 * Sends driver version number to firmware through the manageability 2816 * block. On success return 0 2817 * else returns -EBUSY when encountering an error acquiring 2818 * semaphore, -EIO when command fails or -ENIVAL when incorrect 2819 * params passed. 2820 **/ 2821 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2822 u8 build, u8 sub, u16 len, 2823 const char *driver_ver) 2824 { 2825 struct ixgbe_hic_drv_info2 fw_cmd; 2826 s32 ret_val; 2827 int i; 2828 2829 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2830 return -EINVAL; 2831 2832 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2833 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2834 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2835 fw_cmd.port_num = (u8)hw->bus.func; 2836 fw_cmd.ver_maj = maj; 2837 fw_cmd.ver_min = min; 2838 fw_cmd.ver_build = build; 2839 fw_cmd.ver_sub = sub; 2840 fw_cmd.hdr.checksum = 0; 2841 memcpy(fw_cmd.driver_string, driver_ver, len); 2842 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2843 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2844 2845 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2846 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2847 sizeof(fw_cmd), 2848 IXGBE_HI_COMMAND_TIMEOUT, 2849 true); 2850 if (ret_val) 2851 continue; 2852 2853 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2854 FW_CEM_RESP_STATUS_SUCCESS) 2855 return -EIO; 2856 return 0; 2857 } 2858 2859 return ret_val; 2860 } 2861 2862 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2863 * @hw: pointer to hardware structure 2864 * @lcd_speed: pointer to lowest common link speed 2865 * 2866 * Determine lowest common link speed with link partner. 2867 **/ 2868 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2869 ixgbe_link_speed *lcd_speed) 2870 { 2871 u16 an_lp_status; 2872 s32 status; 2873 u16 word = hw->eeprom.ctrl_word_3; 2874 2875 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2876 2877 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2878 MDIO_MMD_AN, 2879 &an_lp_status); 2880 if (status) 2881 return status; 2882 2883 /* If link partner advertised 1G, return 1G */ 2884 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2885 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2886 return status; 2887 } 2888 2889 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2890 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2891 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2892 return status; 2893 2894 /* Link partner not capable of lower speeds, return 10G */ 2895 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2896 return status; 2897 } 2898 2899 /** 2900 * ixgbe_setup_fc_x550em - Set up flow control 2901 * @hw: pointer to hardware structure 2902 */ 2903 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2904 { 2905 bool pause, asm_dir; 2906 u32 reg_val; 2907 s32 rc = 0; 2908 2909 /* Validate the requested mode */ 2910 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2911 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2912 return -EINVAL; 2913 } 2914 2915 /* 10gig parts do not have a word in the EEPROM to determine the 2916 * default flow control setting, so we explicitly set it to full. 2917 */ 2918 if (hw->fc.requested_mode == ixgbe_fc_default) 2919 hw->fc.requested_mode = ixgbe_fc_full; 2920 2921 /* Determine PAUSE and ASM_DIR bits. */ 2922 switch (hw->fc.requested_mode) { 2923 case ixgbe_fc_none: 2924 pause = false; 2925 asm_dir = false; 2926 break; 2927 case ixgbe_fc_tx_pause: 2928 pause = false; 2929 asm_dir = true; 2930 break; 2931 case ixgbe_fc_rx_pause: 2932 /* Rx Flow control is enabled and Tx Flow control is 2933 * disabled by software override. Since there really 2934 * isn't a way to advertise that we are capable of RX 2935 * Pause ONLY, we will advertise that we support both 2936 * symmetric and asymmetric Rx PAUSE, as such we fall 2937 * through to the fc_full statement. Later, we will 2938 * disable the adapter's ability to send PAUSE frames. 2939 */ 2940 fallthrough; 2941 case ixgbe_fc_full: 2942 pause = true; 2943 asm_dir = true; 2944 break; 2945 default: 2946 hw_err(hw, "Flow control param set incorrectly\n"); 2947 return -EIO; 2948 } 2949 2950 switch (hw->device_id) { 2951 case IXGBE_DEV_ID_X550EM_X_KR: 2952 case IXGBE_DEV_ID_X550EM_A_KR: 2953 case IXGBE_DEV_ID_X550EM_A_KR_L: 2954 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2955 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2956 IXGBE_SB_IOSF_TARGET_KR_PHY, 2957 ®_val); 2958 if (rc) 2959 return rc; 2960 2961 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2962 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2963 if (pause) 2964 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2965 if (asm_dir) 2966 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2967 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2968 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2969 IXGBE_SB_IOSF_TARGET_KR_PHY, 2970 reg_val); 2971 2972 /* This device does not fully support AN. */ 2973 hw->fc.disable_fc_autoneg = true; 2974 break; 2975 case IXGBE_DEV_ID_X550EM_X_XFI: 2976 hw->fc.disable_fc_autoneg = true; 2977 break; 2978 default: 2979 break; 2980 } 2981 return rc; 2982 } 2983 2984 /** 2985 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2986 * @hw: pointer to hardware structure 2987 **/ 2988 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2989 { 2990 u32 link_s1, lp_an_page_low, an_cntl_1; 2991 ixgbe_link_speed speed; 2992 s32 status = -EIO; 2993 bool link_up; 2994 2995 /* AN should have completed when the cable was plugged in. 2996 * Look for reasons to bail out. Bail out if: 2997 * - FC autoneg is disabled, or if 2998 * - link is not up. 2999 */ 3000 if (hw->fc.disable_fc_autoneg) { 3001 hw_err(hw, "Flow control autoneg is disabled"); 3002 goto out; 3003 } 3004 3005 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3006 if (!link_up) { 3007 hw_err(hw, "The link is down"); 3008 goto out; 3009 } 3010 3011 /* Check at auto-negotiation has completed */ 3012 status = hw->mac.ops.read_iosf_sb_reg(hw, 3013 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 3014 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 3015 3016 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 3017 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3018 status = -EIO; 3019 goto out; 3020 } 3021 3022 /* Read the 10g AN autoc and LP ability registers and resolve 3023 * local flow control settings accordingly 3024 */ 3025 status = hw->mac.ops.read_iosf_sb_reg(hw, 3026 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3027 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 3028 3029 if (status) { 3030 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3031 goto out; 3032 } 3033 3034 status = hw->mac.ops.read_iosf_sb_reg(hw, 3035 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 3036 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 3037 3038 if (status) { 3039 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3040 goto out; 3041 } 3042 3043 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 3044 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 3045 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 3046 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 3047 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 3048 3049 out: 3050 if (!status) { 3051 hw->fc.fc_was_autonegged = true; 3052 } else { 3053 hw->fc.fc_was_autonegged = false; 3054 hw->fc.current_mode = hw->fc.requested_mode; 3055 } 3056 } 3057 3058 /** 3059 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 3060 * @hw: pointer to hardware structure 3061 **/ 3062 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 3063 { 3064 hw->fc.fc_was_autonegged = false; 3065 hw->fc.current_mode = hw->fc.requested_mode; 3066 } 3067 3068 /** ixgbe_enter_lplu_x550em - Transition to low power states 3069 * @hw: pointer to hardware structure 3070 * 3071 * Configures Low Power Link Up on transition to low power states 3072 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3073 * the X557 PHY immediately prior to entering LPLU. 3074 **/ 3075 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3076 { 3077 u16 an_10g_cntl_reg, autoneg_reg, speed; 3078 s32 status; 3079 ixgbe_link_speed lcd_speed; 3080 u32 save_autoneg; 3081 bool link_up; 3082 3083 /* If blocked by MNG FW, then don't restart AN */ 3084 if (ixgbe_check_reset_blocked(hw)) 3085 return 0; 3086 3087 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3088 if (status) 3089 return status; 3090 3091 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3092 &hw->eeprom.ctrl_word_3); 3093 if (status) 3094 return status; 3095 3096 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3097 * manageability disabled, then force link down by entering 3098 * low power mode. 3099 */ 3100 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3101 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3102 return ixgbe_set_copper_phy_power(hw, false); 3103 3104 /* Determine LCD */ 3105 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3106 if (status) 3107 return status; 3108 3109 /* If no valid LCD link speed, then force link down and exit. */ 3110 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3111 return ixgbe_set_copper_phy_power(hw, false); 3112 3113 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3114 MDIO_MMD_AN, 3115 &speed); 3116 if (status) 3117 return status; 3118 3119 /* If no link now, speed is invalid so take link down */ 3120 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3121 if (status) 3122 return ixgbe_set_copper_phy_power(hw, false); 3123 3124 /* clear everything but the speed bits */ 3125 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3126 3127 /* If current speed is already LCD, then exit. */ 3128 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3129 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3130 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3131 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3132 return status; 3133 3134 /* Clear AN completed indication */ 3135 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3136 MDIO_MMD_AN, 3137 &autoneg_reg); 3138 if (status) 3139 return status; 3140 3141 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3142 MDIO_MMD_AN, 3143 &an_10g_cntl_reg); 3144 if (status) 3145 return status; 3146 3147 status = hw->phy.ops.read_reg(hw, 3148 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3149 MDIO_MMD_AN, 3150 &autoneg_reg); 3151 if (status) 3152 return status; 3153 3154 save_autoneg = hw->phy.autoneg_advertised; 3155 3156 /* Setup link at least common link speed */ 3157 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3158 3159 /* restore autoneg from before setting lplu speed */ 3160 hw->phy.autoneg_advertised = save_autoneg; 3161 3162 return status; 3163 } 3164 3165 /** 3166 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3167 * @hw: pointer to hardware structure 3168 */ 3169 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3170 { 3171 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3172 s32 rc; 3173 3174 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3175 return 0; 3176 3177 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3178 if (rc) 3179 return rc; 3180 memset(store, 0, sizeof(store)); 3181 3182 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3183 if (rc) 3184 return rc; 3185 3186 return ixgbe_setup_fw_link(hw); 3187 } 3188 3189 /** 3190 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3191 * @hw: pointer to hardware structure 3192 * 3193 * Return true when an overtemp event detected, otherwise false. 3194 */ 3195 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3196 { 3197 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3198 s32 rc; 3199 3200 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3201 if (rc) 3202 return false; 3203 3204 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3205 ixgbe_shutdown_fw_phy(hw); 3206 return true; 3207 } 3208 return false; 3209 } 3210 3211 /** 3212 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3213 * @hw: pointer to hardware structure 3214 * 3215 * Read NW_MNG_IF_SEL register and save field values. 3216 */ 3217 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3218 { 3219 /* Save NW management interface connected on board. This is used 3220 * to determine internal PHY mode. 3221 */ 3222 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3223 3224 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3225 * PHY address. This register field was has only been used for X552. 3226 */ 3227 if (hw->mac.type == ixgbe_mac_x550em_a && 3228 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3229 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD, 3230 hw->phy.nw_mng_if_sel); 3231 } 3232 } 3233 3234 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3235 * @hw: pointer to hardware structure 3236 * 3237 * Initialize any function pointers that were not able to be 3238 * set during init_shared_code because the PHY/SFP type was 3239 * not known. Perform the SFP init if necessary. 3240 **/ 3241 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3242 { 3243 struct ixgbe_phy_info *phy = &hw->phy; 3244 s32 ret_val; 3245 3246 hw->mac.ops.set_lan_id(hw); 3247 3248 ixgbe_read_mng_if_sel_x550em(hw); 3249 3250 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3251 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3252 ixgbe_setup_mux_ctl(hw); 3253 } 3254 3255 /* Identify the PHY or SFP module */ 3256 ret_val = phy->ops.identify(hw); 3257 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT) 3258 return ret_val; 3259 3260 /* Setup function pointers based on detected hardware */ 3261 ixgbe_init_mac_link_ops_X550em(hw); 3262 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3263 phy->ops.reset = NULL; 3264 3265 /* Set functions pointers based on phy type */ 3266 switch (hw->phy.type) { 3267 case ixgbe_phy_x550em_kx4: 3268 phy->ops.setup_link = NULL; 3269 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3270 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3271 break; 3272 case ixgbe_phy_x550em_kr: 3273 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3274 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3275 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3276 break; 3277 case ixgbe_phy_x550em_xfi: 3278 /* link is managed by HW */ 3279 phy->ops.setup_link = NULL; 3280 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3281 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3282 break; 3283 case ixgbe_phy_x550em_ext_t: 3284 /* Save NW management interface connected on board. This is used 3285 * to determine internal PHY mode 3286 */ 3287 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3288 3289 /* If internal link mode is XFI, then setup iXFI internal link, 3290 * else setup KR now. 3291 */ 3292 phy->ops.setup_internal_link = 3293 ixgbe_setup_internal_phy_t_x550em; 3294 3295 /* setup SW LPLU only for first revision */ 3296 if (hw->mac.type == ixgbe_mac_X550EM_x && 3297 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3298 IXGBE_FUSES0_REV_MASK)) 3299 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3300 3301 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3302 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3303 break; 3304 case ixgbe_phy_sgmii: 3305 phy->ops.setup_link = NULL; 3306 break; 3307 case ixgbe_phy_fw: 3308 phy->ops.setup_link = ixgbe_setup_fw_link; 3309 phy->ops.reset = ixgbe_reset_phy_fw; 3310 break; 3311 case ixgbe_phy_ext_1g_t: 3312 phy->ops.setup_link = NULL; 3313 phy->ops.read_reg = NULL; 3314 phy->ops.write_reg = NULL; 3315 phy->ops.reset = NULL; 3316 break; 3317 default: 3318 break; 3319 } 3320 3321 return ret_val; 3322 } 3323 3324 /** ixgbe_get_media_type_X550em - Get media type 3325 * @hw: pointer to hardware structure 3326 * 3327 * Returns the media type (fiber, copper, backplane) 3328 * 3329 */ 3330 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3331 { 3332 enum ixgbe_media_type media_type; 3333 3334 /* Detect if there is a copper PHY attached. */ 3335 switch (hw->device_id) { 3336 case IXGBE_DEV_ID_X550EM_A_SGMII: 3337 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3338 hw->phy.type = ixgbe_phy_sgmii; 3339 fallthrough; 3340 case IXGBE_DEV_ID_X550EM_X_KR: 3341 case IXGBE_DEV_ID_X550EM_X_KX4: 3342 case IXGBE_DEV_ID_X550EM_X_XFI: 3343 case IXGBE_DEV_ID_X550EM_A_KR: 3344 case IXGBE_DEV_ID_X550EM_A_KR_L: 3345 media_type = ixgbe_media_type_backplane; 3346 break; 3347 case IXGBE_DEV_ID_X550EM_X_SFP: 3348 case IXGBE_DEV_ID_X550EM_A_SFP: 3349 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3350 media_type = ixgbe_media_type_fiber; 3351 break; 3352 case IXGBE_DEV_ID_X550EM_X_1G_T: 3353 case IXGBE_DEV_ID_X550EM_X_10G_T: 3354 case IXGBE_DEV_ID_X550EM_A_10G_T: 3355 case IXGBE_DEV_ID_X550EM_A_1G_T: 3356 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3357 media_type = ixgbe_media_type_copper; 3358 break; 3359 default: 3360 media_type = ixgbe_media_type_unknown; 3361 break; 3362 } 3363 return media_type; 3364 } 3365 3366 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3367 ** @hw: pointer to hardware structure 3368 **/ 3369 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3370 { 3371 s32 status; 3372 u16 reg; 3373 3374 status = hw->phy.ops.read_reg(hw, 3375 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3376 MDIO_MMD_PMAPMD, 3377 ®); 3378 if (status) 3379 return status; 3380 3381 /* If PHY FW reset completed bit is set then this is the first 3382 * SW instance after a power on so the PHY FW must be un-stalled. 3383 */ 3384 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3385 status = hw->phy.ops.read_reg(hw, 3386 IXGBE_MDIO_GLOBAL_RES_PR_10, 3387 MDIO_MMD_VEND1, 3388 ®); 3389 if (status) 3390 return status; 3391 3392 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3393 3394 status = hw->phy.ops.write_reg(hw, 3395 IXGBE_MDIO_GLOBAL_RES_PR_10, 3396 MDIO_MMD_VEND1, 3397 reg); 3398 if (status) 3399 return status; 3400 } 3401 3402 return status; 3403 } 3404 3405 /** 3406 * ixgbe_set_mdio_speed - Set MDIO clock speed 3407 * @hw: pointer to hardware structure 3408 */ 3409 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3410 { 3411 u32 hlreg0; 3412 3413 switch (hw->device_id) { 3414 case IXGBE_DEV_ID_X550EM_X_10G_T: 3415 case IXGBE_DEV_ID_X550EM_A_SGMII: 3416 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3417 case IXGBE_DEV_ID_X550EM_A_10G_T: 3418 case IXGBE_DEV_ID_X550EM_A_SFP: 3419 /* Config MDIO clock speed before the first MDIO PHY access */ 3420 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3421 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3422 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3423 break; 3424 case IXGBE_DEV_ID_X550EM_A_1G_T: 3425 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3426 /* Select fast MDIO clock speed for these devices */ 3427 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3428 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3429 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3430 break; 3431 default: 3432 break; 3433 } 3434 } 3435 3436 /** ixgbe_reset_hw_X550em - Perform hardware reset 3437 ** @hw: pointer to hardware structure 3438 ** 3439 ** Resets the hardware by resetting the transmit and receive units, masks 3440 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3441 ** reset. 3442 **/ 3443 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3444 { 3445 ixgbe_link_speed link_speed; 3446 s32 status; 3447 u32 ctrl = 0; 3448 u32 i; 3449 bool link_up = false; 3450 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3451 3452 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3453 status = hw->mac.ops.stop_adapter(hw); 3454 if (status) 3455 return status; 3456 3457 /* flush pending Tx transactions */ 3458 ixgbe_clear_tx_pending(hw); 3459 3460 /* set MDIO speed before talking to the PHY in case it's the 1st time */ 3461 ixgbe_set_mdio_speed(hw); 3462 3463 /* PHY ops must be identified and initialized prior to reset */ 3464 status = hw->phy.ops.init(hw); 3465 if (status == -EOPNOTSUPP || status == -EFAULT) 3466 return status; 3467 3468 /* start the external PHY */ 3469 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3470 status = ixgbe_init_ext_t_x550em(hw); 3471 if (status) 3472 return status; 3473 } 3474 3475 /* Setup SFP module if there is one present. */ 3476 if (hw->phy.sfp_setup_needed) { 3477 status = hw->mac.ops.setup_sfp(hw); 3478 hw->phy.sfp_setup_needed = false; 3479 } 3480 3481 if (status == -EOPNOTSUPP) 3482 return status; 3483 3484 /* Reset PHY */ 3485 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3486 hw->phy.ops.reset(hw); 3487 3488 mac_reset_top: 3489 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3490 * If link reset is used when link is up, it might reset the PHY when 3491 * mng is using it. If link is down or the flag to force full link 3492 * reset is set, then perform link reset. 3493 */ 3494 ctrl = IXGBE_CTRL_LNK_RST; 3495 3496 if (!hw->force_full_reset) { 3497 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3498 if (link_up) 3499 ctrl = IXGBE_CTRL_RST; 3500 } 3501 3502 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3503 if (status) { 3504 hw_dbg(hw, "semaphore failed with %d", status); 3505 return -EBUSY; 3506 } 3507 3508 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3509 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3510 IXGBE_WRITE_FLUSH(hw); 3511 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3512 usleep_range(1000, 1200); 3513 3514 /* Poll for reset bit to self-clear meaning reset is complete */ 3515 for (i = 0; i < 10; i++) { 3516 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3517 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3518 break; 3519 udelay(1); 3520 } 3521 3522 if (ctrl & IXGBE_CTRL_RST_MASK) { 3523 status = -EIO; 3524 hw_dbg(hw, "Reset polling failed to complete.\n"); 3525 } 3526 3527 msleep(50); 3528 3529 /* Double resets are required for recovery from certain error 3530 * clear the multicast table. Also reset num_rar_entries to 128, 3531 * since we modify this value when programming the SAN MAC address. 3532 */ 3533 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3534 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3535 goto mac_reset_top; 3536 } 3537 3538 /* Store the permanent mac address */ 3539 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3540 3541 /* Store MAC address from RAR0, clear receive address registers, and 3542 * clear the multicast table. Also reset num_rar_entries to 128, 3543 * since we modify this value when programming the SAN MAC address. 3544 */ 3545 hw->mac.num_rar_entries = 128; 3546 hw->mac.ops.init_rx_addrs(hw); 3547 3548 ixgbe_set_mdio_speed(hw); 3549 3550 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3551 ixgbe_setup_mux_ctl(hw); 3552 3553 return status; 3554 } 3555 3556 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3557 * anti-spoofing 3558 * @hw: pointer to hardware structure 3559 * @enable: enable or disable switch for Ethertype anti-spoofing 3560 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3561 **/ 3562 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3563 bool enable, int vf) 3564 { 3565 int vf_target_reg = vf >> 3; 3566 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3567 u32 pfvfspoof; 3568 3569 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3570 if (enable) 3571 pfvfspoof |= BIT(vf_target_shift); 3572 else 3573 pfvfspoof &= ~BIT(vf_target_shift); 3574 3575 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3576 } 3577 3578 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3579 * @hw: pointer to hardware structure 3580 * @enable: enable or disable source address pruning 3581 * @pool: Rx pool to set source address pruning for 3582 **/ 3583 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3584 bool enable, 3585 unsigned int pool) 3586 { 3587 u64 pfflp; 3588 3589 /* max rx pool is 63 */ 3590 if (pool > 63) 3591 return; 3592 3593 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3594 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3595 3596 if (enable) 3597 pfflp |= (1ULL << pool); 3598 else 3599 pfflp &= ~(1ULL << pool); 3600 3601 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3602 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3603 } 3604 3605 /** 3606 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3607 * @hw: pointer to hardware structure 3608 * 3609 * Called at init time to set up flow control. 3610 **/ 3611 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3612 { 3613 s32 status = 0; 3614 u32 an_cntl = 0; 3615 3616 /* Validate the requested mode */ 3617 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3618 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3619 return -EINVAL; 3620 } 3621 3622 if (hw->fc.requested_mode == ixgbe_fc_default) 3623 hw->fc.requested_mode = ixgbe_fc_full; 3624 3625 /* Set up the 1G and 10G flow control advertisement registers so the 3626 * HW will be able to do FC autoneg once the cable is plugged in. If 3627 * we link at 10G, the 1G advertisement is harmless and vice versa. 3628 */ 3629 status = hw->mac.ops.read_iosf_sb_reg(hw, 3630 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3631 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3632 3633 if (status) { 3634 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3635 return status; 3636 } 3637 3638 /* The possible values of fc.requested_mode are: 3639 * 0: Flow control is completely disabled 3640 * 1: Rx flow control is enabled (we can receive pause frames, 3641 * but not send pause frames). 3642 * 2: Tx flow control is enabled (we can send pause frames but 3643 * we do not support receiving pause frames). 3644 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3645 * other: Invalid. 3646 */ 3647 switch (hw->fc.requested_mode) { 3648 case ixgbe_fc_none: 3649 /* Flow control completely disabled by software override. */ 3650 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3651 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3652 break; 3653 case ixgbe_fc_tx_pause: 3654 /* Tx Flow control is enabled, and Rx Flow control is 3655 * disabled by software override. 3656 */ 3657 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3658 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3659 break; 3660 case ixgbe_fc_rx_pause: 3661 /* Rx Flow control is enabled and Tx Flow control is 3662 * disabled by software override. Since there really 3663 * isn't a way to advertise that we are capable of RX 3664 * Pause ONLY, we will advertise that we support both 3665 * symmetric and asymmetric Rx PAUSE, as such we fall 3666 * through to the fc_full statement. Later, we will 3667 * disable the adapter's ability to send PAUSE frames. 3668 */ 3669 case ixgbe_fc_full: 3670 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3671 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3672 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3673 break; 3674 default: 3675 hw_err(hw, "Flow control param set incorrectly\n"); 3676 return -EIO; 3677 } 3678 3679 status = hw->mac.ops.write_iosf_sb_reg(hw, 3680 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3681 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3682 3683 /* Restart auto-negotiation. */ 3684 status = ixgbe_restart_an_internal_phy_x550em(hw); 3685 3686 return status; 3687 } 3688 3689 /** 3690 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3691 * @hw: pointer to hardware structure 3692 * @state: set mux if 1, clear if 0 3693 */ 3694 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3695 { 3696 u32 esdp; 3697 3698 if (!hw->bus.lan_id) 3699 return; 3700 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3701 if (state) 3702 esdp |= IXGBE_ESDP_SDP1; 3703 else 3704 esdp &= ~IXGBE_ESDP_SDP1; 3705 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3706 IXGBE_WRITE_FLUSH(hw); 3707 } 3708 3709 /** 3710 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3711 * @hw: pointer to hardware structure 3712 * @mask: Mask to specify which semaphore to acquire 3713 * 3714 * Acquires the SWFW semaphore and sets the I2C MUX 3715 */ 3716 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3717 { 3718 s32 status; 3719 3720 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3721 if (status) 3722 return status; 3723 3724 if (mask & IXGBE_GSSR_I2C_MASK) 3725 ixgbe_set_mux(hw, 1); 3726 3727 return 0; 3728 } 3729 3730 /** 3731 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3732 * @hw: pointer to hardware structure 3733 * @mask: Mask to specify which semaphore to release 3734 * 3735 * Releases the SWFW semaphore and sets the I2C MUX 3736 */ 3737 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3738 { 3739 if (mask & IXGBE_GSSR_I2C_MASK) 3740 ixgbe_set_mux(hw, 0); 3741 3742 ixgbe_release_swfw_sync_X540(hw, mask); 3743 } 3744 3745 /** 3746 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3747 * @hw: pointer to hardware structure 3748 * @mask: Mask to specify which semaphore to acquire 3749 * 3750 * Acquires the SWFW semaphore and get the shared PHY token as needed 3751 */ 3752 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3753 { 3754 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3755 int retries = FW_PHY_TOKEN_RETRIES; 3756 s32 status; 3757 3758 while (--retries) { 3759 status = 0; 3760 if (hmask) 3761 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3762 if (status) 3763 return status; 3764 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3765 return 0; 3766 3767 status = ixgbe_get_phy_token(hw); 3768 if (!status) 3769 return 0; 3770 if (hmask) 3771 ixgbe_release_swfw_sync_X540(hw, hmask); 3772 if (status != -EAGAIN) 3773 return status; 3774 msleep(FW_PHY_TOKEN_DELAY); 3775 } 3776 3777 return status; 3778 } 3779 3780 /** 3781 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3782 * @hw: pointer to hardware structure 3783 * @mask: Mask to specify which semaphore to release 3784 * 3785 * Release the SWFW semaphore and puts the shared PHY token as needed 3786 */ 3787 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3788 { 3789 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3790 3791 if (mask & IXGBE_GSSR_TOKEN_SM) 3792 ixgbe_put_phy_token(hw); 3793 3794 if (hmask) 3795 ixgbe_release_swfw_sync_X540(hw, hmask); 3796 } 3797 3798 /** 3799 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3800 * @hw: pointer to hardware structure 3801 * @reg_addr: 32 bit address of PHY register to read 3802 * @device_type: 5 bit device type 3803 * @phy_data: Pointer to read data from PHY register 3804 * 3805 * Reads a value from a specified PHY register using the SWFW lock and PHY 3806 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3807 * instances. 3808 */ 3809 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3810 u32 device_type, u16 *phy_data) 3811 { 3812 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3813 s32 status; 3814 3815 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3816 return -EBUSY; 3817 3818 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3819 3820 hw->mac.ops.release_swfw_sync(hw, mask); 3821 3822 return status; 3823 } 3824 3825 /** 3826 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3827 * @hw: pointer to hardware structure 3828 * @reg_addr: 32 bit PHY register to write 3829 * @device_type: 5 bit device type 3830 * @phy_data: Data to write to the PHY register 3831 * 3832 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3833 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3834 */ 3835 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3836 u32 device_type, u16 phy_data) 3837 { 3838 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3839 s32 status; 3840 3841 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3842 return -EBUSY; 3843 3844 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3845 hw->mac.ops.release_swfw_sync(hw, mask); 3846 3847 return status; 3848 } 3849 3850 #define X550_COMMON_MAC \ 3851 .init_hw = &ixgbe_init_hw_generic, \ 3852 .start_hw = &ixgbe_start_hw_X540, \ 3853 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3854 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3855 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3856 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3857 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3858 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3859 .read_analog_reg8 = NULL, \ 3860 .write_analog_reg8 = NULL, \ 3861 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3862 .check_link = &ixgbe_check_mac_link_generic, \ 3863 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3864 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3865 .set_rar = &ixgbe_set_rar_generic, \ 3866 .clear_rar = &ixgbe_clear_rar_generic, \ 3867 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3868 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3869 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3870 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3871 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3872 .enable_mc = &ixgbe_enable_mc_generic, \ 3873 .disable_mc = &ixgbe_disable_mc_generic, \ 3874 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3875 .set_vfta = &ixgbe_set_vfta_generic, \ 3876 .fc_enable = &ixgbe_fc_enable_generic, \ 3877 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3878 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3879 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3880 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3881 .set_source_address_pruning = \ 3882 &ixgbe_set_source_address_pruning_X550, \ 3883 .set_ethertype_anti_spoofing = \ 3884 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3885 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3886 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3887 .get_thermal_sensor_data = NULL, \ 3888 .init_thermal_sensor_thresh = NULL, \ 3889 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \ 3890 .enable_rx = &ixgbe_enable_rx_generic, \ 3891 .disable_rx = &ixgbe_disable_rx_x550, \ 3892 3893 static const struct ixgbe_mac_operations mac_ops_X550 = { 3894 X550_COMMON_MAC 3895 .led_on = ixgbe_led_on_generic, 3896 .led_off = ixgbe_led_off_generic, 3897 .init_led_link_act = ixgbe_init_led_link_act_generic, 3898 .reset_hw = &ixgbe_reset_hw_X540, 3899 .get_media_type = &ixgbe_get_media_type_X540, 3900 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3901 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3902 .setup_link = &ixgbe_setup_mac_link_X540, 3903 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3904 .get_bus_info = &ixgbe_get_bus_info_generic, 3905 .setup_sfp = NULL, 3906 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3907 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3908 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3909 .prot_autoc_read = prot_autoc_read_generic, 3910 .prot_autoc_write = prot_autoc_write_generic, 3911 .setup_fc = ixgbe_setup_fc_generic, 3912 .fc_autoneg = ixgbe_fc_autoneg, 3913 }; 3914 3915 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3916 X550_COMMON_MAC 3917 .led_on = ixgbe_led_on_t_x550em, 3918 .led_off = ixgbe_led_off_t_x550em, 3919 .init_led_link_act = ixgbe_init_led_link_act_generic, 3920 .reset_hw = &ixgbe_reset_hw_X550em, 3921 .get_media_type = &ixgbe_get_media_type_X550em, 3922 .get_san_mac_addr = NULL, 3923 .get_wwn_prefix = NULL, 3924 .setup_link = &ixgbe_setup_mac_link_X540, 3925 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3926 .get_bus_info = &ixgbe_get_bus_info_X550em, 3927 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3928 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3929 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3930 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3931 .setup_fc = NULL, /* defined later */ 3932 .fc_autoneg = ixgbe_fc_autoneg, 3933 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3934 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3935 }; 3936 3937 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3938 X550_COMMON_MAC 3939 .led_on = NULL, 3940 .led_off = NULL, 3941 .init_led_link_act = NULL, 3942 .reset_hw = &ixgbe_reset_hw_X550em, 3943 .get_media_type = &ixgbe_get_media_type_X550em, 3944 .get_san_mac_addr = NULL, 3945 .get_wwn_prefix = NULL, 3946 .setup_link = &ixgbe_setup_mac_link_X540, 3947 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3948 .get_bus_info = &ixgbe_get_bus_info_X550em, 3949 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3950 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3951 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3952 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3953 .setup_fc = NULL, 3954 .fc_autoneg = ixgbe_fc_autoneg, 3955 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3956 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3957 }; 3958 3959 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3960 X550_COMMON_MAC 3961 .led_on = ixgbe_led_on_t_x550em, 3962 .led_off = ixgbe_led_off_t_x550em, 3963 .init_led_link_act = ixgbe_init_led_link_act_generic, 3964 .reset_hw = ixgbe_reset_hw_X550em, 3965 .get_media_type = ixgbe_get_media_type_X550em, 3966 .get_san_mac_addr = NULL, 3967 .get_wwn_prefix = NULL, 3968 .setup_link = &ixgbe_setup_mac_link_X540, 3969 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3970 .get_bus_info = ixgbe_get_bus_info_X550em, 3971 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3972 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3973 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3974 .setup_fc = ixgbe_setup_fc_x550em, 3975 .fc_autoneg = ixgbe_fc_autoneg, 3976 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3977 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3978 }; 3979 3980 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3981 X550_COMMON_MAC 3982 .led_on = ixgbe_led_on_generic, 3983 .led_off = ixgbe_led_off_generic, 3984 .init_led_link_act = ixgbe_init_led_link_act_generic, 3985 .reset_hw = ixgbe_reset_hw_X550em, 3986 .get_media_type = ixgbe_get_media_type_X550em, 3987 .get_san_mac_addr = NULL, 3988 .get_wwn_prefix = NULL, 3989 .setup_link = NULL, /* defined later */ 3990 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3991 .get_bus_info = ixgbe_get_bus_info_X550em, 3992 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3993 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3994 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3995 .setup_fc = ixgbe_setup_fc_x550em, 3996 .fc_autoneg = ixgbe_fc_autoneg, 3997 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3998 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3999 }; 4000 4001 #define X550_COMMON_EEP \ 4002 .read = &ixgbe_read_ee_hostif_X550, \ 4003 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 4004 .write = &ixgbe_write_ee_hostif_X550, \ 4005 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 4006 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 4007 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 4008 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 4009 4010 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 4011 X550_COMMON_EEP 4012 .init_params = &ixgbe_init_eeprom_params_X550, 4013 }; 4014 4015 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 4016 X550_COMMON_EEP 4017 .init_params = &ixgbe_init_eeprom_params_X540, 4018 }; 4019 4020 #define X550_COMMON_PHY \ 4021 .identify_sfp = &ixgbe_identify_module_generic, \ 4022 .reset = NULL, \ 4023 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 4024 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 4025 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 4026 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 4027 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 4028 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 4029 .setup_link = &ixgbe_setup_phy_link_generic, \ 4030 .set_phy_power = NULL, 4031 4032 static const struct ixgbe_phy_operations phy_ops_X550 = { 4033 X550_COMMON_PHY 4034 .check_overtemp = &ixgbe_tn_check_overtemp, 4035 .init = NULL, 4036 .identify = &ixgbe_identify_phy_generic, 4037 .read_reg = &ixgbe_read_phy_reg_generic, 4038 .write_reg = &ixgbe_write_phy_reg_generic, 4039 }; 4040 4041 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 4042 X550_COMMON_PHY 4043 .check_overtemp = &ixgbe_tn_check_overtemp, 4044 .init = &ixgbe_init_phy_ops_X550em, 4045 .identify = &ixgbe_identify_phy_x550em, 4046 .read_reg = &ixgbe_read_phy_reg_generic, 4047 .write_reg = &ixgbe_write_phy_reg_generic, 4048 }; 4049 4050 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 4051 X550_COMMON_PHY 4052 .check_overtemp = NULL, 4053 .init = ixgbe_init_phy_ops_X550em, 4054 .identify = ixgbe_identify_phy_x550em, 4055 .read_reg = NULL, 4056 .write_reg = NULL, 4057 .read_reg_mdi = NULL, 4058 .write_reg_mdi = NULL, 4059 }; 4060 4061 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 4062 X550_COMMON_PHY 4063 .check_overtemp = &ixgbe_tn_check_overtemp, 4064 .init = &ixgbe_init_phy_ops_X550em, 4065 .identify = &ixgbe_identify_phy_x550em, 4066 .read_reg = &ixgbe_read_phy_reg_x550a, 4067 .write_reg = &ixgbe_write_phy_reg_x550a, 4068 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 4069 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 4070 }; 4071 4072 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4073 X550_COMMON_PHY 4074 .check_overtemp = ixgbe_check_overtemp_fw, 4075 .init = ixgbe_init_phy_ops_X550em, 4076 .identify = ixgbe_identify_phy_fw, 4077 .read_reg = NULL, 4078 .write_reg = NULL, 4079 .read_reg_mdi = NULL, 4080 .write_reg_mdi = NULL, 4081 }; 4082 4083 static const struct ixgbe_link_operations link_ops_x550em_x = { 4084 .read_link = &ixgbe_read_i2c_combined_generic, 4085 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4086 .write_link = &ixgbe_write_i2c_combined_generic, 4087 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4088 }; 4089 4090 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4091 IXGBE_MVALS_INIT(X550) 4092 }; 4093 4094 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4095 IXGBE_MVALS_INIT(X550EM_x) 4096 }; 4097 4098 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4099 IXGBE_MVALS_INIT(X550EM_a) 4100 }; 4101 4102 const struct ixgbe_info ixgbe_X550_info = { 4103 .mac = ixgbe_mac_X550, 4104 .get_invariants = &ixgbe_get_invariants_X540, 4105 .mac_ops = &mac_ops_X550, 4106 .eeprom_ops = &eeprom_ops_X550, 4107 .phy_ops = &phy_ops_X550, 4108 .mbx_ops = &mbx_ops_generic, 4109 .mvals = ixgbe_mvals_X550, 4110 }; 4111 4112 const struct ixgbe_info ixgbe_X550EM_x_info = { 4113 .mac = ixgbe_mac_X550EM_x, 4114 .get_invariants = &ixgbe_get_invariants_X550_x, 4115 .mac_ops = &mac_ops_X550EM_x, 4116 .eeprom_ops = &eeprom_ops_X550EM_x, 4117 .phy_ops = &phy_ops_X550EM_x, 4118 .mbx_ops = &mbx_ops_generic, 4119 .mvals = ixgbe_mvals_X550EM_x, 4120 .link_ops = &link_ops_x550em_x, 4121 }; 4122 4123 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4124 .mac = ixgbe_mac_X550EM_x, 4125 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4126 .mac_ops = &mac_ops_X550EM_x_fw, 4127 .eeprom_ops = &eeprom_ops_X550EM_x, 4128 .phy_ops = &phy_ops_x550em_x_fw, 4129 .mbx_ops = &mbx_ops_generic, 4130 .mvals = ixgbe_mvals_X550EM_x, 4131 }; 4132 4133 const struct ixgbe_info ixgbe_x550em_a_info = { 4134 .mac = ixgbe_mac_x550em_a, 4135 .get_invariants = &ixgbe_get_invariants_X550_a, 4136 .mac_ops = &mac_ops_x550em_a, 4137 .eeprom_ops = &eeprom_ops_X550EM_x, 4138 .phy_ops = &phy_ops_x550em_a, 4139 .mbx_ops = &mbx_ops_generic, 4140 .mvals = ixgbe_mvals_x550em_a, 4141 }; 4142 4143 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4144 .mac = ixgbe_mac_x550em_a, 4145 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4146 .mac_ops = &mac_ops_x550em_a_fw, 4147 .eeprom_ops = &eeprom_ops_X550EM_x, 4148 .phy_ops = &phy_ops_x550em_a_fw, 4149 .mbx_ops = &mbx_ops_generic, 4150 .mvals = ixgbe_mvals_x550em_a, 4151 }; 4152