1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 30 * @hw: pointer to hardware structure 31 * 32 * Returns error code 33 */ 34 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 35 { 36 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 37 38 switch (hw->device_id) { 39 case IXGBE_DEV_ID_X550EM_X_SFP: 40 /* set up for CS4227 usage */ 41 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 42 if (hw->bus.lan_id) { 43 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 44 esdp |= IXGBE_ESDP_SDP1_DIR; 45 } 46 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 47 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 48 49 return ixgbe_identify_module_generic(hw); 50 case IXGBE_DEV_ID_X550EM_X_KX4: 51 hw->phy.type = ixgbe_phy_x550em_kx4; 52 break; 53 case IXGBE_DEV_ID_X550EM_X_KR: 54 hw->phy.type = ixgbe_phy_x550em_kr; 55 break; 56 case IXGBE_DEV_ID_X550EM_X_1G_T: 57 case IXGBE_DEV_ID_X550EM_X_10G_T: 58 return ixgbe_identify_phy_generic(hw); 59 default: 60 break; 61 } 62 return 0; 63 } 64 65 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 66 u32 device_type, u16 *phy_data) 67 { 68 return IXGBE_NOT_IMPLEMENTED; 69 } 70 71 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 72 u32 device_type, u16 phy_data) 73 { 74 return IXGBE_NOT_IMPLEMENTED; 75 } 76 77 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 78 * @hw: pointer to hardware structure 79 * 80 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 81 * ixgbe_hw struct in order to set up EEPROM access. 82 **/ 83 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 84 { 85 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 86 u32 eec; 87 u16 eeprom_size; 88 89 if (eeprom->type == ixgbe_eeprom_uninitialized) { 90 eeprom->semaphore_delay = 10; 91 eeprom->type = ixgbe_flash; 92 93 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 94 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 95 IXGBE_EEC_SIZE_SHIFT); 96 eeprom->word_size = 1 << (eeprom_size + 97 IXGBE_EEPROM_WORD_SIZE_SHIFT); 98 99 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 100 eeprom->type, eeprom->word_size); 101 } 102 103 return 0; 104 } 105 106 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 107 * IOSF device 108 * @hw: pointer to hardware structure 109 * @reg_addr: 32 bit PHY register to write 110 * @device_type: 3 bit device type 111 * @phy_data: Pointer to read data from the register 112 **/ 113 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 114 u32 device_type, u32 *data) 115 { 116 u32 i, command, error; 117 118 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 119 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 120 121 /* Write IOSF control register */ 122 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 123 124 /* Check every 10 usec to see if the address cycle completed. 125 * The SB IOSF BUSY bit will clear when the operation is 126 * complete 127 */ 128 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 129 usleep_range(10, 20); 130 131 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 132 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 133 break; 134 } 135 136 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 137 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 138 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 139 hw_dbg(hw, "Failed to read, error %x\n", error); 140 return IXGBE_ERR_PHY; 141 } 142 143 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 144 hw_dbg(hw, "Read timed out\n"); 145 return IXGBE_ERR_PHY; 146 } 147 148 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 149 150 return 0; 151 } 152 153 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface 154 * command assuming that the semaphore is already obtained. 155 * @hw: pointer to hardware structure 156 * @offset: offset of word in the EEPROM to read 157 * @data: word read from the EEPROM 158 * 159 * Reads a 16 bit word from the EEPROM using the hostif. 160 **/ 161 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 162 { 163 s32 status; 164 struct ixgbe_hic_read_shadow_ram buffer; 165 166 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 167 buffer.hdr.req.buf_lenh = 0; 168 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 169 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 170 171 /* convert offset from words to bytes */ 172 buffer.address = cpu_to_be32(offset * 2); 173 /* one word */ 174 buffer.length = cpu_to_be16(sizeof(u16)); 175 176 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 177 sizeof(buffer), 178 IXGBE_HI_COMMAND_TIMEOUT, false); 179 if (status) 180 return status; 181 182 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 183 FW_NVM_DATA_OFFSET); 184 185 return 0; 186 } 187 188 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 189 * @hw: pointer to hardware structure 190 * @offset: offset of word in the EEPROM to read 191 * @words: number of words 192 * @data: word(s) read from the EEPROM 193 * 194 * Reads a 16 bit word(s) from the EEPROM using the hostif. 195 **/ 196 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 197 u16 offset, u16 words, u16 *data) 198 { 199 struct ixgbe_hic_read_shadow_ram buffer; 200 u32 current_word = 0; 201 u16 words_to_read; 202 s32 status; 203 u32 i; 204 205 /* Take semaphore for the entire operation. */ 206 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 207 if (status) { 208 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 209 return status; 210 } 211 212 while (words) { 213 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 214 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 215 else 216 words_to_read = words; 217 218 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 219 buffer.hdr.req.buf_lenh = 0; 220 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 221 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 222 223 /* convert offset from words to bytes */ 224 buffer.address = cpu_to_be32((offset + current_word) * 2); 225 buffer.length = cpu_to_be16(words_to_read * 2); 226 227 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 228 sizeof(buffer), 229 IXGBE_HI_COMMAND_TIMEOUT, 230 false); 231 if (status) { 232 hw_dbg(hw, "Host interface command failed\n"); 233 goto out; 234 } 235 236 for (i = 0; i < words_to_read; i++) { 237 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 238 2 * i; 239 u32 value = IXGBE_READ_REG(hw, reg); 240 241 data[current_word] = (u16)(value & 0xffff); 242 current_word++; 243 i++; 244 if (i < words_to_read) { 245 value >>= 16; 246 data[current_word] = (u16)(value & 0xffff); 247 current_word++; 248 } 249 } 250 words -= words_to_read; 251 } 252 253 out: 254 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 255 return status; 256 } 257 258 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 259 * @hw: pointer to hardware structure 260 * @ptr: pointer offset in eeprom 261 * @size: size of section pointed by ptr, if 0 first word will be used as size 262 * @csum: address of checksum to update 263 * 264 * Returns error status for any failure 265 **/ 266 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 267 u16 size, u16 *csum, u16 *buffer, 268 u32 buffer_size) 269 { 270 u16 buf[256]; 271 s32 status; 272 u16 length, bufsz, i, start; 273 u16 *local_buffer; 274 275 bufsz = sizeof(buf) / sizeof(buf[0]); 276 277 /* Read a chunk at the pointer location */ 278 if (!buffer) { 279 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 280 if (status) { 281 hw_dbg(hw, "Failed to read EEPROM image\n"); 282 return status; 283 } 284 local_buffer = buf; 285 } else { 286 if (buffer_size < ptr) 287 return IXGBE_ERR_PARAM; 288 local_buffer = &buffer[ptr]; 289 } 290 291 if (size) { 292 start = 0; 293 length = size; 294 } else { 295 start = 1; 296 length = local_buffer[0]; 297 298 /* Skip pointer section if length is invalid. */ 299 if (length == 0xFFFF || length == 0 || 300 (ptr + length) >= hw->eeprom.word_size) 301 return 0; 302 } 303 304 if (buffer && ((u32)start + (u32)length > buffer_size)) 305 return IXGBE_ERR_PARAM; 306 307 for (i = start; length; i++, length--) { 308 if (i == bufsz && !buffer) { 309 ptr += bufsz; 310 i = 0; 311 if (length < bufsz) 312 bufsz = length; 313 314 /* Read a chunk at the pointer location */ 315 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 316 bufsz, buf); 317 if (status) { 318 hw_dbg(hw, "Failed to read EEPROM image\n"); 319 return status; 320 } 321 } 322 *csum += local_buffer[i]; 323 } 324 return 0; 325 } 326 327 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 328 * @hw: pointer to hardware structure 329 * @buffer: pointer to buffer containing calculated checksum 330 * @buffer_size: size of buffer 331 * 332 * Returns a negative error code on error, or the 16-bit checksum 333 **/ 334 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 335 { 336 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 337 u16 *local_buffer; 338 s32 status; 339 u16 checksum = 0; 340 u16 pointer, i, size; 341 342 hw->eeprom.ops.init_params(hw); 343 344 if (!buffer) { 345 /* Read pointer area */ 346 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 347 IXGBE_EEPROM_LAST_WORD + 1, 348 eeprom_ptrs); 349 if (status) { 350 hw_dbg(hw, "Failed to read EEPROM image\n"); 351 return status; 352 } 353 local_buffer = eeprom_ptrs; 354 } else { 355 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 356 return IXGBE_ERR_PARAM; 357 local_buffer = buffer; 358 } 359 360 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 361 * checksum word itself 362 */ 363 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 364 if (i != IXGBE_EEPROM_CHECKSUM) 365 checksum += local_buffer[i]; 366 367 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 368 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 369 */ 370 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 371 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 372 continue; 373 374 pointer = local_buffer[i]; 375 376 /* Skip pointer section if the pointer is invalid. */ 377 if (pointer == 0xFFFF || pointer == 0 || 378 pointer >= hw->eeprom.word_size) 379 continue; 380 381 switch (i) { 382 case IXGBE_PCIE_GENERAL_PTR: 383 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 384 break; 385 case IXGBE_PCIE_CONFIG0_PTR: 386 case IXGBE_PCIE_CONFIG1_PTR: 387 size = IXGBE_PCIE_CONFIG_SIZE; 388 break; 389 default: 390 size = 0; 391 break; 392 } 393 394 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 395 buffer, buffer_size); 396 if (status) 397 return status; 398 } 399 400 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 401 402 return (s32)checksum; 403 } 404 405 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 406 * @hw: pointer to hardware structure 407 * 408 * Returns a negative error code on error, or the 16-bit checksum 409 **/ 410 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 411 { 412 return ixgbe_calc_checksum_X550(hw, NULL, 0); 413 } 414 415 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 416 * @hw: pointer to hardware structure 417 * @offset: offset of word in the EEPROM to read 418 * @data: word read from the EEPROM 419 * 420 * Reads a 16 bit word from the EEPROM using the hostif. 421 **/ 422 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 423 { 424 s32 status = 0; 425 426 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 427 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 428 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 429 } else { 430 status = IXGBE_ERR_SWFW_SYNC; 431 } 432 433 return status; 434 } 435 436 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 437 * @hw: pointer to hardware structure 438 * @checksum_val: calculated checksum 439 * 440 * Performs checksum calculation and validates the EEPROM checksum. If the 441 * caller does not need checksum_val, the value can be NULL. 442 **/ 443 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 444 { 445 s32 status; 446 u16 checksum; 447 u16 read_checksum = 0; 448 449 /* Read the first word from the EEPROM. If this times out or fails, do 450 * not continue or we could be in for a very long wait while every 451 * EEPROM read fails 452 */ 453 status = hw->eeprom.ops.read(hw, 0, &checksum); 454 if (status) { 455 hw_dbg(hw, "EEPROM read failed\n"); 456 return status; 457 } 458 459 status = hw->eeprom.ops.calc_checksum(hw); 460 if (status < 0) 461 return status; 462 463 checksum = (u16)(status & 0xffff); 464 465 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 466 &read_checksum); 467 if (status) 468 return status; 469 470 /* Verify read checksum from EEPROM is the same as 471 * calculated checksum 472 */ 473 if (read_checksum != checksum) { 474 status = IXGBE_ERR_EEPROM_CHECKSUM; 475 hw_dbg(hw, "Invalid EEPROM checksum"); 476 } 477 478 /* If the user cares, return the calculated checksum */ 479 if (checksum_val) 480 *checksum_val = checksum; 481 482 return status; 483 } 484 485 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 486 * @hw: pointer to hardware structure 487 * @offset: offset of word in the EEPROM to write 488 * @data: word write to the EEPROM 489 * 490 * Write a 16 bit word to the EEPROM using the hostif. 491 **/ 492 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 493 { 494 s32 status; 495 struct ixgbe_hic_write_shadow_ram buffer; 496 497 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 498 buffer.hdr.req.buf_lenh = 0; 499 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 500 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 501 502 /* one word */ 503 buffer.length = cpu_to_be16(sizeof(u16)); 504 buffer.data = data; 505 buffer.address = cpu_to_be32(offset * 2); 506 507 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 508 sizeof(buffer), 509 IXGBE_HI_COMMAND_TIMEOUT, false); 510 return status; 511 } 512 513 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 514 * @hw: pointer to hardware structure 515 * @offset: offset of word in the EEPROM to write 516 * @data: word write to the EEPROM 517 * 518 * Write a 16 bit word to the EEPROM using the hostif. 519 **/ 520 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 521 { 522 s32 status = 0; 523 524 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 525 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 526 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 527 } else { 528 hw_dbg(hw, "write ee hostif failed to get semaphore"); 529 status = IXGBE_ERR_SWFW_SYNC; 530 } 531 532 return status; 533 } 534 535 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 536 * @hw: pointer to hardware structure 537 * 538 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 539 **/ 540 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 541 { 542 s32 status = 0; 543 union ixgbe_hic_hdr2 buffer; 544 545 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 546 buffer.req.buf_lenh = 0; 547 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 548 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 549 550 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 551 sizeof(buffer), 552 IXGBE_HI_COMMAND_TIMEOUT, false); 553 return status; 554 } 555 556 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 557 * @hw: pointer to hardware structure 558 * 559 * After writing EEPROM to shadow RAM using EEWR register, software calculates 560 * checksum and updates the EEPROM and instructs the hardware to update 561 * the flash. 562 **/ 563 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 564 { 565 s32 status; 566 u16 checksum = 0; 567 568 /* Read the first word from the EEPROM. If this times out or fails, do 569 * not continue or we could be in for a very long wait while every 570 * EEPROM read fails 571 */ 572 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 573 if (status) { 574 hw_dbg(hw, "EEPROM read failed\n"); 575 return status; 576 } 577 578 status = ixgbe_calc_eeprom_checksum_X550(hw); 579 if (status < 0) 580 return status; 581 582 checksum = (u16)(status & 0xffff); 583 584 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 585 checksum); 586 if (status) 587 return status; 588 589 status = ixgbe_update_flash_X550(hw); 590 591 return status; 592 } 593 594 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 595 * @hw: pointer to hardware structure 596 * @offset: offset of word in the EEPROM to write 597 * @words: number of words 598 * @data: word(s) write to the EEPROM 599 * 600 * 601 * Write a 16 bit word(s) to the EEPROM using the hostif. 602 **/ 603 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 604 u16 offset, u16 words, u16 *data) 605 { 606 s32 status = 0; 607 u32 i = 0; 608 609 /* Take semaphore for the entire operation. */ 610 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 611 if (status) { 612 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 613 return status; 614 } 615 616 for (i = 0; i < words; i++) { 617 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 618 data[i]); 619 if (status) { 620 hw_dbg(hw, "Eeprom buffered write failed\n"); 621 break; 622 } 623 } 624 625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 626 627 return status; 628 } 629 630 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 631 * @hw: pointer to hardware structure 632 **/ 633 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 634 { 635 struct ixgbe_mac_info *mac = &hw->mac; 636 637 /* CS4227 does not support autoneg, so disable the laser control 638 * functions for SFP+ fiber 639 */ 640 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) { 641 mac->ops.disable_tx_laser = NULL; 642 mac->ops.enable_tx_laser = NULL; 643 mac->ops.flap_tx_laser = NULL; 644 } 645 } 646 647 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 648 * @hw: pointer to hardware structure 649 */ 650 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 651 { 652 bool setup_linear; 653 u16 reg_slice, edc_mode; 654 s32 ret_val; 655 656 switch (hw->phy.sfp_type) { 657 case ixgbe_sfp_type_unknown: 658 return 0; 659 case ixgbe_sfp_type_not_present: 660 return IXGBE_ERR_SFP_NOT_PRESENT; 661 case ixgbe_sfp_type_da_cu_core0: 662 case ixgbe_sfp_type_da_cu_core1: 663 setup_linear = true; 664 break; 665 case ixgbe_sfp_type_srlr_core0: 666 case ixgbe_sfp_type_srlr_core1: 667 case ixgbe_sfp_type_da_act_lmt_core0: 668 case ixgbe_sfp_type_da_act_lmt_core1: 669 case ixgbe_sfp_type_1g_sx_core0: 670 case ixgbe_sfp_type_1g_sx_core1: 671 setup_linear = false; 672 break; 673 default: 674 return IXGBE_ERR_SFP_NOT_SUPPORTED; 675 } 676 677 ixgbe_init_mac_link_ops_X550em(hw); 678 hw->phy.ops.reset = NULL; 679 680 /* The CS4227 slice address is the base address + the port-pair reg 681 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0. 682 */ 683 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12); 684 685 if (setup_linear) 686 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 687 else 688 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 689 690 /* Configure CS4227 for connection type. */ 691 ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 692 edc_mode); 693 694 if (ret_val) 695 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice, 696 edc_mode); 697 698 return ret_val; 699 } 700 701 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 702 * @hw: pointer to hardware structure 703 * @speed: pointer to link speed 704 * @autoneg: true when autoneg or autotry is enabled 705 **/ 706 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 707 ixgbe_link_speed *speed, 708 bool *autoneg) 709 { 710 /* SFP */ 711 if (hw->phy.media_type == ixgbe_media_type_fiber) { 712 /* CS4227 SFP must not enable auto-negotiation */ 713 *autoneg = false; 714 715 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 716 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 717 *speed = IXGBE_LINK_SPEED_1GB_FULL; 718 return 0; 719 } 720 721 /* Link capabilities are based on SFP */ 722 if (hw->phy.multispeed_fiber) 723 *speed = IXGBE_LINK_SPEED_10GB_FULL | 724 IXGBE_LINK_SPEED_1GB_FULL; 725 else 726 *speed = IXGBE_LINK_SPEED_10GB_FULL; 727 } else { 728 *speed = IXGBE_LINK_SPEED_10GB_FULL | 729 IXGBE_LINK_SPEED_1GB_FULL; 730 *autoneg = true; 731 } 732 return 0; 733 } 734 735 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 736 * IOSF device 737 * 738 * @hw: pointer to hardware structure 739 * @reg_addr: 32 bit PHY register to write 740 * @device_type: 3 bit device type 741 * @data: Data to write to the register 742 **/ 743 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 744 u32 device_type, u32 data) 745 { 746 u32 i, command, error; 747 748 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 749 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 750 751 /* Write IOSF control register */ 752 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 753 754 /* Write IOSF data register */ 755 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 756 757 /* Check every 10 usec to see if the address cycle completed. 758 * The SB IOSF BUSY bit will clear when the operation is 759 * complete 760 */ 761 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 762 usleep_range(10, 20); 763 764 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 765 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 766 break; 767 } 768 769 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 770 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 771 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 772 hw_dbg(hw, "Failed to write, error %x\n", error); 773 return IXGBE_ERR_PHY; 774 } 775 776 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 777 hw_dbg(hw, "Write timed out\n"); 778 return IXGBE_ERR_PHY; 779 } 780 781 return 0; 782 } 783 784 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 785 * @hw: pointer to hardware structure 786 * @speed: the link speed to force 787 * 788 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 789 * internal and external PHY at a specific speed, without autonegotiation. 790 **/ 791 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 792 { 793 s32 status; 794 u32 reg_val; 795 796 /* Disable AN and force speed to 10G Serial. */ 797 status = ixgbe_read_iosf_sb_reg_x550(hw, 798 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 799 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 800 if (status) 801 return status; 802 803 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 804 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 805 806 /* Select forced link speed for internal PHY. */ 807 switch (*speed) { 808 case IXGBE_LINK_SPEED_10GB_FULL: 809 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 810 break; 811 case IXGBE_LINK_SPEED_1GB_FULL: 812 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 813 break; 814 default: 815 /* Other link speeds are not supported by internal KR PHY. */ 816 return IXGBE_ERR_LINK_SETUP; 817 } 818 819 status = ixgbe_write_iosf_sb_reg_x550(hw, 820 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 821 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 822 if (status) 823 return status; 824 825 /* Disable training protocol FSM. */ 826 status = ixgbe_read_iosf_sb_reg_x550(hw, 827 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 828 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 829 if (status) 830 return status; 831 832 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 833 status = ixgbe_write_iosf_sb_reg_x550(hw, 834 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 835 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 836 if (status) 837 return status; 838 839 /* Disable Flex from training TXFFE. */ 840 status = ixgbe_read_iosf_sb_reg_x550(hw, 841 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 842 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 843 if (status) 844 return status; 845 846 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 847 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 848 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 849 status = ixgbe_write_iosf_sb_reg_x550(hw, 850 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 851 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 852 if (status) 853 return status; 854 855 status = ixgbe_read_iosf_sb_reg_x550(hw, 856 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 857 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 858 if (status) 859 return status; 860 861 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 862 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 863 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 864 status = ixgbe_write_iosf_sb_reg_x550(hw, 865 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 866 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 867 if (status) 868 return status; 869 870 /* Enable override for coefficients. */ 871 status = ixgbe_read_iosf_sb_reg_x550(hw, 872 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 873 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 874 if (status) 875 return status; 876 877 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 878 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 879 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 880 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 881 status = ixgbe_write_iosf_sb_reg_x550(hw, 882 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 883 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 884 if (status) 885 return status; 886 887 /* Toggle port SW reset by AN reset. */ 888 status = ixgbe_read_iosf_sb_reg_x550(hw, 889 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 890 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 891 if (status) 892 return status; 893 894 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 895 status = ixgbe_write_iosf_sb_reg_x550(hw, 896 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 897 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 898 899 return status; 900 } 901 902 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 903 * @hw: pointer to hardware structure 904 * 905 * Configures the integrated KX4 PHY. 906 **/ 907 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 908 { 909 s32 status; 910 u32 reg_val; 911 912 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 913 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 914 hw->bus.lan_id, ®_val); 915 if (status) 916 return status; 917 918 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 919 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 920 921 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 922 923 /* Advertise 10G support. */ 924 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 925 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 926 927 /* Advertise 1G support. */ 928 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 929 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 930 931 /* Restart auto-negotiation. */ 932 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 933 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 934 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 935 hw->bus.lan_id, reg_val); 936 937 return status; 938 } 939 940 /** ixgbe_setup_kr_x550em - Configure the KR PHY. 941 * @hw: pointer to hardware structure 942 * 943 * Configures the integrated KR PHY. 944 **/ 945 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 946 { 947 s32 status; 948 u32 reg_val; 949 950 status = ixgbe_read_iosf_sb_reg_x550(hw, 951 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 952 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 953 if (status) 954 return status; 955 956 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 957 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ; 958 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 959 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 960 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 961 962 /* Advertise 10G support. */ 963 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 964 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 965 966 /* Advertise 1G support. */ 967 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 968 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 969 970 /* Restart auto-negotiation. */ 971 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 972 status = ixgbe_write_iosf_sb_reg_x550(hw, 973 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 974 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 975 976 return status; 977 } 978 979 /** ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY 980 * @hw: point to hardware structure 981 * 982 * Configures the integrated KR PHY to talk to the external PHY. The base 983 * driver will call this function when it gets notification via interrupt from 984 * the external PHY. This function forces the internal PHY into iXFI mode at 985 * the correct speed. 986 * 987 * A return of a non-zero value indicates an error, and the base driver should 988 * not report link up. 989 **/ 990 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw) 991 { 992 u32 status; 993 u16 lasi, autoneg_status, speed; 994 ixgbe_link_speed force_speed; 995 996 /* Verify that the external link status has changed */ 997 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS, 998 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &lasi); 999 if (status) 1000 return status; 1001 1002 /* If there was no change in link status, we can just exit */ 1003 if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM)) 1004 return 0; 1005 1006 /* we read this twice back to back to indicate current status */ 1007 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1008 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1009 &autoneg_status); 1010 if (status) 1011 return status; 1012 1013 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1014 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1015 &autoneg_status); 1016 if (status) 1017 return status; 1018 1019 /* If link is not up return an error indicating treat link as down */ 1020 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1021 return IXGBE_ERR_INVALID_LINK_SETTINGS; 1022 1023 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1024 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1025 &speed); 1026 1027 /* clear everything but the speed and duplex bits */ 1028 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1029 1030 switch (speed) { 1031 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1032 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1033 break; 1034 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1035 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1036 break; 1037 default: 1038 /* Internal PHY does not support anything else */ 1039 return IXGBE_ERR_INVALID_LINK_SETTINGS; 1040 } 1041 1042 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1043 } 1044 1045 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1046 * @hw: pointer to hardware structure 1047 * 1048 * Initialize any function pointers that were not able to be 1049 * set during init_shared_code because the PHY/SFP type was 1050 * not known. Perform the SFP init if necessary. 1051 **/ 1052 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1053 { 1054 struct ixgbe_phy_info *phy = &hw->phy; 1055 s32 ret_val; 1056 u32 esdp; 1057 1058 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) { 1059 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1060 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1061 1062 if (hw->bus.lan_id) { 1063 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 1064 esdp |= IXGBE_ESDP_SDP1_DIR; 1065 } 1066 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 1067 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 1068 } 1069 1070 /* Identify the PHY or SFP module */ 1071 ret_val = phy->ops.identify(hw); 1072 1073 /* Setup function pointers based on detected SFP module and speeds */ 1074 ixgbe_init_mac_link_ops_X550em(hw); 1075 if (phy->sfp_type != ixgbe_sfp_type_unknown) 1076 phy->ops.reset = NULL; 1077 1078 /* Set functions pointers based on phy type */ 1079 switch (hw->phy.type) { 1080 case ixgbe_phy_x550em_kx4: 1081 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 1082 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1083 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1084 break; 1085 case ixgbe_phy_x550em_kr: 1086 phy->ops.setup_link = ixgbe_setup_kr_x550em; 1087 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1088 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1089 break; 1090 case ixgbe_phy_x550em_ext_t: 1091 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em; 1092 break; 1093 default: 1094 break; 1095 } 1096 return ret_val; 1097 } 1098 1099 /** ixgbe_get_media_type_X550em - Get media type 1100 * @hw: pointer to hardware structure 1101 * 1102 * Returns the media type (fiber, copper, backplane) 1103 * 1104 */ 1105 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1106 { 1107 enum ixgbe_media_type media_type; 1108 1109 /* Detect if there is a copper PHY attached. */ 1110 switch (hw->device_id) { 1111 case IXGBE_DEV_ID_X550EM_X_KR: 1112 case IXGBE_DEV_ID_X550EM_X_KX4: 1113 media_type = ixgbe_media_type_backplane; 1114 break; 1115 case IXGBE_DEV_ID_X550EM_X_SFP: 1116 media_type = ixgbe_media_type_fiber; 1117 break; 1118 case IXGBE_DEV_ID_X550EM_X_1G_T: 1119 case IXGBE_DEV_ID_X550EM_X_10G_T: 1120 media_type = ixgbe_media_type_copper; 1121 break; 1122 default: 1123 media_type = ixgbe_media_type_unknown; 1124 break; 1125 } 1126 return media_type; 1127 } 1128 1129 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1130 ** @hw: pointer to hardware structure 1131 **/ 1132 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1133 { 1134 u32 status; 1135 u16 reg; 1136 u32 retries = 2; 1137 1138 do { 1139 /* decrement retries counter and exit if we hit 0 */ 1140 if (retries < 1) { 1141 hw_dbg(hw, "External PHY not yet finished resetting."); 1142 return IXGBE_ERR_PHY; 1143 } 1144 retries--; 1145 1146 status = hw->phy.ops.read_reg(hw, 1147 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1148 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1149 ®); 1150 if (status) 1151 return status; 1152 1153 /* Verify PHY FW reset has completed */ 1154 } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1); 1155 1156 /* Set port to low power mode */ 1157 status = hw->phy.ops.read_reg(hw, 1158 IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 1159 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1160 ®); 1161 if (status) 1162 return status; 1163 1164 /* Enable the transmitter */ 1165 status = hw->phy.ops.read_reg(hw, 1166 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, 1167 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1168 ®); 1169 if (status) 1170 return status; 1171 1172 reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE; 1173 1174 status = hw->phy.ops.write_reg(hw, 1175 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, 1176 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1177 reg); 1178 if (status) 1179 return status; 1180 1181 /* Un-stall the PHY FW */ 1182 status = hw->phy.ops.read_reg(hw, 1183 IXGBE_MDIO_GLOBAL_RES_PR_10, 1184 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1185 ®); 1186 if (status) 1187 return status; 1188 1189 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1190 1191 status = hw->phy.ops.write_reg(hw, 1192 IXGBE_MDIO_GLOBAL_RES_PR_10, 1193 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1194 reg); 1195 return status; 1196 } 1197 1198 /** ixgbe_reset_hw_X550em - Perform hardware reset 1199 ** @hw: pointer to hardware structure 1200 ** 1201 ** Resets the hardware by resetting the transmit and receive units, masks 1202 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1203 ** reset. 1204 **/ 1205 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1206 { 1207 ixgbe_link_speed link_speed; 1208 s32 status; 1209 u32 ctrl = 0; 1210 u32 i; 1211 bool link_up = false; 1212 1213 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1214 status = hw->mac.ops.stop_adapter(hw); 1215 if (status) 1216 return status; 1217 1218 /* flush pending Tx transactions */ 1219 ixgbe_clear_tx_pending(hw); 1220 1221 /* PHY ops must be identified and initialized prior to reset */ 1222 1223 /* Identify PHY and related function pointers */ 1224 status = hw->phy.ops.init(hw); 1225 1226 /* start the external PHY */ 1227 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1228 status = ixgbe_init_ext_t_x550em(hw); 1229 if (status) 1230 return status; 1231 } 1232 1233 /* Setup SFP module if there is one present. */ 1234 if (hw->phy.sfp_setup_needed) { 1235 status = hw->mac.ops.setup_sfp(hw); 1236 hw->phy.sfp_setup_needed = false; 1237 } 1238 1239 /* Reset PHY */ 1240 if (!hw->phy.reset_disable && hw->phy.ops.reset) 1241 hw->phy.ops.reset(hw); 1242 1243 mac_reset_top: 1244 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1245 * If link reset is used when link is up, it might reset the PHY when 1246 * mng is using it. If link is down or the flag to force full link 1247 * reset is set, then perform link reset. 1248 */ 1249 ctrl = IXGBE_CTRL_LNK_RST; 1250 1251 if (!hw->force_full_reset) { 1252 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1253 if (link_up) 1254 ctrl = IXGBE_CTRL_RST; 1255 } 1256 1257 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1258 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1259 IXGBE_WRITE_FLUSH(hw); 1260 1261 /* Poll for reset bit to self-clear meaning reset is complete */ 1262 for (i = 0; i < 10; i++) { 1263 udelay(1); 1264 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1265 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1266 break; 1267 } 1268 1269 if (ctrl & IXGBE_CTRL_RST_MASK) { 1270 status = IXGBE_ERR_RESET_FAILED; 1271 hw_dbg(hw, "Reset polling failed to complete.\n"); 1272 } 1273 1274 msleep(50); 1275 1276 /* Double resets are required for recovery from certain error 1277 * clear the multicast table. Also reset num_rar_entries to 128, 1278 * since we modify this value when programming the SAN MAC address. 1279 */ 1280 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1281 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1282 goto mac_reset_top; 1283 } 1284 1285 /* Store the permanent mac address */ 1286 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1287 1288 /* Store MAC address from RAR0, clear receive address registers, and 1289 * clear the multicast table. Also reset num_rar_entries to 128, 1290 * since we modify this value when programming the SAN MAC address. 1291 */ 1292 hw->mac.num_rar_entries = 128; 1293 hw->mac.ops.init_rx_addrs(hw); 1294 1295 return status; 1296 } 1297 1298 #define X550_COMMON_MAC \ 1299 .init_hw = &ixgbe_init_hw_generic, \ 1300 .start_hw = &ixgbe_start_hw_X540, \ 1301 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 1302 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 1303 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 1304 .get_device_caps = &ixgbe_get_device_caps_generic, \ 1305 .stop_adapter = &ixgbe_stop_adapter_generic, \ 1306 .get_bus_info = &ixgbe_get_bus_info_generic, \ 1307 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 1308 .read_analog_reg8 = NULL, \ 1309 .write_analog_reg8 = NULL, \ 1310 .set_rxpba = &ixgbe_set_rxpba_generic, \ 1311 .check_link = &ixgbe_check_mac_link_generic, \ 1312 .led_on = &ixgbe_led_on_generic, \ 1313 .led_off = &ixgbe_led_off_generic, \ 1314 .blink_led_start = &ixgbe_blink_led_start_X540, \ 1315 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 1316 .set_rar = &ixgbe_set_rar_generic, \ 1317 .clear_rar = &ixgbe_clear_rar_generic, \ 1318 .set_vmdq = &ixgbe_set_vmdq_generic, \ 1319 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 1320 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 1321 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 1322 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 1323 .enable_mc = &ixgbe_enable_mc_generic, \ 1324 .disable_mc = &ixgbe_disable_mc_generic, \ 1325 .clear_vfta = &ixgbe_clear_vfta_generic, \ 1326 .set_vfta = &ixgbe_set_vfta_generic, \ 1327 .fc_enable = &ixgbe_fc_enable_generic, \ 1328 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \ 1329 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 1330 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 1331 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 1332 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \ 1333 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \ 1334 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 1335 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 1336 .get_thermal_sensor_data = NULL, \ 1337 .init_thermal_sensor_thresh = NULL, \ 1338 .prot_autoc_read = &prot_autoc_read_generic, \ 1339 .prot_autoc_write = &prot_autoc_write_generic, \ 1340 1341 static struct ixgbe_mac_operations mac_ops_X550 = { 1342 X550_COMMON_MAC 1343 .reset_hw = &ixgbe_reset_hw_X540, 1344 .get_media_type = &ixgbe_get_media_type_X540, 1345 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 1346 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 1347 .setup_link = &ixgbe_setup_mac_link_X540, 1348 .set_rxpba = &ixgbe_set_rxpba_generic, 1349 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 1350 .setup_sfp = NULL, 1351 }; 1352 1353 static struct ixgbe_mac_operations mac_ops_X550EM_x = { 1354 X550_COMMON_MAC 1355 .reset_hw = &ixgbe_reset_hw_X550em, 1356 .get_media_type = &ixgbe_get_media_type_X550em, 1357 .get_san_mac_addr = NULL, 1358 .get_wwn_prefix = NULL, 1359 .setup_link = NULL, /* defined later */ 1360 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 1361 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 1362 1363 }; 1364 1365 #define X550_COMMON_EEP \ 1366 .read = &ixgbe_read_ee_hostif_X550, \ 1367 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 1368 .write = &ixgbe_write_ee_hostif_X550, \ 1369 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 1370 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 1371 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 1372 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 1373 1374 static struct ixgbe_eeprom_operations eeprom_ops_X550 = { 1375 X550_COMMON_EEP 1376 .init_params = &ixgbe_init_eeprom_params_X550, 1377 }; 1378 1379 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 1380 X550_COMMON_EEP 1381 .init_params = &ixgbe_init_eeprom_params_X540, 1382 }; 1383 1384 #define X550_COMMON_PHY \ 1385 .identify_sfp = &ixgbe_identify_module_generic, \ 1386 .reset = NULL, \ 1387 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 1388 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 1389 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 1390 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 1391 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 1392 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 1393 .check_overtemp = &ixgbe_tn_check_overtemp, \ 1394 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 1395 1396 static struct ixgbe_phy_operations phy_ops_X550 = { 1397 X550_COMMON_PHY 1398 .init = NULL, 1399 .identify = &ixgbe_identify_phy_generic, 1400 .read_reg = &ixgbe_read_phy_reg_generic, 1401 .write_reg = &ixgbe_write_phy_reg_generic, 1402 .setup_link = &ixgbe_setup_phy_link_generic, 1403 .read_i2c_combined = &ixgbe_read_i2c_combined_generic, 1404 .write_i2c_combined = &ixgbe_write_i2c_combined_generic, 1405 }; 1406 1407 static struct ixgbe_phy_operations phy_ops_X550EM_x = { 1408 X550_COMMON_PHY 1409 .init = &ixgbe_init_phy_ops_X550em, 1410 .identify = &ixgbe_identify_phy_x550em, 1411 .read_reg = NULL, /* defined later */ 1412 .write_reg = NULL, /* defined later */ 1413 .setup_link = NULL, /* defined later */ 1414 }; 1415 1416 struct ixgbe_info ixgbe_X550_info = { 1417 .mac = ixgbe_mac_X550, 1418 .get_invariants = &ixgbe_get_invariants_X540, 1419 .mac_ops = &mac_ops_X550, 1420 .eeprom_ops = &eeprom_ops_X550, 1421 .phy_ops = &phy_ops_X550, 1422 .mbx_ops = &mbx_ops_generic, 1423 }; 1424 1425 struct ixgbe_info ixgbe_X550EM_x_info = { 1426 .mac = ixgbe_mac_X550EM_x, 1427 .get_invariants = &ixgbe_get_invariants_X540, 1428 .mac_ops = &mac_ops_X550EM_x, 1429 .eeprom_ops = &eeprom_ops_X550EM_x, 1430 .phy_ops = &phy_ops_X550EM_x, 1431 .mbx_ops = &mbx_ops_generic, 1432 }; 1433