1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_PHY_H_ 5 #define _IXGBE_PHY_H_ 6 7 #include "ixgbe_type.h" 8 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 9 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 10 11 /* EEPROM byte offsets */ 12 #define IXGBE_SFF_IDENTIFIER 0x0 13 #define IXGBE_SFF_IDENTIFIER_SFP 0x3 14 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 15 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 16 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 17 #define IXGBE_SFF_1GBE_COMP_CODES 0x6 18 #define IXGBE_SFF_10GBE_COMP_CODES 0x3 19 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 20 #define IXGBE_SFF_BITRATE_NOMINAL 0xC 21 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 22 #define IXGBE_SFF_SFF_8472_SWAP 0x5C 23 #define IXGBE_SFF_SFF_8472_COMP 0x5E 24 #define IXGBE_SFF_SFF_8472_OSCB 0x6E 25 #define IXGBE_SFF_SFF_8472_ESCB 0x76 26 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD 27 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 28 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 29 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 30 #define IXGBE_SFF_QSFP_CONNECTOR 0x82 31 #define IXGBE_SFF_QSFP_10GBE_COMP 0x83 32 #define IXGBE_SFF_QSFP_1GBE_COMP 0x86 33 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92 34 #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 35 #define IXGBE_SFF_SM_LENGTH_KM 0xE 36 #define IXGBE_SFF_SM_LENGTH_100M 0xF 37 38 /* Bitmasks */ 39 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 40 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 41 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 42 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 43 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 44 #define IXGBE_SFF_1GBASET_CAPABLE 0x8 45 #define IXGBE_SFF_BASEBX10_CAPABLE 0x40 46 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 47 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 48 #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 49 #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 50 #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 51 #define IXGBE_SFF_ADDRESSING_MODE 0x4 52 #define IXGBE_SFF_DDM_IMPLEMENTED 0x40 53 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 54 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 55 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 56 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 57 #define IXGBE_I2C_EEPROM_READ_MASK 0x100 58 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 59 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 60 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 61 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 62 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 63 #define IXGBE_CS4227 0xBE /* CS4227 address */ 64 #define IXGBE_CS4227_GLOBAL_ID_LSB 0 65 #define IXGBE_CS4227_GLOBAL_ID_MSB 1 66 #define IXGBE_CS4227_SCRATCH 2 67 #define IXGBE_CS4227_EFUSE_PDF_SKU 0x19F 68 #define IXGBE_CS4223_SKU_ID 0x0010 /* Quad port */ 69 #define IXGBE_CS4227_SKU_ID 0x0014 /* Dual port */ 70 #define IXGBE_CS4227_RESET_PENDING 0x1357 71 #define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 72 #define IXGBE_CS4227_RETRIES 15 73 #define IXGBE_CS4227_EFUSE_STATUS 0x0181 74 #define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to set speed */ 75 #define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to set EDC */ 76 #define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to set speed */ 77 #define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */ 78 #define IXGBE_CS4227_EEPROM_STATUS 0x5001 79 #define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001 80 #define IXGBE_CS4227_SPEED_1G 0x8000 81 #define IXGBE_CS4227_SPEED_10G 0 82 #define IXGBE_CS4227_EDC_MODE_CX1 0x0002 83 #define IXGBE_CS4227_EDC_MODE_SR 0x0004 84 #define IXGBE_CS4227_EDC_MODE_DIAG 0x0008 85 #define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */ 86 #define IXGBE_CS4227_RESET_DELAY 500 /* milliseconds */ 87 #define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */ 88 #define IXGBE_PE 0xE0 /* Port expander addr */ 89 #define IXGBE_PE_OUTPUT 1 /* Output reg offset */ 90 #define IXGBE_PE_CONFIG 3 /* Config reg offset */ 91 #define IXGBE_PE_BIT1 BIT(1) 92 93 /* Flow control defines */ 94 #define IXGBE_TAF_SYM_PAUSE 0x400 95 #define IXGBE_TAF_ASM_PAUSE 0x800 96 97 /* Bit-shift macros */ 98 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 99 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 100 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 101 102 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 103 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 104 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 105 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 106 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 107 108 /* I2C SDA and SCL timing parameters for standard mode */ 109 #define IXGBE_I2C_T_HD_STA 4 110 #define IXGBE_I2C_T_LOW 5 111 #define IXGBE_I2C_T_HIGH 4 112 #define IXGBE_I2C_T_SU_STA 5 113 #define IXGBE_I2C_T_HD_DATA 5 114 #define IXGBE_I2C_T_SU_DATA 1 115 #define IXGBE_I2C_T_RISE 1 116 #define IXGBE_I2C_T_FALL 1 117 #define IXGBE_I2C_T_SU_STO 4 118 #define IXGBE_I2C_T_BUF 5 119 120 #define IXGBE_SFP_DETECT_RETRIES 2 121 122 #define IXGBE_TN_LASI_STATUS_REG 0x9005 123 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 124 125 /* SFP+ SFF-8472 Compliance code */ 126 #define IXGBE_SFF_SFF_8472_UNSUP 0x00 127 128 int ixgbe_mii_bus_init(struct ixgbe_hw *hw); 129 130 int ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 131 int ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 132 int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 133 u32 device_type, u16 *phy_data); 134 int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 135 u32 device_type, u16 phy_data); 136 int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 137 u32 device_type, u16 *phy_data); 138 int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 139 u32 device_type, u16 phy_data); 140 int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 141 int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 142 ixgbe_link_speed speed, 143 bool autoneg_wait_to_complete); 144 int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 145 ixgbe_link_speed *speed, 146 bool *autoneg); 147 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw); 148 149 /* PHY specific */ 150 int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 151 ixgbe_link_speed *speed, 152 bool *link_up); 153 int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); 154 155 int ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 156 int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); 157 int ixgbe_identify_module_generic(struct ixgbe_hw *hw); 158 int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 159 int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 160 u16 *list_offset, 161 u16 *data_offset); 162 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); 163 int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 164 u8 dev_addr, u8 *data); 165 int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 166 u8 dev_addr, u8 *data); 167 int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 168 u8 dev_addr, u8 data); 169 int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 170 u8 dev_addr, u8 data); 171 int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 172 u8 *eeprom_data); 173 int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 174 u8 *sff8472_data); 175 int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 176 u8 eeprom_data); 177 int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, 178 u16 *val, bool lock); 179 int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, 180 u16 val, bool lock); 181 #endif /* _IXGBE_PHY_H_ */ 182