1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 36 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 54 * @hw: pointer to the hardware structure 55 * @byte: byte to send 56 * 57 * Returns an error code on error. 58 **/ 59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 60 { 61 s32 status; 62 63 status = ixgbe_clock_out_i2c_byte(hw, byte); 64 if (status) 65 return status; 66 return ixgbe_get_i2c_ack(hw); 67 } 68 69 /** 70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 71 * @hw: pointer to the hardware structure 72 * @byte: pointer to a u8 to receive the byte 73 * 74 * Returns an error code on error. 75 **/ 76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 77 { 78 s32 status; 79 80 status = ixgbe_clock_in_i2c_byte(hw, byte); 81 if (status) 82 return status; 83 /* ACK */ 84 return ixgbe_clock_out_i2c_bit(hw, false); 85 } 86 87 /** 88 * ixgbe_ones_comp_byte_add - Perform one's complement addition 89 * @add1: addend 1 90 * @add2: addend 2 91 * 92 * Returns one's complement 8-bit sum. 93 **/ 94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 95 { 96 u16 sum = add1 + add2; 97 98 sum = (sum & 0xFF) + (sum >> 8); 99 return sum & 0xFF; 100 } 101 102 /** 103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 104 * @hw: pointer to the hardware structure 105 * @addr: I2C bus address to read from 106 * @reg: I2C device register to read from 107 * @val: pointer to location to receive read value 108 * @lock: true if to take and release semaphore 109 * 110 * Returns an error code on error. 111 */ 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 113 u16 reg, u16 *val, bool lock) 114 { 115 u32 swfw_mask = hw->phy.phy_semaphore_mask; 116 int max_retry = 3; 117 int retry = 0; 118 u8 csum_byte; 119 u8 high_bits; 120 u8 low_bits; 121 u8 reg_high; 122 u8 csum; 123 124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 126 csum = ~csum; 127 do { 128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 129 return IXGBE_ERR_SWFW_SYNC; 130 ixgbe_i2c_start(hw); 131 /* Device Address and write indication */ 132 if (ixgbe_out_i2c_byte_ack(hw, addr)) 133 goto fail; 134 /* Write bits 14:8 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 136 goto fail; 137 /* Write bits 7:0 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 139 goto fail; 140 /* Write csum */ 141 if (ixgbe_out_i2c_byte_ack(hw, csum)) 142 goto fail; 143 /* Re-start condition */ 144 ixgbe_i2c_start(hw); 145 /* Device Address and read indication */ 146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 147 goto fail; 148 /* Get upper bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 150 goto fail; 151 /* Get low bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 153 goto fail; 154 /* Get csum */ 155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 156 goto fail; 157 /* NACK */ 158 if (ixgbe_clock_out_i2c_bit(hw, false)) 159 goto fail; 160 ixgbe_i2c_stop(hw); 161 if (lock) 162 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 163 *val = (high_bits << 8) | low_bits; 164 return 0; 165 166 fail: 167 ixgbe_i2c_bus_clear(hw); 168 if (lock) 169 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 170 retry++; 171 if (retry < max_retry) 172 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 173 else 174 hw_dbg(hw, "I2C byte read combined error.\n"); 175 } while (retry < max_retry); 176 177 return IXGBE_ERR_I2C; 178 } 179 180 /** 181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 182 * @hw: pointer to the hardware structure 183 * @addr: I2C bus address to write to 184 * @reg: I2C device register to write to 185 * @val: value to write 186 * @lock: true if to take and release semaphore 187 * 188 * Returns an error code on error. 189 */ 190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 191 u16 reg, u16 val, bool lock) 192 { 193 u32 swfw_mask = hw->phy.phy_semaphore_mask; 194 int max_retry = 1; 195 int retry = 0; 196 u8 reg_high; 197 u8 csum; 198 199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 203 csum = ~csum; 204 do { 205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 206 return IXGBE_ERR_SWFW_SYNC; 207 ixgbe_i2c_start(hw); 208 /* Device Address and write indication */ 209 if (ixgbe_out_i2c_byte_ack(hw, addr)) 210 goto fail; 211 /* Write bits 14:8 */ 212 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 213 goto fail; 214 /* Write bits 7:0 */ 215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 216 goto fail; 217 /* Write data 15:8 */ 218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 219 goto fail; 220 /* Write data 7:0 */ 221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 222 goto fail; 223 /* Write csum */ 224 if (ixgbe_out_i2c_byte_ack(hw, csum)) 225 goto fail; 226 ixgbe_i2c_stop(hw); 227 if (lock) 228 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 229 return 0; 230 231 fail: 232 ixgbe_i2c_bus_clear(hw); 233 if (lock) 234 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 235 retry++; 236 if (retry < max_retry) 237 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 238 else 239 hw_dbg(hw, "I2C byte write combined error.\n"); 240 } while (retry < max_retry); 241 242 return IXGBE_ERR_I2C; 243 } 244 245 /** 246 * ixgbe_probe_phy - Probe a single address for a PHY 247 * @hw: pointer to hardware structure 248 * @phy_addr: PHY address to probe 249 * 250 * Returns true if PHY found 251 **/ 252 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 253 { 254 u16 ext_ability = 0; 255 256 hw->phy.mdio.prtad = phy_addr; 257 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0) 258 return false; 259 260 if (ixgbe_get_phy_id(hw)) 261 return false; 262 263 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 264 265 if (hw->phy.type == ixgbe_phy_unknown) { 266 hw->phy.ops.read_reg(hw, 267 MDIO_PMA_EXTABLE, 268 MDIO_MMD_PMAPMD, 269 &ext_ability); 270 if (ext_ability & 271 (MDIO_PMA_EXTABLE_10GBT | 272 MDIO_PMA_EXTABLE_1000BT)) 273 hw->phy.type = ixgbe_phy_cu_unknown; 274 else 275 hw->phy.type = ixgbe_phy_generic; 276 } 277 278 return true; 279 } 280 281 /** 282 * ixgbe_identify_phy_generic - Get physical layer module 283 * @hw: pointer to hardware structure 284 * 285 * Determines the physical layer module found on the current adapter. 286 **/ 287 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 288 { 289 u32 phy_addr; 290 u32 status = IXGBE_ERR_PHY_ADDR_INVALID; 291 292 if (!hw->phy.phy_semaphore_mask) { 293 if (hw->bus.lan_id) 294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 295 else 296 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 297 } 298 299 if (hw->phy.type != ixgbe_phy_unknown) 300 return 0; 301 302 if (hw->phy.nw_mng_if_sel) { 303 phy_addr = (hw->phy.nw_mng_if_sel & 304 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 305 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 306 if (ixgbe_probe_phy(hw, phy_addr)) 307 return 0; 308 else 309 return IXGBE_ERR_PHY_ADDR_INVALID; 310 } 311 312 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 313 if (ixgbe_probe_phy(hw, phy_addr)) { 314 status = 0; 315 break; 316 } 317 } 318 319 /* Certain media types do not have a phy so an address will not 320 * be found and the code will take this path. Caller has to 321 * decide if it is an error or not. 322 */ 323 if (status) 324 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 325 326 return status; 327 } 328 329 /** 330 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 331 * @hw: pointer to the hardware structure 332 * 333 * This function checks the MMNGC.MNG_VETO bit to see if there are 334 * any constraints on link from manageability. For MAC's that don't 335 * have this bit just return false since the link can not be blocked 336 * via this method. 337 **/ 338 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 339 { 340 u32 mmngc; 341 342 /* If we don't have this bit, it can't be blocking */ 343 if (hw->mac.type == ixgbe_mac_82598EB) 344 return false; 345 346 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 347 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 348 hw_dbg(hw, "MNG_VETO bit detected.\n"); 349 return true; 350 } 351 352 return false; 353 } 354 355 /** 356 * ixgbe_get_phy_id - Get the phy type 357 * @hw: pointer to hardware structure 358 * 359 **/ 360 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 361 { 362 s32 status; 363 u16 phy_id_high = 0; 364 u16 phy_id_low = 0; 365 366 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 367 &phy_id_high); 368 369 if (!status) { 370 hw->phy.id = (u32)(phy_id_high << 16); 371 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 372 &phy_id_low); 373 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 374 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 375 } 376 return status; 377 } 378 379 /** 380 * ixgbe_get_phy_type_from_id - Get the phy type 381 * @hw: pointer to hardware structure 382 * 383 **/ 384 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 385 { 386 enum ixgbe_phy_type phy_type; 387 388 switch (phy_id) { 389 case TN1010_PHY_ID: 390 phy_type = ixgbe_phy_tn; 391 break; 392 case X550_PHY_ID2: 393 case X550_PHY_ID3: 394 case X540_PHY_ID: 395 phy_type = ixgbe_phy_aq; 396 break; 397 case QT2022_PHY_ID: 398 phy_type = ixgbe_phy_qt; 399 break; 400 case ATH_PHY_ID: 401 phy_type = ixgbe_phy_nl; 402 break; 403 case X557_PHY_ID: 404 case X557_PHY_ID2: 405 phy_type = ixgbe_phy_x550em_ext_t; 406 break; 407 default: 408 phy_type = ixgbe_phy_unknown; 409 break; 410 } 411 412 return phy_type; 413 } 414 415 /** 416 * ixgbe_reset_phy_generic - Performs a PHY reset 417 * @hw: pointer to hardware structure 418 **/ 419 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 420 { 421 u32 i; 422 u16 ctrl = 0; 423 s32 status = 0; 424 425 if (hw->phy.type == ixgbe_phy_unknown) 426 status = ixgbe_identify_phy_generic(hw); 427 428 if (status != 0 || hw->phy.type == ixgbe_phy_none) 429 return status; 430 431 /* Don't reset PHY if it's shut down due to overtemp. */ 432 if (!hw->phy.reset_if_overtemp && 433 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 434 return 0; 435 436 /* Blocked by MNG FW so bail */ 437 if (ixgbe_check_reset_blocked(hw)) 438 return 0; 439 440 /* 441 * Perform soft PHY reset to the PHY_XS. 442 * This will cause a soft reset to the PHY 443 */ 444 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 445 MDIO_MMD_PHYXS, 446 MDIO_CTRL1_RESET); 447 448 /* 449 * Poll for reset bit to self-clear indicating reset is complete. 450 * Some PHYs could take up to 3 seconds to complete and need about 451 * 1.7 usec delay after the reset is complete. 452 */ 453 for (i = 0; i < 30; i++) { 454 msleep(100); 455 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 456 status = hw->phy.ops.read_reg(hw, 457 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 458 MDIO_MMD_PMAPMD, &ctrl); 459 if (status) 460 return status; 461 462 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 463 udelay(2); 464 break; 465 } 466 } else { 467 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, 468 MDIO_MMD_PHYXS, &ctrl); 469 if (status) 470 return status; 471 472 if (!(ctrl & MDIO_CTRL1_RESET)) { 473 udelay(2); 474 break; 475 } 476 } 477 } 478 479 if (ctrl & MDIO_CTRL1_RESET) { 480 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 481 return IXGBE_ERR_RESET_FAILED; 482 } 483 484 return 0; 485 } 486 487 /** 488 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 489 * the SWFW lock 490 * @hw: pointer to hardware structure 491 * @reg_addr: 32 bit address of PHY register to read 492 * @phy_data: Pointer to read data from PHY register 493 **/ 494 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 495 u16 *phy_data) 496 { 497 u32 i, data, command; 498 499 /* Setup and write the address cycle command */ 500 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 501 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 502 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 503 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 504 505 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 506 507 /* Check every 10 usec to see if the address cycle completed. 508 * The MDI Command bit will clear when the operation is 509 * complete 510 */ 511 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 512 udelay(10); 513 514 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 515 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 516 break; 517 } 518 519 520 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 521 hw_dbg(hw, "PHY address command did not complete.\n"); 522 return IXGBE_ERR_PHY; 523 } 524 525 /* Address cycle complete, setup and write the read 526 * command 527 */ 528 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 529 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 530 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 531 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 532 533 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 534 535 /* Check every 10 usec to see if the address cycle 536 * completed. The MDI Command bit will clear when the 537 * operation is complete 538 */ 539 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 540 udelay(10); 541 542 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 543 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 544 break; 545 } 546 547 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 548 hw_dbg(hw, "PHY read command didn't complete\n"); 549 return IXGBE_ERR_PHY; 550 } 551 552 /* Read operation is complete. Get the data 553 * from MSRWD 554 */ 555 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 556 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 557 *phy_data = (u16)(data); 558 559 return 0; 560 } 561 562 /** 563 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 564 * using the SWFW lock - this function is needed in most cases 565 * @hw: pointer to hardware structure 566 * @reg_addr: 32 bit address of PHY register to read 567 * @phy_data: Pointer to read data from PHY register 568 **/ 569 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 570 u32 device_type, u16 *phy_data) 571 { 572 s32 status; 573 u32 gssr = hw->phy.phy_semaphore_mask; 574 575 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 576 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 577 phy_data); 578 hw->mac.ops.release_swfw_sync(hw, gssr); 579 } else { 580 return IXGBE_ERR_SWFW_SYNC; 581 } 582 583 return status; 584 } 585 586 /** 587 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 588 * without SWFW lock 589 * @hw: pointer to hardware structure 590 * @reg_addr: 32 bit PHY register to write 591 * @device_type: 5 bit device type 592 * @phy_data: Data to write to the PHY register 593 **/ 594 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 595 u32 device_type, u16 phy_data) 596 { 597 u32 i, command; 598 599 /* Put the data in the MDI single read and write data register*/ 600 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 601 602 /* Setup and write the address cycle command */ 603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 604 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 605 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 606 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 607 608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 609 610 /* 611 * Check every 10 usec to see if the address cycle completed. 612 * The MDI Command bit will clear when the operation is 613 * complete 614 */ 615 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 616 udelay(10); 617 618 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 619 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 620 break; 621 } 622 623 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 624 hw_dbg(hw, "PHY address cmd didn't complete\n"); 625 return IXGBE_ERR_PHY; 626 } 627 628 /* 629 * Address cycle complete, setup and write the write 630 * command 631 */ 632 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 633 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 634 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 635 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 636 637 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 638 639 /* Check every 10 usec to see if the address cycle 640 * completed. The MDI Command bit will clear when the 641 * operation is complete 642 */ 643 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 644 udelay(10); 645 646 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 647 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 648 break; 649 } 650 651 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 652 hw_dbg(hw, "PHY write cmd didn't complete\n"); 653 return IXGBE_ERR_PHY; 654 } 655 656 return 0; 657 } 658 659 /** 660 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 661 * using SWFW lock- this function is needed in most cases 662 * @hw: pointer to hardware structure 663 * @reg_addr: 32 bit PHY register to write 664 * @device_type: 5 bit device type 665 * @phy_data: Data to write to the PHY register 666 **/ 667 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 668 u32 device_type, u16 phy_data) 669 { 670 s32 status; 671 u32 gssr = hw->phy.phy_semaphore_mask; 672 673 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 674 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 675 phy_data); 676 hw->mac.ops.release_swfw_sync(hw, gssr); 677 } else { 678 return IXGBE_ERR_SWFW_SYNC; 679 } 680 681 return status; 682 } 683 684 /** 685 * ixgbe_setup_phy_link_generic - Set and restart autoneg 686 * @hw: pointer to hardware structure 687 * 688 * Restart autonegotiation and PHY and waits for completion. 689 **/ 690 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 691 { 692 s32 status = 0; 693 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 694 bool autoneg = false; 695 ixgbe_link_speed speed; 696 697 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 698 699 /* Set or unset auto-negotiation 10G advertisement */ 700 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); 701 702 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 703 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 704 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 705 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 706 707 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); 708 709 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 710 MDIO_MMD_AN, &autoneg_reg); 711 712 if (hw->mac.type == ixgbe_mac_X550) { 713 /* Set or unset auto-negotiation 5G advertisement */ 714 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 715 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 716 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 717 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 718 719 /* Set or unset auto-negotiation 2.5G advertisement */ 720 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 721 if ((hw->phy.autoneg_advertised & 722 IXGBE_LINK_SPEED_2_5GB_FULL) && 723 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 724 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 725 } 726 727 /* Set or unset auto-negotiation 1G advertisement */ 728 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 729 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 730 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 731 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 732 733 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 734 MDIO_MMD_AN, autoneg_reg); 735 736 /* Set or unset auto-negotiation 100M advertisement */ 737 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); 738 739 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF); 740 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 741 (speed & IXGBE_LINK_SPEED_100_FULL)) 742 autoneg_reg |= ADVERTISE_100FULL; 743 744 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); 745 746 /* Blocked by MNG FW so don't reset PHY */ 747 if (ixgbe_check_reset_blocked(hw)) 748 return 0; 749 750 /* Restart PHY autonegotiation and wait for completion */ 751 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 752 MDIO_MMD_AN, &autoneg_reg); 753 754 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 755 756 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 757 MDIO_MMD_AN, autoneg_reg); 758 759 return status; 760 } 761 762 /** 763 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 764 * @hw: pointer to hardware structure 765 * @speed: new link speed 766 **/ 767 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 768 ixgbe_link_speed speed, 769 bool autoneg_wait_to_complete) 770 { 771 772 /* 773 * Clear autoneg_advertised and set new values based on input link 774 * speed. 775 */ 776 hw->phy.autoneg_advertised = 0; 777 778 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 779 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 780 781 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 782 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 783 784 if (speed & IXGBE_LINK_SPEED_100_FULL) 785 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 786 787 if (speed & IXGBE_LINK_SPEED_10_FULL) 788 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 789 790 /* Setup link based on the new speed settings */ 791 hw->phy.ops.setup_link(hw); 792 793 return 0; 794 } 795 796 /** 797 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy 798 * @hw: pointer to hardware structure 799 * 800 * Determines the supported link capabilities by reading the PHY auto 801 * negotiation register. 802 */ 803 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 804 { 805 u16 speed_ability; 806 s32 status; 807 808 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 809 &speed_ability); 810 if (status) 811 return status; 812 813 if (speed_ability & MDIO_SPEED_10G) 814 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 815 if (speed_ability & MDIO_PMA_SPEED_1000) 816 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 817 if (speed_ability & MDIO_PMA_SPEED_100) 818 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 819 820 switch (hw->mac.type) { 821 case ixgbe_mac_X550: 822 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 823 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 824 break; 825 case ixgbe_mac_X550EM_x: 826 case ixgbe_mac_x550em_a: 827 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 828 break; 829 default: 830 break; 831 } 832 833 return 0; 834 } 835 836 /** 837 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 838 * @hw: pointer to hardware structure 839 * @speed: pointer to link speed 840 * @autoneg: boolean auto-negotiation value 841 */ 842 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 843 ixgbe_link_speed *speed, 844 bool *autoneg) 845 { 846 s32 status = 0; 847 848 *autoneg = true; 849 if (!hw->phy.speeds_supported) 850 status = ixgbe_get_copper_speeds_supported(hw); 851 852 *speed = hw->phy.speeds_supported; 853 return status; 854 } 855 856 /** 857 * ixgbe_check_phy_link_tnx - Determine link and speed status 858 * @hw: pointer to hardware structure 859 * 860 * Reads the VS1 register to determine if link is up and the current speed for 861 * the PHY. 862 **/ 863 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 864 bool *link_up) 865 { 866 s32 status; 867 u32 time_out; 868 u32 max_time_out = 10; 869 u16 phy_link = 0; 870 u16 phy_speed = 0; 871 u16 phy_data = 0; 872 873 /* Initialize speed and link to default case */ 874 *link_up = false; 875 *speed = IXGBE_LINK_SPEED_10GB_FULL; 876 877 /* 878 * Check current speed and link status of the PHY register. 879 * This is a vendor specific register and may have to 880 * be changed for other copper PHYs. 881 */ 882 for (time_out = 0; time_out < max_time_out; time_out++) { 883 udelay(10); 884 status = hw->phy.ops.read_reg(hw, 885 MDIO_STAT1, 886 MDIO_MMD_VEND1, 887 &phy_data); 888 phy_link = phy_data & 889 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 890 phy_speed = phy_data & 891 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 892 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 893 *link_up = true; 894 if (phy_speed == 895 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 896 *speed = IXGBE_LINK_SPEED_1GB_FULL; 897 break; 898 } 899 } 900 901 return status; 902 } 903 904 /** 905 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 906 * @hw: pointer to hardware structure 907 * 908 * Restart autonegotiation and PHY and waits for completion. 909 * This function always returns success, this is nessary since 910 * it is called via a function pointer that could call other 911 * functions that could return an error. 912 **/ 913 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 914 { 915 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 916 bool autoneg = false; 917 ixgbe_link_speed speed; 918 919 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 920 921 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 922 /* Set or unset auto-negotiation 10G advertisement */ 923 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 924 MDIO_MMD_AN, 925 &autoneg_reg); 926 927 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 928 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 929 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 930 931 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 932 MDIO_MMD_AN, 933 autoneg_reg); 934 } 935 936 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 937 /* Set or unset auto-negotiation 1G advertisement */ 938 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 939 MDIO_MMD_AN, 940 &autoneg_reg); 941 942 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 943 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 944 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 945 946 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 947 MDIO_MMD_AN, 948 autoneg_reg); 949 } 950 951 if (speed & IXGBE_LINK_SPEED_100_FULL) { 952 /* Set or unset auto-negotiation 100M advertisement */ 953 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 954 MDIO_MMD_AN, 955 &autoneg_reg); 956 957 autoneg_reg &= ~(ADVERTISE_100FULL | 958 ADVERTISE_100HALF); 959 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 960 autoneg_reg |= ADVERTISE_100FULL; 961 962 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 963 MDIO_MMD_AN, 964 autoneg_reg); 965 } 966 967 /* Blocked by MNG FW so don't reset PHY */ 968 if (ixgbe_check_reset_blocked(hw)) 969 return 0; 970 971 /* Restart PHY autonegotiation and wait for completion */ 972 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 973 MDIO_MMD_AN, &autoneg_reg); 974 975 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 976 977 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 978 MDIO_MMD_AN, autoneg_reg); 979 return 0; 980 } 981 982 /** 983 * ixgbe_reset_phy_nl - Performs a PHY reset 984 * @hw: pointer to hardware structure 985 **/ 986 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 987 { 988 u16 phy_offset, control, eword, edata, block_crc; 989 bool end_data = false; 990 u16 list_offset, data_offset; 991 u16 phy_data = 0; 992 s32 ret_val; 993 u32 i; 994 995 /* Blocked by MNG FW so bail */ 996 if (ixgbe_check_reset_blocked(hw)) 997 return 0; 998 999 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 1000 1001 /* reset the PHY and poll for completion */ 1002 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1003 (phy_data | MDIO_CTRL1_RESET)); 1004 1005 for (i = 0; i < 100; i++) { 1006 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1007 &phy_data); 1008 if ((phy_data & MDIO_CTRL1_RESET) == 0) 1009 break; 1010 usleep_range(10000, 20000); 1011 } 1012 1013 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 1014 hw_dbg(hw, "PHY reset did not complete.\n"); 1015 return IXGBE_ERR_PHY; 1016 } 1017 1018 /* Get init offsets */ 1019 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1020 &data_offset); 1021 if (ret_val) 1022 return ret_val; 1023 1024 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1025 data_offset++; 1026 while (!end_data) { 1027 /* 1028 * Read control word from PHY init contents offset 1029 */ 1030 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1031 if (ret_val) 1032 goto err_eeprom; 1033 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1034 IXGBE_CONTROL_SHIFT_NL; 1035 edata = eword & IXGBE_DATA_MASK_NL; 1036 switch (control) { 1037 case IXGBE_DELAY_NL: 1038 data_offset++; 1039 hw_dbg(hw, "DELAY: %d MS\n", edata); 1040 usleep_range(edata * 1000, edata * 2000); 1041 break; 1042 case IXGBE_DATA_NL: 1043 hw_dbg(hw, "DATA:\n"); 1044 data_offset++; 1045 ret_val = hw->eeprom.ops.read(hw, data_offset++, 1046 &phy_offset); 1047 if (ret_val) 1048 goto err_eeprom; 1049 for (i = 0; i < edata; i++) { 1050 ret_val = hw->eeprom.ops.read(hw, data_offset, 1051 &eword); 1052 if (ret_val) 1053 goto err_eeprom; 1054 hw->phy.ops.write_reg(hw, phy_offset, 1055 MDIO_MMD_PMAPMD, eword); 1056 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1057 phy_offset); 1058 data_offset++; 1059 phy_offset++; 1060 } 1061 break; 1062 case IXGBE_CONTROL_NL: 1063 data_offset++; 1064 hw_dbg(hw, "CONTROL:\n"); 1065 if (edata == IXGBE_CONTROL_EOL_NL) { 1066 hw_dbg(hw, "EOL\n"); 1067 end_data = true; 1068 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1069 hw_dbg(hw, "SOL\n"); 1070 } else { 1071 hw_dbg(hw, "Bad control value\n"); 1072 return IXGBE_ERR_PHY; 1073 } 1074 break; 1075 default: 1076 hw_dbg(hw, "Bad control type\n"); 1077 return IXGBE_ERR_PHY; 1078 } 1079 } 1080 1081 return ret_val; 1082 1083 err_eeprom: 1084 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1085 return IXGBE_ERR_PHY; 1086 } 1087 1088 /** 1089 * ixgbe_identify_module_generic - Identifies module type 1090 * @hw: pointer to hardware structure 1091 * 1092 * Determines HW type and calls appropriate function. 1093 **/ 1094 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1095 { 1096 switch (hw->mac.ops.get_media_type(hw)) { 1097 case ixgbe_media_type_fiber: 1098 return ixgbe_identify_sfp_module_generic(hw); 1099 case ixgbe_media_type_fiber_qsfp: 1100 return ixgbe_identify_qsfp_module_generic(hw); 1101 default: 1102 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1103 return IXGBE_ERR_SFP_NOT_PRESENT; 1104 } 1105 1106 return IXGBE_ERR_SFP_NOT_PRESENT; 1107 } 1108 1109 /** 1110 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1111 * @hw: pointer to hardware structure 1112 * 1113 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1114 **/ 1115 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1116 { 1117 struct ixgbe_adapter *adapter = hw->back; 1118 s32 status; 1119 u32 vendor_oui = 0; 1120 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1121 u8 identifier = 0; 1122 u8 comp_codes_1g = 0; 1123 u8 comp_codes_10g = 0; 1124 u8 oui_bytes[3] = {0, 0, 0}; 1125 u8 cable_tech = 0; 1126 u8 cable_spec = 0; 1127 u16 enforce_sfp = 0; 1128 1129 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1130 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1131 return IXGBE_ERR_SFP_NOT_PRESENT; 1132 } 1133 1134 /* LAN ID is needed for sfp_type determination */ 1135 hw->mac.ops.set_lan_id(hw); 1136 1137 status = hw->phy.ops.read_i2c_eeprom(hw, 1138 IXGBE_SFF_IDENTIFIER, 1139 &identifier); 1140 1141 if (status) 1142 goto err_read_i2c_eeprom; 1143 1144 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1145 hw->phy.type = ixgbe_phy_sfp_unsupported; 1146 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1147 } 1148 status = hw->phy.ops.read_i2c_eeprom(hw, 1149 IXGBE_SFF_1GBE_COMP_CODES, 1150 &comp_codes_1g); 1151 1152 if (status) 1153 goto err_read_i2c_eeprom; 1154 1155 status = hw->phy.ops.read_i2c_eeprom(hw, 1156 IXGBE_SFF_10GBE_COMP_CODES, 1157 &comp_codes_10g); 1158 1159 if (status) 1160 goto err_read_i2c_eeprom; 1161 status = hw->phy.ops.read_i2c_eeprom(hw, 1162 IXGBE_SFF_CABLE_TECHNOLOGY, 1163 &cable_tech); 1164 1165 if (status) 1166 goto err_read_i2c_eeprom; 1167 1168 /* ID Module 1169 * ========= 1170 * 0 SFP_DA_CU 1171 * 1 SFP_SR 1172 * 2 SFP_LR 1173 * 3 SFP_DA_CORE0 - 82599-specific 1174 * 4 SFP_DA_CORE1 - 82599-specific 1175 * 5 SFP_SR/LR_CORE0 - 82599-specific 1176 * 6 SFP_SR/LR_CORE1 - 82599-specific 1177 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1178 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1179 * 9 SFP_1g_cu_CORE0 - 82599-specific 1180 * 10 SFP_1g_cu_CORE1 - 82599-specific 1181 * 11 SFP_1g_sx_CORE0 - 82599-specific 1182 * 12 SFP_1g_sx_CORE1 - 82599-specific 1183 */ 1184 if (hw->mac.type == ixgbe_mac_82598EB) { 1185 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1186 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1187 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1188 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1189 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1190 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1191 else 1192 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1193 } else { 1194 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1195 if (hw->bus.lan_id == 0) 1196 hw->phy.sfp_type = 1197 ixgbe_sfp_type_da_cu_core0; 1198 else 1199 hw->phy.sfp_type = 1200 ixgbe_sfp_type_da_cu_core1; 1201 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1202 hw->phy.ops.read_i2c_eeprom( 1203 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1204 &cable_spec); 1205 if (cable_spec & 1206 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1207 if (hw->bus.lan_id == 0) 1208 hw->phy.sfp_type = 1209 ixgbe_sfp_type_da_act_lmt_core0; 1210 else 1211 hw->phy.sfp_type = 1212 ixgbe_sfp_type_da_act_lmt_core1; 1213 } else { 1214 hw->phy.sfp_type = 1215 ixgbe_sfp_type_unknown; 1216 } 1217 } else if (comp_codes_10g & 1218 (IXGBE_SFF_10GBASESR_CAPABLE | 1219 IXGBE_SFF_10GBASELR_CAPABLE)) { 1220 if (hw->bus.lan_id == 0) 1221 hw->phy.sfp_type = 1222 ixgbe_sfp_type_srlr_core0; 1223 else 1224 hw->phy.sfp_type = 1225 ixgbe_sfp_type_srlr_core1; 1226 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1227 if (hw->bus.lan_id == 0) 1228 hw->phy.sfp_type = 1229 ixgbe_sfp_type_1g_cu_core0; 1230 else 1231 hw->phy.sfp_type = 1232 ixgbe_sfp_type_1g_cu_core1; 1233 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1234 if (hw->bus.lan_id == 0) 1235 hw->phy.sfp_type = 1236 ixgbe_sfp_type_1g_sx_core0; 1237 else 1238 hw->phy.sfp_type = 1239 ixgbe_sfp_type_1g_sx_core1; 1240 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1241 if (hw->bus.lan_id == 0) 1242 hw->phy.sfp_type = 1243 ixgbe_sfp_type_1g_lx_core0; 1244 else 1245 hw->phy.sfp_type = 1246 ixgbe_sfp_type_1g_lx_core1; 1247 } else { 1248 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1249 } 1250 } 1251 1252 if (hw->phy.sfp_type != stored_sfp_type) 1253 hw->phy.sfp_setup_needed = true; 1254 1255 /* Determine if the SFP+ PHY is dual speed or not. */ 1256 hw->phy.multispeed_fiber = false; 1257 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1258 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1259 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1260 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1261 hw->phy.multispeed_fiber = true; 1262 1263 /* Determine PHY vendor */ 1264 if (hw->phy.type != ixgbe_phy_nl) { 1265 hw->phy.id = identifier; 1266 status = hw->phy.ops.read_i2c_eeprom(hw, 1267 IXGBE_SFF_VENDOR_OUI_BYTE0, 1268 &oui_bytes[0]); 1269 1270 if (status != 0) 1271 goto err_read_i2c_eeprom; 1272 1273 status = hw->phy.ops.read_i2c_eeprom(hw, 1274 IXGBE_SFF_VENDOR_OUI_BYTE1, 1275 &oui_bytes[1]); 1276 1277 if (status != 0) 1278 goto err_read_i2c_eeprom; 1279 1280 status = hw->phy.ops.read_i2c_eeprom(hw, 1281 IXGBE_SFF_VENDOR_OUI_BYTE2, 1282 &oui_bytes[2]); 1283 1284 if (status != 0) 1285 goto err_read_i2c_eeprom; 1286 1287 vendor_oui = 1288 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1289 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1290 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1291 1292 switch (vendor_oui) { 1293 case IXGBE_SFF_VENDOR_OUI_TYCO: 1294 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1295 hw->phy.type = 1296 ixgbe_phy_sfp_passive_tyco; 1297 break; 1298 case IXGBE_SFF_VENDOR_OUI_FTL: 1299 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1300 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1301 else 1302 hw->phy.type = ixgbe_phy_sfp_ftl; 1303 break; 1304 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1305 hw->phy.type = ixgbe_phy_sfp_avago; 1306 break; 1307 case IXGBE_SFF_VENDOR_OUI_INTEL: 1308 hw->phy.type = ixgbe_phy_sfp_intel; 1309 break; 1310 default: 1311 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1312 hw->phy.type = 1313 ixgbe_phy_sfp_passive_unknown; 1314 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1315 hw->phy.type = 1316 ixgbe_phy_sfp_active_unknown; 1317 else 1318 hw->phy.type = ixgbe_phy_sfp_unknown; 1319 break; 1320 } 1321 } 1322 1323 /* Allow any DA cable vendor */ 1324 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1325 IXGBE_SFF_DA_ACTIVE_CABLE)) 1326 return 0; 1327 1328 /* Verify supported 1G SFP modules */ 1329 if (comp_codes_10g == 0 && 1330 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1331 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1332 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1333 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1334 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1335 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1336 hw->phy.type = ixgbe_phy_sfp_unsupported; 1337 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1338 } 1339 1340 /* Anything else 82598-based is supported */ 1341 if (hw->mac.type == ixgbe_mac_82598EB) 1342 return 0; 1343 1344 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1345 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1346 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1347 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1348 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1349 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1350 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1351 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1352 /* Make sure we're a supported PHY type */ 1353 if (hw->phy.type == ixgbe_phy_sfp_intel) 1354 return 0; 1355 if (hw->allow_unsupported_sfp) { 1356 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1357 return 0; 1358 } 1359 hw_dbg(hw, "SFP+ module not supported\n"); 1360 hw->phy.type = ixgbe_phy_sfp_unsupported; 1361 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1362 } 1363 return 0; 1364 1365 err_read_i2c_eeprom: 1366 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1367 if (hw->phy.type != ixgbe_phy_nl) { 1368 hw->phy.id = 0; 1369 hw->phy.type = ixgbe_phy_unknown; 1370 } 1371 return IXGBE_ERR_SFP_NOT_PRESENT; 1372 } 1373 1374 /** 1375 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1376 * @hw: pointer to hardware structure 1377 * 1378 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1379 **/ 1380 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1381 { 1382 struct ixgbe_adapter *adapter = hw->back; 1383 s32 status; 1384 u32 vendor_oui = 0; 1385 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1386 u8 identifier = 0; 1387 u8 comp_codes_1g = 0; 1388 u8 comp_codes_10g = 0; 1389 u8 oui_bytes[3] = {0, 0, 0}; 1390 u16 enforce_sfp = 0; 1391 u8 connector = 0; 1392 u8 cable_length = 0; 1393 u8 device_tech = 0; 1394 bool active_cable = false; 1395 1396 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1397 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1398 return IXGBE_ERR_SFP_NOT_PRESENT; 1399 } 1400 1401 /* LAN ID is needed for sfp_type determination */ 1402 hw->mac.ops.set_lan_id(hw); 1403 1404 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1405 &identifier); 1406 1407 if (status != 0) 1408 goto err_read_i2c_eeprom; 1409 1410 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1411 hw->phy.type = ixgbe_phy_sfp_unsupported; 1412 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1413 } 1414 1415 hw->phy.id = identifier; 1416 1417 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1418 &comp_codes_10g); 1419 1420 if (status != 0) 1421 goto err_read_i2c_eeprom; 1422 1423 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1424 &comp_codes_1g); 1425 1426 if (status != 0) 1427 goto err_read_i2c_eeprom; 1428 1429 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1430 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1431 if (hw->bus.lan_id == 0) 1432 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1433 else 1434 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1435 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1436 IXGBE_SFF_10GBASELR_CAPABLE)) { 1437 if (hw->bus.lan_id == 0) 1438 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1439 else 1440 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1441 } else { 1442 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1443 active_cable = true; 1444 1445 if (!active_cable) { 1446 /* check for active DA cables that pre-date 1447 * SFF-8436 v3.6 1448 */ 1449 hw->phy.ops.read_i2c_eeprom(hw, 1450 IXGBE_SFF_QSFP_CONNECTOR, 1451 &connector); 1452 1453 hw->phy.ops.read_i2c_eeprom(hw, 1454 IXGBE_SFF_QSFP_CABLE_LENGTH, 1455 &cable_length); 1456 1457 hw->phy.ops.read_i2c_eeprom(hw, 1458 IXGBE_SFF_QSFP_DEVICE_TECH, 1459 &device_tech); 1460 1461 if ((connector == 1462 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1463 (cable_length > 0) && 1464 ((device_tech >> 4) == 1465 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1466 active_cable = true; 1467 } 1468 1469 if (active_cable) { 1470 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1471 if (hw->bus.lan_id == 0) 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_da_act_lmt_core0; 1474 else 1475 hw->phy.sfp_type = 1476 ixgbe_sfp_type_da_act_lmt_core1; 1477 } else { 1478 /* unsupported module type */ 1479 hw->phy.type = ixgbe_phy_sfp_unsupported; 1480 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1481 } 1482 } 1483 1484 if (hw->phy.sfp_type != stored_sfp_type) 1485 hw->phy.sfp_setup_needed = true; 1486 1487 /* Determine if the QSFP+ PHY is dual speed or not. */ 1488 hw->phy.multispeed_fiber = false; 1489 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1490 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1491 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1492 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1493 hw->phy.multispeed_fiber = true; 1494 1495 /* Determine PHY vendor for optical modules */ 1496 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1497 IXGBE_SFF_10GBASELR_CAPABLE)) { 1498 status = hw->phy.ops.read_i2c_eeprom(hw, 1499 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1500 &oui_bytes[0]); 1501 1502 if (status != 0) 1503 goto err_read_i2c_eeprom; 1504 1505 status = hw->phy.ops.read_i2c_eeprom(hw, 1506 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1507 &oui_bytes[1]); 1508 1509 if (status != 0) 1510 goto err_read_i2c_eeprom; 1511 1512 status = hw->phy.ops.read_i2c_eeprom(hw, 1513 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1514 &oui_bytes[2]); 1515 1516 if (status != 0) 1517 goto err_read_i2c_eeprom; 1518 1519 vendor_oui = 1520 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1521 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1522 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1523 1524 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1525 hw->phy.type = ixgbe_phy_qsfp_intel; 1526 else 1527 hw->phy.type = ixgbe_phy_qsfp_unknown; 1528 1529 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1530 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1531 /* Make sure we're a supported PHY type */ 1532 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1533 return 0; 1534 if (hw->allow_unsupported_sfp) { 1535 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1536 return 0; 1537 } 1538 hw_dbg(hw, "QSFP module not supported\n"); 1539 hw->phy.type = ixgbe_phy_sfp_unsupported; 1540 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1541 } 1542 return 0; 1543 } 1544 return 0; 1545 1546 err_read_i2c_eeprom: 1547 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1548 hw->phy.id = 0; 1549 hw->phy.type = ixgbe_phy_unknown; 1550 1551 return IXGBE_ERR_SFP_NOT_PRESENT; 1552 } 1553 1554 /** 1555 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1556 * @hw: pointer to hardware structure 1557 * @list_offset: offset to the SFP ID list 1558 * @data_offset: offset to the SFP data block 1559 * 1560 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1561 * so it returns the offsets to the phy init sequence block. 1562 **/ 1563 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1564 u16 *list_offset, 1565 u16 *data_offset) 1566 { 1567 u16 sfp_id; 1568 u16 sfp_type = hw->phy.sfp_type; 1569 1570 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1571 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1572 1573 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1574 return IXGBE_ERR_SFP_NOT_PRESENT; 1575 1576 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1577 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1578 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1579 1580 /* 1581 * Limiting active cables and 1G Phys must be initialized as 1582 * SR modules 1583 */ 1584 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1585 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1586 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1587 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1588 sfp_type = ixgbe_sfp_type_srlr_core0; 1589 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1590 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1591 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1592 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1593 sfp_type = ixgbe_sfp_type_srlr_core1; 1594 1595 /* Read offset to PHY init contents */ 1596 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1597 hw_err(hw, "eeprom read at %d failed\n", 1598 IXGBE_PHY_INIT_OFFSET_NL); 1599 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1600 } 1601 1602 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1603 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1604 1605 /* Shift offset to first ID word */ 1606 (*list_offset)++; 1607 1608 /* 1609 * Find the matching SFP ID in the EEPROM 1610 * and program the init sequence 1611 */ 1612 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1613 goto err_phy; 1614 1615 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1616 if (sfp_id == sfp_type) { 1617 (*list_offset)++; 1618 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1619 goto err_phy; 1620 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1621 hw_dbg(hw, "SFP+ module not supported\n"); 1622 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1623 } else { 1624 break; 1625 } 1626 } else { 1627 (*list_offset) += 2; 1628 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1629 goto err_phy; 1630 } 1631 } 1632 1633 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1634 hw_dbg(hw, "No matching SFP+ module found\n"); 1635 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1636 } 1637 1638 return 0; 1639 1640 err_phy: 1641 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1642 return IXGBE_ERR_PHY; 1643 } 1644 1645 /** 1646 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1647 * @hw: pointer to hardware structure 1648 * @byte_offset: EEPROM byte offset to read 1649 * @eeprom_data: value read 1650 * 1651 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1652 **/ 1653 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1654 u8 *eeprom_data) 1655 { 1656 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1657 IXGBE_I2C_EEPROM_DEV_ADDR, 1658 eeprom_data); 1659 } 1660 1661 /** 1662 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1663 * @hw: pointer to hardware structure 1664 * @byte_offset: byte offset at address 0xA2 1665 * @eeprom_data: value read 1666 * 1667 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1668 **/ 1669 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1670 u8 *sff8472_data) 1671 { 1672 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1673 IXGBE_I2C_EEPROM_DEV_ADDR2, 1674 sff8472_data); 1675 } 1676 1677 /** 1678 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1679 * @hw: pointer to hardware structure 1680 * @byte_offset: EEPROM byte offset to write 1681 * @eeprom_data: value to write 1682 * 1683 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1684 **/ 1685 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1686 u8 eeprom_data) 1687 { 1688 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1689 IXGBE_I2C_EEPROM_DEV_ADDR, 1690 eeprom_data); 1691 } 1692 1693 /** 1694 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1695 * @hw: pointer to hardware structure 1696 * @offset: eeprom offset to be read 1697 * @addr: I2C address to be read 1698 */ 1699 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1700 { 1701 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1702 offset == IXGBE_SFF_IDENTIFIER && 1703 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1704 return true; 1705 return false; 1706 } 1707 1708 /** 1709 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1710 * @hw: pointer to hardware structure 1711 * @byte_offset: byte offset to read 1712 * @data: value read 1713 * @lock: true if to take and release semaphore 1714 * 1715 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1716 * a specified device address. 1717 */ 1718 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1719 u8 dev_addr, u8 *data, bool lock) 1720 { 1721 s32 status; 1722 u32 max_retry = 10; 1723 u32 retry = 0; 1724 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1725 bool nack = true; 1726 1727 if (hw->mac.type >= ixgbe_mac_X550) 1728 max_retry = 3; 1729 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 1730 max_retry = IXGBE_SFP_DETECT_RETRIES; 1731 1732 *data = 0; 1733 1734 do { 1735 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1736 return IXGBE_ERR_SWFW_SYNC; 1737 1738 ixgbe_i2c_start(hw); 1739 1740 /* Device Address and write indication */ 1741 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1742 if (status != 0) 1743 goto fail; 1744 1745 status = ixgbe_get_i2c_ack(hw); 1746 if (status != 0) 1747 goto fail; 1748 1749 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1750 if (status != 0) 1751 goto fail; 1752 1753 status = ixgbe_get_i2c_ack(hw); 1754 if (status != 0) 1755 goto fail; 1756 1757 ixgbe_i2c_start(hw); 1758 1759 /* Device Address and read indication */ 1760 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1761 if (status != 0) 1762 goto fail; 1763 1764 status = ixgbe_get_i2c_ack(hw); 1765 if (status != 0) 1766 goto fail; 1767 1768 status = ixgbe_clock_in_i2c_byte(hw, data); 1769 if (status != 0) 1770 goto fail; 1771 1772 status = ixgbe_clock_out_i2c_bit(hw, nack); 1773 if (status != 0) 1774 goto fail; 1775 1776 ixgbe_i2c_stop(hw); 1777 if (lock) 1778 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1779 return 0; 1780 1781 fail: 1782 ixgbe_i2c_bus_clear(hw); 1783 if (lock) { 1784 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1785 msleep(100); 1786 } 1787 retry++; 1788 if (retry < max_retry) 1789 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1790 else 1791 hw_dbg(hw, "I2C byte read error.\n"); 1792 1793 } while (retry < max_retry); 1794 1795 return status; 1796 } 1797 1798 /** 1799 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1800 * @hw: pointer to hardware structure 1801 * @byte_offset: byte offset to read 1802 * @data: value read 1803 * 1804 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1805 * a specified device address. 1806 */ 1807 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1808 u8 dev_addr, u8 *data) 1809 { 1810 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 1811 data, true); 1812 } 1813 1814 /** 1815 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 1816 * @hw: pointer to hardware structure 1817 * @byte_offset: byte offset to read 1818 * @data: value read 1819 * 1820 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1821 * a specified device address. 1822 */ 1823 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1824 u8 dev_addr, u8 *data) 1825 { 1826 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 1827 data, false); 1828 } 1829 1830 /** 1831 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 1832 * @hw: pointer to hardware structure 1833 * @byte_offset: byte offset to write 1834 * @data: value to write 1835 * @lock: true if to take and release semaphore 1836 * 1837 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1838 * a specified device address. 1839 */ 1840 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1841 u8 dev_addr, u8 data, bool lock) 1842 { 1843 s32 status; 1844 u32 max_retry = 1; 1845 u32 retry = 0; 1846 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1847 1848 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1849 return IXGBE_ERR_SWFW_SYNC; 1850 1851 do { 1852 ixgbe_i2c_start(hw); 1853 1854 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1855 if (status != 0) 1856 goto fail; 1857 1858 status = ixgbe_get_i2c_ack(hw); 1859 if (status != 0) 1860 goto fail; 1861 1862 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1863 if (status != 0) 1864 goto fail; 1865 1866 status = ixgbe_get_i2c_ack(hw); 1867 if (status != 0) 1868 goto fail; 1869 1870 status = ixgbe_clock_out_i2c_byte(hw, data); 1871 if (status != 0) 1872 goto fail; 1873 1874 status = ixgbe_get_i2c_ack(hw); 1875 if (status != 0) 1876 goto fail; 1877 1878 ixgbe_i2c_stop(hw); 1879 if (lock) 1880 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1881 return 0; 1882 1883 fail: 1884 ixgbe_i2c_bus_clear(hw); 1885 retry++; 1886 if (retry < max_retry) 1887 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1888 else 1889 hw_dbg(hw, "I2C byte write error.\n"); 1890 } while (retry < max_retry); 1891 1892 if (lock) 1893 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1894 1895 return status; 1896 } 1897 1898 /** 1899 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1900 * @hw: pointer to hardware structure 1901 * @byte_offset: byte offset to write 1902 * @data: value to write 1903 * 1904 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1905 * a specified device address. 1906 */ 1907 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1908 u8 dev_addr, u8 data) 1909 { 1910 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 1911 data, true); 1912 } 1913 1914 /** 1915 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 1916 * @hw: pointer to hardware structure 1917 * @byte_offset: byte offset to write 1918 * @data: value to write 1919 * 1920 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1921 * a specified device address. 1922 */ 1923 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1924 u8 dev_addr, u8 data) 1925 { 1926 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 1927 data, false); 1928 } 1929 1930 /** 1931 * ixgbe_i2c_start - Sets I2C start condition 1932 * @hw: pointer to hardware structure 1933 * 1934 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1935 * Set bit-bang mode on X550 hardware. 1936 **/ 1937 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1938 { 1939 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1940 1941 i2cctl |= IXGBE_I2C_BB_EN(hw); 1942 1943 /* Start condition must begin with data and clock high */ 1944 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1945 ixgbe_raise_i2c_clk(hw, &i2cctl); 1946 1947 /* Setup time for start condition (4.7us) */ 1948 udelay(IXGBE_I2C_T_SU_STA); 1949 1950 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1951 1952 /* Hold time for start condition (4us) */ 1953 udelay(IXGBE_I2C_T_HD_STA); 1954 1955 ixgbe_lower_i2c_clk(hw, &i2cctl); 1956 1957 /* Minimum low period of clock is 4.7 us */ 1958 udelay(IXGBE_I2C_T_LOW); 1959 1960 } 1961 1962 /** 1963 * ixgbe_i2c_stop - Sets I2C stop condition 1964 * @hw: pointer to hardware structure 1965 * 1966 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1967 * Disables bit-bang mode and negates data output enable on X550 1968 * hardware. 1969 **/ 1970 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1971 { 1972 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1973 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 1974 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 1975 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw); 1976 1977 /* Stop condition must begin with data low and clock high */ 1978 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1979 ixgbe_raise_i2c_clk(hw, &i2cctl); 1980 1981 /* Setup time for stop condition (4us) */ 1982 udelay(IXGBE_I2C_T_SU_STO); 1983 1984 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1985 1986 /* bus free time between stop and start (4.7us)*/ 1987 udelay(IXGBE_I2C_T_BUF); 1988 1989 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 1990 i2cctl &= ~bb_en_bit; 1991 i2cctl |= data_oe_bit | clk_oe_bit; 1992 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 1993 IXGBE_WRITE_FLUSH(hw); 1994 } 1995 } 1996 1997 /** 1998 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1999 * @hw: pointer to hardware structure 2000 * @data: data byte to clock in 2001 * 2002 * Clocks in one byte data via I2C data/clock 2003 **/ 2004 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2005 { 2006 s32 i; 2007 bool bit = false; 2008 2009 *data = 0; 2010 for (i = 7; i >= 0; i--) { 2011 ixgbe_clock_in_i2c_bit(hw, &bit); 2012 *data |= bit << i; 2013 } 2014 2015 return 0; 2016 } 2017 2018 /** 2019 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2020 * @hw: pointer to hardware structure 2021 * @data: data byte clocked out 2022 * 2023 * Clocks out one byte data via I2C data/clock 2024 **/ 2025 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2026 { 2027 s32 status; 2028 s32 i; 2029 u32 i2cctl; 2030 bool bit = false; 2031 2032 for (i = 7; i >= 0; i--) { 2033 bit = (data >> i) & 0x1; 2034 status = ixgbe_clock_out_i2c_bit(hw, bit); 2035 2036 if (status != 0) 2037 break; 2038 } 2039 2040 /* Release SDA line (set high) */ 2041 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2042 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2043 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw); 2044 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2045 IXGBE_WRITE_FLUSH(hw); 2046 2047 return status; 2048 } 2049 2050 /** 2051 * ixgbe_get_i2c_ack - Polls for I2C ACK 2052 * @hw: pointer to hardware structure 2053 * 2054 * Clocks in/out one bit via I2C data/clock 2055 **/ 2056 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2057 { 2058 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2059 s32 status = 0; 2060 u32 i = 0; 2061 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2062 u32 timeout = 10; 2063 bool ack = true; 2064 2065 if (data_oe_bit) { 2066 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2067 i2cctl |= data_oe_bit; 2068 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2069 IXGBE_WRITE_FLUSH(hw); 2070 } 2071 ixgbe_raise_i2c_clk(hw, &i2cctl); 2072 2073 /* Minimum high period of clock is 4us */ 2074 udelay(IXGBE_I2C_T_HIGH); 2075 2076 /* Poll for ACK. Note that ACK in I2C spec is 2077 * transition from 1 to 0 */ 2078 for (i = 0; i < timeout; i++) { 2079 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2080 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2081 2082 udelay(1); 2083 if (ack == 0) 2084 break; 2085 } 2086 2087 if (ack == 1) { 2088 hw_dbg(hw, "I2C ack was not received.\n"); 2089 status = IXGBE_ERR_I2C; 2090 } 2091 2092 ixgbe_lower_i2c_clk(hw, &i2cctl); 2093 2094 /* Minimum low period of clock is 4.7 us */ 2095 udelay(IXGBE_I2C_T_LOW); 2096 2097 return status; 2098 } 2099 2100 /** 2101 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2102 * @hw: pointer to hardware structure 2103 * @data: read data value 2104 * 2105 * Clocks in one bit via I2C data/clock 2106 **/ 2107 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2108 { 2109 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2110 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2111 2112 if (data_oe_bit) { 2113 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2114 i2cctl |= data_oe_bit; 2115 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2116 IXGBE_WRITE_FLUSH(hw); 2117 } 2118 ixgbe_raise_i2c_clk(hw, &i2cctl); 2119 2120 /* Minimum high period of clock is 4us */ 2121 udelay(IXGBE_I2C_T_HIGH); 2122 2123 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2124 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2125 2126 ixgbe_lower_i2c_clk(hw, &i2cctl); 2127 2128 /* Minimum low period of clock is 4.7 us */ 2129 udelay(IXGBE_I2C_T_LOW); 2130 2131 return 0; 2132 } 2133 2134 /** 2135 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2136 * @hw: pointer to hardware structure 2137 * @data: data value to write 2138 * 2139 * Clocks out one bit via I2C data/clock 2140 **/ 2141 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2142 { 2143 s32 status; 2144 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2145 2146 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2147 if (status == 0) { 2148 ixgbe_raise_i2c_clk(hw, &i2cctl); 2149 2150 /* Minimum high period of clock is 4us */ 2151 udelay(IXGBE_I2C_T_HIGH); 2152 2153 ixgbe_lower_i2c_clk(hw, &i2cctl); 2154 2155 /* Minimum low period of clock is 4.7 us. 2156 * This also takes care of the data hold time. 2157 */ 2158 udelay(IXGBE_I2C_T_LOW); 2159 } else { 2160 hw_dbg(hw, "I2C data was not set to %X\n", data); 2161 return IXGBE_ERR_I2C; 2162 } 2163 2164 return 0; 2165 } 2166 /** 2167 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2168 * @hw: pointer to hardware structure 2169 * @i2cctl: Current value of I2CCTL register 2170 * 2171 * Raises the I2C clock line '0'->'1' 2172 * Negates the I2C clock output enable on X550 hardware. 2173 **/ 2174 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2175 { 2176 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 2177 u32 i = 0; 2178 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2179 u32 i2cctl_r = 0; 2180 2181 if (clk_oe_bit) { 2182 *i2cctl |= clk_oe_bit; 2183 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2184 } 2185 2186 for (i = 0; i < timeout; i++) { 2187 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); 2188 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2189 IXGBE_WRITE_FLUSH(hw); 2190 /* SCL rise time (1000ns) */ 2191 udelay(IXGBE_I2C_T_RISE); 2192 2193 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2194 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) 2195 break; 2196 } 2197 } 2198 2199 /** 2200 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2201 * @hw: pointer to hardware structure 2202 * @i2cctl: Current value of I2CCTL register 2203 * 2204 * Lowers the I2C clock line '1'->'0' 2205 * Asserts the I2C clock output enable on X550 hardware. 2206 **/ 2207 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2208 { 2209 2210 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); 2211 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw); 2212 2213 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2214 IXGBE_WRITE_FLUSH(hw); 2215 2216 /* SCL fall time (300ns) */ 2217 udelay(IXGBE_I2C_T_FALL); 2218 } 2219 2220 /** 2221 * ixgbe_set_i2c_data - Sets the I2C data bit 2222 * @hw: pointer to hardware structure 2223 * @i2cctl: Current value of I2CCTL register 2224 * @data: I2C data value (0 or 1) to set 2225 * 2226 * Sets the I2C data bit 2227 * Asserts the I2C data output enable on X550 hardware. 2228 **/ 2229 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2230 { 2231 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2232 2233 if (data) 2234 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2235 else 2236 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); 2237 *i2cctl &= ~data_oe_bit; 2238 2239 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2240 IXGBE_WRITE_FLUSH(hw); 2241 2242 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2243 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2244 2245 if (!data) /* Can't verify data in this case */ 2246 return 0; 2247 if (data_oe_bit) { 2248 *i2cctl |= data_oe_bit; 2249 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2250 IXGBE_WRITE_FLUSH(hw); 2251 } 2252 2253 /* Verify data was set correctly */ 2254 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2255 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2256 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2257 return IXGBE_ERR_I2C; 2258 } 2259 2260 return 0; 2261 } 2262 2263 /** 2264 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2265 * @hw: pointer to hardware structure 2266 * @i2cctl: Current value of I2CCTL register 2267 * 2268 * Returns the I2C data bit value 2269 * Negates the I2C data output enable on X550 hardware. 2270 **/ 2271 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2272 { 2273 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2274 2275 if (data_oe_bit) { 2276 *i2cctl |= data_oe_bit; 2277 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2278 IXGBE_WRITE_FLUSH(hw); 2279 udelay(IXGBE_I2C_T_FALL); 2280 } 2281 2282 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) 2283 return true; 2284 return false; 2285 } 2286 2287 /** 2288 * ixgbe_i2c_bus_clear - Clears the I2C bus 2289 * @hw: pointer to hardware structure 2290 * 2291 * Clears the I2C bus by sending nine clock pulses. 2292 * Used when data line is stuck low. 2293 **/ 2294 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2295 { 2296 u32 i2cctl; 2297 u32 i; 2298 2299 ixgbe_i2c_start(hw); 2300 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2301 2302 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2303 2304 for (i = 0; i < 9; i++) { 2305 ixgbe_raise_i2c_clk(hw, &i2cctl); 2306 2307 /* Min high period of clock is 4us */ 2308 udelay(IXGBE_I2C_T_HIGH); 2309 2310 ixgbe_lower_i2c_clk(hw, &i2cctl); 2311 2312 /* Min low period of clock is 4.7us*/ 2313 udelay(IXGBE_I2C_T_LOW); 2314 } 2315 2316 ixgbe_i2c_start(hw); 2317 2318 /* Put the i2c bus back to default state */ 2319 ixgbe_i2c_stop(hw); 2320 } 2321 2322 /** 2323 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2324 * @hw: pointer to hardware structure 2325 * 2326 * Checks if the LASI temp alarm status was triggered due to overtemp 2327 **/ 2328 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2329 { 2330 u16 phy_data = 0; 2331 2332 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2333 return 0; 2334 2335 /* Check that the LASI temp alarm status was triggered */ 2336 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2337 MDIO_MMD_PMAPMD, &phy_data); 2338 2339 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2340 return 0; 2341 2342 return IXGBE_ERR_OVERTEMP; 2343 } 2344 2345 /** ixgbe_set_copper_phy_power - Control power for copper phy 2346 * @hw: pointer to hardware structure 2347 * @on: true for on, false for off 2348 **/ 2349 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2350 { 2351 u32 status; 2352 u16 reg; 2353 2354 /* Bail if we don't have copper phy */ 2355 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2356 return 0; 2357 2358 if (!on && ixgbe_mng_present(hw)) 2359 return 0; 2360 2361 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®); 2362 if (status) 2363 return status; 2364 2365 if (on) { 2366 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2367 } else { 2368 if (ixgbe_check_reset_blocked(hw)) 2369 return 0; 2370 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2371 } 2372 2373 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); 2374 return status; 2375 } 2376