1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 36 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 54 * @hw: pointer to the hardware structure 55 * @byte: byte to send 56 * 57 * Returns an error code on error. 58 **/ 59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 60 { 61 s32 status; 62 63 status = ixgbe_clock_out_i2c_byte(hw, byte); 64 if (status) 65 return status; 66 return ixgbe_get_i2c_ack(hw); 67 } 68 69 /** 70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 71 * @hw: pointer to the hardware structure 72 * @byte: pointer to a u8 to receive the byte 73 * 74 * Returns an error code on error. 75 **/ 76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 77 { 78 s32 status; 79 80 status = ixgbe_clock_in_i2c_byte(hw, byte); 81 if (status) 82 return status; 83 /* ACK */ 84 return ixgbe_clock_out_i2c_bit(hw, false); 85 } 86 87 /** 88 * ixgbe_ones_comp_byte_add - Perform one's complement addition 89 * @add1: addend 1 90 * @add2: addend 2 91 * 92 * Returns one's complement 8-bit sum. 93 **/ 94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 95 { 96 u16 sum = add1 + add2; 97 98 sum = (sum & 0xFF) + (sum >> 8); 99 return sum & 0xFF; 100 } 101 102 /** 103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 104 * @hw: pointer to the hardware structure 105 * @addr: I2C bus address to read from 106 * @reg: I2C device register to read from 107 * @val: pointer to location to receive read value 108 * 109 * Returns an error code on error. 110 **/ 111 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 112 u16 reg, u16 *val) 113 { 114 u32 swfw_mask = hw->phy.phy_semaphore_mask; 115 int max_retry = 10; 116 int retry = 0; 117 u8 csum_byte; 118 u8 high_bits; 119 u8 low_bits; 120 u8 reg_high; 121 u8 csum; 122 123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 125 csum = ~csum; 126 do { 127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 128 return IXGBE_ERR_SWFW_SYNC; 129 ixgbe_i2c_start(hw); 130 /* Device Address and write indication */ 131 if (ixgbe_out_i2c_byte_ack(hw, addr)) 132 goto fail; 133 /* Write bits 14:8 */ 134 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 135 goto fail; 136 /* Write bits 7:0 */ 137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 138 goto fail; 139 /* Write csum */ 140 if (ixgbe_out_i2c_byte_ack(hw, csum)) 141 goto fail; 142 /* Re-start condition */ 143 ixgbe_i2c_start(hw); 144 /* Device Address and read indication */ 145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 146 goto fail; 147 /* Get upper bits */ 148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 149 goto fail; 150 /* Get low bits */ 151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 152 goto fail; 153 /* Get csum */ 154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 155 goto fail; 156 /* NACK */ 157 if (ixgbe_clock_out_i2c_bit(hw, false)) 158 goto fail; 159 ixgbe_i2c_stop(hw); 160 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 161 *val = (high_bits << 8) | low_bits; 162 return 0; 163 164 fail: 165 ixgbe_i2c_bus_clear(hw); 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 retry++; 168 if (retry < max_retry) 169 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 170 else 171 hw_dbg(hw, "I2C byte read combined error.\n"); 172 } while (retry < max_retry); 173 174 return IXGBE_ERR_I2C; 175 } 176 177 /** 178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 179 * @hw: pointer to the hardware structure 180 * @addr: I2C bus address to write to 181 * @reg: I2C device register to write to 182 * @val: value to write 183 * 184 * Returns an error code on error. 185 **/ 186 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 187 u8 addr, u16 reg, u16 val) 188 { 189 int max_retry = 1; 190 int retry = 0; 191 u8 reg_high; 192 u8 csum; 193 194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 198 csum = ~csum; 199 do { 200 ixgbe_i2c_start(hw); 201 /* Device Address and write indication */ 202 if (ixgbe_out_i2c_byte_ack(hw, addr)) 203 goto fail; 204 /* Write bits 14:8 */ 205 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 206 goto fail; 207 /* Write bits 7:0 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 209 goto fail; 210 /* Write data 15:8 */ 211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 212 goto fail; 213 /* Write data 7:0 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 215 goto fail; 216 /* Write csum */ 217 if (ixgbe_out_i2c_byte_ack(hw, csum)) 218 goto fail; 219 ixgbe_i2c_stop(hw); 220 return 0; 221 222 fail: 223 ixgbe_i2c_bus_clear(hw); 224 retry++; 225 if (retry < max_retry) 226 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 227 else 228 hw_dbg(hw, "I2C byte write combined error.\n"); 229 } while (retry < max_retry); 230 231 return IXGBE_ERR_I2C; 232 } 233 234 /** 235 * ixgbe_identify_phy_generic - Get physical layer module 236 * @hw: pointer to hardware structure 237 * 238 * Determines the physical layer module found on the current adapter. 239 **/ 240 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 241 { 242 u32 phy_addr; 243 u16 ext_ability = 0; 244 245 if (!hw->phy.phy_semaphore_mask) { 246 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) & 247 IXGBE_STATUS_LAN_ID_1; 248 if (hw->phy.lan_id) 249 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 250 else 251 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 252 } 253 254 if (hw->phy.type == ixgbe_phy_unknown) { 255 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 256 hw->phy.mdio.prtad = phy_addr; 257 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 258 ixgbe_get_phy_id(hw); 259 hw->phy.type = 260 ixgbe_get_phy_type_from_id(hw->phy.id); 261 262 if (hw->phy.type == ixgbe_phy_unknown) { 263 hw->phy.ops.read_reg(hw, 264 MDIO_PMA_EXTABLE, 265 MDIO_MMD_PMAPMD, 266 &ext_ability); 267 if (ext_ability & 268 (MDIO_PMA_EXTABLE_10GBT | 269 MDIO_PMA_EXTABLE_1000BT)) 270 hw->phy.type = 271 ixgbe_phy_cu_unknown; 272 else 273 hw->phy.type = 274 ixgbe_phy_generic; 275 } 276 277 return 0; 278 } 279 } 280 /* clear value if nothing found */ 281 hw->phy.mdio.prtad = 0; 282 return IXGBE_ERR_PHY_ADDR_INVALID; 283 } 284 return 0; 285 } 286 287 /** 288 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 289 * @hw: pointer to the hardware structure 290 * 291 * This function checks the MMNGC.MNG_VETO bit to see if there are 292 * any constraints on link from manageability. For MAC's that don't 293 * have this bit just return false since the link can not be blocked 294 * via this method. 295 **/ 296 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 297 { 298 u32 mmngc; 299 300 /* If we don't have this bit, it can't be blocking */ 301 if (hw->mac.type == ixgbe_mac_82598EB) 302 return false; 303 304 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 305 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 306 hw_dbg(hw, "MNG_VETO bit detected.\n"); 307 return true; 308 } 309 310 return false; 311 } 312 313 /** 314 * ixgbe_get_phy_id - Get the phy type 315 * @hw: pointer to hardware structure 316 * 317 **/ 318 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 319 { 320 s32 status; 321 u16 phy_id_high = 0; 322 u16 phy_id_low = 0; 323 324 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 325 &phy_id_high); 326 327 if (!status) { 328 hw->phy.id = (u32)(phy_id_high << 16); 329 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 330 &phy_id_low); 331 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 332 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 333 } 334 return status; 335 } 336 337 /** 338 * ixgbe_get_phy_type_from_id - Get the phy type 339 * @hw: pointer to hardware structure 340 * 341 **/ 342 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 343 { 344 enum ixgbe_phy_type phy_type; 345 346 switch (phy_id) { 347 case TN1010_PHY_ID: 348 phy_type = ixgbe_phy_tn; 349 break; 350 case X550_PHY_ID: 351 case X540_PHY_ID: 352 phy_type = ixgbe_phy_aq; 353 break; 354 case QT2022_PHY_ID: 355 phy_type = ixgbe_phy_qt; 356 break; 357 case ATH_PHY_ID: 358 phy_type = ixgbe_phy_nl; 359 break; 360 case X557_PHY_ID: 361 phy_type = ixgbe_phy_x550em_ext_t; 362 break; 363 default: 364 phy_type = ixgbe_phy_unknown; 365 break; 366 } 367 368 return phy_type; 369 } 370 371 /** 372 * ixgbe_reset_phy_generic - Performs a PHY reset 373 * @hw: pointer to hardware structure 374 **/ 375 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 376 { 377 u32 i; 378 u16 ctrl = 0; 379 s32 status = 0; 380 381 if (hw->phy.type == ixgbe_phy_unknown) 382 status = ixgbe_identify_phy_generic(hw); 383 384 if (status != 0 || hw->phy.type == ixgbe_phy_none) 385 return status; 386 387 /* Don't reset PHY if it's shut down due to overtemp. */ 388 if (!hw->phy.reset_if_overtemp && 389 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 390 return 0; 391 392 /* Blocked by MNG FW so bail */ 393 if (ixgbe_check_reset_blocked(hw)) 394 return 0; 395 396 /* 397 * Perform soft PHY reset to the PHY_XS. 398 * This will cause a soft reset to the PHY 399 */ 400 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 401 MDIO_MMD_PHYXS, 402 MDIO_CTRL1_RESET); 403 404 /* 405 * Poll for reset bit to self-clear indicating reset is complete. 406 * Some PHYs could take up to 3 seconds to complete and need about 407 * 1.7 usec delay after the reset is complete. 408 */ 409 for (i = 0; i < 30; i++) { 410 msleep(100); 411 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 412 MDIO_MMD_PHYXS, &ctrl); 413 if (!(ctrl & MDIO_CTRL1_RESET)) { 414 udelay(2); 415 break; 416 } 417 } 418 419 if (ctrl & MDIO_CTRL1_RESET) { 420 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 421 return IXGBE_ERR_RESET_FAILED; 422 } 423 424 return 0; 425 } 426 427 /** 428 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 429 * the SWFW lock 430 * @hw: pointer to hardware structure 431 * @reg_addr: 32 bit address of PHY register to read 432 * @phy_data: Pointer to read data from PHY register 433 **/ 434 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 435 u16 *phy_data) 436 { 437 u32 i, data, command; 438 439 /* Setup and write the address cycle command */ 440 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 441 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 442 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 443 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 444 445 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 446 447 /* Check every 10 usec to see if the address cycle completed. 448 * The MDI Command bit will clear when the operation is 449 * complete 450 */ 451 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 452 udelay(10); 453 454 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 455 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 456 break; 457 } 458 459 460 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 461 hw_dbg(hw, "PHY address command did not complete.\n"); 462 return IXGBE_ERR_PHY; 463 } 464 465 /* Address cycle complete, setup and write the read 466 * command 467 */ 468 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 469 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 470 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 471 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 472 473 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 474 475 /* Check every 10 usec to see if the address cycle 476 * completed. The MDI Command bit will clear when the 477 * operation is complete 478 */ 479 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 480 udelay(10); 481 482 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 483 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 484 break; 485 } 486 487 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 488 hw_dbg(hw, "PHY read command didn't complete\n"); 489 return IXGBE_ERR_PHY; 490 } 491 492 /* Read operation is complete. Get the data 493 * from MSRWD 494 */ 495 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 496 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 497 *phy_data = (u16)(data); 498 499 return 0; 500 } 501 502 /** 503 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 504 * using the SWFW lock - this function is needed in most cases 505 * @hw: pointer to hardware structure 506 * @reg_addr: 32 bit address of PHY register to read 507 * @phy_data: Pointer to read data from PHY register 508 **/ 509 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 510 u32 device_type, u16 *phy_data) 511 { 512 s32 status; 513 u32 gssr = hw->phy.phy_semaphore_mask; 514 515 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 516 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 517 phy_data); 518 hw->mac.ops.release_swfw_sync(hw, gssr); 519 } else { 520 return IXGBE_ERR_SWFW_SYNC; 521 } 522 523 return status; 524 } 525 526 /** 527 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 528 * without SWFW lock 529 * @hw: pointer to hardware structure 530 * @reg_addr: 32 bit PHY register to write 531 * @device_type: 5 bit device type 532 * @phy_data: Data to write to the PHY register 533 **/ 534 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 535 u32 device_type, u16 phy_data) 536 { 537 u32 i, command; 538 539 /* Put the data in the MDI single read and write data register*/ 540 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 541 542 /* Setup and write the address cycle command */ 543 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 544 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 545 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 546 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 547 548 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 549 550 /* 551 * Check every 10 usec to see if the address cycle completed. 552 * The MDI Command bit will clear when the operation is 553 * complete 554 */ 555 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 556 udelay(10); 557 558 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 559 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 560 break; 561 } 562 563 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 564 hw_dbg(hw, "PHY address cmd didn't complete\n"); 565 return IXGBE_ERR_PHY; 566 } 567 568 /* 569 * Address cycle complete, setup and write the write 570 * command 571 */ 572 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 573 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 574 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 575 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 576 577 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 578 579 /* Check every 10 usec to see if the address cycle 580 * completed. The MDI Command bit will clear when the 581 * operation is complete 582 */ 583 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 584 udelay(10); 585 586 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 587 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 588 break; 589 } 590 591 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 592 hw_dbg(hw, "PHY write cmd didn't complete\n"); 593 return IXGBE_ERR_PHY; 594 } 595 596 return 0; 597 } 598 599 /** 600 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 601 * using SWFW lock- this function is needed in most cases 602 * @hw: pointer to hardware structure 603 * @reg_addr: 32 bit PHY register to write 604 * @device_type: 5 bit device type 605 * @phy_data: Data to write to the PHY register 606 **/ 607 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 608 u32 device_type, u16 phy_data) 609 { 610 s32 status; 611 u32 gssr; 612 613 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 614 gssr = IXGBE_GSSR_PHY1_SM; 615 else 616 gssr = IXGBE_GSSR_PHY0_SM; 617 618 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 619 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 620 phy_data); 621 hw->mac.ops.release_swfw_sync(hw, gssr); 622 } else { 623 return IXGBE_ERR_SWFW_SYNC; 624 } 625 626 return status; 627 } 628 629 /** 630 * ixgbe_setup_phy_link_generic - Set and restart autoneg 631 * @hw: pointer to hardware structure 632 * 633 * Restart autonegotiation and PHY and waits for completion. 634 **/ 635 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 636 { 637 s32 status = 0; 638 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 639 bool autoneg = false; 640 ixgbe_link_speed speed; 641 642 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 643 644 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 645 /* Set or unset auto-negotiation 10G advertisement */ 646 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 647 MDIO_MMD_AN, 648 &autoneg_reg); 649 650 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 651 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 652 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 653 654 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 655 MDIO_MMD_AN, 656 autoneg_reg); 657 } 658 659 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 660 /* Set or unset auto-negotiation 1G advertisement */ 661 hw->phy.ops.read_reg(hw, 662 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 663 MDIO_MMD_AN, 664 &autoneg_reg); 665 666 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 667 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 668 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 669 670 hw->phy.ops.write_reg(hw, 671 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 672 MDIO_MMD_AN, 673 autoneg_reg); 674 } 675 676 if (speed & IXGBE_LINK_SPEED_100_FULL) { 677 /* Set or unset auto-negotiation 100M advertisement */ 678 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 679 MDIO_MMD_AN, 680 &autoneg_reg); 681 682 autoneg_reg &= ~(ADVERTISE_100FULL | 683 ADVERTISE_100HALF); 684 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 685 autoneg_reg |= ADVERTISE_100FULL; 686 687 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 688 MDIO_MMD_AN, 689 autoneg_reg); 690 } 691 692 /* Blocked by MNG FW so don't reset PHY */ 693 if (ixgbe_check_reset_blocked(hw)) 694 return 0; 695 696 /* Restart PHY autonegotiation and wait for completion */ 697 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 698 MDIO_MMD_AN, &autoneg_reg); 699 700 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 701 702 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 703 MDIO_MMD_AN, autoneg_reg); 704 705 return status; 706 } 707 708 /** 709 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 710 * @hw: pointer to hardware structure 711 * @speed: new link speed 712 **/ 713 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 714 ixgbe_link_speed speed, 715 bool autoneg_wait_to_complete) 716 { 717 718 /* 719 * Clear autoneg_advertised and set new values based on input link 720 * speed. 721 */ 722 hw->phy.autoneg_advertised = 0; 723 724 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 725 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 726 727 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 728 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 729 730 if (speed & IXGBE_LINK_SPEED_100_FULL) 731 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 732 733 /* Setup link based on the new speed settings */ 734 hw->phy.ops.setup_link(hw); 735 736 return 0; 737 } 738 739 /** 740 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 741 * @hw: pointer to hardware structure 742 * @speed: pointer to link speed 743 * @autoneg: boolean auto-negotiation value 744 * 745 * Determines the link capabilities by reading the AUTOC register. 746 */ 747 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 748 ixgbe_link_speed *speed, 749 bool *autoneg) 750 { 751 s32 status; 752 u16 speed_ability; 753 754 *speed = 0; 755 *autoneg = true; 756 757 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 758 &speed_ability); 759 760 if (status == 0) { 761 if (speed_ability & MDIO_SPEED_10G) 762 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 763 if (speed_ability & MDIO_PMA_SPEED_1000) 764 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 765 if (speed_ability & MDIO_PMA_SPEED_100) 766 *speed |= IXGBE_LINK_SPEED_100_FULL; 767 } 768 769 /* Internal PHY does not support 100 Mbps */ 770 if (hw->mac.type == ixgbe_mac_X550EM_x) 771 *speed &= ~IXGBE_LINK_SPEED_100_FULL; 772 773 return status; 774 } 775 776 /** 777 * ixgbe_check_phy_link_tnx - Determine link and speed status 778 * @hw: pointer to hardware structure 779 * 780 * Reads the VS1 register to determine if link is up and the current speed for 781 * the PHY. 782 **/ 783 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 784 bool *link_up) 785 { 786 s32 status; 787 u32 time_out; 788 u32 max_time_out = 10; 789 u16 phy_link = 0; 790 u16 phy_speed = 0; 791 u16 phy_data = 0; 792 793 /* Initialize speed and link to default case */ 794 *link_up = false; 795 *speed = IXGBE_LINK_SPEED_10GB_FULL; 796 797 /* 798 * Check current speed and link status of the PHY register. 799 * This is a vendor specific register and may have to 800 * be changed for other copper PHYs. 801 */ 802 for (time_out = 0; time_out < max_time_out; time_out++) { 803 udelay(10); 804 status = hw->phy.ops.read_reg(hw, 805 MDIO_STAT1, 806 MDIO_MMD_VEND1, 807 &phy_data); 808 phy_link = phy_data & 809 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 810 phy_speed = phy_data & 811 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 812 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 813 *link_up = true; 814 if (phy_speed == 815 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 816 *speed = IXGBE_LINK_SPEED_1GB_FULL; 817 break; 818 } 819 } 820 821 return status; 822 } 823 824 /** 825 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 826 * @hw: pointer to hardware structure 827 * 828 * Restart autonegotiation and PHY and waits for completion. 829 * This function always returns success, this is nessary since 830 * it is called via a function pointer that could call other 831 * functions that could return an error. 832 **/ 833 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 834 { 835 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 836 bool autoneg = false; 837 ixgbe_link_speed speed; 838 839 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 840 841 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 842 /* Set or unset auto-negotiation 10G advertisement */ 843 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 844 MDIO_MMD_AN, 845 &autoneg_reg); 846 847 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 848 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 849 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 850 851 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 852 MDIO_MMD_AN, 853 autoneg_reg); 854 } 855 856 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 857 /* Set or unset auto-negotiation 1G advertisement */ 858 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 859 MDIO_MMD_AN, 860 &autoneg_reg); 861 862 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 863 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 864 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 865 866 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 867 MDIO_MMD_AN, 868 autoneg_reg); 869 } 870 871 if (speed & IXGBE_LINK_SPEED_100_FULL) { 872 /* Set or unset auto-negotiation 100M advertisement */ 873 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 874 MDIO_MMD_AN, 875 &autoneg_reg); 876 877 autoneg_reg &= ~(ADVERTISE_100FULL | 878 ADVERTISE_100HALF); 879 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 880 autoneg_reg |= ADVERTISE_100FULL; 881 882 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 883 MDIO_MMD_AN, 884 autoneg_reg); 885 } 886 887 /* Blocked by MNG FW so don't reset PHY */ 888 if (ixgbe_check_reset_blocked(hw)) 889 return 0; 890 891 /* Restart PHY autonegotiation and wait for completion */ 892 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 893 MDIO_MMD_AN, &autoneg_reg); 894 895 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 896 897 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 898 MDIO_MMD_AN, autoneg_reg); 899 return 0; 900 } 901 902 /** 903 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 904 * @hw: pointer to hardware structure 905 * @firmware_version: pointer to the PHY Firmware Version 906 **/ 907 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 908 u16 *firmware_version) 909 { 910 s32 status; 911 912 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 913 MDIO_MMD_VEND1, 914 firmware_version); 915 916 return status; 917 } 918 919 /** 920 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 921 * @hw: pointer to hardware structure 922 * @firmware_version: pointer to the PHY Firmware Version 923 **/ 924 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 925 u16 *firmware_version) 926 { 927 s32 status; 928 929 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 930 MDIO_MMD_VEND1, 931 firmware_version); 932 933 return status; 934 } 935 936 /** 937 * ixgbe_reset_phy_nl - Performs a PHY reset 938 * @hw: pointer to hardware structure 939 **/ 940 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 941 { 942 u16 phy_offset, control, eword, edata, block_crc; 943 bool end_data = false; 944 u16 list_offset, data_offset; 945 u16 phy_data = 0; 946 s32 ret_val; 947 u32 i; 948 949 /* Blocked by MNG FW so bail */ 950 if (ixgbe_check_reset_blocked(hw)) 951 return 0; 952 953 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 954 955 /* reset the PHY and poll for completion */ 956 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 957 (phy_data | MDIO_CTRL1_RESET)); 958 959 for (i = 0; i < 100; i++) { 960 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 961 &phy_data); 962 if ((phy_data & MDIO_CTRL1_RESET) == 0) 963 break; 964 usleep_range(10000, 20000); 965 } 966 967 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 968 hw_dbg(hw, "PHY reset did not complete.\n"); 969 return IXGBE_ERR_PHY; 970 } 971 972 /* Get init offsets */ 973 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 974 &data_offset); 975 if (ret_val) 976 return ret_val; 977 978 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 979 data_offset++; 980 while (!end_data) { 981 /* 982 * Read control word from PHY init contents offset 983 */ 984 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 985 if (ret_val) 986 goto err_eeprom; 987 control = (eword & IXGBE_CONTROL_MASK_NL) >> 988 IXGBE_CONTROL_SHIFT_NL; 989 edata = eword & IXGBE_DATA_MASK_NL; 990 switch (control) { 991 case IXGBE_DELAY_NL: 992 data_offset++; 993 hw_dbg(hw, "DELAY: %d MS\n", edata); 994 usleep_range(edata * 1000, edata * 2000); 995 break; 996 case IXGBE_DATA_NL: 997 hw_dbg(hw, "DATA:\n"); 998 data_offset++; 999 ret_val = hw->eeprom.ops.read(hw, data_offset++, 1000 &phy_offset); 1001 if (ret_val) 1002 goto err_eeprom; 1003 for (i = 0; i < edata; i++) { 1004 ret_val = hw->eeprom.ops.read(hw, data_offset, 1005 &eword); 1006 if (ret_val) 1007 goto err_eeprom; 1008 hw->phy.ops.write_reg(hw, phy_offset, 1009 MDIO_MMD_PMAPMD, eword); 1010 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1011 phy_offset); 1012 data_offset++; 1013 phy_offset++; 1014 } 1015 break; 1016 case IXGBE_CONTROL_NL: 1017 data_offset++; 1018 hw_dbg(hw, "CONTROL:\n"); 1019 if (edata == IXGBE_CONTROL_EOL_NL) { 1020 hw_dbg(hw, "EOL\n"); 1021 end_data = true; 1022 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1023 hw_dbg(hw, "SOL\n"); 1024 } else { 1025 hw_dbg(hw, "Bad control value\n"); 1026 return IXGBE_ERR_PHY; 1027 } 1028 break; 1029 default: 1030 hw_dbg(hw, "Bad control type\n"); 1031 return IXGBE_ERR_PHY; 1032 } 1033 } 1034 1035 return ret_val; 1036 1037 err_eeprom: 1038 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1039 return IXGBE_ERR_PHY; 1040 } 1041 1042 /** 1043 * ixgbe_identify_module_generic - Identifies module type 1044 * @hw: pointer to hardware structure 1045 * 1046 * Determines HW type and calls appropriate function. 1047 **/ 1048 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1049 { 1050 switch (hw->mac.ops.get_media_type(hw)) { 1051 case ixgbe_media_type_fiber: 1052 return ixgbe_identify_sfp_module_generic(hw); 1053 case ixgbe_media_type_fiber_qsfp: 1054 return ixgbe_identify_qsfp_module_generic(hw); 1055 default: 1056 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1057 return IXGBE_ERR_SFP_NOT_PRESENT; 1058 } 1059 1060 return IXGBE_ERR_SFP_NOT_PRESENT; 1061 } 1062 1063 /** 1064 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1065 * @hw: pointer to hardware structure 1066 * 1067 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1068 **/ 1069 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1070 { 1071 struct ixgbe_adapter *adapter = hw->back; 1072 s32 status; 1073 u32 vendor_oui = 0; 1074 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1075 u8 identifier = 0; 1076 u8 comp_codes_1g = 0; 1077 u8 comp_codes_10g = 0; 1078 u8 oui_bytes[3] = {0, 0, 0}; 1079 u8 cable_tech = 0; 1080 u8 cable_spec = 0; 1081 u16 enforce_sfp = 0; 1082 1083 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1084 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1085 return IXGBE_ERR_SFP_NOT_PRESENT; 1086 } 1087 1088 status = hw->phy.ops.read_i2c_eeprom(hw, 1089 IXGBE_SFF_IDENTIFIER, 1090 &identifier); 1091 1092 if (status) 1093 goto err_read_i2c_eeprom; 1094 1095 /* LAN ID is needed for sfp_type determination */ 1096 hw->mac.ops.set_lan_id(hw); 1097 1098 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1099 hw->phy.type = ixgbe_phy_sfp_unsupported; 1100 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1101 } 1102 status = hw->phy.ops.read_i2c_eeprom(hw, 1103 IXGBE_SFF_1GBE_COMP_CODES, 1104 &comp_codes_1g); 1105 1106 if (status) 1107 goto err_read_i2c_eeprom; 1108 1109 status = hw->phy.ops.read_i2c_eeprom(hw, 1110 IXGBE_SFF_10GBE_COMP_CODES, 1111 &comp_codes_10g); 1112 1113 if (status) 1114 goto err_read_i2c_eeprom; 1115 status = hw->phy.ops.read_i2c_eeprom(hw, 1116 IXGBE_SFF_CABLE_TECHNOLOGY, 1117 &cable_tech); 1118 1119 if (status) 1120 goto err_read_i2c_eeprom; 1121 1122 /* ID Module 1123 * ========= 1124 * 0 SFP_DA_CU 1125 * 1 SFP_SR 1126 * 2 SFP_LR 1127 * 3 SFP_DA_CORE0 - 82599-specific 1128 * 4 SFP_DA_CORE1 - 82599-specific 1129 * 5 SFP_SR/LR_CORE0 - 82599-specific 1130 * 6 SFP_SR/LR_CORE1 - 82599-specific 1131 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1132 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1133 * 9 SFP_1g_cu_CORE0 - 82599-specific 1134 * 10 SFP_1g_cu_CORE1 - 82599-specific 1135 * 11 SFP_1g_sx_CORE0 - 82599-specific 1136 * 12 SFP_1g_sx_CORE1 - 82599-specific 1137 */ 1138 if (hw->mac.type == ixgbe_mac_82598EB) { 1139 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1140 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1141 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1142 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1143 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1144 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1145 else 1146 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1147 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1148 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1149 if (hw->bus.lan_id == 0) 1150 hw->phy.sfp_type = 1151 ixgbe_sfp_type_da_cu_core0; 1152 else 1153 hw->phy.sfp_type = 1154 ixgbe_sfp_type_da_cu_core1; 1155 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1156 hw->phy.ops.read_i2c_eeprom( 1157 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1158 &cable_spec); 1159 if (cable_spec & 1160 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1161 if (hw->bus.lan_id == 0) 1162 hw->phy.sfp_type = 1163 ixgbe_sfp_type_da_act_lmt_core0; 1164 else 1165 hw->phy.sfp_type = 1166 ixgbe_sfp_type_da_act_lmt_core1; 1167 } else { 1168 hw->phy.sfp_type = 1169 ixgbe_sfp_type_unknown; 1170 } 1171 } else if (comp_codes_10g & 1172 (IXGBE_SFF_10GBASESR_CAPABLE | 1173 IXGBE_SFF_10GBASELR_CAPABLE)) { 1174 if (hw->bus.lan_id == 0) 1175 hw->phy.sfp_type = 1176 ixgbe_sfp_type_srlr_core0; 1177 else 1178 hw->phy.sfp_type = 1179 ixgbe_sfp_type_srlr_core1; 1180 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1181 if (hw->bus.lan_id == 0) 1182 hw->phy.sfp_type = 1183 ixgbe_sfp_type_1g_cu_core0; 1184 else 1185 hw->phy.sfp_type = 1186 ixgbe_sfp_type_1g_cu_core1; 1187 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1188 if (hw->bus.lan_id == 0) 1189 hw->phy.sfp_type = 1190 ixgbe_sfp_type_1g_sx_core0; 1191 else 1192 hw->phy.sfp_type = 1193 ixgbe_sfp_type_1g_sx_core1; 1194 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1195 if (hw->bus.lan_id == 0) 1196 hw->phy.sfp_type = 1197 ixgbe_sfp_type_1g_lx_core0; 1198 else 1199 hw->phy.sfp_type = 1200 ixgbe_sfp_type_1g_lx_core1; 1201 } else { 1202 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1203 } 1204 } 1205 1206 if (hw->phy.sfp_type != stored_sfp_type) 1207 hw->phy.sfp_setup_needed = true; 1208 1209 /* Determine if the SFP+ PHY is dual speed or not. */ 1210 hw->phy.multispeed_fiber = false; 1211 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1212 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1213 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1214 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1215 hw->phy.multispeed_fiber = true; 1216 1217 /* Determine PHY vendor */ 1218 if (hw->phy.type != ixgbe_phy_nl) { 1219 hw->phy.id = identifier; 1220 status = hw->phy.ops.read_i2c_eeprom(hw, 1221 IXGBE_SFF_VENDOR_OUI_BYTE0, 1222 &oui_bytes[0]); 1223 1224 if (status != 0) 1225 goto err_read_i2c_eeprom; 1226 1227 status = hw->phy.ops.read_i2c_eeprom(hw, 1228 IXGBE_SFF_VENDOR_OUI_BYTE1, 1229 &oui_bytes[1]); 1230 1231 if (status != 0) 1232 goto err_read_i2c_eeprom; 1233 1234 status = hw->phy.ops.read_i2c_eeprom(hw, 1235 IXGBE_SFF_VENDOR_OUI_BYTE2, 1236 &oui_bytes[2]); 1237 1238 if (status != 0) 1239 goto err_read_i2c_eeprom; 1240 1241 vendor_oui = 1242 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1243 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1244 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1245 1246 switch (vendor_oui) { 1247 case IXGBE_SFF_VENDOR_OUI_TYCO: 1248 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1249 hw->phy.type = 1250 ixgbe_phy_sfp_passive_tyco; 1251 break; 1252 case IXGBE_SFF_VENDOR_OUI_FTL: 1253 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1254 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1255 else 1256 hw->phy.type = ixgbe_phy_sfp_ftl; 1257 break; 1258 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1259 hw->phy.type = ixgbe_phy_sfp_avago; 1260 break; 1261 case IXGBE_SFF_VENDOR_OUI_INTEL: 1262 hw->phy.type = ixgbe_phy_sfp_intel; 1263 break; 1264 default: 1265 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1266 hw->phy.type = 1267 ixgbe_phy_sfp_passive_unknown; 1268 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1269 hw->phy.type = 1270 ixgbe_phy_sfp_active_unknown; 1271 else 1272 hw->phy.type = ixgbe_phy_sfp_unknown; 1273 break; 1274 } 1275 } 1276 1277 /* Allow any DA cable vendor */ 1278 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1279 IXGBE_SFF_DA_ACTIVE_CABLE)) 1280 return 0; 1281 1282 /* Verify supported 1G SFP modules */ 1283 if (comp_codes_10g == 0 && 1284 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1285 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1286 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1287 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1288 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1289 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1290 hw->phy.type = ixgbe_phy_sfp_unsupported; 1291 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1292 } 1293 1294 /* Anything else 82598-based is supported */ 1295 if (hw->mac.type == ixgbe_mac_82598EB) 1296 return 0; 1297 1298 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1299 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1300 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1301 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1302 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1303 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1304 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1305 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1306 /* Make sure we're a supported PHY type */ 1307 if (hw->phy.type == ixgbe_phy_sfp_intel) 1308 return 0; 1309 if (hw->allow_unsupported_sfp) { 1310 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1311 return 0; 1312 } 1313 hw_dbg(hw, "SFP+ module not supported\n"); 1314 hw->phy.type = ixgbe_phy_sfp_unsupported; 1315 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1316 } 1317 return 0; 1318 1319 err_read_i2c_eeprom: 1320 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1321 if (hw->phy.type != ixgbe_phy_nl) { 1322 hw->phy.id = 0; 1323 hw->phy.type = ixgbe_phy_unknown; 1324 } 1325 return IXGBE_ERR_SFP_NOT_PRESENT; 1326 } 1327 1328 /** 1329 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1330 * @hw: pointer to hardware structure 1331 * 1332 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1333 **/ 1334 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1335 { 1336 struct ixgbe_adapter *adapter = hw->back; 1337 s32 status; 1338 u32 vendor_oui = 0; 1339 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1340 u8 identifier = 0; 1341 u8 comp_codes_1g = 0; 1342 u8 comp_codes_10g = 0; 1343 u8 oui_bytes[3] = {0, 0, 0}; 1344 u16 enforce_sfp = 0; 1345 u8 connector = 0; 1346 u8 cable_length = 0; 1347 u8 device_tech = 0; 1348 bool active_cable = false; 1349 1350 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1351 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1352 return IXGBE_ERR_SFP_NOT_PRESENT; 1353 } 1354 1355 /* LAN ID is needed for sfp_type determination */ 1356 hw->mac.ops.set_lan_id(hw); 1357 1358 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1359 &identifier); 1360 1361 if (status != 0) 1362 goto err_read_i2c_eeprom; 1363 1364 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1365 hw->phy.type = ixgbe_phy_sfp_unsupported; 1366 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1367 } 1368 1369 hw->phy.id = identifier; 1370 1371 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1372 &comp_codes_10g); 1373 1374 if (status != 0) 1375 goto err_read_i2c_eeprom; 1376 1377 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1378 &comp_codes_1g); 1379 1380 if (status != 0) 1381 goto err_read_i2c_eeprom; 1382 1383 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1384 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1385 if (hw->bus.lan_id == 0) 1386 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1387 else 1388 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1389 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1390 IXGBE_SFF_10GBASELR_CAPABLE)) { 1391 if (hw->bus.lan_id == 0) 1392 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1393 else 1394 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1395 } else { 1396 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1397 active_cable = true; 1398 1399 if (!active_cable) { 1400 /* check for active DA cables that pre-date 1401 * SFF-8436 v3.6 1402 */ 1403 hw->phy.ops.read_i2c_eeprom(hw, 1404 IXGBE_SFF_QSFP_CONNECTOR, 1405 &connector); 1406 1407 hw->phy.ops.read_i2c_eeprom(hw, 1408 IXGBE_SFF_QSFP_CABLE_LENGTH, 1409 &cable_length); 1410 1411 hw->phy.ops.read_i2c_eeprom(hw, 1412 IXGBE_SFF_QSFP_DEVICE_TECH, 1413 &device_tech); 1414 1415 if ((connector == 1416 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1417 (cable_length > 0) && 1418 ((device_tech >> 4) == 1419 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1420 active_cable = true; 1421 } 1422 1423 if (active_cable) { 1424 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1425 if (hw->bus.lan_id == 0) 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_da_act_lmt_core0; 1428 else 1429 hw->phy.sfp_type = 1430 ixgbe_sfp_type_da_act_lmt_core1; 1431 } else { 1432 /* unsupported module type */ 1433 hw->phy.type = ixgbe_phy_sfp_unsupported; 1434 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1435 } 1436 } 1437 1438 if (hw->phy.sfp_type != stored_sfp_type) 1439 hw->phy.sfp_setup_needed = true; 1440 1441 /* Determine if the QSFP+ PHY is dual speed or not. */ 1442 hw->phy.multispeed_fiber = false; 1443 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1444 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1445 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1446 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1447 hw->phy.multispeed_fiber = true; 1448 1449 /* Determine PHY vendor for optical modules */ 1450 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1451 IXGBE_SFF_10GBASELR_CAPABLE)) { 1452 status = hw->phy.ops.read_i2c_eeprom(hw, 1453 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1454 &oui_bytes[0]); 1455 1456 if (status != 0) 1457 goto err_read_i2c_eeprom; 1458 1459 status = hw->phy.ops.read_i2c_eeprom(hw, 1460 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1461 &oui_bytes[1]); 1462 1463 if (status != 0) 1464 goto err_read_i2c_eeprom; 1465 1466 status = hw->phy.ops.read_i2c_eeprom(hw, 1467 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1468 &oui_bytes[2]); 1469 1470 if (status != 0) 1471 goto err_read_i2c_eeprom; 1472 1473 vendor_oui = 1474 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1475 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1476 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1477 1478 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1479 hw->phy.type = ixgbe_phy_qsfp_intel; 1480 else 1481 hw->phy.type = ixgbe_phy_qsfp_unknown; 1482 1483 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1484 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1485 /* Make sure we're a supported PHY type */ 1486 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1487 return 0; 1488 if (hw->allow_unsupported_sfp) { 1489 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1490 return 0; 1491 } 1492 hw_dbg(hw, "QSFP module not supported\n"); 1493 hw->phy.type = ixgbe_phy_sfp_unsupported; 1494 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1495 } 1496 return 0; 1497 } 1498 return 0; 1499 1500 err_read_i2c_eeprom: 1501 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1502 hw->phy.id = 0; 1503 hw->phy.type = ixgbe_phy_unknown; 1504 1505 return IXGBE_ERR_SFP_NOT_PRESENT; 1506 } 1507 1508 /** 1509 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1510 * @hw: pointer to hardware structure 1511 * @list_offset: offset to the SFP ID list 1512 * @data_offset: offset to the SFP data block 1513 * 1514 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1515 * so it returns the offsets to the phy init sequence block. 1516 **/ 1517 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1518 u16 *list_offset, 1519 u16 *data_offset) 1520 { 1521 u16 sfp_id; 1522 u16 sfp_type = hw->phy.sfp_type; 1523 1524 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1525 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1526 1527 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1528 return IXGBE_ERR_SFP_NOT_PRESENT; 1529 1530 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1531 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1532 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1533 1534 /* 1535 * Limiting active cables and 1G Phys must be initialized as 1536 * SR modules 1537 */ 1538 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1539 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1540 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1541 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1542 sfp_type = ixgbe_sfp_type_srlr_core0; 1543 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1544 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1545 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1546 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1547 sfp_type = ixgbe_sfp_type_srlr_core1; 1548 1549 /* Read offset to PHY init contents */ 1550 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1551 hw_err(hw, "eeprom read at %d failed\n", 1552 IXGBE_PHY_INIT_OFFSET_NL); 1553 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1554 } 1555 1556 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1557 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1558 1559 /* Shift offset to first ID word */ 1560 (*list_offset)++; 1561 1562 /* 1563 * Find the matching SFP ID in the EEPROM 1564 * and program the init sequence 1565 */ 1566 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1567 goto err_phy; 1568 1569 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1570 if (sfp_id == sfp_type) { 1571 (*list_offset)++; 1572 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1573 goto err_phy; 1574 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1575 hw_dbg(hw, "SFP+ module not supported\n"); 1576 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1577 } else { 1578 break; 1579 } 1580 } else { 1581 (*list_offset) += 2; 1582 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1583 goto err_phy; 1584 } 1585 } 1586 1587 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1588 hw_dbg(hw, "No matching SFP+ module found\n"); 1589 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1590 } 1591 1592 return 0; 1593 1594 err_phy: 1595 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1596 return IXGBE_ERR_PHY; 1597 } 1598 1599 /** 1600 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1601 * @hw: pointer to hardware structure 1602 * @byte_offset: EEPROM byte offset to read 1603 * @eeprom_data: value read 1604 * 1605 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1606 **/ 1607 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1608 u8 *eeprom_data) 1609 { 1610 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1611 IXGBE_I2C_EEPROM_DEV_ADDR, 1612 eeprom_data); 1613 } 1614 1615 /** 1616 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1617 * @hw: pointer to hardware structure 1618 * @byte_offset: byte offset at address 0xA2 1619 * @eeprom_data: value read 1620 * 1621 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1622 **/ 1623 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1624 u8 *sff8472_data) 1625 { 1626 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1627 IXGBE_I2C_EEPROM_DEV_ADDR2, 1628 sff8472_data); 1629 } 1630 1631 /** 1632 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1633 * @hw: pointer to hardware structure 1634 * @byte_offset: EEPROM byte offset to write 1635 * @eeprom_data: value to write 1636 * 1637 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1638 **/ 1639 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1640 u8 eeprom_data) 1641 { 1642 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1643 IXGBE_I2C_EEPROM_DEV_ADDR, 1644 eeprom_data); 1645 } 1646 1647 /** 1648 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1649 * @hw: pointer to hardware structure 1650 * @byte_offset: byte offset to read 1651 * @data: value read 1652 * 1653 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1654 * a specified device address. 1655 **/ 1656 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1657 u8 dev_addr, u8 *data) 1658 { 1659 s32 status; 1660 u32 max_retry = 10; 1661 u32 retry = 0; 1662 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1663 bool nack = true; 1664 *data = 0; 1665 1666 do { 1667 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1668 return IXGBE_ERR_SWFW_SYNC; 1669 1670 ixgbe_i2c_start(hw); 1671 1672 /* Device Address and write indication */ 1673 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1674 if (status != 0) 1675 goto fail; 1676 1677 status = ixgbe_get_i2c_ack(hw); 1678 if (status != 0) 1679 goto fail; 1680 1681 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1682 if (status != 0) 1683 goto fail; 1684 1685 status = ixgbe_get_i2c_ack(hw); 1686 if (status != 0) 1687 goto fail; 1688 1689 ixgbe_i2c_start(hw); 1690 1691 /* Device Address and read indication */ 1692 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1693 if (status != 0) 1694 goto fail; 1695 1696 status = ixgbe_get_i2c_ack(hw); 1697 if (status != 0) 1698 goto fail; 1699 1700 status = ixgbe_clock_in_i2c_byte(hw, data); 1701 if (status != 0) 1702 goto fail; 1703 1704 status = ixgbe_clock_out_i2c_bit(hw, nack); 1705 if (status != 0) 1706 goto fail; 1707 1708 ixgbe_i2c_stop(hw); 1709 break; 1710 1711 fail: 1712 ixgbe_i2c_bus_clear(hw); 1713 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1714 msleep(100); 1715 retry++; 1716 if (retry < max_retry) 1717 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1718 else 1719 hw_dbg(hw, "I2C byte read error.\n"); 1720 1721 } while (retry < max_retry); 1722 1723 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1724 1725 return status; 1726 } 1727 1728 /** 1729 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1730 * @hw: pointer to hardware structure 1731 * @byte_offset: byte offset to write 1732 * @data: value to write 1733 * 1734 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1735 * a specified device address. 1736 **/ 1737 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1738 u8 dev_addr, u8 data) 1739 { 1740 s32 status; 1741 u32 max_retry = 1; 1742 u32 retry = 0; 1743 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1744 1745 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1746 return IXGBE_ERR_SWFW_SYNC; 1747 1748 do { 1749 ixgbe_i2c_start(hw); 1750 1751 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1752 if (status != 0) 1753 goto fail; 1754 1755 status = ixgbe_get_i2c_ack(hw); 1756 if (status != 0) 1757 goto fail; 1758 1759 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1760 if (status != 0) 1761 goto fail; 1762 1763 status = ixgbe_get_i2c_ack(hw); 1764 if (status != 0) 1765 goto fail; 1766 1767 status = ixgbe_clock_out_i2c_byte(hw, data); 1768 if (status != 0) 1769 goto fail; 1770 1771 status = ixgbe_get_i2c_ack(hw); 1772 if (status != 0) 1773 goto fail; 1774 1775 ixgbe_i2c_stop(hw); 1776 break; 1777 1778 fail: 1779 ixgbe_i2c_bus_clear(hw); 1780 retry++; 1781 if (retry < max_retry) 1782 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1783 else 1784 hw_dbg(hw, "I2C byte write error.\n"); 1785 } while (retry < max_retry); 1786 1787 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1788 1789 return status; 1790 } 1791 1792 /** 1793 * ixgbe_i2c_start - Sets I2C start condition 1794 * @hw: pointer to hardware structure 1795 * 1796 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1797 **/ 1798 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1799 { 1800 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1801 1802 /* Start condition must begin with data and clock high */ 1803 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1804 ixgbe_raise_i2c_clk(hw, &i2cctl); 1805 1806 /* Setup time for start condition (4.7us) */ 1807 udelay(IXGBE_I2C_T_SU_STA); 1808 1809 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1810 1811 /* Hold time for start condition (4us) */ 1812 udelay(IXGBE_I2C_T_HD_STA); 1813 1814 ixgbe_lower_i2c_clk(hw, &i2cctl); 1815 1816 /* Minimum low period of clock is 4.7 us */ 1817 udelay(IXGBE_I2C_T_LOW); 1818 1819 } 1820 1821 /** 1822 * ixgbe_i2c_stop - Sets I2C stop condition 1823 * @hw: pointer to hardware structure 1824 * 1825 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1826 **/ 1827 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1828 { 1829 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1830 1831 /* Stop condition must begin with data low and clock high */ 1832 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1833 ixgbe_raise_i2c_clk(hw, &i2cctl); 1834 1835 /* Setup time for stop condition (4us) */ 1836 udelay(IXGBE_I2C_T_SU_STO); 1837 1838 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1839 1840 /* bus free time between stop and start (4.7us)*/ 1841 udelay(IXGBE_I2C_T_BUF); 1842 } 1843 1844 /** 1845 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1846 * @hw: pointer to hardware structure 1847 * @data: data byte to clock in 1848 * 1849 * Clocks in one byte data via I2C data/clock 1850 **/ 1851 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1852 { 1853 s32 i; 1854 bool bit = false; 1855 1856 for (i = 7; i >= 0; i--) { 1857 ixgbe_clock_in_i2c_bit(hw, &bit); 1858 *data |= bit << i; 1859 } 1860 1861 return 0; 1862 } 1863 1864 /** 1865 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1866 * @hw: pointer to hardware structure 1867 * @data: data byte clocked out 1868 * 1869 * Clocks out one byte data via I2C data/clock 1870 **/ 1871 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1872 { 1873 s32 status; 1874 s32 i; 1875 u32 i2cctl; 1876 bool bit = false; 1877 1878 for (i = 7; i >= 0; i--) { 1879 bit = (data >> i) & 0x1; 1880 status = ixgbe_clock_out_i2c_bit(hw, bit); 1881 1882 if (status != 0) 1883 break; 1884 } 1885 1886 /* Release SDA line (set high) */ 1887 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1888 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 1889 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 1890 IXGBE_WRITE_FLUSH(hw); 1891 1892 return status; 1893 } 1894 1895 /** 1896 * ixgbe_get_i2c_ack - Polls for I2C ACK 1897 * @hw: pointer to hardware structure 1898 * 1899 * Clocks in/out one bit via I2C data/clock 1900 **/ 1901 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1902 { 1903 s32 status = 0; 1904 u32 i = 0; 1905 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1906 u32 timeout = 10; 1907 bool ack = true; 1908 1909 ixgbe_raise_i2c_clk(hw, &i2cctl); 1910 1911 1912 /* Minimum high period of clock is 4us */ 1913 udelay(IXGBE_I2C_T_HIGH); 1914 1915 /* Poll for ACK. Note that ACK in I2C spec is 1916 * transition from 1 to 0 */ 1917 for (i = 0; i < timeout; i++) { 1918 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1919 ack = ixgbe_get_i2c_data(hw, &i2cctl); 1920 1921 udelay(1); 1922 if (ack == 0) 1923 break; 1924 } 1925 1926 if (ack == 1) { 1927 hw_dbg(hw, "I2C ack was not received.\n"); 1928 status = IXGBE_ERR_I2C; 1929 } 1930 1931 ixgbe_lower_i2c_clk(hw, &i2cctl); 1932 1933 /* Minimum low period of clock is 4.7 us */ 1934 udelay(IXGBE_I2C_T_LOW); 1935 1936 return status; 1937 } 1938 1939 /** 1940 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1941 * @hw: pointer to hardware structure 1942 * @data: read data value 1943 * 1944 * Clocks in one bit via I2C data/clock 1945 **/ 1946 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1947 { 1948 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1949 1950 ixgbe_raise_i2c_clk(hw, &i2cctl); 1951 1952 /* Minimum high period of clock is 4us */ 1953 udelay(IXGBE_I2C_T_HIGH); 1954 1955 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1956 *data = ixgbe_get_i2c_data(hw, &i2cctl); 1957 1958 ixgbe_lower_i2c_clk(hw, &i2cctl); 1959 1960 /* Minimum low period of clock is 4.7 us */ 1961 udelay(IXGBE_I2C_T_LOW); 1962 1963 return 0; 1964 } 1965 1966 /** 1967 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1968 * @hw: pointer to hardware structure 1969 * @data: data value to write 1970 * 1971 * Clocks out one bit via I2C data/clock 1972 **/ 1973 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1974 { 1975 s32 status; 1976 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1977 1978 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1979 if (status == 0) { 1980 ixgbe_raise_i2c_clk(hw, &i2cctl); 1981 1982 /* Minimum high period of clock is 4us */ 1983 udelay(IXGBE_I2C_T_HIGH); 1984 1985 ixgbe_lower_i2c_clk(hw, &i2cctl); 1986 1987 /* Minimum low period of clock is 4.7 us. 1988 * This also takes care of the data hold time. 1989 */ 1990 udelay(IXGBE_I2C_T_LOW); 1991 } else { 1992 hw_dbg(hw, "I2C data was not set to %X\n", data); 1993 return IXGBE_ERR_I2C; 1994 } 1995 1996 return 0; 1997 } 1998 /** 1999 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2000 * @hw: pointer to hardware structure 2001 * @i2cctl: Current value of I2CCTL register 2002 * 2003 * Raises the I2C clock line '0'->'1' 2004 **/ 2005 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2006 { 2007 u32 i = 0; 2008 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2009 u32 i2cctl_r = 0; 2010 2011 for (i = 0; i < timeout; i++) { 2012 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); 2013 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2014 IXGBE_WRITE_FLUSH(hw); 2015 /* SCL rise time (1000ns) */ 2016 udelay(IXGBE_I2C_T_RISE); 2017 2018 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2019 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) 2020 break; 2021 } 2022 } 2023 2024 /** 2025 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2026 * @hw: pointer to hardware structure 2027 * @i2cctl: Current value of I2CCTL register 2028 * 2029 * Lowers the I2C clock line '1'->'0' 2030 **/ 2031 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2032 { 2033 2034 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); 2035 2036 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2037 IXGBE_WRITE_FLUSH(hw); 2038 2039 /* SCL fall time (300ns) */ 2040 udelay(IXGBE_I2C_T_FALL); 2041 } 2042 2043 /** 2044 * ixgbe_set_i2c_data - Sets the I2C data bit 2045 * @hw: pointer to hardware structure 2046 * @i2cctl: Current value of I2CCTL register 2047 * @data: I2C data value (0 or 1) to set 2048 * 2049 * Sets the I2C data bit 2050 **/ 2051 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2052 { 2053 if (data) 2054 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2055 else 2056 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); 2057 2058 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2059 IXGBE_WRITE_FLUSH(hw); 2060 2061 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2062 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2063 2064 /* Verify data was set correctly */ 2065 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2066 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2067 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2068 return IXGBE_ERR_I2C; 2069 } 2070 2071 return 0; 2072 } 2073 2074 /** 2075 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2076 * @hw: pointer to hardware structure 2077 * @i2cctl: Current value of I2CCTL register 2078 * 2079 * Returns the I2C data bit value 2080 **/ 2081 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2082 { 2083 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) 2084 return true; 2085 return false; 2086 } 2087 2088 /** 2089 * ixgbe_i2c_bus_clear - Clears the I2C bus 2090 * @hw: pointer to hardware structure 2091 * 2092 * Clears the I2C bus by sending nine clock pulses. 2093 * Used when data line is stuck low. 2094 **/ 2095 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2096 { 2097 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2098 u32 i; 2099 2100 ixgbe_i2c_start(hw); 2101 2102 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2103 2104 for (i = 0; i < 9; i++) { 2105 ixgbe_raise_i2c_clk(hw, &i2cctl); 2106 2107 /* Min high period of clock is 4us */ 2108 udelay(IXGBE_I2C_T_HIGH); 2109 2110 ixgbe_lower_i2c_clk(hw, &i2cctl); 2111 2112 /* Min low period of clock is 4.7us*/ 2113 udelay(IXGBE_I2C_T_LOW); 2114 } 2115 2116 ixgbe_i2c_start(hw); 2117 2118 /* Put the i2c bus back to default state */ 2119 ixgbe_i2c_stop(hw); 2120 } 2121 2122 /** 2123 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2124 * @hw: pointer to hardware structure 2125 * 2126 * Checks if the LASI temp alarm status was triggered due to overtemp 2127 **/ 2128 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2129 { 2130 u16 phy_data = 0; 2131 2132 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2133 return 0; 2134 2135 /* Check that the LASI temp alarm status was triggered */ 2136 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2137 MDIO_MMD_PMAPMD, &phy_data); 2138 2139 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2140 return 0; 2141 2142 return IXGBE_ERR_OVERTEMP; 2143 } 2144 2145 /** ixgbe_set_copper_phy_power - Control power for copper phy 2146 * @hw: pointer to hardware structure 2147 * @on: true for on, false for off 2148 **/ 2149 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2150 { 2151 u32 status; 2152 u16 reg; 2153 2154 /* Bail if we don't have copper phy */ 2155 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2156 return 0; 2157 2158 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2159 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2160 ®); 2161 if (status) 2162 return status; 2163 2164 if (on) { 2165 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2166 } else { 2167 if (ixgbe_check_reset_blocked(hw)) 2168 return 0; 2169 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2170 } 2171 2172 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2173 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2174 reg); 2175 return status; 2176 } 2177