1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static const struct net_device_ops ixgbe_netdev_ops; 196 197 static bool netif_is_ixgbe(struct net_device *dev) 198 { 199 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 200 } 201 202 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 203 u32 reg, u16 *value) 204 { 205 struct pci_dev *parent_dev; 206 struct pci_bus *parent_bus; 207 208 parent_bus = adapter->pdev->bus->parent; 209 if (!parent_bus) 210 return -1; 211 212 parent_dev = parent_bus->self; 213 if (!parent_dev) 214 return -1; 215 216 if (!pci_is_pcie(parent_dev)) 217 return -1; 218 219 pcie_capability_read_word(parent_dev, reg, value); 220 if (*value == IXGBE_FAILED_READ_CFG_WORD && 221 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 222 return -1; 223 return 0; 224 } 225 226 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 227 { 228 struct ixgbe_hw *hw = &adapter->hw; 229 u16 link_status = 0; 230 int err; 231 232 hw->bus.type = ixgbe_bus_type_pci_express; 233 234 /* Get the negotiated link width and speed from PCI config space of the 235 * parent, as this device is behind a switch 236 */ 237 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 238 239 /* assume caller will handle error case */ 240 if (err) 241 return err; 242 243 hw->bus.width = ixgbe_convert_bus_width(link_status); 244 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 245 246 return 0; 247 } 248 249 /** 250 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 251 * @hw: hw specific details 252 * 253 * This function is used by probe to determine whether a device's PCI-Express 254 * bandwidth details should be gathered from the parent bus instead of from the 255 * device. Used to ensure that various locations all have the correct device ID 256 * checks. 257 */ 258 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 259 { 260 switch (hw->device_id) { 261 case IXGBE_DEV_ID_82599_SFP_SF_QP: 262 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 263 return true; 264 default: 265 return false; 266 } 267 } 268 269 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 270 int expected_gts) 271 { 272 struct ixgbe_hw *hw = &adapter->hw; 273 int max_gts = 0; 274 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 275 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 276 struct pci_dev *pdev; 277 278 /* Some devices are not connected over PCIe and thus do not negotiate 279 * speed. These devices do not have valid bus info, and thus any report 280 * we generate may not be correct. 281 */ 282 if (hw->bus.type == ixgbe_bus_type_internal) 283 return; 284 285 /* determine whether to use the parent device */ 286 if (ixgbe_pcie_from_parent(&adapter->hw)) 287 pdev = adapter->pdev->bus->parent->self; 288 else 289 pdev = adapter->pdev; 290 291 if (pcie_get_minimum_link(pdev, &speed, &width) || 292 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 293 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 294 return; 295 } 296 297 switch (speed) { 298 case PCIE_SPEED_2_5GT: 299 /* 8b/10b encoding reduces max throughput by 20% */ 300 max_gts = 2 * width; 301 break; 302 case PCIE_SPEED_5_0GT: 303 /* 8b/10b encoding reduces max throughput by 20% */ 304 max_gts = 4 * width; 305 break; 306 case PCIE_SPEED_8_0GT: 307 /* 128b/130b encoding reduces throughput by less than 2% */ 308 max_gts = 8 * width; 309 break; 310 default: 311 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 312 return; 313 } 314 315 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 316 max_gts); 317 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 318 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 319 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 320 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 321 "Unknown"), 322 width, 323 (speed == PCIE_SPEED_2_5GT ? "20%" : 324 speed == PCIE_SPEED_5_0GT ? "20%" : 325 speed == PCIE_SPEED_8_0GT ? "<2%" : 326 "Unknown")); 327 328 if (max_gts < expected_gts) { 329 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 330 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 331 expected_gts); 332 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 333 } 334 } 335 336 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 337 { 338 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 339 !test_bit(__IXGBE_REMOVING, &adapter->state) && 340 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 341 queue_work(ixgbe_wq, &adapter->service_task); 342 } 343 344 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 345 { 346 struct ixgbe_adapter *adapter = hw->back; 347 348 if (!hw->hw_addr) 349 return; 350 hw->hw_addr = NULL; 351 e_dev_err("Adapter removed\n"); 352 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 353 ixgbe_service_event_schedule(adapter); 354 } 355 356 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 357 { 358 u8 __iomem *reg_addr; 359 u32 value; 360 int i; 361 362 reg_addr = READ_ONCE(hw->hw_addr); 363 if (ixgbe_removed(reg_addr)) 364 return IXGBE_FAILED_READ_REG; 365 366 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 367 * so perform several status register reads to determine if the adapter 368 * has been removed. 369 */ 370 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 371 value = readl(reg_addr + IXGBE_STATUS); 372 if (value != IXGBE_FAILED_READ_REG) 373 break; 374 mdelay(3); 375 } 376 377 if (value == IXGBE_FAILED_READ_REG) 378 ixgbe_remove_adapter(hw); 379 else 380 value = readl(reg_addr + reg); 381 return value; 382 } 383 384 /** 385 * ixgbe_read_reg - Read from device register 386 * @hw: hw specific details 387 * @reg: offset of register to read 388 * 389 * Returns : value read or IXGBE_FAILED_READ_REG if removed 390 * 391 * This function is used to read device registers. It checks for device 392 * removal by confirming any read that returns all ones by checking the 393 * status register value for all ones. This function avoids reading from 394 * the hardware if a removal was previously detected in which case it 395 * returns IXGBE_FAILED_READ_REG (all ones). 396 */ 397 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 398 { 399 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 400 u32 value; 401 402 if (ixgbe_removed(reg_addr)) 403 return IXGBE_FAILED_READ_REG; 404 if (unlikely(hw->phy.nw_mng_if_sel & 405 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 406 struct ixgbe_adapter *adapter; 407 int i; 408 409 for (i = 0; i < 200; ++i) { 410 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 411 if (likely(!value)) 412 goto writes_completed; 413 if (value == IXGBE_FAILED_READ_REG) { 414 ixgbe_remove_adapter(hw); 415 return IXGBE_FAILED_READ_REG; 416 } 417 udelay(5); 418 } 419 420 adapter = hw->back; 421 e_warn(hw, "register writes incomplete %08x\n", value); 422 } 423 424 writes_completed: 425 value = readl(reg_addr + reg); 426 if (unlikely(value == IXGBE_FAILED_READ_REG)) 427 value = ixgbe_check_remove(hw, reg); 428 return value; 429 } 430 431 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 432 { 433 u16 value; 434 435 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 436 if (value == IXGBE_FAILED_READ_CFG_WORD) { 437 ixgbe_remove_adapter(hw); 438 return true; 439 } 440 return false; 441 } 442 443 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 444 { 445 struct ixgbe_adapter *adapter = hw->back; 446 u16 value; 447 448 if (ixgbe_removed(hw->hw_addr)) 449 return IXGBE_FAILED_READ_CFG_WORD; 450 pci_read_config_word(adapter->pdev, reg, &value); 451 if (value == IXGBE_FAILED_READ_CFG_WORD && 452 ixgbe_check_cfg_remove(hw, adapter->pdev)) 453 return IXGBE_FAILED_READ_CFG_WORD; 454 return value; 455 } 456 457 #ifdef CONFIG_PCI_IOV 458 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 459 { 460 struct ixgbe_adapter *adapter = hw->back; 461 u32 value; 462 463 if (ixgbe_removed(hw->hw_addr)) 464 return IXGBE_FAILED_READ_CFG_DWORD; 465 pci_read_config_dword(adapter->pdev, reg, &value); 466 if (value == IXGBE_FAILED_READ_CFG_DWORD && 467 ixgbe_check_cfg_remove(hw, adapter->pdev)) 468 return IXGBE_FAILED_READ_CFG_DWORD; 469 return value; 470 } 471 #endif /* CONFIG_PCI_IOV */ 472 473 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 474 { 475 struct ixgbe_adapter *adapter = hw->back; 476 477 if (ixgbe_removed(hw->hw_addr)) 478 return; 479 pci_write_config_word(adapter->pdev, reg, value); 480 } 481 482 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 483 { 484 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 485 486 /* flush memory to make sure state is correct before next watchdog */ 487 smp_mb__before_atomic(); 488 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 489 } 490 491 struct ixgbe_reg_info { 492 u32 ofs; 493 char *name; 494 }; 495 496 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 497 498 /* General Registers */ 499 {IXGBE_CTRL, "CTRL"}, 500 {IXGBE_STATUS, "STATUS"}, 501 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 502 503 /* Interrupt Registers */ 504 {IXGBE_EICR, "EICR"}, 505 506 /* RX Registers */ 507 {IXGBE_SRRCTL(0), "SRRCTL"}, 508 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 509 {IXGBE_RDLEN(0), "RDLEN"}, 510 {IXGBE_RDH(0), "RDH"}, 511 {IXGBE_RDT(0), "RDT"}, 512 {IXGBE_RXDCTL(0), "RXDCTL"}, 513 {IXGBE_RDBAL(0), "RDBAL"}, 514 {IXGBE_RDBAH(0), "RDBAH"}, 515 516 /* TX Registers */ 517 {IXGBE_TDBAL(0), "TDBAL"}, 518 {IXGBE_TDBAH(0), "TDBAH"}, 519 {IXGBE_TDLEN(0), "TDLEN"}, 520 {IXGBE_TDH(0), "TDH"}, 521 {IXGBE_TDT(0), "TDT"}, 522 {IXGBE_TXDCTL(0), "TXDCTL"}, 523 524 /* List Terminator */ 525 { .name = NULL } 526 }; 527 528 529 /* 530 * ixgbe_regdump - register printout routine 531 */ 532 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 533 { 534 int i; 535 char rname[16]; 536 u32 regs[64]; 537 538 switch (reginfo->ofs) { 539 case IXGBE_SRRCTL(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 542 break; 543 case IXGBE_DCA_RXCTRL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 546 break; 547 case IXGBE_RDLEN(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 550 break; 551 case IXGBE_RDH(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 554 break; 555 case IXGBE_RDT(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 558 break; 559 case IXGBE_RXDCTL(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 562 break; 563 case IXGBE_RDBAL(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 566 break; 567 case IXGBE_RDBAH(0): 568 for (i = 0; i < 64; i++) 569 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 570 break; 571 case IXGBE_TDBAL(0): 572 for (i = 0; i < 64; i++) 573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 574 break; 575 case IXGBE_TDBAH(0): 576 for (i = 0; i < 64; i++) 577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 578 break; 579 case IXGBE_TDLEN(0): 580 for (i = 0; i < 64; i++) 581 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 582 break; 583 case IXGBE_TDH(0): 584 for (i = 0; i < 64; i++) 585 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 586 break; 587 case IXGBE_TDT(0): 588 for (i = 0; i < 64; i++) 589 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 590 break; 591 case IXGBE_TXDCTL(0): 592 for (i = 0; i < 64; i++) 593 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 594 break; 595 default: 596 pr_info("%-15s %08x\n", 597 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 598 return; 599 } 600 601 i = 0; 602 while (i < 64) { 603 int j; 604 char buf[9 * 8 + 1]; 605 char *p = buf; 606 607 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 608 for (j = 0; j < 8; j++) 609 p += sprintf(p, " %08x", regs[i++]); 610 pr_err("%-15s%s\n", rname, buf); 611 } 612 613 } 614 615 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 616 { 617 struct ixgbe_tx_buffer *tx_buffer; 618 619 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 620 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 621 n, ring->next_to_use, ring->next_to_clean, 622 (u64)dma_unmap_addr(tx_buffer, dma), 623 dma_unmap_len(tx_buffer, len), 624 tx_buffer->next_to_watch, 625 (u64)tx_buffer->time_stamp); 626 } 627 628 /* 629 * ixgbe_dump - Print registers, tx-rings and rx-rings 630 */ 631 static void ixgbe_dump(struct ixgbe_adapter *adapter) 632 { 633 struct net_device *netdev = adapter->netdev; 634 struct ixgbe_hw *hw = &adapter->hw; 635 struct ixgbe_reg_info *reginfo; 636 int n = 0; 637 struct ixgbe_ring *ring; 638 struct ixgbe_tx_buffer *tx_buffer; 639 union ixgbe_adv_tx_desc *tx_desc; 640 struct my_u0 { u64 a; u64 b; } *u0; 641 struct ixgbe_ring *rx_ring; 642 union ixgbe_adv_rx_desc *rx_desc; 643 struct ixgbe_rx_buffer *rx_buffer_info; 644 int i = 0; 645 646 if (!netif_msg_hw(adapter)) 647 return; 648 649 /* Print netdevice Info */ 650 if (netdev) { 651 dev_info(&adapter->pdev->dev, "Net device Info\n"); 652 pr_info("Device Name state " 653 "trans_start\n"); 654 pr_info("%-15s %016lX %016lX\n", 655 netdev->name, 656 netdev->state, 657 dev_trans_start(netdev)); 658 } 659 660 /* Print Registers */ 661 dev_info(&adapter->pdev->dev, "Register Dump\n"); 662 pr_info(" Register Name Value\n"); 663 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 664 reginfo->name; reginfo++) { 665 ixgbe_regdump(hw, reginfo); 666 } 667 668 /* Print TX Ring Summary */ 669 if (!netdev || !netif_running(netdev)) 670 return; 671 672 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 673 pr_info(" %s %s %s %s\n", 674 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 675 "leng", "ntw", "timestamp"); 676 for (n = 0; n < adapter->num_tx_queues; n++) { 677 ring = adapter->tx_ring[n]; 678 ixgbe_print_buffer(ring, n); 679 } 680 681 for (n = 0; n < adapter->num_xdp_queues; n++) { 682 ring = adapter->xdp_ring[n]; 683 ixgbe_print_buffer(ring, n); 684 } 685 686 /* Print TX Rings */ 687 if (!netif_msg_tx_done(adapter)) 688 goto rx_ring_summary; 689 690 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 691 692 /* Transmit Descriptor Formats 693 * 694 * 82598 Advanced Transmit Descriptor 695 * +--------------------------------------------------------------+ 696 * 0 | Buffer Address [63:0] | 697 * +--------------------------------------------------------------+ 698 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 699 * +--------------------------------------------------------------+ 700 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 701 * 702 * 82598 Advanced Transmit Descriptor (Write-Back Format) 703 * +--------------------------------------------------------------+ 704 * 0 | RSV [63:0] | 705 * +--------------------------------------------------------------+ 706 * 8 | RSV | STA | NXTSEQ | 707 * +--------------------------------------------------------------+ 708 * 63 36 35 32 31 0 709 * 710 * 82599+ Advanced Transmit Descriptor 711 * +--------------------------------------------------------------+ 712 * 0 | Buffer Address [63:0] | 713 * +--------------------------------------------------------------+ 714 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 715 * +--------------------------------------------------------------+ 716 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 717 * 718 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 719 * +--------------------------------------------------------------+ 720 * 0 | RSV [63:0] | 721 * +--------------------------------------------------------------+ 722 * 8 | RSV | STA | RSV | 723 * +--------------------------------------------------------------+ 724 * 63 36 35 32 31 0 725 */ 726 727 for (n = 0; n < adapter->num_tx_queues; n++) { 728 ring = adapter->tx_ring[n]; 729 pr_info("------------------------------------\n"); 730 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 731 pr_info("------------------------------------\n"); 732 pr_info("%s%s %s %s %s %s\n", 733 "T [desc] [address 63:0 ] ", 734 "[PlPOIdStDDt Ln] [bi->dma ] ", 735 "leng", "ntw", "timestamp", "bi->skb"); 736 737 for (i = 0; ring->desc && (i < ring->count); i++) { 738 tx_desc = IXGBE_TX_DESC(ring, i); 739 tx_buffer = &ring->tx_buffer_info[i]; 740 u0 = (struct my_u0 *)tx_desc; 741 if (dma_unmap_len(tx_buffer, len) > 0) { 742 const char *ring_desc; 743 744 if (i == ring->next_to_use && 745 i == ring->next_to_clean) 746 ring_desc = " NTC/U"; 747 else if (i == ring->next_to_use) 748 ring_desc = " NTU"; 749 else if (i == ring->next_to_clean) 750 ring_desc = " NTC"; 751 else 752 ring_desc = ""; 753 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 754 i, 755 le64_to_cpu(u0->a), 756 le64_to_cpu(u0->b), 757 (u64)dma_unmap_addr(tx_buffer, dma), 758 dma_unmap_len(tx_buffer, len), 759 tx_buffer->next_to_watch, 760 (u64)tx_buffer->time_stamp, 761 tx_buffer->skb, 762 ring_desc); 763 764 if (netif_msg_pktdata(adapter) && 765 tx_buffer->skb) 766 print_hex_dump(KERN_INFO, "", 767 DUMP_PREFIX_ADDRESS, 16, 1, 768 tx_buffer->skb->data, 769 dma_unmap_len(tx_buffer, len), 770 true); 771 } 772 } 773 } 774 775 /* Print RX Rings Summary */ 776 rx_ring_summary: 777 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 778 pr_info("Queue [NTU] [NTC]\n"); 779 for (n = 0; n < adapter->num_rx_queues; n++) { 780 rx_ring = adapter->rx_ring[n]; 781 pr_info("%5d %5X %5X\n", 782 n, rx_ring->next_to_use, rx_ring->next_to_clean); 783 } 784 785 /* Print RX Rings */ 786 if (!netif_msg_rx_status(adapter)) 787 return; 788 789 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 790 791 /* Receive Descriptor Formats 792 * 793 * 82598 Advanced Receive Descriptor (Read) Format 794 * 63 1 0 795 * +-----------------------------------------------------+ 796 * 0 | Packet Buffer Address [63:1] |A0/NSE| 797 * +----------------------------------------------+------+ 798 * 8 | Header Buffer Address [63:1] | DD | 799 * +-----------------------------------------------------+ 800 * 801 * 802 * 82598 Advanced Receive Descriptor (Write-Back) Format 803 * 804 * 63 48 47 32 31 30 21 20 16 15 4 3 0 805 * +------------------------------------------------------+ 806 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 807 * | Packet | IP | | | | Type | Type | 808 * | Checksum | Ident | | | | | | 809 * +------------------------------------------------------+ 810 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 811 * +------------------------------------------------------+ 812 * 63 48 47 32 31 20 19 0 813 * 814 * 82599+ Advanced Receive Descriptor (Read) Format 815 * 63 1 0 816 * +-----------------------------------------------------+ 817 * 0 | Packet Buffer Address [63:1] |A0/NSE| 818 * +----------------------------------------------+------+ 819 * 8 | Header Buffer Address [63:1] | DD | 820 * +-----------------------------------------------------+ 821 * 822 * 823 * 82599+ Advanced Receive Descriptor (Write-Back) Format 824 * 825 * 63 48 47 32 31 30 21 20 17 16 4 3 0 826 * +------------------------------------------------------+ 827 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 828 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 829 * |/ Flow Dir Flt ID | | | | | | 830 * +------------------------------------------------------+ 831 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 832 * +------------------------------------------------------+ 833 * 63 48 47 32 31 20 19 0 834 */ 835 836 for (n = 0; n < adapter->num_rx_queues; n++) { 837 rx_ring = adapter->rx_ring[n]; 838 pr_info("------------------------------------\n"); 839 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 840 pr_info("------------------------------------\n"); 841 pr_info("%s%s%s\n", 842 "R [desc] [ PktBuf A0] ", 843 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 844 "<-- Adv Rx Read format"); 845 pr_info("%s%s%s\n", 846 "RWB[desc] [PcsmIpSHl PtRs] ", 847 "[vl er S cks ln] ---------------- [bi->skb ] ", 848 "<-- Adv Rx Write-Back format"); 849 850 for (i = 0; i < rx_ring->count; i++) { 851 const char *ring_desc; 852 853 if (i == rx_ring->next_to_use) 854 ring_desc = " NTU"; 855 else if (i == rx_ring->next_to_clean) 856 ring_desc = " NTC"; 857 else 858 ring_desc = ""; 859 860 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 861 rx_desc = IXGBE_RX_DESC(rx_ring, i); 862 u0 = (struct my_u0 *)rx_desc; 863 if (rx_desc->wb.upper.length) { 864 /* Descriptor Done */ 865 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 866 i, 867 le64_to_cpu(u0->a), 868 le64_to_cpu(u0->b), 869 rx_buffer_info->skb, 870 ring_desc); 871 } else { 872 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 873 i, 874 le64_to_cpu(u0->a), 875 le64_to_cpu(u0->b), 876 (u64)rx_buffer_info->dma, 877 rx_buffer_info->skb, 878 ring_desc); 879 880 if (netif_msg_pktdata(adapter) && 881 rx_buffer_info->dma) { 882 print_hex_dump(KERN_INFO, "", 883 DUMP_PREFIX_ADDRESS, 16, 1, 884 page_address(rx_buffer_info->page) + 885 rx_buffer_info->page_offset, 886 ixgbe_rx_bufsz(rx_ring), true); 887 } 888 } 889 } 890 } 891 } 892 893 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 894 { 895 u32 ctrl_ext; 896 897 /* Let firmware take over control of h/w */ 898 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 900 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 901 } 902 903 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 904 { 905 u32 ctrl_ext; 906 907 /* Let firmware know the driver has taken over */ 908 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 910 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 911 } 912 913 /** 914 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 915 * @adapter: pointer to adapter struct 916 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 917 * @queue: queue to map the corresponding interrupt to 918 * @msix_vector: the vector to map to the corresponding queue 919 * 920 */ 921 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 922 u8 queue, u8 msix_vector) 923 { 924 u32 ivar, index; 925 struct ixgbe_hw *hw = &adapter->hw; 926 switch (hw->mac.type) { 927 case ixgbe_mac_82598EB: 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 if (direction == -1) 930 direction = 0; 931 index = (((direction * 64) + queue) >> 2) & 0x1F; 932 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 933 ivar &= ~(0xFF << (8 * (queue & 0x3))); 934 ivar |= (msix_vector << (8 * (queue & 0x3))); 935 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 936 break; 937 case ixgbe_mac_82599EB: 938 case ixgbe_mac_X540: 939 case ixgbe_mac_X550: 940 case ixgbe_mac_X550EM_x: 941 case ixgbe_mac_x550em_a: 942 if (direction == -1) { 943 /* other causes */ 944 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 945 index = ((queue & 1) * 8); 946 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 947 ivar &= ~(0xFF << index); 948 ivar |= (msix_vector << index); 949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 950 break; 951 } else { 952 /* tx or rx causes */ 953 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 954 index = ((16 * (queue & 1)) + (8 * direction)); 955 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 956 ivar &= ~(0xFF << index); 957 ivar |= (msix_vector << index); 958 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 959 break; 960 } 961 default: 962 break; 963 } 964 } 965 966 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 967 u64 qmask) 968 { 969 u32 mask; 970 971 switch (adapter->hw.mac.type) { 972 case ixgbe_mac_82598EB: 973 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 974 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 975 break; 976 case ixgbe_mac_82599EB: 977 case ixgbe_mac_X540: 978 case ixgbe_mac_X550: 979 case ixgbe_mac_X550EM_x: 980 case ixgbe_mac_x550em_a: 981 mask = (qmask & 0xFFFFFFFF); 982 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 983 mask = (qmask >> 32); 984 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 985 break; 986 default: 987 break; 988 } 989 } 990 991 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 992 { 993 struct ixgbe_hw *hw = &adapter->hw; 994 struct ixgbe_hw_stats *hwstats = &adapter->stats; 995 int i; 996 u32 data; 997 998 if ((hw->fc.current_mode != ixgbe_fc_full) && 999 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 1000 return; 1001 1002 switch (hw->mac.type) { 1003 case ixgbe_mac_82598EB: 1004 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 1005 break; 1006 default: 1007 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 1008 } 1009 hwstats->lxoffrxc += data; 1010 1011 /* refill credits (no tx hang) if we received xoff */ 1012 if (!data) 1013 return; 1014 1015 for (i = 0; i < adapter->num_tx_queues; i++) 1016 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1017 &adapter->tx_ring[i]->state); 1018 1019 for (i = 0; i < adapter->num_xdp_queues; i++) 1020 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1021 &adapter->xdp_ring[i]->state); 1022 } 1023 1024 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1025 { 1026 struct ixgbe_hw *hw = &adapter->hw; 1027 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1028 u32 xoff[8] = {0}; 1029 u8 tc; 1030 int i; 1031 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1032 1033 if (adapter->ixgbe_ieee_pfc) 1034 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1035 1036 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1037 ixgbe_update_xoff_rx_lfc(adapter); 1038 return; 1039 } 1040 1041 /* update stats for each tc, only valid with PFC enabled */ 1042 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1043 u32 pxoffrxc; 1044 1045 switch (hw->mac.type) { 1046 case ixgbe_mac_82598EB: 1047 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1048 break; 1049 default: 1050 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1051 } 1052 hwstats->pxoffrxc[i] += pxoffrxc; 1053 /* Get the TC for given UP */ 1054 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1055 xoff[tc] += pxoffrxc; 1056 } 1057 1058 /* disarm tx queues that have received xoff frames */ 1059 for (i = 0; i < adapter->num_tx_queues; i++) { 1060 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1061 1062 tc = tx_ring->dcb_tc; 1063 if (xoff[tc]) 1064 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1065 } 1066 1067 for (i = 0; i < adapter->num_xdp_queues; i++) { 1068 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1069 1070 tc = xdp_ring->dcb_tc; 1071 if (xoff[tc]) 1072 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1073 } 1074 } 1075 1076 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1077 { 1078 return ring->stats.packets; 1079 } 1080 1081 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1082 { 1083 unsigned int head, tail; 1084 1085 head = ring->next_to_clean; 1086 tail = ring->next_to_use; 1087 1088 return ((head <= tail) ? tail : tail + ring->count) - head; 1089 } 1090 1091 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1092 { 1093 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1094 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1095 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1096 1097 clear_check_for_tx_hang(tx_ring); 1098 1099 /* 1100 * Check for a hung queue, but be thorough. This verifies 1101 * that a transmit has been completed since the previous 1102 * check AND there is at least one packet pending. The 1103 * ARMED bit is set to indicate a potential hang. The 1104 * bit is cleared if a pause frame is received to remove 1105 * false hang detection due to PFC or 802.3x frames. By 1106 * requiring this to fail twice we avoid races with 1107 * pfc clearing the ARMED bit and conditions where we 1108 * run the check_tx_hang logic with a transmit completion 1109 * pending but without time to complete it yet. 1110 */ 1111 if (tx_done_old == tx_done && tx_pending) 1112 /* make sure it is true for two checks in a row */ 1113 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1114 &tx_ring->state); 1115 /* update completed stats and continue */ 1116 tx_ring->tx_stats.tx_done_old = tx_done; 1117 /* reset the countdown */ 1118 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1119 1120 return false; 1121 } 1122 1123 /** 1124 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1125 * @adapter: driver private struct 1126 **/ 1127 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1128 { 1129 1130 /* Do the reset outside of interrupt context */ 1131 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1132 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1133 e_warn(drv, "initiating reset due to tx timeout\n"); 1134 ixgbe_service_event_schedule(adapter); 1135 } 1136 } 1137 1138 /** 1139 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1140 * @netdev: network interface device structure 1141 * @queue_index: Tx queue to set 1142 * @maxrate: desired maximum transmit bitrate 1143 **/ 1144 static int ixgbe_tx_maxrate(struct net_device *netdev, 1145 int queue_index, u32 maxrate) 1146 { 1147 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1148 struct ixgbe_hw *hw = &adapter->hw; 1149 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1150 1151 if (!maxrate) 1152 return 0; 1153 1154 /* Calculate the rate factor values to set */ 1155 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1156 bcnrc_val /= maxrate; 1157 1158 /* clear everything but the rate factor */ 1159 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1160 IXGBE_RTTBCNRC_RF_DEC_MASK; 1161 1162 /* enable the rate scheduler */ 1163 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1164 1165 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1166 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1167 1168 return 0; 1169 } 1170 1171 /** 1172 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1173 * @q_vector: structure containing interrupt and ring information 1174 * @tx_ring: tx ring to clean 1175 * @napi_budget: Used to determine if we are in netpoll 1176 **/ 1177 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1178 struct ixgbe_ring *tx_ring, int napi_budget) 1179 { 1180 struct ixgbe_adapter *adapter = q_vector->adapter; 1181 struct ixgbe_tx_buffer *tx_buffer; 1182 union ixgbe_adv_tx_desc *tx_desc; 1183 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1184 unsigned int budget = q_vector->tx.work_limit; 1185 unsigned int i = tx_ring->next_to_clean; 1186 1187 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1188 return true; 1189 1190 tx_buffer = &tx_ring->tx_buffer_info[i]; 1191 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1192 i -= tx_ring->count; 1193 1194 do { 1195 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1196 1197 /* if next_to_watch is not set then there is no work pending */ 1198 if (!eop_desc) 1199 break; 1200 1201 /* prevent any other reads prior to eop_desc */ 1202 smp_rmb(); 1203 1204 /* if DD is not set pending work has not been completed */ 1205 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1206 break; 1207 1208 /* clear next_to_watch to prevent false hangs */ 1209 tx_buffer->next_to_watch = NULL; 1210 1211 /* update the statistics for this packet */ 1212 total_bytes += tx_buffer->bytecount; 1213 total_packets += tx_buffer->gso_segs; 1214 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1215 total_ipsec++; 1216 1217 /* free the skb */ 1218 if (ring_is_xdp(tx_ring)) 1219 xdp_return_frame(tx_buffer->xdpf); 1220 else 1221 napi_consume_skb(tx_buffer->skb, napi_budget); 1222 1223 /* unmap skb header data */ 1224 dma_unmap_single(tx_ring->dev, 1225 dma_unmap_addr(tx_buffer, dma), 1226 dma_unmap_len(tx_buffer, len), 1227 DMA_TO_DEVICE); 1228 1229 /* clear tx_buffer data */ 1230 dma_unmap_len_set(tx_buffer, len, 0); 1231 1232 /* unmap remaining buffers */ 1233 while (tx_desc != eop_desc) { 1234 tx_buffer++; 1235 tx_desc++; 1236 i++; 1237 if (unlikely(!i)) { 1238 i -= tx_ring->count; 1239 tx_buffer = tx_ring->tx_buffer_info; 1240 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1241 } 1242 1243 /* unmap any remaining paged data */ 1244 if (dma_unmap_len(tx_buffer, len)) { 1245 dma_unmap_page(tx_ring->dev, 1246 dma_unmap_addr(tx_buffer, dma), 1247 dma_unmap_len(tx_buffer, len), 1248 DMA_TO_DEVICE); 1249 dma_unmap_len_set(tx_buffer, len, 0); 1250 } 1251 } 1252 1253 /* move us one more past the eop_desc for start of next pkt */ 1254 tx_buffer++; 1255 tx_desc++; 1256 i++; 1257 if (unlikely(!i)) { 1258 i -= tx_ring->count; 1259 tx_buffer = tx_ring->tx_buffer_info; 1260 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1261 } 1262 1263 /* issue prefetch for next Tx descriptor */ 1264 prefetch(tx_desc); 1265 1266 /* update budget accounting */ 1267 budget--; 1268 } while (likely(budget)); 1269 1270 i += tx_ring->count; 1271 tx_ring->next_to_clean = i; 1272 u64_stats_update_begin(&tx_ring->syncp); 1273 tx_ring->stats.bytes += total_bytes; 1274 tx_ring->stats.packets += total_packets; 1275 u64_stats_update_end(&tx_ring->syncp); 1276 q_vector->tx.total_bytes += total_bytes; 1277 q_vector->tx.total_packets += total_packets; 1278 adapter->tx_ipsec += total_ipsec; 1279 1280 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1281 /* schedule immediate reset if we believe we hung */ 1282 struct ixgbe_hw *hw = &adapter->hw; 1283 e_err(drv, "Detected Tx Unit Hang %s\n" 1284 " Tx Queue <%d>\n" 1285 " TDH, TDT <%x>, <%x>\n" 1286 " next_to_use <%x>\n" 1287 " next_to_clean <%x>\n" 1288 "tx_buffer_info[next_to_clean]\n" 1289 " time_stamp <%lx>\n" 1290 " jiffies <%lx>\n", 1291 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1292 tx_ring->queue_index, 1293 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1294 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1295 tx_ring->next_to_use, i, 1296 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1297 1298 if (!ring_is_xdp(tx_ring)) 1299 netif_stop_subqueue(tx_ring->netdev, 1300 tx_ring->queue_index); 1301 1302 e_info(probe, 1303 "tx hang %d detected on queue %d, resetting adapter\n", 1304 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1305 1306 /* schedule immediate reset if we believe we hung */ 1307 ixgbe_tx_timeout_reset(adapter); 1308 1309 /* the adapter is about to reset, no point in enabling stuff */ 1310 return true; 1311 } 1312 1313 if (ring_is_xdp(tx_ring)) 1314 return !!budget; 1315 1316 netdev_tx_completed_queue(txring_txq(tx_ring), 1317 total_packets, total_bytes); 1318 1319 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1320 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1321 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1322 /* Make sure that anybody stopping the queue after this 1323 * sees the new next_to_clean. 1324 */ 1325 smp_mb(); 1326 if (__netif_subqueue_stopped(tx_ring->netdev, 1327 tx_ring->queue_index) 1328 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1329 netif_wake_subqueue(tx_ring->netdev, 1330 tx_ring->queue_index); 1331 ++tx_ring->tx_stats.restart_queue; 1332 } 1333 } 1334 1335 return !!budget; 1336 } 1337 1338 #ifdef CONFIG_IXGBE_DCA 1339 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1340 struct ixgbe_ring *tx_ring, 1341 int cpu) 1342 { 1343 struct ixgbe_hw *hw = &adapter->hw; 1344 u32 txctrl = 0; 1345 u16 reg_offset; 1346 1347 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1348 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1349 1350 switch (hw->mac.type) { 1351 case ixgbe_mac_82598EB: 1352 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1353 break; 1354 case ixgbe_mac_82599EB: 1355 case ixgbe_mac_X540: 1356 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1357 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1358 break; 1359 default: 1360 /* for unknown hardware do not write register */ 1361 return; 1362 } 1363 1364 /* 1365 * We can enable relaxed ordering for reads, but not writes when 1366 * DCA is enabled. This is due to a known issue in some chipsets 1367 * which will cause the DCA tag to be cleared. 1368 */ 1369 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1370 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1371 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1372 1373 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1374 } 1375 1376 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1377 struct ixgbe_ring *rx_ring, 1378 int cpu) 1379 { 1380 struct ixgbe_hw *hw = &adapter->hw; 1381 u32 rxctrl = 0; 1382 u8 reg_idx = rx_ring->reg_idx; 1383 1384 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1385 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1386 1387 switch (hw->mac.type) { 1388 case ixgbe_mac_82599EB: 1389 case ixgbe_mac_X540: 1390 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1391 break; 1392 default: 1393 break; 1394 } 1395 1396 /* 1397 * We can enable relaxed ordering for reads, but not writes when 1398 * DCA is enabled. This is due to a known issue in some chipsets 1399 * which will cause the DCA tag to be cleared. 1400 */ 1401 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1402 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1403 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1404 1405 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1406 } 1407 1408 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1409 { 1410 struct ixgbe_adapter *adapter = q_vector->adapter; 1411 struct ixgbe_ring *ring; 1412 int cpu = get_cpu(); 1413 1414 if (q_vector->cpu == cpu) 1415 goto out_no_update; 1416 1417 ixgbe_for_each_ring(ring, q_vector->tx) 1418 ixgbe_update_tx_dca(adapter, ring, cpu); 1419 1420 ixgbe_for_each_ring(ring, q_vector->rx) 1421 ixgbe_update_rx_dca(adapter, ring, cpu); 1422 1423 q_vector->cpu = cpu; 1424 out_no_update: 1425 put_cpu(); 1426 } 1427 1428 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1429 { 1430 int i; 1431 1432 /* always use CB2 mode, difference is masked in the CB driver */ 1433 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1435 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1436 else 1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1438 IXGBE_DCA_CTRL_DCA_DISABLE); 1439 1440 for (i = 0; i < adapter->num_q_vectors; i++) { 1441 adapter->q_vector[i]->cpu = -1; 1442 ixgbe_update_dca(adapter->q_vector[i]); 1443 } 1444 } 1445 1446 static int __ixgbe_notify_dca(struct device *dev, void *data) 1447 { 1448 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1449 unsigned long event = *(unsigned long *)data; 1450 1451 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1452 return 0; 1453 1454 switch (event) { 1455 case DCA_PROVIDER_ADD: 1456 /* if we're already enabled, don't do it again */ 1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1458 break; 1459 if (dca_add_requester(dev) == 0) { 1460 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1462 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1463 break; 1464 } 1465 /* fall through - DCA is disabled. */ 1466 case DCA_PROVIDER_REMOVE: 1467 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1468 dca_remove_requester(dev); 1469 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1471 IXGBE_DCA_CTRL_DCA_DISABLE); 1472 } 1473 break; 1474 } 1475 1476 return 0; 1477 } 1478 1479 #endif /* CONFIG_IXGBE_DCA */ 1480 1481 #define IXGBE_RSS_L4_TYPES_MASK \ 1482 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1483 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1484 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1485 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1486 1487 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1488 union ixgbe_adv_rx_desc *rx_desc, 1489 struct sk_buff *skb) 1490 { 1491 u16 rss_type; 1492 1493 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1494 return; 1495 1496 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1497 IXGBE_RXDADV_RSSTYPE_MASK; 1498 1499 if (!rss_type) 1500 return; 1501 1502 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1503 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1504 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1505 } 1506 1507 #ifdef IXGBE_FCOE 1508 /** 1509 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1510 * @ring: structure containing ring specific data 1511 * @rx_desc: advanced rx descriptor 1512 * 1513 * Returns : true if it is FCoE pkt 1514 */ 1515 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1516 union ixgbe_adv_rx_desc *rx_desc) 1517 { 1518 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1519 1520 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1521 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1522 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1523 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1524 } 1525 1526 #endif /* IXGBE_FCOE */ 1527 /** 1528 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1529 * @ring: structure containing ring specific data 1530 * @rx_desc: current Rx descriptor being processed 1531 * @skb: skb currently being received and modified 1532 **/ 1533 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1534 union ixgbe_adv_rx_desc *rx_desc, 1535 struct sk_buff *skb) 1536 { 1537 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1538 bool encap_pkt = false; 1539 1540 skb_checksum_none_assert(skb); 1541 1542 /* Rx csum disabled */ 1543 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1544 return; 1545 1546 /* check for VXLAN and Geneve packets */ 1547 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1548 encap_pkt = true; 1549 skb->encapsulation = 1; 1550 } 1551 1552 /* if IP and error */ 1553 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1554 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1555 ring->rx_stats.csum_err++; 1556 return; 1557 } 1558 1559 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1560 return; 1561 1562 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1563 /* 1564 * 82599 errata, UDP frames with a 0 checksum can be marked as 1565 * checksum errors. 1566 */ 1567 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1568 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1569 return; 1570 1571 ring->rx_stats.csum_err++; 1572 return; 1573 } 1574 1575 /* It must be a TCP or UDP packet with a valid checksum */ 1576 skb->ip_summed = CHECKSUM_UNNECESSARY; 1577 if (encap_pkt) { 1578 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1579 return; 1580 1581 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1582 skb->ip_summed = CHECKSUM_NONE; 1583 return; 1584 } 1585 /* If we checked the outer header let the stack know */ 1586 skb->csum_level = 1; 1587 } 1588 } 1589 1590 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1591 { 1592 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1593 } 1594 1595 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1596 struct ixgbe_rx_buffer *bi) 1597 { 1598 struct page *page = bi->page; 1599 dma_addr_t dma; 1600 1601 /* since we are recycling buffers we should seldom need to alloc */ 1602 if (likely(page)) 1603 return true; 1604 1605 /* alloc new page for storage */ 1606 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1607 if (unlikely(!page)) { 1608 rx_ring->rx_stats.alloc_rx_page_failed++; 1609 return false; 1610 } 1611 1612 /* map page for use */ 1613 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1614 ixgbe_rx_pg_size(rx_ring), 1615 DMA_FROM_DEVICE, 1616 IXGBE_RX_DMA_ATTR); 1617 1618 /* 1619 * if mapping failed free memory back to system since 1620 * there isn't much point in holding memory we can't use 1621 */ 1622 if (dma_mapping_error(rx_ring->dev, dma)) { 1623 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1624 1625 rx_ring->rx_stats.alloc_rx_page_failed++; 1626 return false; 1627 } 1628 1629 bi->dma = dma; 1630 bi->page = page; 1631 bi->page_offset = ixgbe_rx_offset(rx_ring); 1632 page_ref_add(page, USHRT_MAX - 1); 1633 bi->pagecnt_bias = USHRT_MAX; 1634 rx_ring->rx_stats.alloc_rx_page++; 1635 1636 return true; 1637 } 1638 1639 /** 1640 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1641 * @rx_ring: ring to place buffers on 1642 * @cleaned_count: number of buffers to replace 1643 **/ 1644 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1645 { 1646 union ixgbe_adv_rx_desc *rx_desc; 1647 struct ixgbe_rx_buffer *bi; 1648 u16 i = rx_ring->next_to_use; 1649 u16 bufsz; 1650 1651 /* nothing to do */ 1652 if (!cleaned_count) 1653 return; 1654 1655 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1656 bi = &rx_ring->rx_buffer_info[i]; 1657 i -= rx_ring->count; 1658 1659 bufsz = ixgbe_rx_bufsz(rx_ring); 1660 1661 do { 1662 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1663 break; 1664 1665 /* sync the buffer for use by the device */ 1666 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1667 bi->page_offset, bufsz, 1668 DMA_FROM_DEVICE); 1669 1670 /* 1671 * Refresh the desc even if buffer_addrs didn't change 1672 * because each write-back erases this info. 1673 */ 1674 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1675 1676 rx_desc++; 1677 bi++; 1678 i++; 1679 if (unlikely(!i)) { 1680 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1681 bi = rx_ring->rx_buffer_info; 1682 i -= rx_ring->count; 1683 } 1684 1685 /* clear the length for the next_to_use descriptor */ 1686 rx_desc->wb.upper.length = 0; 1687 1688 cleaned_count--; 1689 } while (cleaned_count); 1690 1691 i += rx_ring->count; 1692 1693 if (rx_ring->next_to_use != i) { 1694 rx_ring->next_to_use = i; 1695 1696 /* update next to alloc since we have filled the ring */ 1697 rx_ring->next_to_alloc = i; 1698 1699 /* Force memory writes to complete before letting h/w 1700 * know there are new descriptors to fetch. (Only 1701 * applicable for weak-ordered memory model archs, 1702 * such as IA-64). 1703 */ 1704 wmb(); 1705 writel(i, rx_ring->tail); 1706 } 1707 } 1708 1709 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1710 struct sk_buff *skb) 1711 { 1712 u16 hdr_len = skb_headlen(skb); 1713 1714 /* set gso_size to avoid messing up TCP MSS */ 1715 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1716 IXGBE_CB(skb)->append_cnt); 1717 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1718 } 1719 1720 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1721 struct sk_buff *skb) 1722 { 1723 /* if append_cnt is 0 then frame is not RSC */ 1724 if (!IXGBE_CB(skb)->append_cnt) 1725 return; 1726 1727 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1728 rx_ring->rx_stats.rsc_flush++; 1729 1730 ixgbe_set_rsc_gso_size(rx_ring, skb); 1731 1732 /* gso_size is computed using append_cnt so always clear it last */ 1733 IXGBE_CB(skb)->append_cnt = 0; 1734 } 1735 1736 /** 1737 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1738 * @rx_ring: rx descriptor ring packet is being transacted on 1739 * @rx_desc: pointer to the EOP Rx descriptor 1740 * @skb: pointer to current skb being populated 1741 * 1742 * This function checks the ring, descriptor, and packet information in 1743 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1744 * other fields within the skb. 1745 **/ 1746 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1747 union ixgbe_adv_rx_desc *rx_desc, 1748 struct sk_buff *skb) 1749 { 1750 struct net_device *dev = rx_ring->netdev; 1751 u32 flags = rx_ring->q_vector->adapter->flags; 1752 1753 ixgbe_update_rsc_stats(rx_ring, skb); 1754 1755 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1756 1757 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1758 1759 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1760 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1761 1762 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1763 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1764 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1765 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1766 } 1767 1768 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1769 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1770 1771 /* record Rx queue, or update MACVLAN statistics */ 1772 if (netif_is_ixgbe(dev)) 1773 skb_record_rx_queue(skb, rx_ring->queue_index); 1774 else 1775 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1776 false); 1777 1778 skb->protocol = eth_type_trans(skb, dev); 1779 } 1780 1781 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1782 struct sk_buff *skb) 1783 { 1784 napi_gro_receive(&q_vector->napi, skb); 1785 } 1786 1787 /** 1788 * ixgbe_is_non_eop - process handling of non-EOP buffers 1789 * @rx_ring: Rx ring being processed 1790 * @rx_desc: Rx descriptor for current buffer 1791 * @skb: Current socket buffer containing buffer in progress 1792 * 1793 * This function updates next to clean. If the buffer is an EOP buffer 1794 * this function exits returning false, otherwise it will place the 1795 * sk_buff in the next buffer to be chained and return true indicating 1796 * that this is in fact a non-EOP buffer. 1797 **/ 1798 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1799 union ixgbe_adv_rx_desc *rx_desc, 1800 struct sk_buff *skb) 1801 { 1802 u32 ntc = rx_ring->next_to_clean + 1; 1803 1804 /* fetch, update, and store next to clean */ 1805 ntc = (ntc < rx_ring->count) ? ntc : 0; 1806 rx_ring->next_to_clean = ntc; 1807 1808 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1809 1810 /* update RSC append count if present */ 1811 if (ring_is_rsc_enabled(rx_ring)) { 1812 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1813 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1814 1815 if (unlikely(rsc_enabled)) { 1816 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1817 1818 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1819 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1820 1821 /* update ntc based on RSC value */ 1822 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1823 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1824 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1825 } 1826 } 1827 1828 /* if we are the last buffer then there is nothing else to do */ 1829 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1830 return false; 1831 1832 /* place skb in next buffer to be received */ 1833 rx_ring->rx_buffer_info[ntc].skb = skb; 1834 rx_ring->rx_stats.non_eop_descs++; 1835 1836 return true; 1837 } 1838 1839 /** 1840 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1841 * @rx_ring: rx descriptor ring packet is being transacted on 1842 * @skb: pointer to current skb being adjusted 1843 * 1844 * This function is an ixgbe specific version of __pskb_pull_tail. The 1845 * main difference between this version and the original function is that 1846 * this function can make several assumptions about the state of things 1847 * that allow for significant optimizations versus the standard function. 1848 * As a result we can do things like drop a frag and maintain an accurate 1849 * truesize for the skb. 1850 */ 1851 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1852 struct sk_buff *skb) 1853 { 1854 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1855 unsigned char *va; 1856 unsigned int pull_len; 1857 1858 /* 1859 * it is valid to use page_address instead of kmap since we are 1860 * working with pages allocated out of the lomem pool per 1861 * alloc_page(GFP_ATOMIC) 1862 */ 1863 va = skb_frag_address(frag); 1864 1865 /* 1866 * we need the header to contain the greater of either ETH_HLEN or 1867 * 60 bytes if the skb->len is less than 60 for skb_pad. 1868 */ 1869 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1870 1871 /* align pull length to size of long to optimize memcpy performance */ 1872 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1873 1874 /* update all of the pointers */ 1875 skb_frag_size_sub(frag, pull_len); 1876 frag->page_offset += pull_len; 1877 skb->data_len -= pull_len; 1878 skb->tail += pull_len; 1879 } 1880 1881 /** 1882 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1883 * @rx_ring: rx descriptor ring packet is being transacted on 1884 * @skb: pointer to current skb being updated 1885 * 1886 * This function provides a basic DMA sync up for the first fragment of an 1887 * skb. The reason for doing this is that the first fragment cannot be 1888 * unmapped until we have reached the end of packet descriptor for a buffer 1889 * chain. 1890 */ 1891 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1892 struct sk_buff *skb) 1893 { 1894 /* if the page was released unmap it, else just sync our portion */ 1895 if (unlikely(IXGBE_CB(skb)->page_released)) { 1896 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1897 ixgbe_rx_pg_size(rx_ring), 1898 DMA_FROM_DEVICE, 1899 IXGBE_RX_DMA_ATTR); 1900 } else if (ring_uses_build_skb(rx_ring)) { 1901 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1902 1903 dma_sync_single_range_for_cpu(rx_ring->dev, 1904 IXGBE_CB(skb)->dma, 1905 offset, 1906 skb_headlen(skb), 1907 DMA_FROM_DEVICE); 1908 } else { 1909 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1910 1911 dma_sync_single_range_for_cpu(rx_ring->dev, 1912 IXGBE_CB(skb)->dma, 1913 frag->page_offset, 1914 skb_frag_size(frag), 1915 DMA_FROM_DEVICE); 1916 } 1917 } 1918 1919 /** 1920 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1921 * @rx_ring: rx descriptor ring packet is being transacted on 1922 * @rx_desc: pointer to the EOP Rx descriptor 1923 * @skb: pointer to current skb being fixed 1924 * 1925 * Check if the skb is valid in the XDP case it will be an error pointer. 1926 * Return true in this case to abort processing and advance to next 1927 * descriptor. 1928 * 1929 * Check for corrupted packet headers caused by senders on the local L2 1930 * embedded NIC switch not setting up their Tx Descriptors right. These 1931 * should be very rare. 1932 * 1933 * Also address the case where we are pulling data in on pages only 1934 * and as such no data is present in the skb header. 1935 * 1936 * In addition if skb is not at least 60 bytes we need to pad it so that 1937 * it is large enough to qualify as a valid Ethernet frame. 1938 * 1939 * Returns true if an error was encountered and skb was freed. 1940 **/ 1941 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1942 union ixgbe_adv_rx_desc *rx_desc, 1943 struct sk_buff *skb) 1944 { 1945 struct net_device *netdev = rx_ring->netdev; 1946 1947 /* XDP packets use error pointer so abort at this point */ 1948 if (IS_ERR(skb)) 1949 return true; 1950 1951 /* Verify netdev is present, and that packet does not have any 1952 * errors that would be unacceptable to the netdev. 1953 */ 1954 if (!netdev || 1955 (unlikely(ixgbe_test_staterr(rx_desc, 1956 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1957 !(netdev->features & NETIF_F_RXALL)))) { 1958 dev_kfree_skb_any(skb); 1959 return true; 1960 } 1961 1962 /* place header in linear portion of buffer */ 1963 if (!skb_headlen(skb)) 1964 ixgbe_pull_tail(rx_ring, skb); 1965 1966 #ifdef IXGBE_FCOE 1967 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1968 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1969 return false; 1970 1971 #endif 1972 /* if eth_skb_pad returns an error the skb was freed */ 1973 if (eth_skb_pad(skb)) 1974 return true; 1975 1976 return false; 1977 } 1978 1979 /** 1980 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1981 * @rx_ring: rx descriptor ring to store buffers on 1982 * @old_buff: donor buffer to have page reused 1983 * 1984 * Synchronizes page for reuse by the adapter 1985 **/ 1986 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1987 struct ixgbe_rx_buffer *old_buff) 1988 { 1989 struct ixgbe_rx_buffer *new_buff; 1990 u16 nta = rx_ring->next_to_alloc; 1991 1992 new_buff = &rx_ring->rx_buffer_info[nta]; 1993 1994 /* update, and store next to alloc */ 1995 nta++; 1996 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1997 1998 /* Transfer page from old buffer to new buffer. 1999 * Move each member individually to avoid possible store 2000 * forwarding stalls and unnecessary copy of skb. 2001 */ 2002 new_buff->dma = old_buff->dma; 2003 new_buff->page = old_buff->page; 2004 new_buff->page_offset = old_buff->page_offset; 2005 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 2006 } 2007 2008 static inline bool ixgbe_page_is_reserved(struct page *page) 2009 { 2010 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 2011 } 2012 2013 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 2014 { 2015 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 2016 struct page *page = rx_buffer->page; 2017 2018 /* avoid re-using remote pages */ 2019 if (unlikely(ixgbe_page_is_reserved(page))) 2020 return false; 2021 2022 #if (PAGE_SIZE < 8192) 2023 /* if we are only owner of page we can reuse it */ 2024 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 2025 return false; 2026 #else 2027 /* The last offset is a bit aggressive in that we assume the 2028 * worst case of FCoE being enabled and using a 3K buffer. 2029 * However this should have minimal impact as the 1K extra is 2030 * still less than one buffer in size. 2031 */ 2032 #define IXGBE_LAST_OFFSET \ 2033 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2034 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2035 return false; 2036 #endif 2037 2038 /* If we have drained the page fragment pool we need to update 2039 * the pagecnt_bias and page count so that we fully restock the 2040 * number of references the driver holds. 2041 */ 2042 if (unlikely(pagecnt_bias == 1)) { 2043 page_ref_add(page, USHRT_MAX - 1); 2044 rx_buffer->pagecnt_bias = USHRT_MAX; 2045 } 2046 2047 return true; 2048 } 2049 2050 /** 2051 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2052 * @rx_ring: rx descriptor ring to transact packets on 2053 * @rx_buffer: buffer containing page to add 2054 * @skb: sk_buff to place the data into 2055 * @size: size of data in rx_buffer 2056 * 2057 * This function will add the data contained in rx_buffer->page to the skb. 2058 * This is done either through a direct copy if the data in the buffer is 2059 * less than the skb header size, otherwise it will just attach the page as 2060 * a frag to the skb. 2061 * 2062 * The function will then update the page offset if necessary and return 2063 * true if the buffer can be reused by the adapter. 2064 **/ 2065 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2066 struct ixgbe_rx_buffer *rx_buffer, 2067 struct sk_buff *skb, 2068 unsigned int size) 2069 { 2070 #if (PAGE_SIZE < 8192) 2071 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2072 #else 2073 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2074 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2075 SKB_DATA_ALIGN(size); 2076 #endif 2077 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2078 rx_buffer->page_offset, size, truesize); 2079 #if (PAGE_SIZE < 8192) 2080 rx_buffer->page_offset ^= truesize; 2081 #else 2082 rx_buffer->page_offset += truesize; 2083 #endif 2084 } 2085 2086 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2087 union ixgbe_adv_rx_desc *rx_desc, 2088 struct sk_buff **skb, 2089 const unsigned int size) 2090 { 2091 struct ixgbe_rx_buffer *rx_buffer; 2092 2093 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2094 prefetchw(rx_buffer->page); 2095 *skb = rx_buffer->skb; 2096 2097 /* Delay unmapping of the first packet. It carries the header 2098 * information, HW may still access the header after the writeback. 2099 * Only unmap it when EOP is reached 2100 */ 2101 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2102 if (!*skb) 2103 goto skip_sync; 2104 } else { 2105 if (*skb) 2106 ixgbe_dma_sync_frag(rx_ring, *skb); 2107 } 2108 2109 /* we are reusing so sync this buffer for CPU use */ 2110 dma_sync_single_range_for_cpu(rx_ring->dev, 2111 rx_buffer->dma, 2112 rx_buffer->page_offset, 2113 size, 2114 DMA_FROM_DEVICE); 2115 skip_sync: 2116 rx_buffer->pagecnt_bias--; 2117 2118 return rx_buffer; 2119 } 2120 2121 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2122 struct ixgbe_rx_buffer *rx_buffer, 2123 struct sk_buff *skb) 2124 { 2125 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2126 /* hand second half of page back to the ring */ 2127 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2128 } else { 2129 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2130 /* the page has been released from the ring */ 2131 IXGBE_CB(skb)->page_released = true; 2132 } else { 2133 /* we are not reusing the buffer so unmap it */ 2134 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2135 ixgbe_rx_pg_size(rx_ring), 2136 DMA_FROM_DEVICE, 2137 IXGBE_RX_DMA_ATTR); 2138 } 2139 __page_frag_cache_drain(rx_buffer->page, 2140 rx_buffer->pagecnt_bias); 2141 } 2142 2143 /* clear contents of rx_buffer */ 2144 rx_buffer->page = NULL; 2145 rx_buffer->skb = NULL; 2146 } 2147 2148 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2149 struct ixgbe_rx_buffer *rx_buffer, 2150 struct xdp_buff *xdp, 2151 union ixgbe_adv_rx_desc *rx_desc) 2152 { 2153 unsigned int size = xdp->data_end - xdp->data; 2154 #if (PAGE_SIZE < 8192) 2155 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2156 #else 2157 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2158 xdp->data_hard_start); 2159 #endif 2160 struct sk_buff *skb; 2161 2162 /* prefetch first cache line of first page */ 2163 prefetch(xdp->data); 2164 #if L1_CACHE_BYTES < 128 2165 prefetch(xdp->data + L1_CACHE_BYTES); 2166 #endif 2167 /* Note, we get here by enabling legacy-rx via: 2168 * 2169 * ethtool --set-priv-flags <dev> legacy-rx on 2170 * 2171 * In this mode, we currently get 0 extra XDP headroom as 2172 * opposed to having legacy-rx off, where we process XDP 2173 * packets going to stack via ixgbe_build_skb(). The latter 2174 * provides us currently with 192 bytes of headroom. 2175 * 2176 * For ixgbe_construct_skb() mode it means that the 2177 * xdp->data_meta will always point to xdp->data, since 2178 * the helper cannot expand the head. Should this ever 2179 * change in future for legacy-rx mode on, then lets also 2180 * add xdp->data_meta handling here. 2181 */ 2182 2183 /* allocate a skb to store the frags */ 2184 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2185 if (unlikely(!skb)) 2186 return NULL; 2187 2188 if (size > IXGBE_RX_HDR_SIZE) { 2189 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2190 IXGBE_CB(skb)->dma = rx_buffer->dma; 2191 2192 skb_add_rx_frag(skb, 0, rx_buffer->page, 2193 xdp->data - page_address(rx_buffer->page), 2194 size, truesize); 2195 #if (PAGE_SIZE < 8192) 2196 rx_buffer->page_offset ^= truesize; 2197 #else 2198 rx_buffer->page_offset += truesize; 2199 #endif 2200 } else { 2201 memcpy(__skb_put(skb, size), 2202 xdp->data, ALIGN(size, sizeof(long))); 2203 rx_buffer->pagecnt_bias++; 2204 } 2205 2206 return skb; 2207 } 2208 2209 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2210 struct ixgbe_rx_buffer *rx_buffer, 2211 struct xdp_buff *xdp, 2212 union ixgbe_adv_rx_desc *rx_desc) 2213 { 2214 unsigned int metasize = xdp->data - xdp->data_meta; 2215 #if (PAGE_SIZE < 8192) 2216 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2217 #else 2218 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2219 SKB_DATA_ALIGN(xdp->data_end - 2220 xdp->data_hard_start); 2221 #endif 2222 struct sk_buff *skb; 2223 2224 /* Prefetch first cache line of first page. If xdp->data_meta 2225 * is unused, this points extactly as xdp->data, otherwise we 2226 * likely have a consumer accessing first few bytes of meta 2227 * data, and then actual data. 2228 */ 2229 prefetch(xdp->data_meta); 2230 #if L1_CACHE_BYTES < 128 2231 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2232 #endif 2233 2234 /* build an skb to around the page buffer */ 2235 skb = build_skb(xdp->data_hard_start, truesize); 2236 if (unlikely(!skb)) 2237 return NULL; 2238 2239 /* update pointers within the skb to store the data */ 2240 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2241 __skb_put(skb, xdp->data_end - xdp->data); 2242 if (metasize) 2243 skb_metadata_set(skb, metasize); 2244 2245 /* record DMA address if this is the start of a chain of buffers */ 2246 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2247 IXGBE_CB(skb)->dma = rx_buffer->dma; 2248 2249 /* update buffer offset */ 2250 #if (PAGE_SIZE < 8192) 2251 rx_buffer->page_offset ^= truesize; 2252 #else 2253 rx_buffer->page_offset += truesize; 2254 #endif 2255 2256 return skb; 2257 } 2258 2259 #define IXGBE_XDP_PASS 0 2260 #define IXGBE_XDP_CONSUMED 1 2261 #define IXGBE_XDP_TX 2 2262 2263 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2264 struct xdp_frame *xdpf); 2265 2266 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2267 struct ixgbe_ring *rx_ring, 2268 struct xdp_buff *xdp) 2269 { 2270 int err, result = IXGBE_XDP_PASS; 2271 struct bpf_prog *xdp_prog; 2272 struct xdp_frame *xdpf; 2273 u32 act; 2274 2275 rcu_read_lock(); 2276 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2277 2278 if (!xdp_prog) 2279 goto xdp_out; 2280 2281 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2282 2283 act = bpf_prog_run_xdp(xdp_prog, xdp); 2284 switch (act) { 2285 case XDP_PASS: 2286 break; 2287 case XDP_TX: 2288 xdpf = convert_to_xdp_frame(xdp); 2289 if (unlikely(!xdpf)) { 2290 result = IXGBE_XDP_CONSUMED; 2291 break; 2292 } 2293 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2294 break; 2295 case XDP_REDIRECT: 2296 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2297 if (!err) 2298 result = IXGBE_XDP_TX; 2299 else 2300 result = IXGBE_XDP_CONSUMED; 2301 break; 2302 default: 2303 bpf_warn_invalid_xdp_action(act); 2304 /* fallthrough */ 2305 case XDP_ABORTED: 2306 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2307 /* fallthrough -- handle aborts by dropping packet */ 2308 case XDP_DROP: 2309 result = IXGBE_XDP_CONSUMED; 2310 break; 2311 } 2312 xdp_out: 2313 rcu_read_unlock(); 2314 return ERR_PTR(-result); 2315 } 2316 2317 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2318 struct ixgbe_rx_buffer *rx_buffer, 2319 unsigned int size) 2320 { 2321 #if (PAGE_SIZE < 8192) 2322 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2323 2324 rx_buffer->page_offset ^= truesize; 2325 #else 2326 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2327 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2328 SKB_DATA_ALIGN(size); 2329 2330 rx_buffer->page_offset += truesize; 2331 #endif 2332 } 2333 2334 /** 2335 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2336 * @q_vector: structure containing interrupt and ring information 2337 * @rx_ring: rx descriptor ring to transact packets on 2338 * @budget: Total limit on number of packets to process 2339 * 2340 * This function provides a "bounce buffer" approach to Rx interrupt 2341 * processing. The advantage to this is that on systems that have 2342 * expensive overhead for IOMMU access this provides a means of avoiding 2343 * it by maintaining the mapping of the page to the syste. 2344 * 2345 * Returns amount of work completed 2346 **/ 2347 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2348 struct ixgbe_ring *rx_ring, 2349 const int budget) 2350 { 2351 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2352 struct ixgbe_adapter *adapter = q_vector->adapter; 2353 #ifdef IXGBE_FCOE 2354 int ddp_bytes; 2355 unsigned int mss = 0; 2356 #endif /* IXGBE_FCOE */ 2357 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2358 bool xdp_xmit = false; 2359 struct xdp_buff xdp; 2360 2361 xdp.rxq = &rx_ring->xdp_rxq; 2362 2363 while (likely(total_rx_packets < budget)) { 2364 union ixgbe_adv_rx_desc *rx_desc; 2365 struct ixgbe_rx_buffer *rx_buffer; 2366 struct sk_buff *skb; 2367 unsigned int size; 2368 2369 /* return some buffers to hardware, one at a time is too slow */ 2370 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2371 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2372 cleaned_count = 0; 2373 } 2374 2375 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2376 size = le16_to_cpu(rx_desc->wb.upper.length); 2377 if (!size) 2378 break; 2379 2380 /* This memory barrier is needed to keep us from reading 2381 * any other fields out of the rx_desc until we know the 2382 * descriptor has been written back 2383 */ 2384 dma_rmb(); 2385 2386 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2387 2388 /* retrieve a buffer from the ring */ 2389 if (!skb) { 2390 xdp.data = page_address(rx_buffer->page) + 2391 rx_buffer->page_offset; 2392 xdp.data_meta = xdp.data; 2393 xdp.data_hard_start = xdp.data - 2394 ixgbe_rx_offset(rx_ring); 2395 xdp.data_end = xdp.data + size; 2396 2397 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2398 } 2399 2400 if (IS_ERR(skb)) { 2401 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2402 xdp_xmit = true; 2403 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2404 } else { 2405 rx_buffer->pagecnt_bias++; 2406 } 2407 total_rx_packets++; 2408 total_rx_bytes += size; 2409 } else if (skb) { 2410 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2411 } else if (ring_uses_build_skb(rx_ring)) { 2412 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2413 &xdp, rx_desc); 2414 } else { 2415 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2416 &xdp, rx_desc); 2417 } 2418 2419 /* exit if we failed to retrieve a buffer */ 2420 if (!skb) { 2421 rx_ring->rx_stats.alloc_rx_buff_failed++; 2422 rx_buffer->pagecnt_bias++; 2423 break; 2424 } 2425 2426 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2427 cleaned_count++; 2428 2429 /* place incomplete frames back on ring for completion */ 2430 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2431 continue; 2432 2433 /* verify the packet layout is correct */ 2434 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2435 continue; 2436 2437 /* probably a little skewed due to removing CRC */ 2438 total_rx_bytes += skb->len; 2439 2440 /* populate checksum, timestamp, VLAN, and protocol */ 2441 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2442 2443 #ifdef IXGBE_FCOE 2444 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2445 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2446 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2447 /* include DDPed FCoE data */ 2448 if (ddp_bytes > 0) { 2449 if (!mss) { 2450 mss = rx_ring->netdev->mtu - 2451 sizeof(struct fcoe_hdr) - 2452 sizeof(struct fc_frame_header) - 2453 sizeof(struct fcoe_crc_eof); 2454 if (mss > 512) 2455 mss &= ~511; 2456 } 2457 total_rx_bytes += ddp_bytes; 2458 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2459 mss); 2460 } 2461 if (!ddp_bytes) { 2462 dev_kfree_skb_any(skb); 2463 continue; 2464 } 2465 } 2466 2467 #endif /* IXGBE_FCOE */ 2468 ixgbe_rx_skb(q_vector, skb); 2469 2470 /* update budget accounting */ 2471 total_rx_packets++; 2472 } 2473 2474 if (xdp_xmit) { 2475 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2476 2477 /* Force memory writes to complete before letting h/w 2478 * know there are new descriptors to fetch. 2479 */ 2480 wmb(); 2481 writel(ring->next_to_use, ring->tail); 2482 2483 xdp_do_flush_map(); 2484 } 2485 2486 u64_stats_update_begin(&rx_ring->syncp); 2487 rx_ring->stats.packets += total_rx_packets; 2488 rx_ring->stats.bytes += total_rx_bytes; 2489 u64_stats_update_end(&rx_ring->syncp); 2490 q_vector->rx.total_packets += total_rx_packets; 2491 q_vector->rx.total_bytes += total_rx_bytes; 2492 2493 return total_rx_packets; 2494 } 2495 2496 /** 2497 * ixgbe_configure_msix - Configure MSI-X hardware 2498 * @adapter: board private structure 2499 * 2500 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2501 * interrupts. 2502 **/ 2503 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2504 { 2505 struct ixgbe_q_vector *q_vector; 2506 int v_idx; 2507 u32 mask; 2508 2509 /* Populate MSIX to EITR Select */ 2510 if (adapter->num_vfs > 32) { 2511 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2512 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2513 } 2514 2515 /* 2516 * Populate the IVAR table and set the ITR values to the 2517 * corresponding register. 2518 */ 2519 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2520 struct ixgbe_ring *ring; 2521 q_vector = adapter->q_vector[v_idx]; 2522 2523 ixgbe_for_each_ring(ring, q_vector->rx) 2524 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2525 2526 ixgbe_for_each_ring(ring, q_vector->tx) 2527 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2528 2529 ixgbe_write_eitr(q_vector); 2530 } 2531 2532 switch (adapter->hw.mac.type) { 2533 case ixgbe_mac_82598EB: 2534 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2535 v_idx); 2536 break; 2537 case ixgbe_mac_82599EB: 2538 case ixgbe_mac_X540: 2539 case ixgbe_mac_X550: 2540 case ixgbe_mac_X550EM_x: 2541 case ixgbe_mac_x550em_a: 2542 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2543 break; 2544 default: 2545 break; 2546 } 2547 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2548 2549 /* set up to autoclear timer, and the vectors */ 2550 mask = IXGBE_EIMS_ENABLE_MASK; 2551 mask &= ~(IXGBE_EIMS_OTHER | 2552 IXGBE_EIMS_MAILBOX | 2553 IXGBE_EIMS_LSC); 2554 2555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2556 } 2557 2558 /** 2559 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2560 * @q_vector: structure containing interrupt and ring information 2561 * @ring_container: structure containing ring performance data 2562 * 2563 * Stores a new ITR value based on packets and byte 2564 * counts during the last interrupt. The advantage of per interrupt 2565 * computation is faster updates and more accurate ITR for the current 2566 * traffic pattern. Constants in this function were computed 2567 * based on theoretical maximum wire speed and thresholds were set based 2568 * on testing data as well as attempting to minimize response time 2569 * while increasing bulk throughput. 2570 **/ 2571 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2572 struct ixgbe_ring_container *ring_container) 2573 { 2574 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2575 IXGBE_ITR_ADAPTIVE_LATENCY; 2576 unsigned int avg_wire_size, packets, bytes; 2577 unsigned long next_update = jiffies; 2578 2579 /* If we don't have any rings just leave ourselves set for maximum 2580 * possible latency so we take ourselves out of the equation. 2581 */ 2582 if (!ring_container->ring) 2583 return; 2584 2585 /* If we didn't update within up to 1 - 2 jiffies we can assume 2586 * that either packets are coming in so slow there hasn't been 2587 * any work, or that there is so much work that NAPI is dealing 2588 * with interrupt moderation and we don't need to do anything. 2589 */ 2590 if (time_after(next_update, ring_container->next_update)) 2591 goto clear_counts; 2592 2593 packets = ring_container->total_packets; 2594 2595 /* We have no packets to actually measure against. This means 2596 * either one of the other queues on this vector is active or 2597 * we are a Tx queue doing TSO with too high of an interrupt rate. 2598 * 2599 * When this occurs just tick up our delay by the minimum value 2600 * and hope that this extra delay will prevent us from being called 2601 * without any work on our queue. 2602 */ 2603 if (!packets) { 2604 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2605 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2606 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2607 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2608 goto clear_counts; 2609 } 2610 2611 bytes = ring_container->total_bytes; 2612 2613 /* If packets are less than 4 or bytes are less than 9000 assume 2614 * insufficient data to use bulk rate limiting approach. We are 2615 * likely latency driven. 2616 */ 2617 if (packets < 4 && bytes < 9000) { 2618 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2619 goto adjust_by_size; 2620 } 2621 2622 /* Between 4 and 48 we can assume that our current interrupt delay 2623 * is only slightly too low. As such we should increase it by a small 2624 * fixed amount. 2625 */ 2626 if (packets < 48) { 2627 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2628 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2629 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2630 goto clear_counts; 2631 } 2632 2633 /* Between 48 and 96 is our "goldilocks" zone where we are working 2634 * out "just right". Just report that our current ITR is good for us. 2635 */ 2636 if (packets < 96) { 2637 itr = q_vector->itr >> 2; 2638 goto clear_counts; 2639 } 2640 2641 /* If packet count is 96 or greater we are likely looking at a slight 2642 * overrun of the delay we want. Try halving our delay to see if that 2643 * will cut the number of packets in half per interrupt. 2644 */ 2645 if (packets < 256) { 2646 itr = q_vector->itr >> 3; 2647 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2648 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2649 goto clear_counts; 2650 } 2651 2652 /* The paths below assume we are dealing with a bulk ITR since number 2653 * of packets is 256 or greater. We are just going to have to compute 2654 * a value and try to bring the count under control, though for smaller 2655 * packet sizes there isn't much we can do as NAPI polling will likely 2656 * be kicking in sooner rather than later. 2657 */ 2658 itr = IXGBE_ITR_ADAPTIVE_BULK; 2659 2660 adjust_by_size: 2661 /* If packet counts are 256 or greater we can assume we have a gross 2662 * overestimation of what the rate should be. Instead of trying to fine 2663 * tune it just use the formula below to try and dial in an exact value 2664 * give the current packet size of the frame. 2665 */ 2666 avg_wire_size = bytes / packets; 2667 2668 /* The following is a crude approximation of: 2669 * wmem_default / (size + overhead) = desired_pkts_per_int 2670 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2671 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2672 * 2673 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2674 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2675 * formula down to 2676 * 2677 * (170 * (size + 24)) / (size + 640) = ITR 2678 * 2679 * We first do some math on the packet size and then finally bitshift 2680 * by 8 after rounding up. We also have to account for PCIe link speed 2681 * difference as ITR scales based on this. 2682 */ 2683 if (avg_wire_size <= 60) { 2684 /* Start at 50k ints/sec */ 2685 avg_wire_size = 5120; 2686 } else if (avg_wire_size <= 316) { 2687 /* 50K ints/sec to 16K ints/sec */ 2688 avg_wire_size *= 40; 2689 avg_wire_size += 2720; 2690 } else if (avg_wire_size <= 1084) { 2691 /* 16K ints/sec to 9.2K ints/sec */ 2692 avg_wire_size *= 15; 2693 avg_wire_size += 11452; 2694 } else if (avg_wire_size <= 1980) { 2695 /* 9.2K ints/sec to 8K ints/sec */ 2696 avg_wire_size *= 5; 2697 avg_wire_size += 22420; 2698 } else { 2699 /* plateau at a limit of 8K ints/sec */ 2700 avg_wire_size = 32256; 2701 } 2702 2703 /* If we are in low latency mode half our delay which doubles the rate 2704 * to somewhere between 100K to 16K ints/sec 2705 */ 2706 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2707 avg_wire_size >>= 1; 2708 2709 /* Resultant value is 256 times larger than it needs to be. This 2710 * gives us room to adjust the value as needed to either increase 2711 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2712 * 2713 * Use addition as we have already recorded the new latency flag 2714 * for the ITR value. 2715 */ 2716 switch (q_vector->adapter->link_speed) { 2717 case IXGBE_LINK_SPEED_10GB_FULL: 2718 case IXGBE_LINK_SPEED_100_FULL: 2719 default: 2720 itr += DIV_ROUND_UP(avg_wire_size, 2721 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2722 IXGBE_ITR_ADAPTIVE_MIN_INC; 2723 break; 2724 case IXGBE_LINK_SPEED_2_5GB_FULL: 2725 case IXGBE_LINK_SPEED_1GB_FULL: 2726 case IXGBE_LINK_SPEED_10_FULL: 2727 itr += DIV_ROUND_UP(avg_wire_size, 2728 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2729 IXGBE_ITR_ADAPTIVE_MIN_INC; 2730 break; 2731 } 2732 2733 clear_counts: 2734 /* write back value */ 2735 ring_container->itr = itr; 2736 2737 /* next update should occur within next jiffy */ 2738 ring_container->next_update = next_update + 1; 2739 2740 ring_container->total_bytes = 0; 2741 ring_container->total_packets = 0; 2742 } 2743 2744 /** 2745 * ixgbe_write_eitr - write EITR register in hardware specific way 2746 * @q_vector: structure containing interrupt and ring information 2747 * 2748 * This function is made to be called by ethtool and by the driver 2749 * when it needs to update EITR registers at runtime. Hardware 2750 * specific quirks/differences are taken care of here. 2751 */ 2752 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2753 { 2754 struct ixgbe_adapter *adapter = q_vector->adapter; 2755 struct ixgbe_hw *hw = &adapter->hw; 2756 int v_idx = q_vector->v_idx; 2757 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2758 2759 switch (adapter->hw.mac.type) { 2760 case ixgbe_mac_82598EB: 2761 /* must write high and low 16 bits to reset counter */ 2762 itr_reg |= (itr_reg << 16); 2763 break; 2764 case ixgbe_mac_82599EB: 2765 case ixgbe_mac_X540: 2766 case ixgbe_mac_X550: 2767 case ixgbe_mac_X550EM_x: 2768 case ixgbe_mac_x550em_a: 2769 /* 2770 * set the WDIS bit to not clear the timer bits and cause an 2771 * immediate assertion of the interrupt 2772 */ 2773 itr_reg |= IXGBE_EITR_CNT_WDIS; 2774 break; 2775 default: 2776 break; 2777 } 2778 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2779 } 2780 2781 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2782 { 2783 u32 new_itr; 2784 2785 ixgbe_update_itr(q_vector, &q_vector->tx); 2786 ixgbe_update_itr(q_vector, &q_vector->rx); 2787 2788 /* use the smallest value of new ITR delay calculations */ 2789 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2790 2791 /* Clear latency flag if set, shift into correct position */ 2792 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2793 new_itr <<= 2; 2794 2795 if (new_itr != q_vector->itr) { 2796 /* save the algorithm value here */ 2797 q_vector->itr = new_itr; 2798 2799 ixgbe_write_eitr(q_vector); 2800 } 2801 } 2802 2803 /** 2804 * ixgbe_check_overtemp_subtask - check for over temperature 2805 * @adapter: pointer to adapter 2806 **/ 2807 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2808 { 2809 struct ixgbe_hw *hw = &adapter->hw; 2810 u32 eicr = adapter->interrupt_event; 2811 s32 rc; 2812 2813 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2814 return; 2815 2816 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2817 return; 2818 2819 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2820 2821 switch (hw->device_id) { 2822 case IXGBE_DEV_ID_82599_T3_LOM: 2823 /* 2824 * Since the warning interrupt is for both ports 2825 * we don't have to check if: 2826 * - This interrupt wasn't for our port. 2827 * - We may have missed the interrupt so always have to 2828 * check if we got a LSC 2829 */ 2830 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2831 !(eicr & IXGBE_EICR_LSC)) 2832 return; 2833 2834 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2835 u32 speed; 2836 bool link_up = false; 2837 2838 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2839 2840 if (link_up) 2841 return; 2842 } 2843 2844 /* Check if this is not due to overtemp */ 2845 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2846 return; 2847 2848 break; 2849 case IXGBE_DEV_ID_X550EM_A_1G_T: 2850 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2851 rc = hw->phy.ops.check_overtemp(hw); 2852 if (rc != IXGBE_ERR_OVERTEMP) 2853 return; 2854 break; 2855 default: 2856 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2857 return; 2858 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2859 return; 2860 break; 2861 } 2862 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2863 2864 adapter->interrupt_event = 0; 2865 } 2866 2867 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2868 { 2869 struct ixgbe_hw *hw = &adapter->hw; 2870 2871 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2872 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2873 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2874 /* write to clear the interrupt */ 2875 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2876 } 2877 } 2878 2879 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2880 { 2881 struct ixgbe_hw *hw = &adapter->hw; 2882 2883 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2884 return; 2885 2886 switch (adapter->hw.mac.type) { 2887 case ixgbe_mac_82599EB: 2888 /* 2889 * Need to check link state so complete overtemp check 2890 * on service task 2891 */ 2892 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2893 (eicr & IXGBE_EICR_LSC)) && 2894 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2895 adapter->interrupt_event = eicr; 2896 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2897 ixgbe_service_event_schedule(adapter); 2898 return; 2899 } 2900 return; 2901 case ixgbe_mac_x550em_a: 2902 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2903 adapter->interrupt_event = eicr; 2904 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2905 ixgbe_service_event_schedule(adapter); 2906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2907 IXGBE_EICR_GPI_SDP0_X550EM_a); 2908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2909 IXGBE_EICR_GPI_SDP0_X550EM_a); 2910 } 2911 return; 2912 case ixgbe_mac_X550: 2913 case ixgbe_mac_X540: 2914 if (!(eicr & IXGBE_EICR_TS)) 2915 return; 2916 break; 2917 default: 2918 return; 2919 } 2920 2921 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2922 } 2923 2924 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2925 { 2926 switch (hw->mac.type) { 2927 case ixgbe_mac_82598EB: 2928 if (hw->phy.type == ixgbe_phy_nl) 2929 return true; 2930 return false; 2931 case ixgbe_mac_82599EB: 2932 case ixgbe_mac_X550EM_x: 2933 case ixgbe_mac_x550em_a: 2934 switch (hw->mac.ops.get_media_type(hw)) { 2935 case ixgbe_media_type_fiber: 2936 case ixgbe_media_type_fiber_qsfp: 2937 return true; 2938 default: 2939 return false; 2940 } 2941 default: 2942 return false; 2943 } 2944 } 2945 2946 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2947 { 2948 struct ixgbe_hw *hw = &adapter->hw; 2949 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2950 2951 if (!ixgbe_is_sfp(hw)) 2952 return; 2953 2954 /* Later MAC's use different SDP */ 2955 if (hw->mac.type >= ixgbe_mac_X540) 2956 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2957 2958 if (eicr & eicr_mask) { 2959 /* Clear the interrupt */ 2960 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2961 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2962 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2963 adapter->sfp_poll_time = 0; 2964 ixgbe_service_event_schedule(adapter); 2965 } 2966 } 2967 2968 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2969 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2970 /* Clear the interrupt */ 2971 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2972 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2973 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2974 ixgbe_service_event_schedule(adapter); 2975 } 2976 } 2977 } 2978 2979 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2980 { 2981 struct ixgbe_hw *hw = &adapter->hw; 2982 2983 adapter->lsc_int++; 2984 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2985 adapter->link_check_timeout = jiffies; 2986 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2987 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2988 IXGBE_WRITE_FLUSH(hw); 2989 ixgbe_service_event_schedule(adapter); 2990 } 2991 } 2992 2993 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2994 u64 qmask) 2995 { 2996 u32 mask; 2997 struct ixgbe_hw *hw = &adapter->hw; 2998 2999 switch (hw->mac.type) { 3000 case ixgbe_mac_82598EB: 3001 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3002 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3003 break; 3004 case ixgbe_mac_82599EB: 3005 case ixgbe_mac_X540: 3006 case ixgbe_mac_X550: 3007 case ixgbe_mac_X550EM_x: 3008 case ixgbe_mac_x550em_a: 3009 mask = (qmask & 0xFFFFFFFF); 3010 if (mask) 3011 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3012 mask = (qmask >> 32); 3013 if (mask) 3014 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3015 break; 3016 default: 3017 break; 3018 } 3019 /* skip the flush */ 3020 } 3021 3022 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 3023 u64 qmask) 3024 { 3025 u32 mask; 3026 struct ixgbe_hw *hw = &adapter->hw; 3027 3028 switch (hw->mac.type) { 3029 case ixgbe_mac_82598EB: 3030 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3031 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3032 break; 3033 case ixgbe_mac_82599EB: 3034 case ixgbe_mac_X540: 3035 case ixgbe_mac_X550: 3036 case ixgbe_mac_X550EM_x: 3037 case ixgbe_mac_x550em_a: 3038 mask = (qmask & 0xFFFFFFFF); 3039 if (mask) 3040 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3041 mask = (qmask >> 32); 3042 if (mask) 3043 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3044 break; 3045 default: 3046 break; 3047 } 3048 /* skip the flush */ 3049 } 3050 3051 /** 3052 * ixgbe_irq_enable - Enable default interrupt generation settings 3053 * @adapter: board private structure 3054 * @queues: enable irqs for queues 3055 * @flush: flush register write 3056 **/ 3057 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3058 bool flush) 3059 { 3060 struct ixgbe_hw *hw = &adapter->hw; 3061 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3062 3063 /* don't reenable LSC while waiting for link */ 3064 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3065 mask &= ~IXGBE_EIMS_LSC; 3066 3067 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3068 switch (adapter->hw.mac.type) { 3069 case ixgbe_mac_82599EB: 3070 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3071 break; 3072 case ixgbe_mac_X540: 3073 case ixgbe_mac_X550: 3074 case ixgbe_mac_X550EM_x: 3075 case ixgbe_mac_x550em_a: 3076 mask |= IXGBE_EIMS_TS; 3077 break; 3078 default: 3079 break; 3080 } 3081 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3082 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3083 switch (adapter->hw.mac.type) { 3084 case ixgbe_mac_82599EB: 3085 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3086 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3087 /* fall through */ 3088 case ixgbe_mac_X540: 3089 case ixgbe_mac_X550: 3090 case ixgbe_mac_X550EM_x: 3091 case ixgbe_mac_x550em_a: 3092 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3093 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3094 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3095 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3096 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3097 mask |= IXGBE_EICR_GPI_SDP0_X540; 3098 mask |= IXGBE_EIMS_ECC; 3099 mask |= IXGBE_EIMS_MAILBOX; 3100 break; 3101 default: 3102 break; 3103 } 3104 3105 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3106 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3107 mask |= IXGBE_EIMS_FLOW_DIR; 3108 3109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3110 if (queues) 3111 ixgbe_irq_enable_queues(adapter, ~0); 3112 if (flush) 3113 IXGBE_WRITE_FLUSH(&adapter->hw); 3114 } 3115 3116 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3117 { 3118 struct ixgbe_adapter *adapter = data; 3119 struct ixgbe_hw *hw = &adapter->hw; 3120 u32 eicr; 3121 3122 /* 3123 * Workaround for Silicon errata. Use clear-by-write instead 3124 * of clear-by-read. Reading with EICS will return the 3125 * interrupt causes without clearing, which later be done 3126 * with the write to EICR. 3127 */ 3128 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3129 3130 /* The lower 16bits of the EICR register are for the queue interrupts 3131 * which should be masked here in order to not accidentally clear them if 3132 * the bits are high when ixgbe_msix_other is called. There is a race 3133 * condition otherwise which results in possible performance loss 3134 * especially if the ixgbe_msix_other interrupt is triggering 3135 * consistently (as it would when PPS is turned on for the X540 device) 3136 */ 3137 eicr &= 0xFFFF0000; 3138 3139 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3140 3141 if (eicr & IXGBE_EICR_LSC) 3142 ixgbe_check_lsc(adapter); 3143 3144 if (eicr & IXGBE_EICR_MAILBOX) 3145 ixgbe_msg_task(adapter); 3146 3147 switch (hw->mac.type) { 3148 case ixgbe_mac_82599EB: 3149 case ixgbe_mac_X540: 3150 case ixgbe_mac_X550: 3151 case ixgbe_mac_X550EM_x: 3152 case ixgbe_mac_x550em_a: 3153 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3154 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3155 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3156 ixgbe_service_event_schedule(adapter); 3157 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3158 IXGBE_EICR_GPI_SDP0_X540); 3159 } 3160 if (eicr & IXGBE_EICR_ECC) { 3161 e_info(link, "Received ECC Err, initiating reset\n"); 3162 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3163 ixgbe_service_event_schedule(adapter); 3164 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3165 } 3166 /* Handle Flow Director Full threshold interrupt */ 3167 if (eicr & IXGBE_EICR_FLOW_DIR) { 3168 int reinit_count = 0; 3169 int i; 3170 for (i = 0; i < adapter->num_tx_queues; i++) { 3171 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3172 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3173 &ring->state)) 3174 reinit_count++; 3175 } 3176 if (reinit_count) { 3177 /* no more flow director interrupts until after init */ 3178 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3179 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3180 ixgbe_service_event_schedule(adapter); 3181 } 3182 } 3183 ixgbe_check_sfp_event(adapter, eicr); 3184 ixgbe_check_overtemp_event(adapter, eicr); 3185 break; 3186 default: 3187 break; 3188 } 3189 3190 ixgbe_check_fan_failure(adapter, eicr); 3191 3192 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3193 ixgbe_ptp_check_pps_event(adapter); 3194 3195 /* re-enable the original interrupt state, no lsc, no queues */ 3196 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3197 ixgbe_irq_enable(adapter, false, false); 3198 3199 return IRQ_HANDLED; 3200 } 3201 3202 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3203 { 3204 struct ixgbe_q_vector *q_vector = data; 3205 3206 /* EIAM disabled interrupts (on this vector) for us */ 3207 3208 if (q_vector->rx.ring || q_vector->tx.ring) 3209 napi_schedule_irqoff(&q_vector->napi); 3210 3211 return IRQ_HANDLED; 3212 } 3213 3214 /** 3215 * ixgbe_poll - NAPI Rx polling callback 3216 * @napi: structure for representing this polling device 3217 * @budget: how many packets driver is allowed to clean 3218 * 3219 * This function is used for legacy and MSI, NAPI mode 3220 **/ 3221 int ixgbe_poll(struct napi_struct *napi, int budget) 3222 { 3223 struct ixgbe_q_vector *q_vector = 3224 container_of(napi, struct ixgbe_q_vector, napi); 3225 struct ixgbe_adapter *adapter = q_vector->adapter; 3226 struct ixgbe_ring *ring; 3227 int per_ring_budget, work_done = 0; 3228 bool clean_complete = true; 3229 3230 #ifdef CONFIG_IXGBE_DCA 3231 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3232 ixgbe_update_dca(q_vector); 3233 #endif 3234 3235 ixgbe_for_each_ring(ring, q_vector->tx) { 3236 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3237 clean_complete = false; 3238 } 3239 3240 /* Exit if we are called by netpoll */ 3241 if (budget <= 0) 3242 return budget; 3243 3244 /* attempt to distribute budget to each queue fairly, but don't allow 3245 * the budget to go below 1 because we'll exit polling */ 3246 if (q_vector->rx.count > 1) 3247 per_ring_budget = max(budget/q_vector->rx.count, 1); 3248 else 3249 per_ring_budget = budget; 3250 3251 ixgbe_for_each_ring(ring, q_vector->rx) { 3252 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3253 per_ring_budget); 3254 3255 work_done += cleaned; 3256 if (cleaned >= per_ring_budget) 3257 clean_complete = false; 3258 } 3259 3260 /* If all work not completed, return budget and keep polling */ 3261 if (!clean_complete) 3262 return budget; 3263 3264 /* all work done, exit the polling mode */ 3265 napi_complete_done(napi, work_done); 3266 if (adapter->rx_itr_setting & 1) 3267 ixgbe_set_itr(q_vector); 3268 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3269 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3270 3271 return min(work_done, budget - 1); 3272 } 3273 3274 /** 3275 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3276 * @adapter: board private structure 3277 * 3278 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3279 * interrupts from the kernel. 3280 **/ 3281 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3282 { 3283 struct net_device *netdev = adapter->netdev; 3284 unsigned int ri = 0, ti = 0; 3285 int vector, err; 3286 3287 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3288 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3289 struct msix_entry *entry = &adapter->msix_entries[vector]; 3290 3291 if (q_vector->tx.ring && q_vector->rx.ring) { 3292 snprintf(q_vector->name, sizeof(q_vector->name), 3293 "%s-TxRx-%u", netdev->name, ri++); 3294 ti++; 3295 } else if (q_vector->rx.ring) { 3296 snprintf(q_vector->name, sizeof(q_vector->name), 3297 "%s-rx-%u", netdev->name, ri++); 3298 } else if (q_vector->tx.ring) { 3299 snprintf(q_vector->name, sizeof(q_vector->name), 3300 "%s-tx-%u", netdev->name, ti++); 3301 } else { 3302 /* skip this unused q_vector */ 3303 continue; 3304 } 3305 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3306 q_vector->name, q_vector); 3307 if (err) { 3308 e_err(probe, "request_irq failed for MSIX interrupt " 3309 "Error: %d\n", err); 3310 goto free_queue_irqs; 3311 } 3312 /* If Flow Director is enabled, set interrupt affinity */ 3313 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3314 /* assign the mask for this irq */ 3315 irq_set_affinity_hint(entry->vector, 3316 &q_vector->affinity_mask); 3317 } 3318 } 3319 3320 err = request_irq(adapter->msix_entries[vector].vector, 3321 ixgbe_msix_other, 0, netdev->name, adapter); 3322 if (err) { 3323 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3324 goto free_queue_irqs; 3325 } 3326 3327 return 0; 3328 3329 free_queue_irqs: 3330 while (vector) { 3331 vector--; 3332 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3333 NULL); 3334 free_irq(adapter->msix_entries[vector].vector, 3335 adapter->q_vector[vector]); 3336 } 3337 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3338 pci_disable_msix(adapter->pdev); 3339 kfree(adapter->msix_entries); 3340 adapter->msix_entries = NULL; 3341 return err; 3342 } 3343 3344 /** 3345 * ixgbe_intr - legacy mode Interrupt Handler 3346 * @irq: interrupt number 3347 * @data: pointer to a network interface device structure 3348 **/ 3349 static irqreturn_t ixgbe_intr(int irq, void *data) 3350 { 3351 struct ixgbe_adapter *adapter = data; 3352 struct ixgbe_hw *hw = &adapter->hw; 3353 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3354 u32 eicr; 3355 3356 /* 3357 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3358 * before the read of EICR. 3359 */ 3360 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3361 3362 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3363 * therefore no explicit interrupt disable is necessary */ 3364 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3365 if (!eicr) { 3366 /* 3367 * shared interrupt alert! 3368 * make sure interrupts are enabled because the read will 3369 * have disabled interrupts due to EIAM 3370 * finish the workaround of silicon errata on 82598. Unmask 3371 * the interrupt that we masked before the EICR read. 3372 */ 3373 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3374 ixgbe_irq_enable(adapter, true, true); 3375 return IRQ_NONE; /* Not our interrupt */ 3376 } 3377 3378 if (eicr & IXGBE_EICR_LSC) 3379 ixgbe_check_lsc(adapter); 3380 3381 switch (hw->mac.type) { 3382 case ixgbe_mac_82599EB: 3383 ixgbe_check_sfp_event(adapter, eicr); 3384 /* Fall through */ 3385 case ixgbe_mac_X540: 3386 case ixgbe_mac_X550: 3387 case ixgbe_mac_X550EM_x: 3388 case ixgbe_mac_x550em_a: 3389 if (eicr & IXGBE_EICR_ECC) { 3390 e_info(link, "Received ECC Err, initiating reset\n"); 3391 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3392 ixgbe_service_event_schedule(adapter); 3393 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3394 } 3395 ixgbe_check_overtemp_event(adapter, eicr); 3396 break; 3397 default: 3398 break; 3399 } 3400 3401 ixgbe_check_fan_failure(adapter, eicr); 3402 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3403 ixgbe_ptp_check_pps_event(adapter); 3404 3405 /* would disable interrupts here but EIAM disabled it */ 3406 napi_schedule_irqoff(&q_vector->napi); 3407 3408 /* 3409 * re-enable link(maybe) and non-queue interrupts, no flush. 3410 * ixgbe_poll will re-enable the queue interrupts 3411 */ 3412 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3413 ixgbe_irq_enable(adapter, false, false); 3414 3415 return IRQ_HANDLED; 3416 } 3417 3418 /** 3419 * ixgbe_request_irq - initialize interrupts 3420 * @adapter: board private structure 3421 * 3422 * Attempts to configure interrupts using the best available 3423 * capabilities of the hardware and kernel. 3424 **/ 3425 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3426 { 3427 struct net_device *netdev = adapter->netdev; 3428 int err; 3429 3430 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3431 err = ixgbe_request_msix_irqs(adapter); 3432 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3433 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3434 netdev->name, adapter); 3435 else 3436 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3437 netdev->name, adapter); 3438 3439 if (err) 3440 e_err(probe, "request_irq failed, Error %d\n", err); 3441 3442 return err; 3443 } 3444 3445 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3446 { 3447 int vector; 3448 3449 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3450 free_irq(adapter->pdev->irq, adapter); 3451 return; 3452 } 3453 3454 if (!adapter->msix_entries) 3455 return; 3456 3457 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3458 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3459 struct msix_entry *entry = &adapter->msix_entries[vector]; 3460 3461 /* free only the irqs that were actually requested */ 3462 if (!q_vector->rx.ring && !q_vector->tx.ring) 3463 continue; 3464 3465 /* clear the affinity_mask in the IRQ descriptor */ 3466 irq_set_affinity_hint(entry->vector, NULL); 3467 3468 free_irq(entry->vector, q_vector); 3469 } 3470 3471 free_irq(adapter->msix_entries[vector].vector, adapter); 3472 } 3473 3474 /** 3475 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3476 * @adapter: board private structure 3477 **/ 3478 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3479 { 3480 switch (adapter->hw.mac.type) { 3481 case ixgbe_mac_82598EB: 3482 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3483 break; 3484 case ixgbe_mac_82599EB: 3485 case ixgbe_mac_X540: 3486 case ixgbe_mac_X550: 3487 case ixgbe_mac_X550EM_x: 3488 case ixgbe_mac_x550em_a: 3489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3492 break; 3493 default: 3494 break; 3495 } 3496 IXGBE_WRITE_FLUSH(&adapter->hw); 3497 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3498 int vector; 3499 3500 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3501 synchronize_irq(adapter->msix_entries[vector].vector); 3502 3503 synchronize_irq(adapter->msix_entries[vector++].vector); 3504 } else { 3505 synchronize_irq(adapter->pdev->irq); 3506 } 3507 } 3508 3509 /** 3510 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3511 * @adapter: board private structure 3512 * 3513 **/ 3514 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3515 { 3516 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3517 3518 ixgbe_write_eitr(q_vector); 3519 3520 ixgbe_set_ivar(adapter, 0, 0, 0); 3521 ixgbe_set_ivar(adapter, 1, 0, 0); 3522 3523 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3524 } 3525 3526 /** 3527 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3528 * @adapter: board private structure 3529 * @ring: structure containing ring specific data 3530 * 3531 * Configure the Tx descriptor ring after a reset. 3532 **/ 3533 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3534 struct ixgbe_ring *ring) 3535 { 3536 struct ixgbe_hw *hw = &adapter->hw; 3537 u64 tdba = ring->dma; 3538 int wait_loop = 10; 3539 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3540 u8 reg_idx = ring->reg_idx; 3541 3542 /* disable queue to avoid issues while updating state */ 3543 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3544 IXGBE_WRITE_FLUSH(hw); 3545 3546 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3547 (tdba & DMA_BIT_MASK(32))); 3548 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3549 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3550 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3551 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3552 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3553 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3554 3555 /* 3556 * set WTHRESH to encourage burst writeback, it should not be set 3557 * higher than 1 when: 3558 * - ITR is 0 as it could cause false TX hangs 3559 * - ITR is set to > 100k int/sec and BQL is enabled 3560 * 3561 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3562 * to or less than the number of on chip descriptors, which is 3563 * currently 40. 3564 */ 3565 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3566 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3567 else 3568 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3569 3570 /* 3571 * Setting PTHRESH to 32 both improves performance 3572 * and avoids a TX hang with DFP enabled 3573 */ 3574 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3575 32; /* PTHRESH = 32 */ 3576 3577 /* reinitialize flowdirector state */ 3578 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3579 ring->atr_sample_rate = adapter->atr_sample_rate; 3580 ring->atr_count = 0; 3581 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3582 } else { 3583 ring->atr_sample_rate = 0; 3584 } 3585 3586 /* initialize XPS */ 3587 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3588 struct ixgbe_q_vector *q_vector = ring->q_vector; 3589 3590 if (q_vector) 3591 netif_set_xps_queue(ring->netdev, 3592 &q_vector->affinity_mask, 3593 ring->queue_index); 3594 } 3595 3596 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3597 3598 /* reinitialize tx_buffer_info */ 3599 memset(ring->tx_buffer_info, 0, 3600 sizeof(struct ixgbe_tx_buffer) * ring->count); 3601 3602 /* enable queue */ 3603 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3604 3605 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3606 if (hw->mac.type == ixgbe_mac_82598EB && 3607 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3608 return; 3609 3610 /* poll to verify queue is enabled */ 3611 do { 3612 usleep_range(1000, 2000); 3613 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3614 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3615 if (!wait_loop) 3616 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3617 } 3618 3619 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3620 { 3621 struct ixgbe_hw *hw = &adapter->hw; 3622 u32 rttdcs, mtqc; 3623 u8 tcs = adapter->hw_tcs; 3624 3625 if (hw->mac.type == ixgbe_mac_82598EB) 3626 return; 3627 3628 /* disable the arbiter while setting MTQC */ 3629 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3630 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3631 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3632 3633 /* set transmit pool layout */ 3634 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3635 mtqc = IXGBE_MTQC_VT_ENA; 3636 if (tcs > 4) 3637 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3638 else if (tcs > 1) 3639 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3640 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3641 IXGBE_82599_VMDQ_4Q_MASK) 3642 mtqc |= IXGBE_MTQC_32VF; 3643 else 3644 mtqc |= IXGBE_MTQC_64VF; 3645 } else { 3646 if (tcs > 4) 3647 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3648 else if (tcs > 1) 3649 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3650 else 3651 mtqc = IXGBE_MTQC_64Q_1PB; 3652 } 3653 3654 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3655 3656 /* Enable Security TX Buffer IFG for multiple pb */ 3657 if (tcs) { 3658 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3659 sectx |= IXGBE_SECTX_DCB; 3660 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3661 } 3662 3663 /* re-enable the arbiter */ 3664 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3665 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3666 } 3667 3668 /** 3669 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3670 * @adapter: board private structure 3671 * 3672 * Configure the Tx unit of the MAC after a reset. 3673 **/ 3674 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3675 { 3676 struct ixgbe_hw *hw = &adapter->hw; 3677 u32 dmatxctl; 3678 u32 i; 3679 3680 ixgbe_setup_mtqc(adapter); 3681 3682 if (hw->mac.type != ixgbe_mac_82598EB) { 3683 /* DMATXCTL.EN must be before Tx queues are enabled */ 3684 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3685 dmatxctl |= IXGBE_DMATXCTL_TE; 3686 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3687 } 3688 3689 /* Setup the HW Tx Head and Tail descriptor pointers */ 3690 for (i = 0; i < adapter->num_tx_queues; i++) 3691 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3692 for (i = 0; i < adapter->num_xdp_queues; i++) 3693 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3694 } 3695 3696 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3697 struct ixgbe_ring *ring) 3698 { 3699 struct ixgbe_hw *hw = &adapter->hw; 3700 u8 reg_idx = ring->reg_idx; 3701 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3702 3703 srrctl |= IXGBE_SRRCTL_DROP_EN; 3704 3705 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3706 } 3707 3708 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3709 struct ixgbe_ring *ring) 3710 { 3711 struct ixgbe_hw *hw = &adapter->hw; 3712 u8 reg_idx = ring->reg_idx; 3713 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3714 3715 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3716 3717 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3718 } 3719 3720 #ifdef CONFIG_IXGBE_DCB 3721 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3722 #else 3723 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3724 #endif 3725 { 3726 int i; 3727 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3728 3729 if (adapter->ixgbe_ieee_pfc) 3730 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3731 3732 /* 3733 * We should set the drop enable bit if: 3734 * SR-IOV is enabled 3735 * or 3736 * Number of Rx queues > 1 and flow control is disabled 3737 * 3738 * This allows us to avoid head of line blocking for security 3739 * and performance reasons. 3740 */ 3741 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3742 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3743 for (i = 0; i < adapter->num_rx_queues; i++) 3744 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3745 } else { 3746 for (i = 0; i < adapter->num_rx_queues; i++) 3747 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3748 } 3749 } 3750 3751 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3752 3753 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3754 struct ixgbe_ring *rx_ring) 3755 { 3756 struct ixgbe_hw *hw = &adapter->hw; 3757 u32 srrctl; 3758 u8 reg_idx = rx_ring->reg_idx; 3759 3760 if (hw->mac.type == ixgbe_mac_82598EB) { 3761 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3762 3763 /* 3764 * if VMDq is not active we must program one srrctl register 3765 * per RSS queue since we have enabled RDRXCTL.MVMEN 3766 */ 3767 reg_idx &= mask; 3768 } 3769 3770 /* configure header buffer length, needed for RSC */ 3771 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3772 3773 /* configure the packet buffer length */ 3774 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3775 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3776 else 3777 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3778 3779 /* configure descriptor type */ 3780 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3781 3782 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3783 } 3784 3785 /** 3786 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3787 * @adapter: device handle 3788 * 3789 * - 82598/82599/X540: 128 3790 * - X550(non-SRIOV mode): 512 3791 * - X550(SRIOV mode): 64 3792 */ 3793 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3794 { 3795 if (adapter->hw.mac.type < ixgbe_mac_X550) 3796 return 128; 3797 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3798 return 64; 3799 else 3800 return 512; 3801 } 3802 3803 /** 3804 * ixgbe_store_key - Write the RSS key to HW 3805 * @adapter: device handle 3806 * 3807 * Write the RSS key stored in adapter.rss_key to HW. 3808 */ 3809 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3810 { 3811 struct ixgbe_hw *hw = &adapter->hw; 3812 int i; 3813 3814 for (i = 0; i < 10; i++) 3815 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3816 } 3817 3818 /** 3819 * ixgbe_init_rss_key - Initialize adapter RSS key 3820 * @adapter: device handle 3821 * 3822 * Allocates and initializes the RSS key if it is not allocated. 3823 **/ 3824 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3825 { 3826 u32 *rss_key; 3827 3828 if (!adapter->rss_key) { 3829 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3830 if (unlikely(!rss_key)) 3831 return -ENOMEM; 3832 3833 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3834 adapter->rss_key = rss_key; 3835 } 3836 3837 return 0; 3838 } 3839 3840 /** 3841 * ixgbe_store_reta - Write the RETA table to HW 3842 * @adapter: device handle 3843 * 3844 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3845 */ 3846 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3847 { 3848 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3849 struct ixgbe_hw *hw = &adapter->hw; 3850 u32 reta = 0; 3851 u32 indices_multi; 3852 u8 *indir_tbl = adapter->rss_indir_tbl; 3853 3854 /* Fill out the redirection table as follows: 3855 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3856 * indices. 3857 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3858 * - X550: 8 bit wide entries containing 6 bit RSS index 3859 */ 3860 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3861 indices_multi = 0x11; 3862 else 3863 indices_multi = 0x1; 3864 3865 /* Write redirection table to HW */ 3866 for (i = 0; i < reta_entries; i++) { 3867 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3868 if ((i & 3) == 3) { 3869 if (i < 128) 3870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3871 else 3872 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3873 reta); 3874 reta = 0; 3875 } 3876 } 3877 } 3878 3879 /** 3880 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3881 * @adapter: device handle 3882 * 3883 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3884 */ 3885 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3886 { 3887 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3888 struct ixgbe_hw *hw = &adapter->hw; 3889 u32 vfreta = 0; 3890 3891 /* Write redirection table to HW */ 3892 for (i = 0; i < reta_entries; i++) { 3893 u16 pool = adapter->num_rx_pools; 3894 3895 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3896 if ((i & 3) != 3) 3897 continue; 3898 3899 while (pool--) 3900 IXGBE_WRITE_REG(hw, 3901 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3902 vfreta); 3903 vfreta = 0; 3904 } 3905 } 3906 3907 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3908 { 3909 u32 i, j; 3910 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3911 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3912 3913 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3914 * make full use of any rings they may have. We will use the 3915 * PSRTYPE register to control how many rings we use within the PF. 3916 */ 3917 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3918 rss_i = 4; 3919 3920 /* Fill out hash function seeds */ 3921 ixgbe_store_key(adapter); 3922 3923 /* Fill out redirection table */ 3924 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3925 3926 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3927 if (j == rss_i) 3928 j = 0; 3929 3930 adapter->rss_indir_tbl[i] = j; 3931 } 3932 3933 ixgbe_store_reta(adapter); 3934 } 3935 3936 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3937 { 3938 struct ixgbe_hw *hw = &adapter->hw; 3939 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3940 int i, j; 3941 3942 /* Fill out hash function seeds */ 3943 for (i = 0; i < 10; i++) { 3944 u16 pool = adapter->num_rx_pools; 3945 3946 while (pool--) 3947 IXGBE_WRITE_REG(hw, 3948 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3949 *(adapter->rss_key + i)); 3950 } 3951 3952 /* Fill out the redirection table */ 3953 for (i = 0, j = 0; i < 64; i++, j++) { 3954 if (j == rss_i) 3955 j = 0; 3956 3957 adapter->rss_indir_tbl[i] = j; 3958 } 3959 3960 ixgbe_store_vfreta(adapter); 3961 } 3962 3963 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3964 { 3965 struct ixgbe_hw *hw = &adapter->hw; 3966 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3967 u32 rxcsum; 3968 3969 /* Disable indicating checksum in descriptor, enables RSS hash */ 3970 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3971 rxcsum |= IXGBE_RXCSUM_PCSD; 3972 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3973 3974 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3975 if (adapter->ring_feature[RING_F_RSS].mask) 3976 mrqc = IXGBE_MRQC_RSSEN; 3977 } else { 3978 u8 tcs = adapter->hw_tcs; 3979 3980 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3981 if (tcs > 4) 3982 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3983 else if (tcs > 1) 3984 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3985 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3986 IXGBE_82599_VMDQ_4Q_MASK) 3987 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3988 else 3989 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3990 3991 /* Enable L3/L4 for Tx Switched packets */ 3992 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3993 } else { 3994 if (tcs > 4) 3995 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3996 else if (tcs > 1) 3997 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3998 else 3999 mrqc = IXGBE_MRQC_RSSEN; 4000 } 4001 } 4002 4003 /* Perform hash on these packet types */ 4004 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 4005 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 4006 IXGBE_MRQC_RSS_FIELD_IPV6 | 4007 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 4008 4009 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 4010 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 4011 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 4012 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 4013 4014 if ((hw->mac.type >= ixgbe_mac_X550) && 4015 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4016 u16 pool = adapter->num_rx_pools; 4017 4018 /* Enable VF RSS mode */ 4019 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4020 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4021 4022 /* Setup RSS through the VF registers */ 4023 ixgbe_setup_vfreta(adapter); 4024 vfmrqc = IXGBE_MRQC_RSSEN; 4025 vfmrqc |= rss_field; 4026 4027 while (pool--) 4028 IXGBE_WRITE_REG(hw, 4029 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4030 vfmrqc); 4031 } else { 4032 ixgbe_setup_reta(adapter); 4033 mrqc |= rss_field; 4034 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4035 } 4036 } 4037 4038 /** 4039 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4040 * @adapter: address of board private structure 4041 * @ring: structure containing ring specific data 4042 **/ 4043 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4044 struct ixgbe_ring *ring) 4045 { 4046 struct ixgbe_hw *hw = &adapter->hw; 4047 u32 rscctrl; 4048 u8 reg_idx = ring->reg_idx; 4049 4050 if (!ring_is_rsc_enabled(ring)) 4051 return; 4052 4053 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4054 rscctrl |= IXGBE_RSCCTL_RSCEN; 4055 /* 4056 * we must limit the number of descriptors so that the 4057 * total size of max desc * buf_len is not greater 4058 * than 65536 4059 */ 4060 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4061 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4062 } 4063 4064 #define IXGBE_MAX_RX_DESC_POLL 10 4065 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4066 struct ixgbe_ring *ring) 4067 { 4068 struct ixgbe_hw *hw = &adapter->hw; 4069 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4070 u32 rxdctl; 4071 u8 reg_idx = ring->reg_idx; 4072 4073 if (ixgbe_removed(hw->hw_addr)) 4074 return; 4075 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4076 if (hw->mac.type == ixgbe_mac_82598EB && 4077 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4078 return; 4079 4080 do { 4081 usleep_range(1000, 2000); 4082 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4083 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4084 4085 if (!wait_loop) { 4086 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4087 "the polling period\n", reg_idx); 4088 } 4089 } 4090 4091 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4092 struct ixgbe_ring *ring) 4093 { 4094 struct ixgbe_hw *hw = &adapter->hw; 4095 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4096 u32 rxdctl; 4097 u8 reg_idx = ring->reg_idx; 4098 4099 if (ixgbe_removed(hw->hw_addr)) 4100 return; 4101 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4102 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4103 4104 /* write value back with RXDCTL.ENABLE bit cleared */ 4105 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4106 4107 if (hw->mac.type == ixgbe_mac_82598EB && 4108 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4109 return; 4110 4111 /* the hardware may take up to 100us to really disable the rx queue */ 4112 do { 4113 udelay(10); 4114 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4115 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4116 4117 if (!wait_loop) { 4118 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4119 "the polling period\n", reg_idx); 4120 } 4121 } 4122 4123 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4124 struct ixgbe_ring *ring) 4125 { 4126 struct ixgbe_hw *hw = &adapter->hw; 4127 union ixgbe_adv_rx_desc *rx_desc; 4128 u64 rdba = ring->dma; 4129 u32 rxdctl; 4130 u8 reg_idx = ring->reg_idx; 4131 4132 /* disable queue to avoid issues while updating state */ 4133 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4134 ixgbe_disable_rx_queue(adapter, ring); 4135 4136 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4137 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4138 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4139 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4140 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4141 IXGBE_WRITE_FLUSH(hw); 4142 4143 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4144 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4145 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4146 4147 ixgbe_configure_srrctl(adapter, ring); 4148 ixgbe_configure_rscctl(adapter, ring); 4149 4150 if (hw->mac.type == ixgbe_mac_82598EB) { 4151 /* 4152 * enable cache line friendly hardware writes: 4153 * PTHRESH=32 descriptors (half the internal cache), 4154 * this also removes ugly rx_no_buffer_count increment 4155 * HTHRESH=4 descriptors (to minimize latency on fetch) 4156 * WTHRESH=8 burst writeback up to two cache lines 4157 */ 4158 rxdctl &= ~0x3FFFFF; 4159 rxdctl |= 0x080420; 4160 #if (PAGE_SIZE < 8192) 4161 /* RXDCTL.RLPML does not work on 82599 */ 4162 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4163 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4164 IXGBE_RXDCTL_RLPML_EN); 4165 4166 /* Limit the maximum frame size so we don't overrun the skb. 4167 * This can happen in SRIOV mode when the MTU of the VF is 4168 * higher than the MTU of the PF. 4169 */ 4170 if (ring_uses_build_skb(ring) && 4171 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4172 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4173 IXGBE_RXDCTL_RLPML_EN; 4174 #endif 4175 } 4176 4177 /* initialize rx_buffer_info */ 4178 memset(ring->rx_buffer_info, 0, 4179 sizeof(struct ixgbe_rx_buffer) * ring->count); 4180 4181 /* initialize Rx descriptor 0 */ 4182 rx_desc = IXGBE_RX_DESC(ring, 0); 4183 rx_desc->wb.upper.length = 0; 4184 4185 /* enable receive descriptor ring */ 4186 rxdctl |= IXGBE_RXDCTL_ENABLE; 4187 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4188 4189 ixgbe_rx_desc_queue_enable(adapter, ring); 4190 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4191 } 4192 4193 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4194 { 4195 struct ixgbe_hw *hw = &adapter->hw; 4196 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4197 u16 pool = adapter->num_rx_pools; 4198 4199 /* PSRTYPE must be initialized in non 82598 adapters */ 4200 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4201 IXGBE_PSRTYPE_UDPHDR | 4202 IXGBE_PSRTYPE_IPV4HDR | 4203 IXGBE_PSRTYPE_L2HDR | 4204 IXGBE_PSRTYPE_IPV6HDR; 4205 4206 if (hw->mac.type == ixgbe_mac_82598EB) 4207 return; 4208 4209 if (rss_i > 3) 4210 psrtype |= 2u << 29; 4211 else if (rss_i > 1) 4212 psrtype |= 1u << 29; 4213 4214 while (pool--) 4215 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4216 } 4217 4218 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4219 { 4220 struct ixgbe_hw *hw = &adapter->hw; 4221 u16 pool = adapter->num_rx_pools; 4222 u32 reg_offset, vf_shift, vmolr; 4223 u32 gcr_ext, vmdctl; 4224 int i; 4225 4226 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4227 return; 4228 4229 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4230 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4231 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4232 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4233 vmdctl |= IXGBE_VT_CTL_REPLEN; 4234 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4235 4236 /* accept untagged packets until a vlan tag is 4237 * specifically set for the VMDQ queue/pool 4238 */ 4239 vmolr = IXGBE_VMOLR_AUPE; 4240 while (pool--) 4241 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4242 4243 vf_shift = VMDQ_P(0) % 32; 4244 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4245 4246 /* Enable only the PF's pool for Tx/Rx */ 4247 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4248 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4249 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4250 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4251 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4252 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4253 4254 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4255 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4256 4257 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4258 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4259 4260 /* 4261 * Set up VF register offsets for selected VT Mode, 4262 * i.e. 32 or 64 VFs for SR-IOV 4263 */ 4264 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4265 case IXGBE_82599_VMDQ_8Q_MASK: 4266 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4267 break; 4268 case IXGBE_82599_VMDQ_4Q_MASK: 4269 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4270 break; 4271 default: 4272 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4273 break; 4274 } 4275 4276 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4277 4278 for (i = 0; i < adapter->num_vfs; i++) { 4279 /* configure spoof checking */ 4280 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4281 adapter->vfinfo[i].spoofchk_enabled); 4282 4283 /* Enable/Disable RSS query feature */ 4284 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4285 adapter->vfinfo[i].rss_query_enabled); 4286 } 4287 } 4288 4289 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4290 { 4291 struct ixgbe_hw *hw = &adapter->hw; 4292 struct net_device *netdev = adapter->netdev; 4293 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4294 struct ixgbe_ring *rx_ring; 4295 int i; 4296 u32 mhadd, hlreg0; 4297 4298 #ifdef IXGBE_FCOE 4299 /* adjust max frame to be able to do baby jumbo for FCoE */ 4300 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4301 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4302 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4303 4304 #endif /* IXGBE_FCOE */ 4305 4306 /* adjust max frame to be at least the size of a standard frame */ 4307 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4308 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4309 4310 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4311 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4312 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4313 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4314 4315 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4316 } 4317 4318 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4319 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4320 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4321 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4322 4323 /* 4324 * Setup the HW Rx Head and Tail Descriptor Pointers and 4325 * the Base and Length of the Rx Descriptor Ring 4326 */ 4327 for (i = 0; i < adapter->num_rx_queues; i++) { 4328 rx_ring = adapter->rx_ring[i]; 4329 4330 clear_ring_rsc_enabled(rx_ring); 4331 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4332 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4333 4334 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4335 set_ring_rsc_enabled(rx_ring); 4336 4337 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4338 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4339 4340 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4341 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4342 continue; 4343 4344 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4345 4346 #if (PAGE_SIZE < 8192) 4347 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4348 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4349 4350 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4351 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4352 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4353 #endif 4354 } 4355 } 4356 4357 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4358 { 4359 struct ixgbe_hw *hw = &adapter->hw; 4360 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4361 4362 switch (hw->mac.type) { 4363 case ixgbe_mac_82598EB: 4364 /* 4365 * For VMDq support of different descriptor types or 4366 * buffer sizes through the use of multiple SRRCTL 4367 * registers, RDRXCTL.MVMEN must be set to 1 4368 * 4369 * also, the manual doesn't mention it clearly but DCA hints 4370 * will only use queue 0's tags unless this bit is set. Side 4371 * effects of setting this bit are only that SRRCTL must be 4372 * fully programmed [0..15] 4373 */ 4374 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4375 break; 4376 case ixgbe_mac_X550: 4377 case ixgbe_mac_X550EM_x: 4378 case ixgbe_mac_x550em_a: 4379 if (adapter->num_vfs) 4380 rdrxctl |= IXGBE_RDRXCTL_PSP; 4381 /* fall through */ 4382 case ixgbe_mac_82599EB: 4383 case ixgbe_mac_X540: 4384 /* Disable RSC for ACK packets */ 4385 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4386 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4387 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4388 /* hardware requires some bits to be set by default */ 4389 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4390 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4391 break; 4392 default: 4393 /* We should do nothing since we don't know this hardware */ 4394 return; 4395 } 4396 4397 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4398 } 4399 4400 /** 4401 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4402 * @adapter: board private structure 4403 * 4404 * Configure the Rx unit of the MAC after a reset. 4405 **/ 4406 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4407 { 4408 struct ixgbe_hw *hw = &adapter->hw; 4409 int i; 4410 u32 rxctrl, rfctl; 4411 4412 /* disable receives while setting up the descriptors */ 4413 hw->mac.ops.disable_rx(hw); 4414 4415 ixgbe_setup_psrtype(adapter); 4416 ixgbe_setup_rdrxctl(adapter); 4417 4418 /* RSC Setup */ 4419 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4420 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4421 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4422 rfctl |= IXGBE_RFCTL_RSC_DIS; 4423 4424 /* disable NFS filtering */ 4425 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4426 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4427 4428 /* Program registers for the distribution of queues */ 4429 ixgbe_setup_mrqc(adapter); 4430 4431 /* set_rx_buffer_len must be called before ring initialization */ 4432 ixgbe_set_rx_buffer_len(adapter); 4433 4434 /* 4435 * Setup the HW Rx Head and Tail Descriptor Pointers and 4436 * the Base and Length of the Rx Descriptor Ring 4437 */ 4438 for (i = 0; i < adapter->num_rx_queues; i++) 4439 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4440 4441 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4442 /* disable drop enable for 82598 parts */ 4443 if (hw->mac.type == ixgbe_mac_82598EB) 4444 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4445 4446 /* enable all receives */ 4447 rxctrl |= IXGBE_RXCTRL_RXEN; 4448 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4449 } 4450 4451 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4452 __be16 proto, u16 vid) 4453 { 4454 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4455 struct ixgbe_hw *hw = &adapter->hw; 4456 4457 /* add VID to filter table */ 4458 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4459 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4460 4461 set_bit(vid, adapter->active_vlans); 4462 4463 return 0; 4464 } 4465 4466 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4467 { 4468 u32 vlvf; 4469 int idx; 4470 4471 /* short cut the special case */ 4472 if (vlan == 0) 4473 return 0; 4474 4475 /* Search for the vlan id in the VLVF entries */ 4476 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4477 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4478 if ((vlvf & VLAN_VID_MASK) == vlan) 4479 break; 4480 } 4481 4482 return idx; 4483 } 4484 4485 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4486 { 4487 struct ixgbe_hw *hw = &adapter->hw; 4488 u32 bits, word; 4489 int idx; 4490 4491 idx = ixgbe_find_vlvf_entry(hw, vid); 4492 if (!idx) 4493 return; 4494 4495 /* See if any other pools are set for this VLAN filter 4496 * entry other than the PF. 4497 */ 4498 word = idx * 2 + (VMDQ_P(0) / 32); 4499 bits = ~BIT(VMDQ_P(0) % 32); 4500 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4501 4502 /* Disable the filter so this falls into the default pool. */ 4503 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4504 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4505 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4506 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4507 } 4508 } 4509 4510 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4511 __be16 proto, u16 vid) 4512 { 4513 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4514 struct ixgbe_hw *hw = &adapter->hw; 4515 4516 /* remove VID from filter table */ 4517 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4518 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4519 4520 clear_bit(vid, adapter->active_vlans); 4521 4522 return 0; 4523 } 4524 4525 /** 4526 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4527 * @adapter: driver data 4528 */ 4529 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4530 { 4531 struct ixgbe_hw *hw = &adapter->hw; 4532 u32 vlnctrl; 4533 int i, j; 4534 4535 switch (hw->mac.type) { 4536 case ixgbe_mac_82598EB: 4537 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4538 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4539 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4540 break; 4541 case ixgbe_mac_82599EB: 4542 case ixgbe_mac_X540: 4543 case ixgbe_mac_X550: 4544 case ixgbe_mac_X550EM_x: 4545 case ixgbe_mac_x550em_a: 4546 for (i = 0; i < adapter->num_rx_queues; i++) { 4547 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4548 4549 if (!netif_is_ixgbe(ring->netdev)) 4550 continue; 4551 4552 j = ring->reg_idx; 4553 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4554 vlnctrl &= ~IXGBE_RXDCTL_VME; 4555 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4556 } 4557 break; 4558 default: 4559 break; 4560 } 4561 } 4562 4563 /** 4564 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4565 * @adapter: driver data 4566 */ 4567 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4568 { 4569 struct ixgbe_hw *hw = &adapter->hw; 4570 u32 vlnctrl; 4571 int i, j; 4572 4573 switch (hw->mac.type) { 4574 case ixgbe_mac_82598EB: 4575 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4576 vlnctrl |= IXGBE_VLNCTRL_VME; 4577 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4578 break; 4579 case ixgbe_mac_82599EB: 4580 case ixgbe_mac_X540: 4581 case ixgbe_mac_X550: 4582 case ixgbe_mac_X550EM_x: 4583 case ixgbe_mac_x550em_a: 4584 for (i = 0; i < adapter->num_rx_queues; i++) { 4585 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4586 4587 if (!netif_is_ixgbe(ring->netdev)) 4588 continue; 4589 4590 j = ring->reg_idx; 4591 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4592 vlnctrl |= IXGBE_RXDCTL_VME; 4593 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4594 } 4595 break; 4596 default: 4597 break; 4598 } 4599 } 4600 4601 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4602 { 4603 struct ixgbe_hw *hw = &adapter->hw; 4604 u32 vlnctrl, i; 4605 4606 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4607 4608 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4609 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4610 vlnctrl |= IXGBE_VLNCTRL_VFE; 4611 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4612 } else { 4613 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4614 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4615 return; 4616 } 4617 4618 /* Nothing to do for 82598 */ 4619 if (hw->mac.type == ixgbe_mac_82598EB) 4620 return; 4621 4622 /* We are already in VLAN promisc, nothing to do */ 4623 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4624 return; 4625 4626 /* Set flag so we don't redo unnecessary work */ 4627 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4628 4629 /* Add PF to all active pools */ 4630 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4631 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4632 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4633 4634 vlvfb |= BIT(VMDQ_P(0) % 32); 4635 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4636 } 4637 4638 /* Set all bits in the VLAN filter table array */ 4639 for (i = hw->mac.vft_size; i--;) 4640 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4641 } 4642 4643 #define VFTA_BLOCK_SIZE 8 4644 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4645 { 4646 struct ixgbe_hw *hw = &adapter->hw; 4647 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4648 u32 vid_start = vfta_offset * 32; 4649 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4650 u32 i, vid, word, bits; 4651 4652 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4653 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4654 4655 /* pull VLAN ID from VLVF */ 4656 vid = vlvf & VLAN_VID_MASK; 4657 4658 /* only concern outselves with a certain range */ 4659 if (vid < vid_start || vid >= vid_end) 4660 continue; 4661 4662 if (vlvf) { 4663 /* record VLAN ID in VFTA */ 4664 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4665 4666 /* if PF is part of this then continue */ 4667 if (test_bit(vid, adapter->active_vlans)) 4668 continue; 4669 } 4670 4671 /* remove PF from the pool */ 4672 word = i * 2 + VMDQ_P(0) / 32; 4673 bits = ~BIT(VMDQ_P(0) % 32); 4674 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4675 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4676 } 4677 4678 /* extract values from active_vlans and write back to VFTA */ 4679 for (i = VFTA_BLOCK_SIZE; i--;) { 4680 vid = (vfta_offset + i) * 32; 4681 word = vid / BITS_PER_LONG; 4682 bits = vid % BITS_PER_LONG; 4683 4684 vfta[i] |= adapter->active_vlans[word] >> bits; 4685 4686 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4687 } 4688 } 4689 4690 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4691 { 4692 struct ixgbe_hw *hw = &adapter->hw; 4693 u32 vlnctrl, i; 4694 4695 /* Set VLAN filtering to enabled */ 4696 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4697 vlnctrl |= IXGBE_VLNCTRL_VFE; 4698 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4699 4700 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4701 hw->mac.type == ixgbe_mac_82598EB) 4702 return; 4703 4704 /* We are not in VLAN promisc, nothing to do */ 4705 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4706 return; 4707 4708 /* Set flag so we don't redo unnecessary work */ 4709 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4710 4711 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4712 ixgbe_scrub_vfta(adapter, i); 4713 } 4714 4715 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4716 { 4717 u16 vid = 1; 4718 4719 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4720 4721 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4722 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4723 } 4724 4725 /** 4726 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4727 * @netdev: network interface device structure 4728 * 4729 * Writes multicast address list to the MTA hash table. 4730 * Returns: -ENOMEM on failure 4731 * 0 on no addresses written 4732 * X on writing X addresses to MTA 4733 **/ 4734 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4735 { 4736 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4737 struct ixgbe_hw *hw = &adapter->hw; 4738 4739 if (!netif_running(netdev)) 4740 return 0; 4741 4742 if (hw->mac.ops.update_mc_addr_list) 4743 hw->mac.ops.update_mc_addr_list(hw, netdev); 4744 else 4745 return -ENOMEM; 4746 4747 #ifdef CONFIG_PCI_IOV 4748 ixgbe_restore_vf_multicasts(adapter); 4749 #endif 4750 4751 return netdev_mc_count(netdev); 4752 } 4753 4754 #ifdef CONFIG_PCI_IOV 4755 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4756 { 4757 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4758 struct ixgbe_hw *hw = &adapter->hw; 4759 int i; 4760 4761 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4762 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4763 4764 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4765 hw->mac.ops.set_rar(hw, i, 4766 mac_table->addr, 4767 mac_table->pool, 4768 IXGBE_RAH_AV); 4769 else 4770 hw->mac.ops.clear_rar(hw, i); 4771 } 4772 } 4773 4774 #endif 4775 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4776 { 4777 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4778 struct ixgbe_hw *hw = &adapter->hw; 4779 int i; 4780 4781 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4782 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4783 continue; 4784 4785 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4786 4787 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4788 hw->mac.ops.set_rar(hw, i, 4789 mac_table->addr, 4790 mac_table->pool, 4791 IXGBE_RAH_AV); 4792 else 4793 hw->mac.ops.clear_rar(hw, i); 4794 } 4795 } 4796 4797 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4798 { 4799 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4800 struct ixgbe_hw *hw = &adapter->hw; 4801 int i; 4802 4803 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4804 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4805 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4806 } 4807 4808 ixgbe_sync_mac_table(adapter); 4809 } 4810 4811 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4812 { 4813 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4814 struct ixgbe_hw *hw = &adapter->hw; 4815 int i, count = 0; 4816 4817 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4818 /* do not count default RAR as available */ 4819 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4820 continue; 4821 4822 /* only count unused and addresses that belong to us */ 4823 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4824 if (mac_table->pool != pool) 4825 continue; 4826 } 4827 4828 count++; 4829 } 4830 4831 return count; 4832 } 4833 4834 /* this function destroys the first RAR entry */ 4835 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4836 { 4837 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4838 struct ixgbe_hw *hw = &adapter->hw; 4839 4840 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4841 mac_table->pool = VMDQ_P(0); 4842 4843 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4844 4845 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4846 IXGBE_RAH_AV); 4847 } 4848 4849 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4850 const u8 *addr, u16 pool) 4851 { 4852 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4853 struct ixgbe_hw *hw = &adapter->hw; 4854 int i; 4855 4856 if (is_zero_ether_addr(addr)) 4857 return -EINVAL; 4858 4859 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4860 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4861 continue; 4862 4863 ether_addr_copy(mac_table->addr, addr); 4864 mac_table->pool = pool; 4865 4866 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4867 IXGBE_MAC_STATE_IN_USE; 4868 4869 ixgbe_sync_mac_table(adapter); 4870 4871 return i; 4872 } 4873 4874 return -ENOMEM; 4875 } 4876 4877 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4878 const u8 *addr, u16 pool) 4879 { 4880 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4881 struct ixgbe_hw *hw = &adapter->hw; 4882 int i; 4883 4884 if (is_zero_ether_addr(addr)) 4885 return -EINVAL; 4886 4887 /* search table for addr, if found clear IN_USE flag and sync */ 4888 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4889 /* we can only delete an entry if it is in use */ 4890 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4891 continue; 4892 /* we only care about entries that belong to the given pool */ 4893 if (mac_table->pool != pool) 4894 continue; 4895 /* we only care about a specific MAC address */ 4896 if (!ether_addr_equal(addr, mac_table->addr)) 4897 continue; 4898 4899 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4900 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4901 4902 ixgbe_sync_mac_table(adapter); 4903 4904 return 0; 4905 } 4906 4907 return -ENOMEM; 4908 } 4909 4910 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4911 { 4912 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4913 int ret; 4914 4915 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4916 4917 return min_t(int, ret, 0); 4918 } 4919 4920 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4921 { 4922 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4923 4924 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4925 4926 return 0; 4927 } 4928 4929 /** 4930 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4931 * @netdev: network interface device structure 4932 * 4933 * The set_rx_method entry point is called whenever the unicast/multicast 4934 * address list or the network interface flags are updated. This routine is 4935 * responsible for configuring the hardware for proper unicast, multicast and 4936 * promiscuous mode. 4937 **/ 4938 void ixgbe_set_rx_mode(struct net_device *netdev) 4939 { 4940 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4941 struct ixgbe_hw *hw = &adapter->hw; 4942 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4943 netdev_features_t features = netdev->features; 4944 int count; 4945 4946 /* Check for Promiscuous and All Multicast modes */ 4947 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4948 4949 /* set all bits that we expect to always be set */ 4950 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4951 fctrl |= IXGBE_FCTRL_BAM; 4952 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4953 fctrl |= IXGBE_FCTRL_PMCF; 4954 4955 /* clear the bits we are changing the status of */ 4956 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4957 if (netdev->flags & IFF_PROMISC) { 4958 hw->addr_ctrl.user_set_promisc = true; 4959 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4960 vmolr |= IXGBE_VMOLR_MPE; 4961 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4962 } else { 4963 if (netdev->flags & IFF_ALLMULTI) { 4964 fctrl |= IXGBE_FCTRL_MPE; 4965 vmolr |= IXGBE_VMOLR_MPE; 4966 } 4967 hw->addr_ctrl.user_set_promisc = false; 4968 } 4969 4970 /* 4971 * Write addresses to available RAR registers, if there is not 4972 * sufficient space to store all the addresses then enable 4973 * unicast promiscuous mode 4974 */ 4975 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4976 fctrl |= IXGBE_FCTRL_UPE; 4977 vmolr |= IXGBE_VMOLR_ROPE; 4978 } 4979 4980 /* Write addresses to the MTA, if the attempt fails 4981 * then we should just turn on promiscuous mode so 4982 * that we can at least receive multicast traffic 4983 */ 4984 count = ixgbe_write_mc_addr_list(netdev); 4985 if (count < 0) { 4986 fctrl |= IXGBE_FCTRL_MPE; 4987 vmolr |= IXGBE_VMOLR_MPE; 4988 } else if (count) { 4989 vmolr |= IXGBE_VMOLR_ROMPE; 4990 } 4991 4992 if (hw->mac.type != ixgbe_mac_82598EB) { 4993 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4994 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4995 IXGBE_VMOLR_ROPE); 4996 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4997 } 4998 4999 /* This is useful for sniffing bad packets. */ 5000 if (features & NETIF_F_RXALL) { 5001 /* UPE and MPE will be handled by normal PROMISC logic 5002 * in e1000e_set_rx_mode */ 5003 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5004 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5005 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5006 5007 fctrl &= ~(IXGBE_FCTRL_DPF); 5008 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5009 } 5010 5011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5012 5013 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5014 ixgbe_vlan_strip_enable(adapter); 5015 else 5016 ixgbe_vlan_strip_disable(adapter); 5017 5018 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5019 ixgbe_vlan_promisc_disable(adapter); 5020 else 5021 ixgbe_vlan_promisc_enable(adapter); 5022 } 5023 5024 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5025 { 5026 int q_idx; 5027 5028 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5029 napi_enable(&adapter->q_vector[q_idx]->napi); 5030 } 5031 5032 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5033 { 5034 int q_idx; 5035 5036 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5037 napi_disable(&adapter->q_vector[q_idx]->napi); 5038 } 5039 5040 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5041 { 5042 struct ixgbe_hw *hw = &adapter->hw; 5043 u32 vxlanctrl; 5044 5045 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5046 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5047 return; 5048 5049 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5050 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5051 5052 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5053 adapter->vxlan_port = 0; 5054 5055 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5056 adapter->geneve_port = 0; 5057 } 5058 5059 #ifdef CONFIG_IXGBE_DCB 5060 /** 5061 * ixgbe_configure_dcb - Configure DCB hardware 5062 * @adapter: ixgbe adapter struct 5063 * 5064 * This is called by the driver on open to configure the DCB hardware. 5065 * This is also called by the gennetlink interface when reconfiguring 5066 * the DCB state. 5067 */ 5068 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5069 { 5070 struct ixgbe_hw *hw = &adapter->hw; 5071 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5072 5073 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5074 if (hw->mac.type == ixgbe_mac_82598EB) 5075 netif_set_gso_max_size(adapter->netdev, 65536); 5076 return; 5077 } 5078 5079 if (hw->mac.type == ixgbe_mac_82598EB) 5080 netif_set_gso_max_size(adapter->netdev, 32768); 5081 5082 #ifdef IXGBE_FCOE 5083 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5084 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5085 #endif 5086 5087 /* reconfigure the hardware */ 5088 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5089 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5090 DCB_TX_CONFIG); 5091 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5092 DCB_RX_CONFIG); 5093 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5094 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5095 ixgbe_dcb_hw_ets(&adapter->hw, 5096 adapter->ixgbe_ieee_ets, 5097 max_frame); 5098 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5099 adapter->ixgbe_ieee_pfc->pfc_en, 5100 adapter->ixgbe_ieee_ets->prio_tc); 5101 } 5102 5103 /* Enable RSS Hash per TC */ 5104 if (hw->mac.type != ixgbe_mac_82598EB) { 5105 u32 msb = 0; 5106 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5107 5108 while (rss_i) { 5109 msb++; 5110 rss_i >>= 1; 5111 } 5112 5113 /* write msb to all 8 TCs in one write */ 5114 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5115 } 5116 } 5117 #endif 5118 5119 /* Additional bittime to account for IXGBE framing */ 5120 #define IXGBE_ETH_FRAMING 20 5121 5122 /** 5123 * ixgbe_hpbthresh - calculate high water mark for flow control 5124 * 5125 * @adapter: board private structure to calculate for 5126 * @pb: packet buffer to calculate 5127 */ 5128 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5129 { 5130 struct ixgbe_hw *hw = &adapter->hw; 5131 struct net_device *dev = adapter->netdev; 5132 int link, tc, kb, marker; 5133 u32 dv_id, rx_pba; 5134 5135 /* Calculate max LAN frame size */ 5136 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5137 5138 #ifdef IXGBE_FCOE 5139 /* FCoE traffic class uses FCOE jumbo frames */ 5140 if ((dev->features & NETIF_F_FCOE_MTU) && 5141 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5142 (pb == ixgbe_fcoe_get_tc(adapter))) 5143 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5144 #endif 5145 5146 /* Calculate delay value for device */ 5147 switch (hw->mac.type) { 5148 case ixgbe_mac_X540: 5149 case ixgbe_mac_X550: 5150 case ixgbe_mac_X550EM_x: 5151 case ixgbe_mac_x550em_a: 5152 dv_id = IXGBE_DV_X540(link, tc); 5153 break; 5154 default: 5155 dv_id = IXGBE_DV(link, tc); 5156 break; 5157 } 5158 5159 /* Loopback switch introduces additional latency */ 5160 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5161 dv_id += IXGBE_B2BT(tc); 5162 5163 /* Delay value is calculated in bit times convert to KB */ 5164 kb = IXGBE_BT2KB(dv_id); 5165 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5166 5167 marker = rx_pba - kb; 5168 5169 /* It is possible that the packet buffer is not large enough 5170 * to provide required headroom. In this case throw an error 5171 * to user and a do the best we can. 5172 */ 5173 if (marker < 0) { 5174 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5175 "headroom to support flow control." 5176 "Decrease MTU or number of traffic classes\n", pb); 5177 marker = tc + 1; 5178 } 5179 5180 return marker; 5181 } 5182 5183 /** 5184 * ixgbe_lpbthresh - calculate low water mark for for flow control 5185 * 5186 * @adapter: board private structure to calculate for 5187 * @pb: packet buffer to calculate 5188 */ 5189 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5190 { 5191 struct ixgbe_hw *hw = &adapter->hw; 5192 struct net_device *dev = adapter->netdev; 5193 int tc; 5194 u32 dv_id; 5195 5196 /* Calculate max LAN frame size */ 5197 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5198 5199 #ifdef IXGBE_FCOE 5200 /* FCoE traffic class uses FCOE jumbo frames */ 5201 if ((dev->features & NETIF_F_FCOE_MTU) && 5202 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5203 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5204 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5205 #endif 5206 5207 /* Calculate delay value for device */ 5208 switch (hw->mac.type) { 5209 case ixgbe_mac_X540: 5210 case ixgbe_mac_X550: 5211 case ixgbe_mac_X550EM_x: 5212 case ixgbe_mac_x550em_a: 5213 dv_id = IXGBE_LOW_DV_X540(tc); 5214 break; 5215 default: 5216 dv_id = IXGBE_LOW_DV(tc); 5217 break; 5218 } 5219 5220 /* Delay value is calculated in bit times convert to KB */ 5221 return IXGBE_BT2KB(dv_id); 5222 } 5223 5224 /* 5225 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5226 */ 5227 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5228 { 5229 struct ixgbe_hw *hw = &adapter->hw; 5230 int num_tc = adapter->hw_tcs; 5231 int i; 5232 5233 if (!num_tc) 5234 num_tc = 1; 5235 5236 for (i = 0; i < num_tc; i++) { 5237 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5238 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5239 5240 /* Low water marks must not be larger than high water marks */ 5241 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5242 hw->fc.low_water[i] = 0; 5243 } 5244 5245 for (; i < MAX_TRAFFIC_CLASS; i++) 5246 hw->fc.high_water[i] = 0; 5247 } 5248 5249 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5250 { 5251 struct ixgbe_hw *hw = &adapter->hw; 5252 int hdrm; 5253 u8 tc = adapter->hw_tcs; 5254 5255 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5256 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5257 hdrm = 32 << adapter->fdir_pballoc; 5258 else 5259 hdrm = 0; 5260 5261 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5262 ixgbe_pbthresh_setup(adapter); 5263 } 5264 5265 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5266 { 5267 struct ixgbe_hw *hw = &adapter->hw; 5268 struct hlist_node *node2; 5269 struct ixgbe_fdir_filter *filter; 5270 5271 spin_lock(&adapter->fdir_perfect_lock); 5272 5273 if (!hlist_empty(&adapter->fdir_filter_list)) 5274 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5275 5276 hlist_for_each_entry_safe(filter, node2, 5277 &adapter->fdir_filter_list, fdir_node) { 5278 ixgbe_fdir_write_perfect_filter_82599(hw, 5279 &filter->filter, 5280 filter->sw_idx, 5281 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5282 IXGBE_FDIR_DROP_QUEUE : 5283 adapter->rx_ring[filter->action]->reg_idx); 5284 } 5285 5286 spin_unlock(&adapter->fdir_perfect_lock); 5287 } 5288 5289 /** 5290 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5291 * @rx_ring: ring to free buffers from 5292 **/ 5293 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5294 { 5295 u16 i = rx_ring->next_to_clean; 5296 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5297 5298 /* Free all the Rx ring sk_buffs */ 5299 while (i != rx_ring->next_to_alloc) { 5300 if (rx_buffer->skb) { 5301 struct sk_buff *skb = rx_buffer->skb; 5302 if (IXGBE_CB(skb)->page_released) 5303 dma_unmap_page_attrs(rx_ring->dev, 5304 IXGBE_CB(skb)->dma, 5305 ixgbe_rx_pg_size(rx_ring), 5306 DMA_FROM_DEVICE, 5307 IXGBE_RX_DMA_ATTR); 5308 dev_kfree_skb(skb); 5309 } 5310 5311 /* Invalidate cache lines that may have been written to by 5312 * device so that we avoid corrupting memory. 5313 */ 5314 dma_sync_single_range_for_cpu(rx_ring->dev, 5315 rx_buffer->dma, 5316 rx_buffer->page_offset, 5317 ixgbe_rx_bufsz(rx_ring), 5318 DMA_FROM_DEVICE); 5319 5320 /* free resources associated with mapping */ 5321 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5322 ixgbe_rx_pg_size(rx_ring), 5323 DMA_FROM_DEVICE, 5324 IXGBE_RX_DMA_ATTR); 5325 __page_frag_cache_drain(rx_buffer->page, 5326 rx_buffer->pagecnt_bias); 5327 5328 i++; 5329 rx_buffer++; 5330 if (i == rx_ring->count) { 5331 i = 0; 5332 rx_buffer = rx_ring->rx_buffer_info; 5333 } 5334 } 5335 5336 rx_ring->next_to_alloc = 0; 5337 rx_ring->next_to_clean = 0; 5338 rx_ring->next_to_use = 0; 5339 } 5340 5341 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5342 struct ixgbe_fwd_adapter *accel) 5343 { 5344 struct net_device *vdev = accel->netdev; 5345 int i, baseq, err; 5346 5347 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5348 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5349 accel->pool, adapter->num_rx_pools, 5350 baseq, baseq + adapter->num_rx_queues_per_pool); 5351 5352 accel->rx_base_queue = baseq; 5353 accel->tx_base_queue = baseq; 5354 5355 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5356 adapter->rx_ring[baseq + i]->netdev = vdev; 5357 5358 /* Guarantee all rings are updated before we update the 5359 * MAC address filter. 5360 */ 5361 wmb(); 5362 5363 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5364 * need to only treat it as an error value if it is negative. 5365 */ 5366 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5367 VMDQ_P(accel->pool)); 5368 if (err >= 0) 5369 return 0; 5370 5371 /* if we cannot add the MAC rule then disable the offload */ 5372 macvlan_release_l2fw_offload(vdev); 5373 5374 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5375 adapter->rx_ring[baseq + i]->netdev = NULL; 5376 5377 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5378 5379 clear_bit(accel->pool, adapter->fwd_bitmask); 5380 kfree(accel); 5381 5382 return err; 5383 } 5384 5385 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5386 { 5387 struct ixgbe_adapter *adapter = data; 5388 struct ixgbe_fwd_adapter *accel; 5389 5390 if (!netif_is_macvlan(vdev)) 5391 return 0; 5392 5393 accel = macvlan_accel_priv(vdev); 5394 if (!accel) 5395 return 0; 5396 5397 ixgbe_fwd_ring_up(adapter, accel); 5398 5399 return 0; 5400 } 5401 5402 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5403 { 5404 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5405 ixgbe_macvlan_up, adapter); 5406 } 5407 5408 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5409 { 5410 struct ixgbe_hw *hw = &adapter->hw; 5411 5412 ixgbe_configure_pb(adapter); 5413 #ifdef CONFIG_IXGBE_DCB 5414 ixgbe_configure_dcb(adapter); 5415 #endif 5416 /* 5417 * We must restore virtualization before VLANs or else 5418 * the VLVF registers will not be populated 5419 */ 5420 ixgbe_configure_virtualization(adapter); 5421 5422 ixgbe_set_rx_mode(adapter->netdev); 5423 ixgbe_restore_vlan(adapter); 5424 ixgbe_ipsec_restore(adapter); 5425 5426 switch (hw->mac.type) { 5427 case ixgbe_mac_82599EB: 5428 case ixgbe_mac_X540: 5429 hw->mac.ops.disable_rx_buff(hw); 5430 break; 5431 default: 5432 break; 5433 } 5434 5435 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5436 ixgbe_init_fdir_signature_82599(&adapter->hw, 5437 adapter->fdir_pballoc); 5438 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5439 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5440 adapter->fdir_pballoc); 5441 ixgbe_fdir_filter_restore(adapter); 5442 } 5443 5444 switch (hw->mac.type) { 5445 case ixgbe_mac_82599EB: 5446 case ixgbe_mac_X540: 5447 hw->mac.ops.enable_rx_buff(hw); 5448 break; 5449 default: 5450 break; 5451 } 5452 5453 #ifdef CONFIG_IXGBE_DCA 5454 /* configure DCA */ 5455 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5456 ixgbe_setup_dca(adapter); 5457 #endif /* CONFIG_IXGBE_DCA */ 5458 5459 #ifdef IXGBE_FCOE 5460 /* configure FCoE L2 filters, redirection table, and Rx control */ 5461 ixgbe_configure_fcoe(adapter); 5462 5463 #endif /* IXGBE_FCOE */ 5464 ixgbe_configure_tx(adapter); 5465 ixgbe_configure_rx(adapter); 5466 ixgbe_configure_dfwd(adapter); 5467 } 5468 5469 /** 5470 * ixgbe_sfp_link_config - set up SFP+ link 5471 * @adapter: pointer to private adapter struct 5472 **/ 5473 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5474 { 5475 /* 5476 * We are assuming the worst case scenario here, and that 5477 * is that an SFP was inserted/removed after the reset 5478 * but before SFP detection was enabled. As such the best 5479 * solution is to just start searching as soon as we start 5480 */ 5481 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5482 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5483 5484 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5485 adapter->sfp_poll_time = 0; 5486 } 5487 5488 /** 5489 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5490 * @hw: pointer to private hardware struct 5491 * 5492 * Returns 0 on success, negative on failure 5493 **/ 5494 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5495 { 5496 u32 speed; 5497 bool autoneg, link_up = false; 5498 int ret = IXGBE_ERR_LINK_SETUP; 5499 5500 if (hw->mac.ops.check_link) 5501 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5502 5503 if (ret) 5504 return ret; 5505 5506 speed = hw->phy.autoneg_advertised; 5507 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5508 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5509 &autoneg); 5510 if (ret) 5511 return ret; 5512 5513 if (hw->mac.ops.setup_link) 5514 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5515 5516 return ret; 5517 } 5518 5519 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5520 { 5521 struct ixgbe_hw *hw = &adapter->hw; 5522 u32 gpie = 0; 5523 5524 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5525 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5526 IXGBE_GPIE_OCD; 5527 gpie |= IXGBE_GPIE_EIAME; 5528 /* 5529 * use EIAM to auto-mask when MSI-X interrupt is asserted 5530 * this saves a register write for every interrupt 5531 */ 5532 switch (hw->mac.type) { 5533 case ixgbe_mac_82598EB: 5534 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5535 break; 5536 case ixgbe_mac_82599EB: 5537 case ixgbe_mac_X540: 5538 case ixgbe_mac_X550: 5539 case ixgbe_mac_X550EM_x: 5540 case ixgbe_mac_x550em_a: 5541 default: 5542 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5543 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5544 break; 5545 } 5546 } else { 5547 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5548 * specifically only auto mask tx and rx interrupts */ 5549 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5550 } 5551 5552 /* XXX: to interrupt immediately for EICS writes, enable this */ 5553 /* gpie |= IXGBE_GPIE_EIMEN; */ 5554 5555 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5556 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5557 5558 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5559 case IXGBE_82599_VMDQ_8Q_MASK: 5560 gpie |= IXGBE_GPIE_VTMODE_16; 5561 break; 5562 case IXGBE_82599_VMDQ_4Q_MASK: 5563 gpie |= IXGBE_GPIE_VTMODE_32; 5564 break; 5565 default: 5566 gpie |= IXGBE_GPIE_VTMODE_64; 5567 break; 5568 } 5569 } 5570 5571 /* Enable Thermal over heat sensor interrupt */ 5572 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5573 switch (adapter->hw.mac.type) { 5574 case ixgbe_mac_82599EB: 5575 gpie |= IXGBE_SDP0_GPIEN_8259X; 5576 break; 5577 default: 5578 break; 5579 } 5580 } 5581 5582 /* Enable fan failure interrupt */ 5583 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5584 gpie |= IXGBE_SDP1_GPIEN(hw); 5585 5586 switch (hw->mac.type) { 5587 case ixgbe_mac_82599EB: 5588 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5589 break; 5590 case ixgbe_mac_X550EM_x: 5591 case ixgbe_mac_x550em_a: 5592 gpie |= IXGBE_SDP0_GPIEN_X540; 5593 break; 5594 default: 5595 break; 5596 } 5597 5598 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5599 } 5600 5601 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5602 { 5603 struct ixgbe_hw *hw = &adapter->hw; 5604 int err; 5605 u32 ctrl_ext; 5606 5607 ixgbe_get_hw_control(adapter); 5608 ixgbe_setup_gpie(adapter); 5609 5610 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5611 ixgbe_configure_msix(adapter); 5612 else 5613 ixgbe_configure_msi_and_legacy(adapter); 5614 5615 /* enable the optics for 82599 SFP+ fiber */ 5616 if (hw->mac.ops.enable_tx_laser) 5617 hw->mac.ops.enable_tx_laser(hw); 5618 5619 if (hw->phy.ops.set_phy_power) 5620 hw->phy.ops.set_phy_power(hw, true); 5621 5622 smp_mb__before_atomic(); 5623 clear_bit(__IXGBE_DOWN, &adapter->state); 5624 ixgbe_napi_enable_all(adapter); 5625 5626 if (ixgbe_is_sfp(hw)) { 5627 ixgbe_sfp_link_config(adapter); 5628 } else { 5629 err = ixgbe_non_sfp_link_config(hw); 5630 if (err) 5631 e_err(probe, "link_config FAILED %d\n", err); 5632 } 5633 5634 /* clear any pending interrupts, may auto mask */ 5635 IXGBE_READ_REG(hw, IXGBE_EICR); 5636 ixgbe_irq_enable(adapter, true, true); 5637 5638 /* 5639 * If this adapter has a fan, check to see if we had a failure 5640 * before we enabled the interrupt. 5641 */ 5642 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5643 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5644 if (esdp & IXGBE_ESDP_SDP1) 5645 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5646 } 5647 5648 /* bring the link up in the watchdog, this could race with our first 5649 * link up interrupt but shouldn't be a problem */ 5650 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5651 adapter->link_check_timeout = jiffies; 5652 mod_timer(&adapter->service_timer, jiffies); 5653 5654 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5655 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5656 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5657 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5658 } 5659 5660 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5661 { 5662 WARN_ON(in_interrupt()); 5663 /* put off any impending NetWatchDogTimeout */ 5664 netif_trans_update(adapter->netdev); 5665 5666 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5667 usleep_range(1000, 2000); 5668 if (adapter->hw.phy.type == ixgbe_phy_fw) 5669 ixgbe_watchdog_link_is_down(adapter); 5670 ixgbe_down(adapter); 5671 /* 5672 * If SR-IOV enabled then wait a bit before bringing the adapter 5673 * back up to give the VFs time to respond to the reset. The 5674 * two second wait is based upon the watchdog timer cycle in 5675 * the VF driver. 5676 */ 5677 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5678 msleep(2000); 5679 ixgbe_up(adapter); 5680 clear_bit(__IXGBE_RESETTING, &adapter->state); 5681 } 5682 5683 void ixgbe_up(struct ixgbe_adapter *adapter) 5684 { 5685 /* hardware has been reset, we need to reload some things */ 5686 ixgbe_configure(adapter); 5687 5688 ixgbe_up_complete(adapter); 5689 } 5690 5691 void ixgbe_reset(struct ixgbe_adapter *adapter) 5692 { 5693 struct ixgbe_hw *hw = &adapter->hw; 5694 struct net_device *netdev = adapter->netdev; 5695 int err; 5696 5697 if (ixgbe_removed(hw->hw_addr)) 5698 return; 5699 /* lock SFP init bit to prevent race conditions with the watchdog */ 5700 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5701 usleep_range(1000, 2000); 5702 5703 /* clear all SFP and link config related flags while holding SFP_INIT */ 5704 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5705 IXGBE_FLAG2_SFP_NEEDS_RESET); 5706 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5707 5708 err = hw->mac.ops.init_hw(hw); 5709 switch (err) { 5710 case 0: 5711 case IXGBE_ERR_SFP_NOT_PRESENT: 5712 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5713 break; 5714 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5715 e_dev_err("master disable timed out\n"); 5716 break; 5717 case IXGBE_ERR_EEPROM_VERSION: 5718 /* We are running on a pre-production device, log a warning */ 5719 e_dev_warn("This device is a pre-production adapter/LOM. " 5720 "Please be aware there may be issues associated with " 5721 "your hardware. If you are experiencing problems " 5722 "please contact your Intel or hardware " 5723 "representative who provided you with this " 5724 "hardware.\n"); 5725 break; 5726 default: 5727 e_dev_err("Hardware Error: %d\n", err); 5728 } 5729 5730 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5731 5732 /* flush entries out of MAC table */ 5733 ixgbe_flush_sw_mac_table(adapter); 5734 __dev_uc_unsync(netdev, NULL); 5735 5736 /* do not flush user set addresses */ 5737 ixgbe_mac_set_default_filter(adapter); 5738 5739 /* update SAN MAC vmdq pool selection */ 5740 if (hw->mac.san_mac_rar_index) 5741 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5742 5743 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5744 ixgbe_ptp_reset(adapter); 5745 5746 if (hw->phy.ops.set_phy_power) { 5747 if (!netif_running(adapter->netdev) && !adapter->wol) 5748 hw->phy.ops.set_phy_power(hw, false); 5749 else 5750 hw->phy.ops.set_phy_power(hw, true); 5751 } 5752 } 5753 5754 /** 5755 * ixgbe_clean_tx_ring - Free Tx Buffers 5756 * @tx_ring: ring to be cleaned 5757 **/ 5758 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5759 { 5760 u16 i = tx_ring->next_to_clean; 5761 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5762 5763 while (i != tx_ring->next_to_use) { 5764 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5765 5766 /* Free all the Tx ring sk_buffs */ 5767 if (ring_is_xdp(tx_ring)) 5768 xdp_return_frame(tx_buffer->xdpf); 5769 else 5770 dev_kfree_skb_any(tx_buffer->skb); 5771 5772 /* unmap skb header data */ 5773 dma_unmap_single(tx_ring->dev, 5774 dma_unmap_addr(tx_buffer, dma), 5775 dma_unmap_len(tx_buffer, len), 5776 DMA_TO_DEVICE); 5777 5778 /* check for eop_desc to determine the end of the packet */ 5779 eop_desc = tx_buffer->next_to_watch; 5780 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5781 5782 /* unmap remaining buffers */ 5783 while (tx_desc != eop_desc) { 5784 tx_buffer++; 5785 tx_desc++; 5786 i++; 5787 if (unlikely(i == tx_ring->count)) { 5788 i = 0; 5789 tx_buffer = tx_ring->tx_buffer_info; 5790 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5791 } 5792 5793 /* unmap any remaining paged data */ 5794 if (dma_unmap_len(tx_buffer, len)) 5795 dma_unmap_page(tx_ring->dev, 5796 dma_unmap_addr(tx_buffer, dma), 5797 dma_unmap_len(tx_buffer, len), 5798 DMA_TO_DEVICE); 5799 } 5800 5801 /* move us one more past the eop_desc for start of next pkt */ 5802 tx_buffer++; 5803 i++; 5804 if (unlikely(i == tx_ring->count)) { 5805 i = 0; 5806 tx_buffer = tx_ring->tx_buffer_info; 5807 } 5808 } 5809 5810 /* reset BQL for queue */ 5811 if (!ring_is_xdp(tx_ring)) 5812 netdev_tx_reset_queue(txring_txq(tx_ring)); 5813 5814 /* reset next_to_use and next_to_clean */ 5815 tx_ring->next_to_use = 0; 5816 tx_ring->next_to_clean = 0; 5817 } 5818 5819 /** 5820 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5821 * @adapter: board private structure 5822 **/ 5823 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5824 { 5825 int i; 5826 5827 for (i = 0; i < adapter->num_rx_queues; i++) 5828 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5829 } 5830 5831 /** 5832 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5833 * @adapter: board private structure 5834 **/ 5835 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5836 { 5837 int i; 5838 5839 for (i = 0; i < adapter->num_tx_queues; i++) 5840 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5841 for (i = 0; i < adapter->num_xdp_queues; i++) 5842 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5843 } 5844 5845 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5846 { 5847 struct hlist_node *node2; 5848 struct ixgbe_fdir_filter *filter; 5849 5850 spin_lock(&adapter->fdir_perfect_lock); 5851 5852 hlist_for_each_entry_safe(filter, node2, 5853 &adapter->fdir_filter_list, fdir_node) { 5854 hlist_del(&filter->fdir_node); 5855 kfree(filter); 5856 } 5857 adapter->fdir_filter_count = 0; 5858 5859 spin_unlock(&adapter->fdir_perfect_lock); 5860 } 5861 5862 void ixgbe_down(struct ixgbe_adapter *adapter) 5863 { 5864 struct net_device *netdev = adapter->netdev; 5865 struct ixgbe_hw *hw = &adapter->hw; 5866 int i; 5867 5868 /* signal that we are down to the interrupt handler */ 5869 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5870 return; /* do nothing if already down */ 5871 5872 /* disable receives */ 5873 hw->mac.ops.disable_rx(hw); 5874 5875 /* disable all enabled rx queues */ 5876 for (i = 0; i < adapter->num_rx_queues; i++) 5877 /* this call also flushes the previous write */ 5878 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5879 5880 usleep_range(10000, 20000); 5881 5882 /* synchronize_sched() needed for pending XDP buffers to drain */ 5883 if (adapter->xdp_ring[0]) 5884 synchronize_sched(); 5885 netif_tx_stop_all_queues(netdev); 5886 5887 /* call carrier off first to avoid false dev_watchdog timeouts */ 5888 netif_carrier_off(netdev); 5889 netif_tx_disable(netdev); 5890 5891 ixgbe_irq_disable(adapter); 5892 5893 ixgbe_napi_disable_all(adapter); 5894 5895 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5896 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5897 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5898 5899 del_timer_sync(&adapter->service_timer); 5900 5901 if (adapter->num_vfs) { 5902 /* Clear EITR Select mapping */ 5903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5904 5905 /* Mark all the VFs as inactive */ 5906 for (i = 0 ; i < adapter->num_vfs; i++) 5907 adapter->vfinfo[i].clear_to_send = false; 5908 5909 /* ping all the active vfs to let them know we are going down */ 5910 ixgbe_ping_all_vfs(adapter); 5911 5912 /* Disable all VFTE/VFRE TX/RX */ 5913 ixgbe_disable_tx_rx(adapter); 5914 } 5915 5916 /* disable transmits in the hardware now that interrupts are off */ 5917 for (i = 0; i < adapter->num_tx_queues; i++) { 5918 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5919 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5920 } 5921 for (i = 0; i < adapter->num_xdp_queues; i++) { 5922 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5923 5924 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5925 } 5926 5927 /* Disable the Tx DMA engine on 82599 and later MAC */ 5928 switch (hw->mac.type) { 5929 case ixgbe_mac_82599EB: 5930 case ixgbe_mac_X540: 5931 case ixgbe_mac_X550: 5932 case ixgbe_mac_X550EM_x: 5933 case ixgbe_mac_x550em_a: 5934 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5935 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5936 ~IXGBE_DMATXCTL_TE)); 5937 break; 5938 default: 5939 break; 5940 } 5941 5942 if (!pci_channel_offline(adapter->pdev)) 5943 ixgbe_reset(adapter); 5944 5945 /* power down the optics for 82599 SFP+ fiber */ 5946 if (hw->mac.ops.disable_tx_laser) 5947 hw->mac.ops.disable_tx_laser(hw); 5948 5949 ixgbe_clean_all_tx_rings(adapter); 5950 ixgbe_clean_all_rx_rings(adapter); 5951 } 5952 5953 /** 5954 * ixgbe_eee_capable - helper function to determine EEE support on X550 5955 * @adapter: board private structure 5956 */ 5957 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5958 { 5959 struct ixgbe_hw *hw = &adapter->hw; 5960 5961 switch (hw->device_id) { 5962 case IXGBE_DEV_ID_X550EM_A_1G_T: 5963 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5964 if (!hw->phy.eee_speeds_supported) 5965 break; 5966 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5967 if (!hw->phy.eee_speeds_advertised) 5968 break; 5969 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5970 break; 5971 default: 5972 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5973 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5974 break; 5975 } 5976 } 5977 5978 /** 5979 * ixgbe_tx_timeout - Respond to a Tx Hang 5980 * @netdev: network interface device structure 5981 **/ 5982 static void ixgbe_tx_timeout(struct net_device *netdev) 5983 { 5984 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5985 5986 /* Do the reset outside of interrupt context */ 5987 ixgbe_tx_timeout_reset(adapter); 5988 } 5989 5990 #ifdef CONFIG_IXGBE_DCB 5991 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5992 { 5993 struct ixgbe_hw *hw = &adapter->hw; 5994 struct tc_configuration *tc; 5995 int j; 5996 5997 switch (hw->mac.type) { 5998 case ixgbe_mac_82598EB: 5999 case ixgbe_mac_82599EB: 6000 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6001 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6002 break; 6003 case ixgbe_mac_X540: 6004 case ixgbe_mac_X550: 6005 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6006 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6007 break; 6008 case ixgbe_mac_X550EM_x: 6009 case ixgbe_mac_x550em_a: 6010 default: 6011 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6012 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6013 break; 6014 } 6015 6016 /* Configure DCB traffic classes */ 6017 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6018 tc = &adapter->dcb_cfg.tc_config[j]; 6019 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6020 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6021 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6022 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6023 tc->dcb_pfc = pfc_disabled; 6024 } 6025 6026 /* Initialize default user to priority mapping, UPx->TC0 */ 6027 tc = &adapter->dcb_cfg.tc_config[0]; 6028 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6029 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6030 6031 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6032 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6033 adapter->dcb_cfg.pfc_mode_enable = false; 6034 adapter->dcb_set_bitmap = 0x00; 6035 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6036 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6037 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6038 sizeof(adapter->temp_dcb_cfg)); 6039 } 6040 #endif 6041 6042 /** 6043 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6044 * @adapter: board private structure to initialize 6045 * @ii: pointer to ixgbe_info for device 6046 * 6047 * ixgbe_sw_init initializes the Adapter private data structure. 6048 * Fields are initialized based on PCI device information and 6049 * OS network device settings (MTU size). 6050 **/ 6051 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6052 const struct ixgbe_info *ii) 6053 { 6054 struct ixgbe_hw *hw = &adapter->hw; 6055 struct pci_dev *pdev = adapter->pdev; 6056 unsigned int rss, fdir; 6057 u32 fwsm; 6058 int i; 6059 6060 /* PCI config space info */ 6061 6062 hw->vendor_id = pdev->vendor; 6063 hw->device_id = pdev->device; 6064 hw->revision_id = pdev->revision; 6065 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6066 hw->subsystem_device_id = pdev->subsystem_device; 6067 6068 /* get_invariants needs the device IDs */ 6069 ii->get_invariants(hw); 6070 6071 /* Set common capability flags and settings */ 6072 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6073 adapter->ring_feature[RING_F_RSS].limit = rss; 6074 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6075 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6076 adapter->atr_sample_rate = 20; 6077 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6078 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6079 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6080 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6081 #ifdef CONFIG_IXGBE_DCA 6082 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6083 #endif 6084 #ifdef CONFIG_IXGBE_DCB 6085 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6086 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6087 #endif 6088 #ifdef IXGBE_FCOE 6089 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6090 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6091 #ifdef CONFIG_IXGBE_DCB 6092 /* Default traffic class to use for FCoE */ 6093 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6094 #endif /* CONFIG_IXGBE_DCB */ 6095 #endif /* IXGBE_FCOE */ 6096 6097 /* initialize static ixgbe jump table entries */ 6098 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6099 GFP_KERNEL); 6100 if (!adapter->jump_tables[0]) 6101 return -ENOMEM; 6102 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6103 6104 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6105 adapter->jump_tables[i] = NULL; 6106 6107 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6108 hw->mac.num_rar_entries, 6109 GFP_ATOMIC); 6110 if (!adapter->mac_table) 6111 return -ENOMEM; 6112 6113 if (ixgbe_init_rss_key(adapter)) 6114 return -ENOMEM; 6115 6116 /* Set MAC specific capability flags and exceptions */ 6117 switch (hw->mac.type) { 6118 case ixgbe_mac_82598EB: 6119 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6120 6121 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6122 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6123 6124 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6125 adapter->ring_feature[RING_F_FDIR].limit = 0; 6126 adapter->atr_sample_rate = 0; 6127 adapter->fdir_pballoc = 0; 6128 #ifdef IXGBE_FCOE 6129 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6130 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6131 #ifdef CONFIG_IXGBE_DCB 6132 adapter->fcoe.up = 0; 6133 #endif /* IXGBE_DCB */ 6134 #endif /* IXGBE_FCOE */ 6135 break; 6136 case ixgbe_mac_82599EB: 6137 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6138 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6139 break; 6140 case ixgbe_mac_X540: 6141 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6142 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6143 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6144 break; 6145 case ixgbe_mac_x550em_a: 6146 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6147 switch (hw->device_id) { 6148 case IXGBE_DEV_ID_X550EM_A_1G_T: 6149 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6150 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6151 break; 6152 default: 6153 break; 6154 } 6155 /* fall through */ 6156 case ixgbe_mac_X550EM_x: 6157 #ifdef CONFIG_IXGBE_DCB 6158 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6159 #endif 6160 #ifdef IXGBE_FCOE 6161 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6162 #ifdef CONFIG_IXGBE_DCB 6163 adapter->fcoe.up = 0; 6164 #endif /* IXGBE_DCB */ 6165 #endif /* IXGBE_FCOE */ 6166 /* Fall Through */ 6167 case ixgbe_mac_X550: 6168 if (hw->mac.type == ixgbe_mac_X550) 6169 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6170 #ifdef CONFIG_IXGBE_DCA 6171 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6172 #endif 6173 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6174 break; 6175 default: 6176 break; 6177 } 6178 6179 #ifdef IXGBE_FCOE 6180 /* FCoE support exists, always init the FCoE lock */ 6181 spin_lock_init(&adapter->fcoe.lock); 6182 6183 #endif 6184 /* n-tuple support exists, always init our spinlock */ 6185 spin_lock_init(&adapter->fdir_perfect_lock); 6186 6187 #ifdef CONFIG_IXGBE_DCB 6188 ixgbe_init_dcb(adapter); 6189 #endif 6190 6191 /* default flow control settings */ 6192 hw->fc.requested_mode = ixgbe_fc_full; 6193 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6194 ixgbe_pbthresh_setup(adapter); 6195 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6196 hw->fc.send_xon = true; 6197 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6198 6199 #ifdef CONFIG_PCI_IOV 6200 if (max_vfs > 0) 6201 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6202 6203 /* assign number of SR-IOV VFs */ 6204 if (hw->mac.type != ixgbe_mac_82598EB) { 6205 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6206 max_vfs = 0; 6207 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6208 } 6209 } 6210 #endif /* CONFIG_PCI_IOV */ 6211 6212 /* enable itr by default in dynamic mode */ 6213 adapter->rx_itr_setting = 1; 6214 adapter->tx_itr_setting = 1; 6215 6216 /* set default ring sizes */ 6217 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6218 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6219 6220 /* set default work limits */ 6221 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6222 6223 /* initialize eeprom parameters */ 6224 if (ixgbe_init_eeprom_params_generic(hw)) { 6225 e_dev_err("EEPROM initialization failed\n"); 6226 return -EIO; 6227 } 6228 6229 /* PF holds first pool slot */ 6230 set_bit(0, adapter->fwd_bitmask); 6231 set_bit(__IXGBE_DOWN, &adapter->state); 6232 6233 return 0; 6234 } 6235 6236 /** 6237 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6238 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6239 * 6240 * Return 0 on success, negative on failure 6241 **/ 6242 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6243 { 6244 struct device *dev = tx_ring->dev; 6245 int orig_node = dev_to_node(dev); 6246 int ring_node = -1; 6247 int size; 6248 6249 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6250 6251 if (tx_ring->q_vector) 6252 ring_node = tx_ring->q_vector->numa_node; 6253 6254 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6255 if (!tx_ring->tx_buffer_info) 6256 tx_ring->tx_buffer_info = vmalloc(size); 6257 if (!tx_ring->tx_buffer_info) 6258 goto err; 6259 6260 /* round up to nearest 4K */ 6261 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6262 tx_ring->size = ALIGN(tx_ring->size, 4096); 6263 6264 set_dev_node(dev, ring_node); 6265 tx_ring->desc = dma_alloc_coherent(dev, 6266 tx_ring->size, 6267 &tx_ring->dma, 6268 GFP_KERNEL); 6269 set_dev_node(dev, orig_node); 6270 if (!tx_ring->desc) 6271 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6272 &tx_ring->dma, GFP_KERNEL); 6273 if (!tx_ring->desc) 6274 goto err; 6275 6276 tx_ring->next_to_use = 0; 6277 tx_ring->next_to_clean = 0; 6278 return 0; 6279 6280 err: 6281 vfree(tx_ring->tx_buffer_info); 6282 tx_ring->tx_buffer_info = NULL; 6283 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6284 return -ENOMEM; 6285 } 6286 6287 /** 6288 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6289 * @adapter: board private structure 6290 * 6291 * If this function returns with an error, then it's possible one or 6292 * more of the rings is populated (while the rest are not). It is the 6293 * callers duty to clean those orphaned rings. 6294 * 6295 * Return 0 on success, negative on failure 6296 **/ 6297 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6298 { 6299 int i, j = 0, err = 0; 6300 6301 for (i = 0; i < adapter->num_tx_queues; i++) { 6302 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6303 if (!err) 6304 continue; 6305 6306 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6307 goto err_setup_tx; 6308 } 6309 for (j = 0; j < adapter->num_xdp_queues; j++) { 6310 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6311 if (!err) 6312 continue; 6313 6314 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6315 goto err_setup_tx; 6316 } 6317 6318 return 0; 6319 err_setup_tx: 6320 /* rewind the index freeing the rings as we go */ 6321 while (j--) 6322 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6323 while (i--) 6324 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6325 return err; 6326 } 6327 6328 /** 6329 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6330 * @adapter: pointer to ixgbe_adapter 6331 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6332 * 6333 * Returns 0 on success, negative on failure 6334 **/ 6335 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6336 struct ixgbe_ring *rx_ring) 6337 { 6338 struct device *dev = rx_ring->dev; 6339 int orig_node = dev_to_node(dev); 6340 int ring_node = -1; 6341 int size, err; 6342 6343 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6344 6345 if (rx_ring->q_vector) 6346 ring_node = rx_ring->q_vector->numa_node; 6347 6348 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6349 if (!rx_ring->rx_buffer_info) 6350 rx_ring->rx_buffer_info = vmalloc(size); 6351 if (!rx_ring->rx_buffer_info) 6352 goto err; 6353 6354 /* Round up to nearest 4K */ 6355 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6356 rx_ring->size = ALIGN(rx_ring->size, 4096); 6357 6358 set_dev_node(dev, ring_node); 6359 rx_ring->desc = dma_alloc_coherent(dev, 6360 rx_ring->size, 6361 &rx_ring->dma, 6362 GFP_KERNEL); 6363 set_dev_node(dev, orig_node); 6364 if (!rx_ring->desc) 6365 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6366 &rx_ring->dma, GFP_KERNEL); 6367 if (!rx_ring->desc) 6368 goto err; 6369 6370 rx_ring->next_to_clean = 0; 6371 rx_ring->next_to_use = 0; 6372 6373 /* XDP RX-queue info */ 6374 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6375 rx_ring->queue_index) < 0) 6376 goto err; 6377 6378 err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq, 6379 MEM_TYPE_PAGE_SHARED, NULL); 6380 if (err) { 6381 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6382 goto err; 6383 } 6384 6385 rx_ring->xdp_prog = adapter->xdp_prog; 6386 6387 return 0; 6388 err: 6389 vfree(rx_ring->rx_buffer_info); 6390 rx_ring->rx_buffer_info = NULL; 6391 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6392 return -ENOMEM; 6393 } 6394 6395 /** 6396 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6397 * @adapter: board private structure 6398 * 6399 * If this function returns with an error, then it's possible one or 6400 * more of the rings is populated (while the rest are not). It is the 6401 * callers duty to clean those orphaned rings. 6402 * 6403 * Return 0 on success, negative on failure 6404 **/ 6405 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6406 { 6407 int i, err = 0; 6408 6409 for (i = 0; i < adapter->num_rx_queues; i++) { 6410 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6411 if (!err) 6412 continue; 6413 6414 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6415 goto err_setup_rx; 6416 } 6417 6418 #ifdef IXGBE_FCOE 6419 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6420 if (!err) 6421 #endif 6422 return 0; 6423 err_setup_rx: 6424 /* rewind the index freeing the rings as we go */ 6425 while (i--) 6426 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6427 return err; 6428 } 6429 6430 /** 6431 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6432 * @tx_ring: Tx descriptor ring for a specific queue 6433 * 6434 * Free all transmit software resources 6435 **/ 6436 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6437 { 6438 ixgbe_clean_tx_ring(tx_ring); 6439 6440 vfree(tx_ring->tx_buffer_info); 6441 tx_ring->tx_buffer_info = NULL; 6442 6443 /* if not set, then don't free */ 6444 if (!tx_ring->desc) 6445 return; 6446 6447 dma_free_coherent(tx_ring->dev, tx_ring->size, 6448 tx_ring->desc, tx_ring->dma); 6449 6450 tx_ring->desc = NULL; 6451 } 6452 6453 /** 6454 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6455 * @adapter: board private structure 6456 * 6457 * Free all transmit software resources 6458 **/ 6459 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6460 { 6461 int i; 6462 6463 for (i = 0; i < adapter->num_tx_queues; i++) 6464 if (adapter->tx_ring[i]->desc) 6465 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6466 for (i = 0; i < adapter->num_xdp_queues; i++) 6467 if (adapter->xdp_ring[i]->desc) 6468 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6469 } 6470 6471 /** 6472 * ixgbe_free_rx_resources - Free Rx Resources 6473 * @rx_ring: ring to clean the resources from 6474 * 6475 * Free all receive software resources 6476 **/ 6477 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6478 { 6479 ixgbe_clean_rx_ring(rx_ring); 6480 6481 rx_ring->xdp_prog = NULL; 6482 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6483 vfree(rx_ring->rx_buffer_info); 6484 rx_ring->rx_buffer_info = NULL; 6485 6486 /* if not set, then don't free */ 6487 if (!rx_ring->desc) 6488 return; 6489 6490 dma_free_coherent(rx_ring->dev, rx_ring->size, 6491 rx_ring->desc, rx_ring->dma); 6492 6493 rx_ring->desc = NULL; 6494 } 6495 6496 /** 6497 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6498 * @adapter: board private structure 6499 * 6500 * Free all receive software resources 6501 **/ 6502 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6503 { 6504 int i; 6505 6506 #ifdef IXGBE_FCOE 6507 ixgbe_free_fcoe_ddp_resources(adapter); 6508 6509 #endif 6510 for (i = 0; i < adapter->num_rx_queues; i++) 6511 if (adapter->rx_ring[i]->desc) 6512 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6513 } 6514 6515 /** 6516 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6517 * @netdev: network interface device structure 6518 * @new_mtu: new value for maximum frame size 6519 * 6520 * Returns 0 on success, negative on failure 6521 **/ 6522 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6523 { 6524 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6525 6526 /* 6527 * For 82599EB we cannot allow legacy VFs to enable their receive 6528 * paths when MTU greater than 1500 is configured. So display a 6529 * warning that legacy VFs will be disabled. 6530 */ 6531 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6532 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6533 (new_mtu > ETH_DATA_LEN)) 6534 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6535 6536 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6537 6538 /* must set new MTU before calling down or up */ 6539 netdev->mtu = new_mtu; 6540 6541 if (netif_running(netdev)) 6542 ixgbe_reinit_locked(adapter); 6543 6544 return 0; 6545 } 6546 6547 /** 6548 * ixgbe_open - Called when a network interface is made active 6549 * @netdev: network interface device structure 6550 * 6551 * Returns 0 on success, negative value on failure 6552 * 6553 * The open entry point is called when a network interface is made 6554 * active by the system (IFF_UP). At this point all resources needed 6555 * for transmit and receive operations are allocated, the interrupt 6556 * handler is registered with the OS, the watchdog timer is started, 6557 * and the stack is notified that the interface is ready. 6558 **/ 6559 int ixgbe_open(struct net_device *netdev) 6560 { 6561 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6562 struct ixgbe_hw *hw = &adapter->hw; 6563 int err, queues; 6564 6565 /* disallow open during test */ 6566 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6567 return -EBUSY; 6568 6569 netif_carrier_off(netdev); 6570 6571 /* allocate transmit descriptors */ 6572 err = ixgbe_setup_all_tx_resources(adapter); 6573 if (err) 6574 goto err_setup_tx; 6575 6576 /* allocate receive descriptors */ 6577 err = ixgbe_setup_all_rx_resources(adapter); 6578 if (err) 6579 goto err_setup_rx; 6580 6581 ixgbe_configure(adapter); 6582 6583 err = ixgbe_request_irq(adapter); 6584 if (err) 6585 goto err_req_irq; 6586 6587 /* Notify the stack of the actual queue counts. */ 6588 queues = adapter->num_tx_queues; 6589 err = netif_set_real_num_tx_queues(netdev, queues); 6590 if (err) 6591 goto err_set_queues; 6592 6593 queues = adapter->num_rx_queues; 6594 err = netif_set_real_num_rx_queues(netdev, queues); 6595 if (err) 6596 goto err_set_queues; 6597 6598 ixgbe_ptp_init(adapter); 6599 6600 ixgbe_up_complete(adapter); 6601 6602 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6603 udp_tunnel_get_rx_info(netdev); 6604 6605 return 0; 6606 6607 err_set_queues: 6608 ixgbe_free_irq(adapter); 6609 err_req_irq: 6610 ixgbe_free_all_rx_resources(adapter); 6611 if (hw->phy.ops.set_phy_power && !adapter->wol) 6612 hw->phy.ops.set_phy_power(&adapter->hw, false); 6613 err_setup_rx: 6614 ixgbe_free_all_tx_resources(adapter); 6615 err_setup_tx: 6616 ixgbe_reset(adapter); 6617 6618 return err; 6619 } 6620 6621 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6622 { 6623 ixgbe_ptp_suspend(adapter); 6624 6625 if (adapter->hw.phy.ops.enter_lplu) { 6626 adapter->hw.phy.reset_disable = true; 6627 ixgbe_down(adapter); 6628 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6629 adapter->hw.phy.reset_disable = false; 6630 } else { 6631 ixgbe_down(adapter); 6632 } 6633 6634 ixgbe_free_irq(adapter); 6635 6636 ixgbe_free_all_tx_resources(adapter); 6637 ixgbe_free_all_rx_resources(adapter); 6638 } 6639 6640 /** 6641 * ixgbe_close - Disables a network interface 6642 * @netdev: network interface device structure 6643 * 6644 * Returns 0, this is not allowed to fail 6645 * 6646 * The close entry point is called when an interface is de-activated 6647 * by the OS. The hardware is still under the drivers control, but 6648 * needs to be disabled. A global MAC reset is issued to stop the 6649 * hardware, and all transmit and receive resources are freed. 6650 **/ 6651 int ixgbe_close(struct net_device *netdev) 6652 { 6653 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6654 6655 ixgbe_ptp_stop(adapter); 6656 6657 if (netif_device_present(netdev)) 6658 ixgbe_close_suspend(adapter); 6659 6660 ixgbe_fdir_filter_exit(adapter); 6661 6662 ixgbe_release_hw_control(adapter); 6663 6664 return 0; 6665 } 6666 6667 #ifdef CONFIG_PM 6668 static int ixgbe_resume(struct pci_dev *pdev) 6669 { 6670 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6671 struct net_device *netdev = adapter->netdev; 6672 u32 err; 6673 6674 adapter->hw.hw_addr = adapter->io_addr; 6675 pci_set_power_state(pdev, PCI_D0); 6676 pci_restore_state(pdev); 6677 /* 6678 * pci_restore_state clears dev->state_saved so call 6679 * pci_save_state to restore it. 6680 */ 6681 pci_save_state(pdev); 6682 6683 err = pci_enable_device_mem(pdev); 6684 if (err) { 6685 e_dev_err("Cannot enable PCI device from suspend\n"); 6686 return err; 6687 } 6688 smp_mb__before_atomic(); 6689 clear_bit(__IXGBE_DISABLED, &adapter->state); 6690 pci_set_master(pdev); 6691 6692 pci_wake_from_d3(pdev, false); 6693 6694 ixgbe_reset(adapter); 6695 6696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6697 6698 rtnl_lock(); 6699 err = ixgbe_init_interrupt_scheme(adapter); 6700 if (!err && netif_running(netdev)) 6701 err = ixgbe_open(netdev); 6702 6703 6704 if (!err) 6705 netif_device_attach(netdev); 6706 rtnl_unlock(); 6707 6708 return err; 6709 } 6710 #endif /* CONFIG_PM */ 6711 6712 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6713 { 6714 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6715 struct net_device *netdev = adapter->netdev; 6716 struct ixgbe_hw *hw = &adapter->hw; 6717 u32 ctrl; 6718 u32 wufc = adapter->wol; 6719 #ifdef CONFIG_PM 6720 int retval = 0; 6721 #endif 6722 6723 rtnl_lock(); 6724 netif_device_detach(netdev); 6725 6726 if (netif_running(netdev)) 6727 ixgbe_close_suspend(adapter); 6728 6729 ixgbe_clear_interrupt_scheme(adapter); 6730 rtnl_unlock(); 6731 6732 #ifdef CONFIG_PM 6733 retval = pci_save_state(pdev); 6734 if (retval) 6735 return retval; 6736 6737 #endif 6738 if (hw->mac.ops.stop_link_on_d3) 6739 hw->mac.ops.stop_link_on_d3(hw); 6740 6741 if (wufc) { 6742 u32 fctrl; 6743 6744 ixgbe_set_rx_mode(netdev); 6745 6746 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6747 if (hw->mac.ops.enable_tx_laser) 6748 hw->mac.ops.enable_tx_laser(hw); 6749 6750 /* enable the reception of multicast packets */ 6751 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6752 fctrl |= IXGBE_FCTRL_MPE; 6753 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6754 6755 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6756 ctrl |= IXGBE_CTRL_GIO_DIS; 6757 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6758 6759 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6760 } else { 6761 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6762 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6763 } 6764 6765 switch (hw->mac.type) { 6766 case ixgbe_mac_82598EB: 6767 pci_wake_from_d3(pdev, false); 6768 break; 6769 case ixgbe_mac_82599EB: 6770 case ixgbe_mac_X540: 6771 case ixgbe_mac_X550: 6772 case ixgbe_mac_X550EM_x: 6773 case ixgbe_mac_x550em_a: 6774 pci_wake_from_d3(pdev, !!wufc); 6775 break; 6776 default: 6777 break; 6778 } 6779 6780 *enable_wake = !!wufc; 6781 if (hw->phy.ops.set_phy_power && !*enable_wake) 6782 hw->phy.ops.set_phy_power(hw, false); 6783 6784 ixgbe_release_hw_control(adapter); 6785 6786 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6787 pci_disable_device(pdev); 6788 6789 return 0; 6790 } 6791 6792 #ifdef CONFIG_PM 6793 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6794 { 6795 int retval; 6796 bool wake; 6797 6798 retval = __ixgbe_shutdown(pdev, &wake); 6799 if (retval) 6800 return retval; 6801 6802 if (wake) { 6803 pci_prepare_to_sleep(pdev); 6804 } else { 6805 pci_wake_from_d3(pdev, false); 6806 pci_set_power_state(pdev, PCI_D3hot); 6807 } 6808 6809 return 0; 6810 } 6811 #endif /* CONFIG_PM */ 6812 6813 static void ixgbe_shutdown(struct pci_dev *pdev) 6814 { 6815 bool wake; 6816 6817 __ixgbe_shutdown(pdev, &wake); 6818 6819 if (system_state == SYSTEM_POWER_OFF) { 6820 pci_wake_from_d3(pdev, wake); 6821 pci_set_power_state(pdev, PCI_D3hot); 6822 } 6823 } 6824 6825 /** 6826 * ixgbe_update_stats - Update the board statistics counters. 6827 * @adapter: board private structure 6828 **/ 6829 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6830 { 6831 struct net_device *netdev = adapter->netdev; 6832 struct ixgbe_hw *hw = &adapter->hw; 6833 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6834 u64 total_mpc = 0; 6835 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6836 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6837 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6838 u64 alloc_rx_page = 0; 6839 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6840 6841 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6842 test_bit(__IXGBE_RESETTING, &adapter->state)) 6843 return; 6844 6845 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6846 u64 rsc_count = 0; 6847 u64 rsc_flush = 0; 6848 for (i = 0; i < adapter->num_rx_queues; i++) { 6849 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6850 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6851 } 6852 adapter->rsc_total_count = rsc_count; 6853 adapter->rsc_total_flush = rsc_flush; 6854 } 6855 6856 for (i = 0; i < adapter->num_rx_queues; i++) { 6857 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6858 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6859 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6860 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6861 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6862 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6863 bytes += rx_ring->stats.bytes; 6864 packets += rx_ring->stats.packets; 6865 } 6866 adapter->non_eop_descs = non_eop_descs; 6867 adapter->alloc_rx_page = alloc_rx_page; 6868 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6869 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6870 adapter->hw_csum_rx_error = hw_csum_rx_error; 6871 netdev->stats.rx_bytes = bytes; 6872 netdev->stats.rx_packets = packets; 6873 6874 bytes = 0; 6875 packets = 0; 6876 /* gather some stats to the adapter struct that are per queue */ 6877 for (i = 0; i < adapter->num_tx_queues; i++) { 6878 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6879 restart_queue += tx_ring->tx_stats.restart_queue; 6880 tx_busy += tx_ring->tx_stats.tx_busy; 6881 bytes += tx_ring->stats.bytes; 6882 packets += tx_ring->stats.packets; 6883 } 6884 for (i = 0; i < adapter->num_xdp_queues; i++) { 6885 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6886 6887 restart_queue += xdp_ring->tx_stats.restart_queue; 6888 tx_busy += xdp_ring->tx_stats.tx_busy; 6889 bytes += xdp_ring->stats.bytes; 6890 packets += xdp_ring->stats.packets; 6891 } 6892 adapter->restart_queue = restart_queue; 6893 adapter->tx_busy = tx_busy; 6894 netdev->stats.tx_bytes = bytes; 6895 netdev->stats.tx_packets = packets; 6896 6897 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6898 6899 /* 8 register reads */ 6900 for (i = 0; i < 8; i++) { 6901 /* for packet buffers not used, the register should read 0 */ 6902 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6903 missed_rx += mpc; 6904 hwstats->mpc[i] += mpc; 6905 total_mpc += hwstats->mpc[i]; 6906 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6907 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6908 switch (hw->mac.type) { 6909 case ixgbe_mac_82598EB: 6910 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6911 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6912 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6913 hwstats->pxonrxc[i] += 6914 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6915 break; 6916 case ixgbe_mac_82599EB: 6917 case ixgbe_mac_X540: 6918 case ixgbe_mac_X550: 6919 case ixgbe_mac_X550EM_x: 6920 case ixgbe_mac_x550em_a: 6921 hwstats->pxonrxc[i] += 6922 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6923 break; 6924 default: 6925 break; 6926 } 6927 } 6928 6929 /*16 register reads */ 6930 for (i = 0; i < 16; i++) { 6931 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6932 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6933 if ((hw->mac.type == ixgbe_mac_82599EB) || 6934 (hw->mac.type == ixgbe_mac_X540) || 6935 (hw->mac.type == ixgbe_mac_X550) || 6936 (hw->mac.type == ixgbe_mac_X550EM_x) || 6937 (hw->mac.type == ixgbe_mac_x550em_a)) { 6938 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6939 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6940 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6941 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6942 } 6943 } 6944 6945 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6946 /* work around hardware counting issue */ 6947 hwstats->gprc -= missed_rx; 6948 6949 ixgbe_update_xoff_received(adapter); 6950 6951 /* 82598 hardware only has a 32 bit counter in the high register */ 6952 switch (hw->mac.type) { 6953 case ixgbe_mac_82598EB: 6954 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6955 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6956 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6957 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6958 break; 6959 case ixgbe_mac_X540: 6960 case ixgbe_mac_X550: 6961 case ixgbe_mac_X550EM_x: 6962 case ixgbe_mac_x550em_a: 6963 /* OS2BMC stats are X540 and later */ 6964 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6965 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6966 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6967 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6968 /* fall through */ 6969 case ixgbe_mac_82599EB: 6970 for (i = 0; i < 16; i++) 6971 adapter->hw_rx_no_dma_resources += 6972 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6973 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6974 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6975 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6976 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6977 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6978 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6979 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6980 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6981 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6982 #ifdef IXGBE_FCOE 6983 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6984 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6985 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6986 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6987 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6988 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6989 /* Add up per cpu counters for total ddp aloc fail */ 6990 if (adapter->fcoe.ddp_pool) { 6991 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6992 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6993 unsigned int cpu; 6994 u64 noddp = 0, noddp_ext_buff = 0; 6995 for_each_possible_cpu(cpu) { 6996 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6997 noddp += ddp_pool->noddp; 6998 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6999 } 7000 hwstats->fcoe_noddp = noddp; 7001 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7002 } 7003 #endif /* IXGBE_FCOE */ 7004 break; 7005 default: 7006 break; 7007 } 7008 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7009 hwstats->bprc += bprc; 7010 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7011 if (hw->mac.type == ixgbe_mac_82598EB) 7012 hwstats->mprc -= bprc; 7013 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7014 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7015 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7016 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7017 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7018 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7019 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7020 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7021 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7022 hwstats->lxontxc += lxon; 7023 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7024 hwstats->lxofftxc += lxoff; 7025 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7026 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7027 /* 7028 * 82598 errata - tx of flow control packets is included in tx counters 7029 */ 7030 xon_off_tot = lxon + lxoff; 7031 hwstats->gptc -= xon_off_tot; 7032 hwstats->mptc -= xon_off_tot; 7033 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7034 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7035 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7036 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7037 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7038 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7039 hwstats->ptc64 -= xon_off_tot; 7040 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7041 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7042 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7043 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7044 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7045 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7046 7047 /* Fill out the OS statistics structure */ 7048 netdev->stats.multicast = hwstats->mprc; 7049 7050 /* Rx Errors */ 7051 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7052 netdev->stats.rx_dropped = 0; 7053 netdev->stats.rx_length_errors = hwstats->rlec; 7054 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7055 netdev->stats.rx_missed_errors = total_mpc; 7056 } 7057 7058 /** 7059 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7060 * @adapter: pointer to the device adapter structure 7061 **/ 7062 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7063 { 7064 struct ixgbe_hw *hw = &adapter->hw; 7065 int i; 7066 7067 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7068 return; 7069 7070 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7071 7072 /* if interface is down do nothing */ 7073 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7074 return; 7075 7076 /* do nothing if we are not using signature filters */ 7077 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7078 return; 7079 7080 adapter->fdir_overflow++; 7081 7082 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7083 for (i = 0; i < adapter->num_tx_queues; i++) 7084 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7085 &(adapter->tx_ring[i]->state)); 7086 for (i = 0; i < adapter->num_xdp_queues; i++) 7087 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7088 &adapter->xdp_ring[i]->state); 7089 /* re-enable flow director interrupts */ 7090 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7091 } else { 7092 e_err(probe, "failed to finish FDIR re-initialization, " 7093 "ignored adding FDIR ATR filters\n"); 7094 } 7095 } 7096 7097 /** 7098 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7099 * @adapter: pointer to the device adapter structure 7100 * 7101 * This function serves two purposes. First it strobes the interrupt lines 7102 * in order to make certain interrupts are occurring. Secondly it sets the 7103 * bits needed to check for TX hangs. As a result we should immediately 7104 * determine if a hang has occurred. 7105 */ 7106 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7107 { 7108 struct ixgbe_hw *hw = &adapter->hw; 7109 u64 eics = 0; 7110 int i; 7111 7112 /* If we're down, removing or resetting, just bail */ 7113 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7114 test_bit(__IXGBE_REMOVING, &adapter->state) || 7115 test_bit(__IXGBE_RESETTING, &adapter->state)) 7116 return; 7117 7118 /* Force detection of hung controller */ 7119 if (netif_carrier_ok(adapter->netdev)) { 7120 for (i = 0; i < adapter->num_tx_queues; i++) 7121 set_check_for_tx_hang(adapter->tx_ring[i]); 7122 for (i = 0; i < adapter->num_xdp_queues; i++) 7123 set_check_for_tx_hang(adapter->xdp_ring[i]); 7124 } 7125 7126 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7127 /* 7128 * for legacy and MSI interrupts don't set any bits 7129 * that are enabled for EIAM, because this operation 7130 * would set *both* EIMS and EICS for any bit in EIAM 7131 */ 7132 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7133 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7134 } else { 7135 /* get one bit for every active tx/rx interrupt vector */ 7136 for (i = 0; i < adapter->num_q_vectors; i++) { 7137 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7138 if (qv->rx.ring || qv->tx.ring) 7139 eics |= BIT_ULL(i); 7140 } 7141 } 7142 7143 /* Cause software interrupt to ensure rings are cleaned */ 7144 ixgbe_irq_rearm_queues(adapter, eics); 7145 } 7146 7147 /** 7148 * ixgbe_watchdog_update_link - update the link status 7149 * @adapter: pointer to the device adapter structure 7150 **/ 7151 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7152 { 7153 struct ixgbe_hw *hw = &adapter->hw; 7154 u32 link_speed = adapter->link_speed; 7155 bool link_up = adapter->link_up; 7156 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7157 7158 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7159 return; 7160 7161 if (hw->mac.ops.check_link) { 7162 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7163 } else { 7164 /* always assume link is up, if no check link function */ 7165 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7166 link_up = true; 7167 } 7168 7169 if (adapter->ixgbe_ieee_pfc) 7170 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7171 7172 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7173 hw->mac.ops.fc_enable(hw); 7174 ixgbe_set_rx_drop_en(adapter); 7175 } 7176 7177 if (link_up || 7178 time_after(jiffies, (adapter->link_check_timeout + 7179 IXGBE_TRY_LINK_TIMEOUT))) { 7180 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7181 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7182 IXGBE_WRITE_FLUSH(hw); 7183 } 7184 7185 adapter->link_up = link_up; 7186 adapter->link_speed = link_speed; 7187 } 7188 7189 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7190 { 7191 #ifdef CONFIG_IXGBE_DCB 7192 struct net_device *netdev = adapter->netdev; 7193 struct dcb_app app = { 7194 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7195 .protocol = 0, 7196 }; 7197 u8 up = 0; 7198 7199 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7200 up = dcb_ieee_getapp_mask(netdev, &app); 7201 7202 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7203 #endif 7204 } 7205 7206 /** 7207 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7208 * print link up message 7209 * @adapter: pointer to the device adapter structure 7210 **/ 7211 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7212 { 7213 struct net_device *netdev = adapter->netdev; 7214 struct ixgbe_hw *hw = &adapter->hw; 7215 u32 link_speed = adapter->link_speed; 7216 const char *speed_str; 7217 bool flow_rx, flow_tx; 7218 7219 /* only continue if link was previously down */ 7220 if (netif_carrier_ok(netdev)) 7221 return; 7222 7223 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7224 7225 switch (hw->mac.type) { 7226 case ixgbe_mac_82598EB: { 7227 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7228 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7229 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7230 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7231 } 7232 break; 7233 case ixgbe_mac_X540: 7234 case ixgbe_mac_X550: 7235 case ixgbe_mac_X550EM_x: 7236 case ixgbe_mac_x550em_a: 7237 case ixgbe_mac_82599EB: { 7238 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7239 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7240 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7241 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7242 } 7243 break; 7244 default: 7245 flow_tx = false; 7246 flow_rx = false; 7247 break; 7248 } 7249 7250 adapter->last_rx_ptp_check = jiffies; 7251 7252 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7253 ixgbe_ptp_start_cyclecounter(adapter); 7254 7255 switch (link_speed) { 7256 case IXGBE_LINK_SPEED_10GB_FULL: 7257 speed_str = "10 Gbps"; 7258 break; 7259 case IXGBE_LINK_SPEED_5GB_FULL: 7260 speed_str = "5 Gbps"; 7261 break; 7262 case IXGBE_LINK_SPEED_2_5GB_FULL: 7263 speed_str = "2.5 Gbps"; 7264 break; 7265 case IXGBE_LINK_SPEED_1GB_FULL: 7266 speed_str = "1 Gbps"; 7267 break; 7268 case IXGBE_LINK_SPEED_100_FULL: 7269 speed_str = "100 Mbps"; 7270 break; 7271 case IXGBE_LINK_SPEED_10_FULL: 7272 speed_str = "10 Mbps"; 7273 break; 7274 default: 7275 speed_str = "unknown speed"; 7276 break; 7277 } 7278 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7279 ((flow_rx && flow_tx) ? "RX/TX" : 7280 (flow_rx ? "RX" : 7281 (flow_tx ? "TX" : "None")))); 7282 7283 netif_carrier_on(netdev); 7284 ixgbe_check_vf_rate_limit(adapter); 7285 7286 /* enable transmits */ 7287 netif_tx_wake_all_queues(adapter->netdev); 7288 7289 /* update the default user priority for VFs */ 7290 ixgbe_update_default_up(adapter); 7291 7292 /* ping all the active vfs to let them know link has changed */ 7293 ixgbe_ping_all_vfs(adapter); 7294 } 7295 7296 /** 7297 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7298 * print link down message 7299 * @adapter: pointer to the adapter structure 7300 **/ 7301 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7302 { 7303 struct net_device *netdev = adapter->netdev; 7304 struct ixgbe_hw *hw = &adapter->hw; 7305 7306 adapter->link_up = false; 7307 adapter->link_speed = 0; 7308 7309 /* only continue if link was up previously */ 7310 if (!netif_carrier_ok(netdev)) 7311 return; 7312 7313 /* poll for SFP+ cable when link is down */ 7314 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7315 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7316 7317 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7318 ixgbe_ptp_start_cyclecounter(adapter); 7319 7320 e_info(drv, "NIC Link is Down\n"); 7321 netif_carrier_off(netdev); 7322 7323 /* ping all the active vfs to let them know link has changed */ 7324 ixgbe_ping_all_vfs(adapter); 7325 } 7326 7327 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7328 { 7329 int i; 7330 7331 for (i = 0; i < adapter->num_tx_queues; i++) { 7332 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7333 7334 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7335 return true; 7336 } 7337 7338 for (i = 0; i < adapter->num_xdp_queues; i++) { 7339 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7340 7341 if (ring->next_to_use != ring->next_to_clean) 7342 return true; 7343 } 7344 7345 return false; 7346 } 7347 7348 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7349 { 7350 struct ixgbe_hw *hw = &adapter->hw; 7351 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7352 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7353 7354 int i, j; 7355 7356 if (!adapter->num_vfs) 7357 return false; 7358 7359 /* resetting the PF is only needed for MAC before X550 */ 7360 if (hw->mac.type >= ixgbe_mac_X550) 7361 return false; 7362 7363 for (i = 0; i < adapter->num_vfs; i++) { 7364 for (j = 0; j < q_per_pool; j++) { 7365 u32 h, t; 7366 7367 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7368 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7369 7370 if (h != t) 7371 return true; 7372 } 7373 } 7374 7375 return false; 7376 } 7377 7378 /** 7379 * ixgbe_watchdog_flush_tx - flush queues on link down 7380 * @adapter: pointer to the device adapter structure 7381 **/ 7382 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7383 { 7384 if (!netif_carrier_ok(adapter->netdev)) { 7385 if (ixgbe_ring_tx_pending(adapter) || 7386 ixgbe_vf_tx_pending(adapter)) { 7387 /* We've lost link, so the controller stops DMA, 7388 * but we've got queued Tx work that's never going 7389 * to get done, so reset controller to flush Tx. 7390 * (Do the reset outside of interrupt context). 7391 */ 7392 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7393 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7394 } 7395 } 7396 } 7397 7398 #ifdef CONFIG_PCI_IOV 7399 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7400 { 7401 struct ixgbe_hw *hw = &adapter->hw; 7402 struct pci_dev *pdev = adapter->pdev; 7403 unsigned int vf; 7404 u32 gpc; 7405 7406 if (!(netif_carrier_ok(adapter->netdev))) 7407 return; 7408 7409 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7410 if (gpc) /* If incrementing then no need for the check below */ 7411 return; 7412 /* Check to see if a bad DMA write target from an errant or 7413 * malicious VF has caused a PCIe error. If so then we can 7414 * issue a VFLR to the offending VF(s) and then resume without 7415 * requesting a full slot reset. 7416 */ 7417 7418 if (!pdev) 7419 return; 7420 7421 /* check status reg for all VFs owned by this PF */ 7422 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7423 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7424 u16 status_reg; 7425 7426 if (!vfdev) 7427 continue; 7428 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7429 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7430 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7431 pcie_flr(vfdev); 7432 } 7433 } 7434 7435 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7436 { 7437 u32 ssvpc; 7438 7439 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7440 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7441 adapter->num_vfs == 0) 7442 return; 7443 7444 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7445 7446 /* 7447 * ssvpc register is cleared on read, if zero then no 7448 * spoofed packets in the last interval. 7449 */ 7450 if (!ssvpc) 7451 return; 7452 7453 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7454 } 7455 #else 7456 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7457 { 7458 } 7459 7460 static void 7461 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7462 { 7463 } 7464 #endif /* CONFIG_PCI_IOV */ 7465 7466 7467 /** 7468 * ixgbe_watchdog_subtask - check and bring link up 7469 * @adapter: pointer to the device adapter structure 7470 **/ 7471 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7472 { 7473 /* if interface is down, removing or resetting, do nothing */ 7474 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7475 test_bit(__IXGBE_REMOVING, &adapter->state) || 7476 test_bit(__IXGBE_RESETTING, &adapter->state)) 7477 return; 7478 7479 ixgbe_watchdog_update_link(adapter); 7480 7481 if (adapter->link_up) 7482 ixgbe_watchdog_link_is_up(adapter); 7483 else 7484 ixgbe_watchdog_link_is_down(adapter); 7485 7486 ixgbe_check_for_bad_vf(adapter); 7487 ixgbe_spoof_check(adapter); 7488 ixgbe_update_stats(adapter); 7489 7490 ixgbe_watchdog_flush_tx(adapter); 7491 } 7492 7493 /** 7494 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7495 * @adapter: the ixgbe adapter structure 7496 **/ 7497 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7498 { 7499 struct ixgbe_hw *hw = &adapter->hw; 7500 s32 err; 7501 7502 /* not searching for SFP so there is nothing to do here */ 7503 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7504 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7505 return; 7506 7507 if (adapter->sfp_poll_time && 7508 time_after(adapter->sfp_poll_time, jiffies)) 7509 return; /* If not yet time to poll for SFP */ 7510 7511 /* someone else is in init, wait until next service event */ 7512 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7513 return; 7514 7515 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7516 7517 err = hw->phy.ops.identify_sfp(hw); 7518 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7519 goto sfp_out; 7520 7521 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7522 /* If no cable is present, then we need to reset 7523 * the next time we find a good cable. */ 7524 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7525 } 7526 7527 /* exit on error */ 7528 if (err) 7529 goto sfp_out; 7530 7531 /* exit if reset not needed */ 7532 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7533 goto sfp_out; 7534 7535 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7536 7537 /* 7538 * A module may be identified correctly, but the EEPROM may not have 7539 * support for that module. setup_sfp() will fail in that case, so 7540 * we should not allow that module to load. 7541 */ 7542 if (hw->mac.type == ixgbe_mac_82598EB) 7543 err = hw->phy.ops.reset(hw); 7544 else 7545 err = hw->mac.ops.setup_sfp(hw); 7546 7547 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7548 goto sfp_out; 7549 7550 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7551 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7552 7553 sfp_out: 7554 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7555 7556 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7557 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7558 e_dev_err("failed to initialize because an unsupported " 7559 "SFP+ module type was detected.\n"); 7560 e_dev_err("Reload the driver after installing a " 7561 "supported module.\n"); 7562 unregister_netdev(adapter->netdev); 7563 } 7564 } 7565 7566 /** 7567 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7568 * @adapter: the ixgbe adapter structure 7569 **/ 7570 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7571 { 7572 struct ixgbe_hw *hw = &adapter->hw; 7573 u32 cap_speed; 7574 u32 speed; 7575 bool autoneg = false; 7576 7577 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7578 return; 7579 7580 /* someone else is in init, wait until next service event */ 7581 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7582 return; 7583 7584 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7585 7586 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7587 7588 /* advertise highest capable link speed */ 7589 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7590 speed = IXGBE_LINK_SPEED_10GB_FULL; 7591 else 7592 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7593 IXGBE_LINK_SPEED_1GB_FULL); 7594 7595 if (hw->mac.ops.setup_link) 7596 hw->mac.ops.setup_link(hw, speed, true); 7597 7598 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7599 adapter->link_check_timeout = jiffies; 7600 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7601 } 7602 7603 /** 7604 * ixgbe_service_timer - Timer Call-back 7605 * @t: pointer to timer_list structure 7606 **/ 7607 static void ixgbe_service_timer(struct timer_list *t) 7608 { 7609 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7610 unsigned long next_event_offset; 7611 7612 /* poll faster when waiting for link */ 7613 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7614 next_event_offset = HZ / 10; 7615 else 7616 next_event_offset = HZ * 2; 7617 7618 /* Reset the timer */ 7619 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7620 7621 ixgbe_service_event_schedule(adapter); 7622 } 7623 7624 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7625 { 7626 struct ixgbe_hw *hw = &adapter->hw; 7627 u32 status; 7628 7629 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7630 return; 7631 7632 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7633 7634 if (!hw->phy.ops.handle_lasi) 7635 return; 7636 7637 status = hw->phy.ops.handle_lasi(&adapter->hw); 7638 if (status != IXGBE_ERR_OVERTEMP) 7639 return; 7640 7641 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7642 } 7643 7644 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7645 { 7646 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7647 return; 7648 7649 /* If we're already down, removing or resetting, just bail */ 7650 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7651 test_bit(__IXGBE_REMOVING, &adapter->state) || 7652 test_bit(__IXGBE_RESETTING, &adapter->state)) 7653 return; 7654 7655 ixgbe_dump(adapter); 7656 netdev_err(adapter->netdev, "Reset adapter\n"); 7657 adapter->tx_timeout_count++; 7658 7659 rtnl_lock(); 7660 ixgbe_reinit_locked(adapter); 7661 rtnl_unlock(); 7662 } 7663 7664 /** 7665 * ixgbe_service_task - manages and runs subtasks 7666 * @work: pointer to work_struct containing our data 7667 **/ 7668 static void ixgbe_service_task(struct work_struct *work) 7669 { 7670 struct ixgbe_adapter *adapter = container_of(work, 7671 struct ixgbe_adapter, 7672 service_task); 7673 if (ixgbe_removed(adapter->hw.hw_addr)) { 7674 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7675 rtnl_lock(); 7676 ixgbe_down(adapter); 7677 rtnl_unlock(); 7678 } 7679 ixgbe_service_event_complete(adapter); 7680 return; 7681 } 7682 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7683 rtnl_lock(); 7684 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7685 udp_tunnel_get_rx_info(adapter->netdev); 7686 rtnl_unlock(); 7687 } 7688 ixgbe_reset_subtask(adapter); 7689 ixgbe_phy_interrupt_subtask(adapter); 7690 ixgbe_sfp_detection_subtask(adapter); 7691 ixgbe_sfp_link_config_subtask(adapter); 7692 ixgbe_check_overtemp_subtask(adapter); 7693 ixgbe_watchdog_subtask(adapter); 7694 ixgbe_fdir_reinit_subtask(adapter); 7695 ixgbe_check_hang_subtask(adapter); 7696 7697 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7698 ixgbe_ptp_overflow_check(adapter); 7699 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7700 ixgbe_ptp_rx_hang(adapter); 7701 ixgbe_ptp_tx_hang(adapter); 7702 } 7703 7704 ixgbe_service_event_complete(adapter); 7705 } 7706 7707 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7708 struct ixgbe_tx_buffer *first, 7709 u8 *hdr_len, 7710 struct ixgbe_ipsec_tx_data *itd) 7711 { 7712 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7713 struct sk_buff *skb = first->skb; 7714 union { 7715 struct iphdr *v4; 7716 struct ipv6hdr *v6; 7717 unsigned char *hdr; 7718 } ip; 7719 union { 7720 struct tcphdr *tcp; 7721 unsigned char *hdr; 7722 } l4; 7723 u32 paylen, l4_offset; 7724 u32 fceof_saidx = 0; 7725 int err; 7726 7727 if (skb->ip_summed != CHECKSUM_PARTIAL) 7728 return 0; 7729 7730 if (!skb_is_gso(skb)) 7731 return 0; 7732 7733 err = skb_cow_head(skb, 0); 7734 if (err < 0) 7735 return err; 7736 7737 if (eth_p_mpls(first->protocol)) 7738 ip.hdr = skb_inner_network_header(skb); 7739 else 7740 ip.hdr = skb_network_header(skb); 7741 l4.hdr = skb_checksum_start(skb); 7742 7743 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7744 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7745 7746 /* initialize outer IP header fields */ 7747 if (ip.v4->version == 4) { 7748 unsigned char *csum_start = skb_checksum_start(skb); 7749 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7750 int len = csum_start - trans_start; 7751 7752 /* IP header will have to cancel out any data that 7753 * is not a part of the outer IP header, so set to 7754 * a reverse csum if needed, else init check to 0. 7755 */ 7756 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7757 csum_fold(csum_partial(trans_start, 7758 len, 0)) : 0; 7759 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7760 7761 ip.v4->tot_len = 0; 7762 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7763 IXGBE_TX_FLAGS_CSUM | 7764 IXGBE_TX_FLAGS_IPV4; 7765 } else { 7766 ip.v6->payload_len = 0; 7767 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7768 IXGBE_TX_FLAGS_CSUM; 7769 } 7770 7771 /* determine offset of inner transport header */ 7772 l4_offset = l4.hdr - skb->data; 7773 7774 /* compute length of segmentation header */ 7775 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7776 7777 /* remove payload length from inner checksum */ 7778 paylen = skb->len - l4_offset; 7779 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7780 7781 /* update gso size and bytecount with header size */ 7782 first->gso_segs = skb_shinfo(skb)->gso_segs; 7783 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7784 7785 /* mss_l4len_id: use 0 as index for TSO */ 7786 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7787 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7788 7789 fceof_saidx |= itd->sa_idx; 7790 type_tucmd |= itd->flags | itd->trailer_len; 7791 7792 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7793 vlan_macip_lens = l4.hdr - ip.hdr; 7794 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7795 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7796 7797 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 7798 mss_l4len_idx); 7799 7800 return 1; 7801 } 7802 7803 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7804 { 7805 unsigned int offset = 0; 7806 7807 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7808 7809 return offset == skb_checksum_start_offset(skb); 7810 } 7811 7812 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7813 struct ixgbe_tx_buffer *first, 7814 struct ixgbe_ipsec_tx_data *itd) 7815 { 7816 struct sk_buff *skb = first->skb; 7817 u32 vlan_macip_lens = 0; 7818 u32 fceof_saidx = 0; 7819 u32 type_tucmd = 0; 7820 7821 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7822 csum_failed: 7823 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7824 IXGBE_TX_FLAGS_CC))) 7825 return; 7826 goto no_csum; 7827 } 7828 7829 switch (skb->csum_offset) { 7830 case offsetof(struct tcphdr, check): 7831 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7832 /* fall through */ 7833 case offsetof(struct udphdr, check): 7834 break; 7835 case offsetof(struct sctphdr, checksum): 7836 /* validate that this is actually an SCTP request */ 7837 if (((first->protocol == htons(ETH_P_IP)) && 7838 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7839 ((first->protocol == htons(ETH_P_IPV6)) && 7840 ixgbe_ipv6_csum_is_sctp(skb))) { 7841 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7842 break; 7843 } 7844 /* fall through */ 7845 default: 7846 skb_checksum_help(skb); 7847 goto csum_failed; 7848 } 7849 7850 /* update TX checksum flag */ 7851 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7852 vlan_macip_lens = skb_checksum_start_offset(skb) - 7853 skb_network_offset(skb); 7854 no_csum: 7855 /* vlan_macip_lens: MACLEN, VLAN tag */ 7856 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7857 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7858 7859 fceof_saidx |= itd->sa_idx; 7860 type_tucmd |= itd->flags | itd->trailer_len; 7861 7862 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 7863 } 7864 7865 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7866 ((_flag <= _result) ? \ 7867 ((u32)(_input & _flag) * (_result / _flag)) : \ 7868 ((u32)(_input & _flag) / (_flag / _result))) 7869 7870 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7871 { 7872 /* set type for advanced descriptor with frame checksum insertion */ 7873 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7874 IXGBE_ADVTXD_DCMD_DEXT | 7875 IXGBE_ADVTXD_DCMD_IFCS; 7876 7877 /* set HW vlan bit if vlan is present */ 7878 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7879 IXGBE_ADVTXD_DCMD_VLE); 7880 7881 /* set segmentation enable bits for TSO/FSO */ 7882 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7883 IXGBE_ADVTXD_DCMD_TSE); 7884 7885 /* set timestamp bit if present */ 7886 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7887 IXGBE_ADVTXD_MAC_TSTAMP); 7888 7889 /* insert frame checksum */ 7890 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7891 7892 return cmd_type; 7893 } 7894 7895 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7896 u32 tx_flags, unsigned int paylen) 7897 { 7898 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7899 7900 /* enable L4 checksum for TSO and TX checksum offload */ 7901 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7902 IXGBE_TX_FLAGS_CSUM, 7903 IXGBE_ADVTXD_POPTS_TXSM); 7904 7905 /* enable IPv4 checksum for TSO */ 7906 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7907 IXGBE_TX_FLAGS_IPV4, 7908 IXGBE_ADVTXD_POPTS_IXSM); 7909 7910 /* enable IPsec */ 7911 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7912 IXGBE_TX_FLAGS_IPSEC, 7913 IXGBE_ADVTXD_POPTS_IPSEC); 7914 7915 /* 7916 * Check Context must be set if Tx switch is enabled, which it 7917 * always is for case where virtual functions are running 7918 */ 7919 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7920 IXGBE_TX_FLAGS_CC, 7921 IXGBE_ADVTXD_CC); 7922 7923 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7924 } 7925 7926 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7927 { 7928 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7929 7930 /* Herbert's original patch had: 7931 * smp_mb__after_netif_stop_queue(); 7932 * but since that doesn't exist yet, just open code it. 7933 */ 7934 smp_mb(); 7935 7936 /* We need to check again in a case another CPU has just 7937 * made room available. 7938 */ 7939 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7940 return -EBUSY; 7941 7942 /* A reprieve! - use start_queue because it doesn't call schedule */ 7943 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7944 ++tx_ring->tx_stats.restart_queue; 7945 return 0; 7946 } 7947 7948 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7949 { 7950 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7951 return 0; 7952 7953 return __ixgbe_maybe_stop_tx(tx_ring, size); 7954 } 7955 7956 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7957 IXGBE_TXD_CMD_RS) 7958 7959 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7960 struct ixgbe_tx_buffer *first, 7961 const u8 hdr_len) 7962 { 7963 struct sk_buff *skb = first->skb; 7964 struct ixgbe_tx_buffer *tx_buffer; 7965 union ixgbe_adv_tx_desc *tx_desc; 7966 struct skb_frag_struct *frag; 7967 dma_addr_t dma; 7968 unsigned int data_len, size; 7969 u32 tx_flags = first->tx_flags; 7970 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7971 u16 i = tx_ring->next_to_use; 7972 7973 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7974 7975 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7976 7977 size = skb_headlen(skb); 7978 data_len = skb->data_len; 7979 7980 #ifdef IXGBE_FCOE 7981 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7982 if (data_len < sizeof(struct fcoe_crc_eof)) { 7983 size -= sizeof(struct fcoe_crc_eof) - data_len; 7984 data_len = 0; 7985 } else { 7986 data_len -= sizeof(struct fcoe_crc_eof); 7987 } 7988 } 7989 7990 #endif 7991 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7992 7993 tx_buffer = first; 7994 7995 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7996 if (dma_mapping_error(tx_ring->dev, dma)) 7997 goto dma_error; 7998 7999 /* record length, and DMA address */ 8000 dma_unmap_len_set(tx_buffer, len, size); 8001 dma_unmap_addr_set(tx_buffer, dma, dma); 8002 8003 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8004 8005 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8006 tx_desc->read.cmd_type_len = 8007 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8008 8009 i++; 8010 tx_desc++; 8011 if (i == tx_ring->count) { 8012 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8013 i = 0; 8014 } 8015 tx_desc->read.olinfo_status = 0; 8016 8017 dma += IXGBE_MAX_DATA_PER_TXD; 8018 size -= IXGBE_MAX_DATA_PER_TXD; 8019 8020 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8021 } 8022 8023 if (likely(!data_len)) 8024 break; 8025 8026 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8027 8028 i++; 8029 tx_desc++; 8030 if (i == tx_ring->count) { 8031 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8032 i = 0; 8033 } 8034 tx_desc->read.olinfo_status = 0; 8035 8036 #ifdef IXGBE_FCOE 8037 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8038 #else 8039 size = skb_frag_size(frag); 8040 #endif 8041 data_len -= size; 8042 8043 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8044 DMA_TO_DEVICE); 8045 8046 tx_buffer = &tx_ring->tx_buffer_info[i]; 8047 } 8048 8049 /* write last descriptor with RS and EOP bits */ 8050 cmd_type |= size | IXGBE_TXD_CMD; 8051 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8052 8053 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8054 8055 /* set the timestamp */ 8056 first->time_stamp = jiffies; 8057 8058 /* 8059 * Force memory writes to complete before letting h/w know there 8060 * are new descriptors to fetch. (Only applicable for weak-ordered 8061 * memory model archs, such as IA-64). 8062 * 8063 * We also need this memory barrier to make certain all of the 8064 * status bits have been updated before next_to_watch is written. 8065 */ 8066 wmb(); 8067 8068 /* set next_to_watch value indicating a packet is present */ 8069 first->next_to_watch = tx_desc; 8070 8071 i++; 8072 if (i == tx_ring->count) 8073 i = 0; 8074 8075 tx_ring->next_to_use = i; 8076 8077 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8078 8079 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8080 writel(i, tx_ring->tail); 8081 8082 /* we need this if more than one processor can write to our tail 8083 * at a time, it synchronizes IO on IA64/Altix systems 8084 */ 8085 mmiowb(); 8086 } 8087 8088 return 0; 8089 dma_error: 8090 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8091 8092 /* clear dma mappings for failed tx_buffer_info map */ 8093 for (;;) { 8094 tx_buffer = &tx_ring->tx_buffer_info[i]; 8095 if (dma_unmap_len(tx_buffer, len)) 8096 dma_unmap_page(tx_ring->dev, 8097 dma_unmap_addr(tx_buffer, dma), 8098 dma_unmap_len(tx_buffer, len), 8099 DMA_TO_DEVICE); 8100 dma_unmap_len_set(tx_buffer, len, 0); 8101 if (tx_buffer == first) 8102 break; 8103 if (i == 0) 8104 i += tx_ring->count; 8105 i--; 8106 } 8107 8108 dev_kfree_skb_any(first->skb); 8109 first->skb = NULL; 8110 8111 tx_ring->next_to_use = i; 8112 8113 return -1; 8114 } 8115 8116 static void ixgbe_atr(struct ixgbe_ring *ring, 8117 struct ixgbe_tx_buffer *first) 8118 { 8119 struct ixgbe_q_vector *q_vector = ring->q_vector; 8120 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8121 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8122 union { 8123 unsigned char *network; 8124 struct iphdr *ipv4; 8125 struct ipv6hdr *ipv6; 8126 } hdr; 8127 struct tcphdr *th; 8128 unsigned int hlen; 8129 struct sk_buff *skb; 8130 __be16 vlan_id; 8131 int l4_proto; 8132 8133 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8134 if (!q_vector) 8135 return; 8136 8137 /* do nothing if sampling is disabled */ 8138 if (!ring->atr_sample_rate) 8139 return; 8140 8141 ring->atr_count++; 8142 8143 /* currently only IPv4/IPv6 with TCP is supported */ 8144 if ((first->protocol != htons(ETH_P_IP)) && 8145 (first->protocol != htons(ETH_P_IPV6))) 8146 return; 8147 8148 /* snag network header to get L4 type and address */ 8149 skb = first->skb; 8150 hdr.network = skb_network_header(skb); 8151 if (unlikely(hdr.network <= skb->data)) 8152 return; 8153 if (skb->encapsulation && 8154 first->protocol == htons(ETH_P_IP) && 8155 hdr.ipv4->protocol == IPPROTO_UDP) { 8156 struct ixgbe_adapter *adapter = q_vector->adapter; 8157 8158 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8159 VXLAN_HEADROOM)) 8160 return; 8161 8162 /* verify the port is recognized as VXLAN */ 8163 if (adapter->vxlan_port && 8164 udp_hdr(skb)->dest == adapter->vxlan_port) 8165 hdr.network = skb_inner_network_header(skb); 8166 8167 if (adapter->geneve_port && 8168 udp_hdr(skb)->dest == adapter->geneve_port) 8169 hdr.network = skb_inner_network_header(skb); 8170 } 8171 8172 /* Make sure we have at least [minimum IPv4 header + TCP] 8173 * or [IPv6 header] bytes 8174 */ 8175 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8176 return; 8177 8178 /* Currently only IPv4/IPv6 with TCP is supported */ 8179 switch (hdr.ipv4->version) { 8180 case IPVERSION: 8181 /* access ihl as u8 to avoid unaligned access on ia64 */ 8182 hlen = (hdr.network[0] & 0x0F) << 2; 8183 l4_proto = hdr.ipv4->protocol; 8184 break; 8185 case 6: 8186 hlen = hdr.network - skb->data; 8187 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8188 hlen -= hdr.network - skb->data; 8189 break; 8190 default: 8191 return; 8192 } 8193 8194 if (l4_proto != IPPROTO_TCP) 8195 return; 8196 8197 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8198 hlen + sizeof(struct tcphdr))) 8199 return; 8200 8201 th = (struct tcphdr *)(hdr.network + hlen); 8202 8203 /* skip this packet since the socket is closing */ 8204 if (th->fin) 8205 return; 8206 8207 /* sample on all syn packets or once every atr sample count */ 8208 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8209 return; 8210 8211 /* reset sample count */ 8212 ring->atr_count = 0; 8213 8214 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8215 8216 /* 8217 * src and dst are inverted, think how the receiver sees them 8218 * 8219 * The input is broken into two sections, a non-compressed section 8220 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8221 * is XORed together and stored in the compressed dword. 8222 */ 8223 input.formatted.vlan_id = vlan_id; 8224 8225 /* 8226 * since src port and flex bytes occupy the same word XOR them together 8227 * and write the value to source port portion of compressed dword 8228 */ 8229 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8230 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8231 else 8232 common.port.src ^= th->dest ^ first->protocol; 8233 common.port.dst ^= th->source; 8234 8235 switch (hdr.ipv4->version) { 8236 case IPVERSION: 8237 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8238 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8239 break; 8240 case 6: 8241 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8242 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8243 hdr.ipv6->saddr.s6_addr32[1] ^ 8244 hdr.ipv6->saddr.s6_addr32[2] ^ 8245 hdr.ipv6->saddr.s6_addr32[3] ^ 8246 hdr.ipv6->daddr.s6_addr32[0] ^ 8247 hdr.ipv6->daddr.s6_addr32[1] ^ 8248 hdr.ipv6->daddr.s6_addr32[2] ^ 8249 hdr.ipv6->daddr.s6_addr32[3]; 8250 break; 8251 default: 8252 break; 8253 } 8254 8255 if (hdr.network != skb_network_header(skb)) 8256 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8257 8258 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8259 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8260 input, common, ring->queue_index); 8261 } 8262 8263 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8264 void *accel_priv, select_queue_fallback_t fallback) 8265 { 8266 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8267 struct ixgbe_adapter *adapter; 8268 int txq; 8269 #ifdef IXGBE_FCOE 8270 struct ixgbe_ring_feature *f; 8271 #endif 8272 8273 if (fwd_adapter) { 8274 adapter = netdev_priv(dev); 8275 txq = reciprocal_scale(skb_get_hash(skb), 8276 adapter->num_rx_queues_per_pool); 8277 8278 return txq + fwd_adapter->tx_base_queue; 8279 } 8280 8281 #ifdef IXGBE_FCOE 8282 8283 /* 8284 * only execute the code below if protocol is FCoE 8285 * or FIP and we have FCoE enabled on the adapter 8286 */ 8287 switch (vlan_get_protocol(skb)) { 8288 case htons(ETH_P_FCOE): 8289 case htons(ETH_P_FIP): 8290 adapter = netdev_priv(dev); 8291 8292 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8293 break; 8294 /* fall through */ 8295 default: 8296 return fallback(dev, skb); 8297 } 8298 8299 f = &adapter->ring_feature[RING_F_FCOE]; 8300 8301 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8302 smp_processor_id(); 8303 8304 while (txq >= f->indices) 8305 txq -= f->indices; 8306 8307 return txq + f->offset; 8308 #else 8309 return fallback(dev, skb); 8310 #endif 8311 } 8312 8313 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8314 struct xdp_frame *xdpf) 8315 { 8316 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8317 struct ixgbe_tx_buffer *tx_buffer; 8318 union ixgbe_adv_tx_desc *tx_desc; 8319 u32 len, cmd_type; 8320 dma_addr_t dma; 8321 u16 i; 8322 8323 len = xdpf->len; 8324 8325 if (unlikely(!ixgbe_desc_unused(ring))) 8326 return IXGBE_XDP_CONSUMED; 8327 8328 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8329 if (dma_mapping_error(ring->dev, dma)) 8330 return IXGBE_XDP_CONSUMED; 8331 8332 /* record the location of the first descriptor for this packet */ 8333 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8334 tx_buffer->bytecount = len; 8335 tx_buffer->gso_segs = 1; 8336 tx_buffer->protocol = 0; 8337 8338 i = ring->next_to_use; 8339 tx_desc = IXGBE_TX_DESC(ring, i); 8340 8341 dma_unmap_len_set(tx_buffer, len, len); 8342 dma_unmap_addr_set(tx_buffer, dma, dma); 8343 tx_buffer->xdpf = xdpf; 8344 8345 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8346 8347 /* put descriptor type bits */ 8348 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8349 IXGBE_ADVTXD_DCMD_DEXT | 8350 IXGBE_ADVTXD_DCMD_IFCS; 8351 cmd_type |= len | IXGBE_TXD_CMD; 8352 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8353 tx_desc->read.olinfo_status = 8354 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8355 8356 /* Avoid any potential race with xdp_xmit and cleanup */ 8357 smp_wmb(); 8358 8359 /* set next_to_watch value indicating a packet is present */ 8360 i++; 8361 if (i == ring->count) 8362 i = 0; 8363 8364 tx_buffer->next_to_watch = tx_desc; 8365 ring->next_to_use = i; 8366 8367 return IXGBE_XDP_TX; 8368 } 8369 8370 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8371 struct ixgbe_adapter *adapter, 8372 struct ixgbe_ring *tx_ring) 8373 { 8374 struct ixgbe_tx_buffer *first; 8375 int tso; 8376 u32 tx_flags = 0; 8377 unsigned short f; 8378 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8379 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8380 __be16 protocol = skb->protocol; 8381 u8 hdr_len = 0; 8382 8383 /* 8384 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8385 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8386 * + 2 desc gap to keep tail from touching head, 8387 * + 1 desc for context descriptor, 8388 * otherwise try next time 8389 */ 8390 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8391 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8392 8393 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8394 tx_ring->tx_stats.tx_busy++; 8395 return NETDEV_TX_BUSY; 8396 } 8397 8398 /* record the location of the first descriptor for this packet */ 8399 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8400 first->skb = skb; 8401 first->bytecount = skb->len; 8402 first->gso_segs = 1; 8403 8404 /* if we have a HW VLAN tag being added default to the HW one */ 8405 if (skb_vlan_tag_present(skb)) { 8406 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8407 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8408 /* else if it is a SW VLAN check the next protocol and store the tag */ 8409 } else if (protocol == htons(ETH_P_8021Q)) { 8410 struct vlan_hdr *vhdr, _vhdr; 8411 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8412 if (!vhdr) 8413 goto out_drop; 8414 8415 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8416 IXGBE_TX_FLAGS_VLAN_SHIFT; 8417 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8418 } 8419 protocol = vlan_get_protocol(skb); 8420 8421 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8422 adapter->ptp_clock) { 8423 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8424 &adapter->state)) { 8425 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8426 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8427 8428 /* schedule check for Tx timestamp */ 8429 adapter->ptp_tx_skb = skb_get(skb); 8430 adapter->ptp_tx_start = jiffies; 8431 schedule_work(&adapter->ptp_tx_work); 8432 } else { 8433 adapter->tx_hwtstamp_skipped++; 8434 } 8435 } 8436 8437 skb_tx_timestamp(skb); 8438 8439 #ifdef CONFIG_PCI_IOV 8440 /* 8441 * Use the l2switch_enable flag - would be false if the DMA 8442 * Tx switch had been disabled. 8443 */ 8444 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8445 tx_flags |= IXGBE_TX_FLAGS_CC; 8446 8447 #endif 8448 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8449 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8450 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8451 (skb->priority != TC_PRIO_CONTROL))) { 8452 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8453 tx_flags |= (skb->priority & 0x7) << 8454 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8455 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8456 struct vlan_ethhdr *vhdr; 8457 8458 if (skb_cow_head(skb, 0)) 8459 goto out_drop; 8460 vhdr = (struct vlan_ethhdr *)skb->data; 8461 vhdr->h_vlan_TCI = htons(tx_flags >> 8462 IXGBE_TX_FLAGS_VLAN_SHIFT); 8463 } else { 8464 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8465 } 8466 } 8467 8468 /* record initial flags and protocol */ 8469 first->tx_flags = tx_flags; 8470 first->protocol = protocol; 8471 8472 #ifdef IXGBE_FCOE 8473 /* setup tx offload for FCoE */ 8474 if ((protocol == htons(ETH_P_FCOE)) && 8475 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8476 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8477 if (tso < 0) 8478 goto out_drop; 8479 8480 goto xmit_fcoe; 8481 } 8482 8483 #endif /* IXGBE_FCOE */ 8484 8485 #ifdef CONFIG_XFRM_OFFLOAD 8486 if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8487 goto out_drop; 8488 #endif 8489 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8490 if (tso < 0) 8491 goto out_drop; 8492 else if (!tso) 8493 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8494 8495 /* add the ATR filter if ATR is on */ 8496 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8497 ixgbe_atr(tx_ring, first); 8498 8499 #ifdef IXGBE_FCOE 8500 xmit_fcoe: 8501 #endif /* IXGBE_FCOE */ 8502 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8503 goto cleanup_tx_timestamp; 8504 8505 return NETDEV_TX_OK; 8506 8507 out_drop: 8508 dev_kfree_skb_any(first->skb); 8509 first->skb = NULL; 8510 cleanup_tx_timestamp: 8511 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8512 dev_kfree_skb_any(adapter->ptp_tx_skb); 8513 adapter->ptp_tx_skb = NULL; 8514 cancel_work_sync(&adapter->ptp_tx_work); 8515 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8516 } 8517 8518 return NETDEV_TX_OK; 8519 } 8520 8521 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8522 struct net_device *netdev, 8523 struct ixgbe_ring *ring) 8524 { 8525 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8526 struct ixgbe_ring *tx_ring; 8527 8528 /* 8529 * The minimum packet size for olinfo paylen is 17 so pad the skb 8530 * in order to meet this minimum size requirement. 8531 */ 8532 if (skb_put_padto(skb, 17)) 8533 return NETDEV_TX_OK; 8534 8535 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8536 8537 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8538 } 8539 8540 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8541 struct net_device *netdev) 8542 { 8543 return __ixgbe_xmit_frame(skb, netdev, NULL); 8544 } 8545 8546 /** 8547 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8548 * @netdev: network interface device structure 8549 * @p: pointer to an address structure 8550 * 8551 * Returns 0 on success, negative on failure 8552 **/ 8553 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8554 { 8555 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8556 struct ixgbe_hw *hw = &adapter->hw; 8557 struct sockaddr *addr = p; 8558 8559 if (!is_valid_ether_addr(addr->sa_data)) 8560 return -EADDRNOTAVAIL; 8561 8562 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8563 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8564 8565 ixgbe_mac_set_default_filter(adapter); 8566 8567 return 0; 8568 } 8569 8570 static int 8571 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8572 { 8573 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8574 struct ixgbe_hw *hw = &adapter->hw; 8575 u16 value; 8576 int rc; 8577 8578 if (prtad != hw->phy.mdio.prtad) 8579 return -EINVAL; 8580 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8581 if (!rc) 8582 rc = value; 8583 return rc; 8584 } 8585 8586 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8587 u16 addr, u16 value) 8588 { 8589 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8590 struct ixgbe_hw *hw = &adapter->hw; 8591 8592 if (prtad != hw->phy.mdio.prtad) 8593 return -EINVAL; 8594 return hw->phy.ops.write_reg(hw, addr, devad, value); 8595 } 8596 8597 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8598 { 8599 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8600 8601 switch (cmd) { 8602 case SIOCSHWTSTAMP: 8603 return ixgbe_ptp_set_ts_config(adapter, req); 8604 case SIOCGHWTSTAMP: 8605 return ixgbe_ptp_get_ts_config(adapter, req); 8606 case SIOCGMIIPHY: 8607 if (!adapter->hw.phy.ops.read_reg) 8608 return -EOPNOTSUPP; 8609 /* fall through */ 8610 default: 8611 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8612 } 8613 } 8614 8615 /** 8616 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8617 * netdev->dev_addrs 8618 * @dev: network interface device structure 8619 * 8620 * Returns non-zero on failure 8621 **/ 8622 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8623 { 8624 int err = 0; 8625 struct ixgbe_adapter *adapter = netdev_priv(dev); 8626 struct ixgbe_hw *hw = &adapter->hw; 8627 8628 if (is_valid_ether_addr(hw->mac.san_addr)) { 8629 rtnl_lock(); 8630 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8631 rtnl_unlock(); 8632 8633 /* update SAN MAC vmdq pool selection */ 8634 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8635 } 8636 return err; 8637 } 8638 8639 /** 8640 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8641 * netdev->dev_addrs 8642 * @dev: network interface device structure 8643 * 8644 * Returns non-zero on failure 8645 **/ 8646 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8647 { 8648 int err = 0; 8649 struct ixgbe_adapter *adapter = netdev_priv(dev); 8650 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8651 8652 if (is_valid_ether_addr(mac->san_addr)) { 8653 rtnl_lock(); 8654 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8655 rtnl_unlock(); 8656 } 8657 return err; 8658 } 8659 8660 #ifdef CONFIG_NET_POLL_CONTROLLER 8661 /* 8662 * Polling 'interrupt' - used by things like netconsole to send skbs 8663 * without having to re-enable interrupts. It's not called while 8664 * the interrupt routine is executing. 8665 */ 8666 static void ixgbe_netpoll(struct net_device *netdev) 8667 { 8668 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8669 int i; 8670 8671 /* if interface is down do nothing */ 8672 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8673 return; 8674 8675 /* loop through and schedule all active queues */ 8676 for (i = 0; i < adapter->num_q_vectors; i++) 8677 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8678 } 8679 8680 #endif 8681 8682 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8683 struct ixgbe_ring *ring) 8684 { 8685 u64 bytes, packets; 8686 unsigned int start; 8687 8688 if (ring) { 8689 do { 8690 start = u64_stats_fetch_begin_irq(&ring->syncp); 8691 packets = ring->stats.packets; 8692 bytes = ring->stats.bytes; 8693 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8694 stats->tx_packets += packets; 8695 stats->tx_bytes += bytes; 8696 } 8697 } 8698 8699 static void ixgbe_get_stats64(struct net_device *netdev, 8700 struct rtnl_link_stats64 *stats) 8701 { 8702 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8703 int i; 8704 8705 rcu_read_lock(); 8706 for (i = 0; i < adapter->num_rx_queues; i++) { 8707 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8708 u64 bytes, packets; 8709 unsigned int start; 8710 8711 if (ring) { 8712 do { 8713 start = u64_stats_fetch_begin_irq(&ring->syncp); 8714 packets = ring->stats.packets; 8715 bytes = ring->stats.bytes; 8716 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8717 stats->rx_packets += packets; 8718 stats->rx_bytes += bytes; 8719 } 8720 } 8721 8722 for (i = 0; i < adapter->num_tx_queues; i++) { 8723 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8724 8725 ixgbe_get_ring_stats64(stats, ring); 8726 } 8727 for (i = 0; i < adapter->num_xdp_queues; i++) { 8728 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8729 8730 ixgbe_get_ring_stats64(stats, ring); 8731 } 8732 rcu_read_unlock(); 8733 8734 /* following stats updated by ixgbe_watchdog_task() */ 8735 stats->multicast = netdev->stats.multicast; 8736 stats->rx_errors = netdev->stats.rx_errors; 8737 stats->rx_length_errors = netdev->stats.rx_length_errors; 8738 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8739 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8740 } 8741 8742 #ifdef CONFIG_IXGBE_DCB 8743 /** 8744 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8745 * @adapter: pointer to ixgbe_adapter 8746 * @tc: number of traffic classes currently enabled 8747 * 8748 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8749 * 802.1Q priority maps to a packet buffer that exists. 8750 */ 8751 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8752 { 8753 struct ixgbe_hw *hw = &adapter->hw; 8754 u32 reg, rsave; 8755 int i; 8756 8757 /* 82598 have a static priority to TC mapping that can not 8758 * be changed so no validation is needed. 8759 */ 8760 if (hw->mac.type == ixgbe_mac_82598EB) 8761 return; 8762 8763 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8764 rsave = reg; 8765 8766 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8767 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8768 8769 /* If up2tc is out of bounds default to zero */ 8770 if (up2tc > tc) 8771 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8772 } 8773 8774 if (reg != rsave) 8775 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8776 8777 return; 8778 } 8779 8780 /** 8781 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8782 * @adapter: Pointer to adapter struct 8783 * 8784 * Populate the netdev user priority to tc map 8785 */ 8786 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8787 { 8788 struct net_device *dev = adapter->netdev; 8789 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8790 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8791 u8 prio; 8792 8793 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8794 u8 tc = 0; 8795 8796 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8797 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8798 else if (ets) 8799 tc = ets->prio_tc[prio]; 8800 8801 netdev_set_prio_tc_map(dev, prio, tc); 8802 } 8803 } 8804 8805 #endif /* CONFIG_IXGBE_DCB */ 8806 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 8807 { 8808 struct ixgbe_adapter *adapter = data; 8809 struct ixgbe_fwd_adapter *accel; 8810 int pool; 8811 8812 /* we only care about macvlans... */ 8813 if (!netif_is_macvlan(vdev)) 8814 return 0; 8815 8816 /* that have hardware offload enabled... */ 8817 accel = macvlan_accel_priv(vdev); 8818 if (!accel) 8819 return 0; 8820 8821 /* If we can relocate to a different bit do so */ 8822 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 8823 if (pool < adapter->num_rx_pools) { 8824 set_bit(pool, adapter->fwd_bitmask); 8825 accel->pool = pool; 8826 return 0; 8827 } 8828 8829 /* if we cannot find a free pool then disable the offload */ 8830 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 8831 macvlan_release_l2fw_offload(vdev); 8832 kfree(accel); 8833 8834 return 0; 8835 } 8836 8837 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 8838 { 8839 struct ixgbe_adapter *adapter = netdev_priv(dev); 8840 8841 /* flush any stale bits out of the fwd bitmask */ 8842 bitmap_clear(adapter->fwd_bitmask, 1, 63); 8843 8844 /* walk through upper devices reassigning pools */ 8845 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 8846 adapter); 8847 } 8848 8849 /** 8850 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8851 * 8852 * @dev: net device to configure 8853 * @tc: number of traffic classes to enable 8854 */ 8855 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8856 { 8857 struct ixgbe_adapter *adapter = netdev_priv(dev); 8858 struct ixgbe_hw *hw = &adapter->hw; 8859 8860 /* Hardware supports up to 8 traffic classes */ 8861 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8862 return -EINVAL; 8863 8864 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8865 return -EINVAL; 8866 8867 /* Hardware has to reinitialize queues and interrupts to 8868 * match packet buffer alignment. Unfortunately, the 8869 * hardware is not flexible enough to do this dynamically. 8870 */ 8871 if (netif_running(dev)) 8872 ixgbe_close(dev); 8873 else 8874 ixgbe_reset(adapter); 8875 8876 ixgbe_clear_interrupt_scheme(adapter); 8877 8878 #ifdef CONFIG_IXGBE_DCB 8879 if (tc) { 8880 netdev_set_num_tc(dev, tc); 8881 ixgbe_set_prio_tc_map(adapter); 8882 8883 adapter->hw_tcs = tc; 8884 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8885 8886 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8887 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8888 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8889 } 8890 } else { 8891 netdev_reset_tc(dev); 8892 8893 /* To support macvlan offload we have to use num_tc to 8894 * restrict the queues that can be used by the device. 8895 * By doing this we can avoid reporting a false number of 8896 * queues. 8897 */ 8898 if (!tc && adapter->num_rx_pools > 1) 8899 netdev_set_num_tc(dev, 1); 8900 8901 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8902 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8903 8904 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8905 adapter->hw_tcs = tc; 8906 8907 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8908 adapter->dcb_cfg.pfc_mode_enable = false; 8909 } 8910 8911 ixgbe_validate_rtr(adapter, tc); 8912 8913 #endif /* CONFIG_IXGBE_DCB */ 8914 ixgbe_init_interrupt_scheme(adapter); 8915 8916 ixgbe_defrag_macvlan_pools(dev); 8917 8918 if (netif_running(dev)) 8919 return ixgbe_open(dev); 8920 8921 return 0; 8922 } 8923 8924 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8925 struct tc_cls_u32_offload *cls) 8926 { 8927 u32 hdl = cls->knode.handle; 8928 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8929 u32 loc = cls->knode.handle & 0xfffff; 8930 int err = 0, i, j; 8931 struct ixgbe_jump_table *jump = NULL; 8932 8933 if (loc > IXGBE_MAX_HW_ENTRIES) 8934 return -EINVAL; 8935 8936 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8937 return -EINVAL; 8938 8939 /* Clear this filter in the link data it is associated with */ 8940 if (uhtid != 0x800) { 8941 jump = adapter->jump_tables[uhtid]; 8942 if (!jump) 8943 return -EINVAL; 8944 if (!test_bit(loc - 1, jump->child_loc_map)) 8945 return -EINVAL; 8946 clear_bit(loc - 1, jump->child_loc_map); 8947 } 8948 8949 /* Check if the filter being deleted is a link */ 8950 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8951 jump = adapter->jump_tables[i]; 8952 if (jump && jump->link_hdl == hdl) { 8953 /* Delete filters in the hardware in the child hash 8954 * table associated with this link 8955 */ 8956 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8957 if (!test_bit(j, jump->child_loc_map)) 8958 continue; 8959 spin_lock(&adapter->fdir_perfect_lock); 8960 err = ixgbe_update_ethtool_fdir_entry(adapter, 8961 NULL, 8962 j + 1); 8963 spin_unlock(&adapter->fdir_perfect_lock); 8964 clear_bit(j, jump->child_loc_map); 8965 } 8966 /* Remove resources for this link */ 8967 kfree(jump->input); 8968 kfree(jump->mask); 8969 kfree(jump); 8970 adapter->jump_tables[i] = NULL; 8971 return err; 8972 } 8973 } 8974 8975 spin_lock(&adapter->fdir_perfect_lock); 8976 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8977 spin_unlock(&adapter->fdir_perfect_lock); 8978 return err; 8979 } 8980 8981 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8982 struct tc_cls_u32_offload *cls) 8983 { 8984 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8985 8986 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8987 return -EINVAL; 8988 8989 /* This ixgbe devices do not support hash tables at the moment 8990 * so abort when given hash tables. 8991 */ 8992 if (cls->hnode.divisor > 0) 8993 return -EINVAL; 8994 8995 set_bit(uhtid - 1, &adapter->tables); 8996 return 0; 8997 } 8998 8999 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9000 struct tc_cls_u32_offload *cls) 9001 { 9002 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9003 9004 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9005 return -EINVAL; 9006 9007 clear_bit(uhtid - 1, &adapter->tables); 9008 return 0; 9009 } 9010 9011 #ifdef CONFIG_NET_CLS_ACT 9012 struct upper_walk_data { 9013 struct ixgbe_adapter *adapter; 9014 u64 action; 9015 int ifindex; 9016 u8 queue; 9017 }; 9018 9019 static int get_macvlan_queue(struct net_device *upper, void *_data) 9020 { 9021 if (netif_is_macvlan(upper)) { 9022 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9023 struct upper_walk_data *data = _data; 9024 struct ixgbe_adapter *adapter = data->adapter; 9025 int ifindex = data->ifindex; 9026 9027 if (vadapter && upper->ifindex == ifindex) { 9028 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9029 data->action = data->queue; 9030 return 1; 9031 } 9032 } 9033 9034 return 0; 9035 } 9036 9037 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9038 u8 *queue, u64 *action) 9039 { 9040 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9041 unsigned int num_vfs = adapter->num_vfs, vf; 9042 struct upper_walk_data data; 9043 struct net_device *upper; 9044 9045 /* redirect to a SRIOV VF */ 9046 for (vf = 0; vf < num_vfs; ++vf) { 9047 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9048 if (upper->ifindex == ifindex) { 9049 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9050 *action = vf + 1; 9051 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9052 return 0; 9053 } 9054 } 9055 9056 /* redirect to a offloaded macvlan netdev */ 9057 data.adapter = adapter; 9058 data.ifindex = ifindex; 9059 data.action = 0; 9060 data.queue = 0; 9061 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9062 get_macvlan_queue, &data)) { 9063 *action = data.action; 9064 *queue = data.queue; 9065 9066 return 0; 9067 } 9068 9069 return -EINVAL; 9070 } 9071 9072 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9073 struct tcf_exts *exts, u64 *action, u8 *queue) 9074 { 9075 const struct tc_action *a; 9076 LIST_HEAD(actions); 9077 int err; 9078 9079 if (!tcf_exts_has_actions(exts)) 9080 return -EINVAL; 9081 9082 tcf_exts_to_list(exts, &actions); 9083 list_for_each_entry(a, &actions, list) { 9084 9085 /* Drop action */ 9086 if (is_tcf_gact_shot(a)) { 9087 *action = IXGBE_FDIR_DROP_QUEUE; 9088 *queue = IXGBE_FDIR_DROP_QUEUE; 9089 return 0; 9090 } 9091 9092 /* Redirect to a VF or a offloaded macvlan */ 9093 if (is_tcf_mirred_egress_redirect(a)) { 9094 struct net_device *dev = tcf_mirred_dev(a); 9095 9096 if (!dev) 9097 return -EINVAL; 9098 err = handle_redirect_action(adapter, dev->ifindex, queue, 9099 action); 9100 if (err == 0) 9101 return err; 9102 } 9103 } 9104 9105 return -EINVAL; 9106 } 9107 #else 9108 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9109 struct tcf_exts *exts, u64 *action, u8 *queue) 9110 { 9111 return -EINVAL; 9112 } 9113 #endif /* CONFIG_NET_CLS_ACT */ 9114 9115 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9116 union ixgbe_atr_input *mask, 9117 struct tc_cls_u32_offload *cls, 9118 struct ixgbe_mat_field *field_ptr, 9119 struct ixgbe_nexthdr *nexthdr) 9120 { 9121 int i, j, off; 9122 __be32 val, m; 9123 bool found_entry = false, found_jump_field = false; 9124 9125 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9126 off = cls->knode.sel->keys[i].off; 9127 val = cls->knode.sel->keys[i].val; 9128 m = cls->knode.sel->keys[i].mask; 9129 9130 for (j = 0; field_ptr[j].val; j++) { 9131 if (field_ptr[j].off == off) { 9132 field_ptr[j].val(input, mask, val, m); 9133 input->filter.formatted.flow_type |= 9134 field_ptr[j].type; 9135 found_entry = true; 9136 break; 9137 } 9138 } 9139 if (nexthdr) { 9140 if (nexthdr->off == cls->knode.sel->keys[i].off && 9141 nexthdr->val == cls->knode.sel->keys[i].val && 9142 nexthdr->mask == cls->knode.sel->keys[i].mask) 9143 found_jump_field = true; 9144 else 9145 continue; 9146 } 9147 } 9148 9149 if (nexthdr && !found_jump_field) 9150 return -EINVAL; 9151 9152 if (!found_entry) 9153 return 0; 9154 9155 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9156 IXGBE_ATR_L4TYPE_MASK; 9157 9158 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9159 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9160 9161 return 0; 9162 } 9163 9164 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9165 struct tc_cls_u32_offload *cls) 9166 { 9167 __be16 protocol = cls->common.protocol; 9168 u32 loc = cls->knode.handle & 0xfffff; 9169 struct ixgbe_hw *hw = &adapter->hw; 9170 struct ixgbe_mat_field *field_ptr; 9171 struct ixgbe_fdir_filter *input = NULL; 9172 union ixgbe_atr_input *mask = NULL; 9173 struct ixgbe_jump_table *jump = NULL; 9174 int i, err = -EINVAL; 9175 u8 queue; 9176 u32 uhtid, link_uhtid; 9177 9178 uhtid = TC_U32_USERHTID(cls->knode.handle); 9179 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9180 9181 /* At the moment cls_u32 jumps to network layer and skips past 9182 * L2 headers. The canonical method to match L2 frames is to use 9183 * negative values. However this is error prone at best but really 9184 * just broken because there is no way to "know" what sort of hdr 9185 * is in front of the network layer. Fix cls_u32 to support L2 9186 * headers when needed. 9187 */ 9188 if (protocol != htons(ETH_P_IP)) 9189 return err; 9190 9191 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9192 e_err(drv, "Location out of range\n"); 9193 return err; 9194 } 9195 9196 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9197 * links and also the fields used to advance the parser across each 9198 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9199 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9200 * To add support for new nodes update ixgbe_model.h parse structures 9201 * this function _should_ be generic try not to hardcode values here. 9202 */ 9203 if (uhtid == 0x800) { 9204 field_ptr = (adapter->jump_tables[0])->mat; 9205 } else { 9206 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9207 return err; 9208 if (!adapter->jump_tables[uhtid]) 9209 return err; 9210 field_ptr = (adapter->jump_tables[uhtid])->mat; 9211 } 9212 9213 if (!field_ptr) 9214 return err; 9215 9216 /* At this point we know the field_ptr is valid and need to either 9217 * build cls_u32 link or attach filter. Because adding a link to 9218 * a handle that does not exist is invalid and the same for adding 9219 * rules to handles that don't exist. 9220 */ 9221 9222 if (link_uhtid) { 9223 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9224 9225 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9226 return err; 9227 9228 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9229 return err; 9230 9231 /* Multiple filters as links to the same hash table are not 9232 * supported. To add a new filter with the same next header 9233 * but different match/jump conditions, create a new hash table 9234 * and link to it. 9235 */ 9236 if (adapter->jump_tables[link_uhtid] && 9237 (adapter->jump_tables[link_uhtid])->link_hdl) { 9238 e_err(drv, "Link filter exists for link: %x\n", 9239 link_uhtid); 9240 return err; 9241 } 9242 9243 for (i = 0; nexthdr[i].jump; i++) { 9244 if (nexthdr[i].o != cls->knode.sel->offoff || 9245 nexthdr[i].s != cls->knode.sel->offshift || 9246 nexthdr[i].m != cls->knode.sel->offmask) 9247 return err; 9248 9249 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9250 if (!jump) 9251 return -ENOMEM; 9252 input = kzalloc(sizeof(*input), GFP_KERNEL); 9253 if (!input) { 9254 err = -ENOMEM; 9255 goto free_jump; 9256 } 9257 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9258 if (!mask) { 9259 err = -ENOMEM; 9260 goto free_input; 9261 } 9262 jump->input = input; 9263 jump->mask = mask; 9264 jump->link_hdl = cls->knode.handle; 9265 9266 err = ixgbe_clsu32_build_input(input, mask, cls, 9267 field_ptr, &nexthdr[i]); 9268 if (!err) { 9269 jump->mat = nexthdr[i].jump; 9270 adapter->jump_tables[link_uhtid] = jump; 9271 break; 9272 } 9273 } 9274 return 0; 9275 } 9276 9277 input = kzalloc(sizeof(*input), GFP_KERNEL); 9278 if (!input) 9279 return -ENOMEM; 9280 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9281 if (!mask) { 9282 err = -ENOMEM; 9283 goto free_input; 9284 } 9285 9286 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9287 if ((adapter->jump_tables[uhtid])->input) 9288 memcpy(input, (adapter->jump_tables[uhtid])->input, 9289 sizeof(*input)); 9290 if ((adapter->jump_tables[uhtid])->mask) 9291 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9292 sizeof(*mask)); 9293 9294 /* Lookup in all child hash tables if this location is already 9295 * filled with a filter 9296 */ 9297 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9298 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9299 9300 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9301 e_err(drv, "Filter exists in location: %x\n", 9302 loc); 9303 err = -EINVAL; 9304 goto err_out; 9305 } 9306 } 9307 } 9308 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9309 if (err) 9310 goto err_out; 9311 9312 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9313 &queue); 9314 if (err < 0) 9315 goto err_out; 9316 9317 input->sw_idx = loc; 9318 9319 spin_lock(&adapter->fdir_perfect_lock); 9320 9321 if (hlist_empty(&adapter->fdir_filter_list)) { 9322 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9323 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9324 if (err) 9325 goto err_out_w_lock; 9326 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9327 err = -EINVAL; 9328 goto err_out_w_lock; 9329 } 9330 9331 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9332 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9333 input->sw_idx, queue); 9334 if (!err) 9335 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9336 spin_unlock(&adapter->fdir_perfect_lock); 9337 9338 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9339 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9340 9341 kfree(mask); 9342 return err; 9343 err_out_w_lock: 9344 spin_unlock(&adapter->fdir_perfect_lock); 9345 err_out: 9346 kfree(mask); 9347 free_input: 9348 kfree(input); 9349 free_jump: 9350 kfree(jump); 9351 return err; 9352 } 9353 9354 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9355 struct tc_cls_u32_offload *cls_u32) 9356 { 9357 switch (cls_u32->command) { 9358 case TC_CLSU32_NEW_KNODE: 9359 case TC_CLSU32_REPLACE_KNODE: 9360 return ixgbe_configure_clsu32(adapter, cls_u32); 9361 case TC_CLSU32_DELETE_KNODE: 9362 return ixgbe_delete_clsu32(adapter, cls_u32); 9363 case TC_CLSU32_NEW_HNODE: 9364 case TC_CLSU32_REPLACE_HNODE: 9365 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9366 case TC_CLSU32_DELETE_HNODE: 9367 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9368 default: 9369 return -EOPNOTSUPP; 9370 } 9371 } 9372 9373 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9374 void *cb_priv) 9375 { 9376 struct ixgbe_adapter *adapter = cb_priv; 9377 9378 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9379 return -EOPNOTSUPP; 9380 9381 switch (type) { 9382 case TC_SETUP_CLSU32: 9383 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9384 default: 9385 return -EOPNOTSUPP; 9386 } 9387 } 9388 9389 static int ixgbe_setup_tc_block(struct net_device *dev, 9390 struct tc_block_offload *f) 9391 { 9392 struct ixgbe_adapter *adapter = netdev_priv(dev); 9393 9394 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9395 return -EOPNOTSUPP; 9396 9397 switch (f->command) { 9398 case TC_BLOCK_BIND: 9399 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9400 adapter, adapter); 9401 case TC_BLOCK_UNBIND: 9402 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9403 adapter); 9404 return 0; 9405 default: 9406 return -EOPNOTSUPP; 9407 } 9408 } 9409 9410 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9411 struct tc_mqprio_qopt *mqprio) 9412 { 9413 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9414 return ixgbe_setup_tc(dev, mqprio->num_tc); 9415 } 9416 9417 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9418 void *type_data) 9419 { 9420 switch (type) { 9421 case TC_SETUP_BLOCK: 9422 return ixgbe_setup_tc_block(dev, type_data); 9423 case TC_SETUP_QDISC_MQPRIO: 9424 return ixgbe_setup_tc_mqprio(dev, type_data); 9425 default: 9426 return -EOPNOTSUPP; 9427 } 9428 } 9429 9430 #ifdef CONFIG_PCI_IOV 9431 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9432 { 9433 struct net_device *netdev = adapter->netdev; 9434 9435 rtnl_lock(); 9436 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9437 rtnl_unlock(); 9438 } 9439 9440 #endif 9441 void ixgbe_do_reset(struct net_device *netdev) 9442 { 9443 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9444 9445 if (netif_running(netdev)) 9446 ixgbe_reinit_locked(adapter); 9447 else 9448 ixgbe_reset(adapter); 9449 } 9450 9451 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9452 netdev_features_t features) 9453 { 9454 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9455 9456 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9457 if (!(features & NETIF_F_RXCSUM)) 9458 features &= ~NETIF_F_LRO; 9459 9460 /* Turn off LRO if not RSC capable */ 9461 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9462 features &= ~NETIF_F_LRO; 9463 9464 return features; 9465 } 9466 9467 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9468 { 9469 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9470 num_online_cpus()); 9471 9472 /* go back to full RSS if we're not running SR-IOV */ 9473 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9474 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9475 IXGBE_FLAG_SRIOV_ENABLED); 9476 9477 adapter->ring_feature[RING_F_RSS].limit = rss; 9478 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9479 9480 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9481 } 9482 9483 static int ixgbe_set_features(struct net_device *netdev, 9484 netdev_features_t features) 9485 { 9486 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9487 netdev_features_t changed = netdev->features ^ features; 9488 bool need_reset = false; 9489 9490 /* Make sure RSC matches LRO, reset if change */ 9491 if (!(features & NETIF_F_LRO)) { 9492 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9493 need_reset = true; 9494 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9495 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9496 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9497 if (adapter->rx_itr_setting == 1 || 9498 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9499 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9500 need_reset = true; 9501 } else if ((changed ^ features) & NETIF_F_LRO) { 9502 e_info(probe, "rx-usecs set too low, " 9503 "disabling RSC\n"); 9504 } 9505 } 9506 9507 /* 9508 * Check if Flow Director n-tuple support or hw_tc support was 9509 * enabled or disabled. If the state changed, we need to reset. 9510 */ 9511 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9512 /* turn off ATR, enable perfect filters and reset */ 9513 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9514 need_reset = true; 9515 9516 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9517 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9518 } else { 9519 /* turn off perfect filters, enable ATR and reset */ 9520 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9521 need_reset = true; 9522 9523 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9524 9525 /* We cannot enable ATR if SR-IOV is enabled */ 9526 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9527 /* We cannot enable ATR if we have 2 or more tcs */ 9528 (adapter->hw_tcs > 1) || 9529 /* We cannot enable ATR if RSS is disabled */ 9530 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9531 /* A sample rate of 0 indicates ATR disabled */ 9532 (!adapter->atr_sample_rate)) 9533 ; /* do nothing not supported */ 9534 else /* otherwise supported and set the flag */ 9535 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9536 } 9537 9538 if (changed & NETIF_F_RXALL) 9539 need_reset = true; 9540 9541 netdev->features = features; 9542 9543 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9544 if (features & NETIF_F_RXCSUM) { 9545 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9546 } else { 9547 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9548 9549 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9550 } 9551 } 9552 9553 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9554 if (features & NETIF_F_RXCSUM) { 9555 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9556 } else { 9557 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9558 9559 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9560 } 9561 } 9562 9563 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9564 ixgbe_reset_l2fw_offload(adapter); 9565 else if (need_reset) 9566 ixgbe_do_reset(netdev); 9567 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9568 NETIF_F_HW_VLAN_CTAG_FILTER)) 9569 ixgbe_set_rx_mode(netdev); 9570 9571 return 0; 9572 } 9573 9574 /** 9575 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9576 * @dev: The port's netdev 9577 * @ti: Tunnel endpoint information 9578 **/ 9579 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9580 struct udp_tunnel_info *ti) 9581 { 9582 struct ixgbe_adapter *adapter = netdev_priv(dev); 9583 struct ixgbe_hw *hw = &adapter->hw; 9584 __be16 port = ti->port; 9585 u32 port_shift = 0; 9586 u32 reg; 9587 9588 if (ti->sa_family != AF_INET) 9589 return; 9590 9591 switch (ti->type) { 9592 case UDP_TUNNEL_TYPE_VXLAN: 9593 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9594 return; 9595 9596 if (adapter->vxlan_port == port) 9597 return; 9598 9599 if (adapter->vxlan_port) { 9600 netdev_info(dev, 9601 "VXLAN port %d set, not adding port %d\n", 9602 ntohs(adapter->vxlan_port), 9603 ntohs(port)); 9604 return; 9605 } 9606 9607 adapter->vxlan_port = port; 9608 break; 9609 case UDP_TUNNEL_TYPE_GENEVE: 9610 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9611 return; 9612 9613 if (adapter->geneve_port == port) 9614 return; 9615 9616 if (adapter->geneve_port) { 9617 netdev_info(dev, 9618 "GENEVE port %d set, not adding port %d\n", 9619 ntohs(adapter->geneve_port), 9620 ntohs(port)); 9621 return; 9622 } 9623 9624 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9625 adapter->geneve_port = port; 9626 break; 9627 default: 9628 return; 9629 } 9630 9631 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9632 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9633 } 9634 9635 /** 9636 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9637 * @dev: The port's netdev 9638 * @ti: Tunnel endpoint information 9639 **/ 9640 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9641 struct udp_tunnel_info *ti) 9642 { 9643 struct ixgbe_adapter *adapter = netdev_priv(dev); 9644 u32 port_mask; 9645 9646 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9647 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9648 return; 9649 9650 if (ti->sa_family != AF_INET) 9651 return; 9652 9653 switch (ti->type) { 9654 case UDP_TUNNEL_TYPE_VXLAN: 9655 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9656 return; 9657 9658 if (adapter->vxlan_port != ti->port) { 9659 netdev_info(dev, "VXLAN port %d not found\n", 9660 ntohs(ti->port)); 9661 return; 9662 } 9663 9664 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9665 break; 9666 case UDP_TUNNEL_TYPE_GENEVE: 9667 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9668 return; 9669 9670 if (adapter->geneve_port != ti->port) { 9671 netdev_info(dev, "GENEVE port %d not found\n", 9672 ntohs(ti->port)); 9673 return; 9674 } 9675 9676 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9677 break; 9678 default: 9679 return; 9680 } 9681 9682 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9683 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9684 } 9685 9686 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9687 struct net_device *dev, 9688 const unsigned char *addr, u16 vid, 9689 u16 flags) 9690 { 9691 /* guarantee we can provide a unique filter for the unicast address */ 9692 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9693 struct ixgbe_adapter *adapter = netdev_priv(dev); 9694 u16 pool = VMDQ_P(0); 9695 9696 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9697 return -ENOMEM; 9698 } 9699 9700 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9701 } 9702 9703 /** 9704 * ixgbe_configure_bridge_mode - set various bridge modes 9705 * @adapter: the private structure 9706 * @mode: requested bridge mode 9707 * 9708 * Configure some settings require for various bridge modes. 9709 **/ 9710 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9711 __u16 mode) 9712 { 9713 struct ixgbe_hw *hw = &adapter->hw; 9714 unsigned int p, num_pools; 9715 u32 vmdctl; 9716 9717 switch (mode) { 9718 case BRIDGE_MODE_VEPA: 9719 /* disable Tx loopback, rely on switch hairpin mode */ 9720 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9721 9722 /* must enable Rx switching replication to allow multicast 9723 * packet reception on all VFs, and to enable source address 9724 * pruning. 9725 */ 9726 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9727 vmdctl |= IXGBE_VT_CTL_REPLEN; 9728 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9729 9730 /* enable Rx source address pruning. Note, this requires 9731 * replication to be enabled or else it does nothing. 9732 */ 9733 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9734 for (p = 0; p < num_pools; p++) { 9735 if (hw->mac.ops.set_source_address_pruning) 9736 hw->mac.ops.set_source_address_pruning(hw, 9737 true, 9738 p); 9739 } 9740 break; 9741 case BRIDGE_MODE_VEB: 9742 /* enable Tx loopback for internal VF/PF communication */ 9743 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9744 IXGBE_PFDTXGSWC_VT_LBEN); 9745 9746 /* disable Rx switching replication unless we have SR-IOV 9747 * virtual functions 9748 */ 9749 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9750 if (!adapter->num_vfs) 9751 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9752 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9753 9754 /* disable Rx source address pruning, since we don't expect to 9755 * be receiving external loopback of our transmitted frames. 9756 */ 9757 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9758 for (p = 0; p < num_pools; p++) { 9759 if (hw->mac.ops.set_source_address_pruning) 9760 hw->mac.ops.set_source_address_pruning(hw, 9761 false, 9762 p); 9763 } 9764 break; 9765 default: 9766 return -EINVAL; 9767 } 9768 9769 adapter->bridge_mode = mode; 9770 9771 e_info(drv, "enabling bridge mode: %s\n", 9772 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9773 9774 return 0; 9775 } 9776 9777 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9778 struct nlmsghdr *nlh, u16 flags) 9779 { 9780 struct ixgbe_adapter *adapter = netdev_priv(dev); 9781 struct nlattr *attr, *br_spec; 9782 int rem; 9783 9784 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9785 return -EOPNOTSUPP; 9786 9787 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9788 if (!br_spec) 9789 return -EINVAL; 9790 9791 nla_for_each_nested(attr, br_spec, rem) { 9792 int status; 9793 __u16 mode; 9794 9795 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9796 continue; 9797 9798 if (nla_len(attr) < sizeof(mode)) 9799 return -EINVAL; 9800 9801 mode = nla_get_u16(attr); 9802 status = ixgbe_configure_bridge_mode(adapter, mode); 9803 if (status) 9804 return status; 9805 9806 break; 9807 } 9808 9809 return 0; 9810 } 9811 9812 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9813 struct net_device *dev, 9814 u32 filter_mask, int nlflags) 9815 { 9816 struct ixgbe_adapter *adapter = netdev_priv(dev); 9817 9818 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9819 return 0; 9820 9821 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9822 adapter->bridge_mode, 0, 0, nlflags, 9823 filter_mask, NULL); 9824 } 9825 9826 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9827 { 9828 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9829 struct ixgbe_fwd_adapter *accel; 9830 int tcs = adapter->hw_tcs ? : 1; 9831 int pool, err; 9832 9833 /* The hardware supported by ixgbe only filters on the destination MAC 9834 * address. In order to avoid issues we only support offloading modes 9835 * where the hardware can actually provide the functionality. 9836 */ 9837 if (!macvlan_supports_dest_filter(vdev)) 9838 return ERR_PTR(-EMEDIUMTYPE); 9839 9840 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9841 if (pool == adapter->num_rx_pools) { 9842 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 9843 u16 reserved_pools; 9844 9845 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9846 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9847 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 9848 return ERR_PTR(-EBUSY); 9849 9850 /* Hardware has a limited number of available pools. Each VF, 9851 * and the PF require a pool. Check to ensure we don't 9852 * attempt to use more then the available number of pools. 9853 */ 9854 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9855 return ERR_PTR(-EBUSY); 9856 9857 /* Enable VMDq flag so device will be set in VM mode */ 9858 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 9859 IXGBE_FLAG_SRIOV_ENABLED; 9860 9861 /* Try to reserve as many queues per pool as possible, 9862 * we start with the configurations that support 4 queues 9863 * per pools, followed by 2, and then by just 1 per pool. 9864 */ 9865 if (used_pools < 32 && adapter->num_rx_pools < 16) 9866 reserved_pools = min_t(u16, 9867 32 - used_pools, 9868 16 - adapter->num_rx_pools); 9869 else if (adapter->num_rx_pools < 32) 9870 reserved_pools = min_t(u16, 9871 64 - used_pools, 9872 32 - adapter->num_rx_pools); 9873 else 9874 reserved_pools = 64 - used_pools; 9875 9876 9877 if (!reserved_pools) 9878 return ERR_PTR(-EBUSY); 9879 9880 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 9881 9882 /* Force reinit of ring allocation with VMDQ enabled */ 9883 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9884 if (err) 9885 return ERR_PTR(err); 9886 9887 if (pool >= adapter->num_rx_pools) 9888 return ERR_PTR(-ENOMEM); 9889 } 9890 9891 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 9892 if (!accel) 9893 return ERR_PTR(-ENOMEM); 9894 9895 set_bit(pool, adapter->fwd_bitmask); 9896 accel->pool = pool; 9897 accel->netdev = vdev; 9898 9899 if (!netif_running(pdev)) 9900 return accel; 9901 9902 err = ixgbe_fwd_ring_up(adapter, accel); 9903 if (err) 9904 return ERR_PTR(err); 9905 9906 return accel; 9907 } 9908 9909 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9910 { 9911 struct ixgbe_fwd_adapter *accel = priv; 9912 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9913 unsigned int rxbase = accel->rx_base_queue; 9914 unsigned int i; 9915 9916 /* delete unicast filter associated with offloaded interface */ 9917 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 9918 VMDQ_P(accel->pool)); 9919 9920 /* Allow remaining Rx packets to get flushed out of the 9921 * Rx FIFO before we drop the netdev for the ring. 9922 */ 9923 usleep_range(10000, 20000); 9924 9925 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 9926 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 9927 struct ixgbe_q_vector *qv = ring->q_vector; 9928 9929 /* Make sure we aren't processing any packets and clear 9930 * netdev to shut down the ring. 9931 */ 9932 if (netif_running(adapter->netdev)) 9933 napi_synchronize(&qv->napi); 9934 ring->netdev = NULL; 9935 } 9936 9937 clear_bit(accel->pool, adapter->fwd_bitmask); 9938 kfree(accel); 9939 } 9940 9941 #define IXGBE_MAX_MAC_HDR_LEN 127 9942 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9943 9944 static netdev_features_t 9945 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9946 netdev_features_t features) 9947 { 9948 unsigned int network_hdr_len, mac_hdr_len; 9949 9950 /* Make certain the headers can be described by a context descriptor */ 9951 mac_hdr_len = skb_network_header(skb) - skb->data; 9952 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9953 return features & ~(NETIF_F_HW_CSUM | 9954 NETIF_F_SCTP_CRC | 9955 NETIF_F_HW_VLAN_CTAG_TX | 9956 NETIF_F_TSO | 9957 NETIF_F_TSO6); 9958 9959 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9960 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9961 return features & ~(NETIF_F_HW_CSUM | 9962 NETIF_F_SCTP_CRC | 9963 NETIF_F_TSO | 9964 NETIF_F_TSO6); 9965 9966 /* We can only support IPV4 TSO in tunnels if we can mangle the 9967 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9968 * IPsec offoad sets skb->encapsulation but still can handle 9969 * the TSO, so it's the exception. 9970 */ 9971 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 9972 #ifdef CONFIG_XFRM 9973 if (!skb->sp) 9974 #endif 9975 features &= ~NETIF_F_TSO; 9976 } 9977 9978 return features; 9979 } 9980 9981 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9982 { 9983 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9984 struct ixgbe_adapter *adapter = netdev_priv(dev); 9985 struct bpf_prog *old_prog; 9986 9987 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9988 return -EINVAL; 9989 9990 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9991 return -EINVAL; 9992 9993 /* verify ixgbe ring attributes are sufficient for XDP */ 9994 for (i = 0; i < adapter->num_rx_queues; i++) { 9995 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9996 9997 if (ring_is_rsc_enabled(ring)) 9998 return -EINVAL; 9999 10000 if (frame_size > ixgbe_rx_bufsz(ring)) 10001 return -EINVAL; 10002 } 10003 10004 if (nr_cpu_ids > MAX_XDP_QUEUES) 10005 return -ENOMEM; 10006 10007 old_prog = xchg(&adapter->xdp_prog, prog); 10008 10009 /* If transitioning XDP modes reconfigure rings */ 10010 if (!!prog != !!old_prog) { 10011 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10012 10013 if (err) { 10014 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10015 return -EINVAL; 10016 } 10017 } else { 10018 for (i = 0; i < adapter->num_rx_queues; i++) 10019 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 10020 } 10021 10022 if (old_prog) 10023 bpf_prog_put(old_prog); 10024 10025 return 0; 10026 } 10027 10028 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10029 { 10030 struct ixgbe_adapter *adapter = netdev_priv(dev); 10031 10032 switch (xdp->command) { 10033 case XDP_SETUP_PROG: 10034 return ixgbe_xdp_setup(dev, xdp->prog); 10035 case XDP_QUERY_PROG: 10036 xdp->prog_attached = !!(adapter->xdp_prog); 10037 xdp->prog_id = adapter->xdp_prog ? 10038 adapter->xdp_prog->aux->id : 0; 10039 return 0; 10040 default: 10041 return -EINVAL; 10042 } 10043 } 10044 10045 static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_frame *xdpf) 10046 { 10047 struct ixgbe_adapter *adapter = netdev_priv(dev); 10048 struct ixgbe_ring *ring; 10049 int err; 10050 10051 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10052 return -ENETDOWN; 10053 10054 /* During program transitions its possible adapter->xdp_prog is assigned 10055 * but ring has not been configured yet. In this case simply abort xmit. 10056 */ 10057 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10058 if (unlikely(!ring)) 10059 return -ENXIO; 10060 10061 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10062 if (err != IXGBE_XDP_TX) 10063 return -ENOSPC; 10064 10065 return 0; 10066 } 10067 10068 static void ixgbe_xdp_flush(struct net_device *dev) 10069 { 10070 struct ixgbe_adapter *adapter = netdev_priv(dev); 10071 struct ixgbe_ring *ring; 10072 10073 /* Its possible the device went down between xdp xmit and flush so 10074 * we need to ensure device is still up. 10075 */ 10076 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10077 return; 10078 10079 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10080 if (unlikely(!ring)) 10081 return; 10082 10083 /* Force memory writes to complete before letting h/w know there 10084 * are new descriptors to fetch. 10085 */ 10086 wmb(); 10087 writel(ring->next_to_use, ring->tail); 10088 10089 return; 10090 } 10091 10092 static const struct net_device_ops ixgbe_netdev_ops = { 10093 .ndo_open = ixgbe_open, 10094 .ndo_stop = ixgbe_close, 10095 .ndo_start_xmit = ixgbe_xmit_frame, 10096 .ndo_select_queue = ixgbe_select_queue, 10097 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10098 .ndo_validate_addr = eth_validate_addr, 10099 .ndo_set_mac_address = ixgbe_set_mac, 10100 .ndo_change_mtu = ixgbe_change_mtu, 10101 .ndo_tx_timeout = ixgbe_tx_timeout, 10102 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10103 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10104 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10105 .ndo_do_ioctl = ixgbe_ioctl, 10106 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10107 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10108 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10109 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10110 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10111 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10112 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10113 .ndo_get_stats64 = ixgbe_get_stats64, 10114 .ndo_setup_tc = __ixgbe_setup_tc, 10115 #ifdef CONFIG_NET_POLL_CONTROLLER 10116 .ndo_poll_controller = ixgbe_netpoll, 10117 #endif 10118 #ifdef IXGBE_FCOE 10119 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10120 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10121 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10122 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10123 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10124 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10125 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10126 #endif /* IXGBE_FCOE */ 10127 .ndo_set_features = ixgbe_set_features, 10128 .ndo_fix_features = ixgbe_fix_features, 10129 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10130 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10131 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10132 .ndo_dfwd_add_station = ixgbe_fwd_add, 10133 .ndo_dfwd_del_station = ixgbe_fwd_del, 10134 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10135 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10136 .ndo_features_check = ixgbe_features_check, 10137 .ndo_bpf = ixgbe_xdp, 10138 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10139 .ndo_xdp_flush = ixgbe_xdp_flush, 10140 }; 10141 10142 /** 10143 * ixgbe_enumerate_functions - Get the number of ports this device has 10144 * @adapter: adapter structure 10145 * 10146 * This function enumerates the phsyical functions co-located on a single slot, 10147 * in order to determine how many ports a device has. This is most useful in 10148 * determining the required GT/s of PCIe bandwidth necessary for optimal 10149 * performance. 10150 **/ 10151 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10152 { 10153 struct pci_dev *entry, *pdev = adapter->pdev; 10154 int physfns = 0; 10155 10156 /* Some cards can not use the generic count PCIe functions method, 10157 * because they are behind a parent switch, so we hardcode these with 10158 * the correct number of functions. 10159 */ 10160 if (ixgbe_pcie_from_parent(&adapter->hw)) 10161 physfns = 4; 10162 10163 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10164 /* don't count virtual functions */ 10165 if (entry->is_virtfn) 10166 continue; 10167 10168 /* When the devices on the bus don't all match our device ID, 10169 * we can't reliably determine the correct number of 10170 * functions. This can occur if a function has been direct 10171 * attached to a virtual machine using VT-d, for example. In 10172 * this case, simply return -1 to indicate this. 10173 */ 10174 if ((entry->vendor != pdev->vendor) || 10175 (entry->device != pdev->device)) 10176 return -1; 10177 10178 physfns++; 10179 } 10180 10181 return physfns; 10182 } 10183 10184 /** 10185 * ixgbe_wol_supported - Check whether device supports WoL 10186 * @adapter: the adapter private structure 10187 * @device_id: the device ID 10188 * @subdevice_id: the subsystem device ID 10189 * 10190 * This function is used by probe and ethtool to determine 10191 * which devices have WoL support 10192 * 10193 **/ 10194 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10195 u16 subdevice_id) 10196 { 10197 struct ixgbe_hw *hw = &adapter->hw; 10198 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10199 10200 /* WOL not supported on 82598 */ 10201 if (hw->mac.type == ixgbe_mac_82598EB) 10202 return false; 10203 10204 /* check eeprom to see if WOL is enabled for X540 and newer */ 10205 if (hw->mac.type >= ixgbe_mac_X540) { 10206 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10207 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10208 (hw->bus.func == 0))) 10209 return true; 10210 } 10211 10212 /* WOL is determined based on device IDs for 82599 MACs */ 10213 switch (device_id) { 10214 case IXGBE_DEV_ID_82599_SFP: 10215 /* Only these subdevices could supports WOL */ 10216 switch (subdevice_id) { 10217 case IXGBE_SUBDEV_ID_82599_560FLR: 10218 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10219 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10220 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10221 /* only support first port */ 10222 if (hw->bus.func != 0) 10223 break; 10224 /* fall through */ 10225 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10226 case IXGBE_SUBDEV_ID_82599_SFP: 10227 case IXGBE_SUBDEV_ID_82599_RNDC: 10228 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10229 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10230 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10231 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10232 return true; 10233 } 10234 break; 10235 case IXGBE_DEV_ID_82599EN_SFP: 10236 /* Only these subdevices support WOL */ 10237 switch (subdevice_id) { 10238 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10239 return true; 10240 } 10241 break; 10242 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10243 /* All except this subdevice support WOL */ 10244 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10245 return true; 10246 break; 10247 case IXGBE_DEV_ID_82599_KX4: 10248 return true; 10249 default: 10250 break; 10251 } 10252 10253 return false; 10254 } 10255 10256 /** 10257 * ixgbe_set_fw_version - Set FW version 10258 * @adapter: the adapter private structure 10259 * 10260 * This function is used by probe and ethtool to determine the FW version to 10261 * format to display. The FW version is taken from the EEPROM/NVM. 10262 */ 10263 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10264 { 10265 struct ixgbe_hw *hw = &adapter->hw; 10266 struct ixgbe_nvm_version nvm_ver; 10267 10268 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10269 if (nvm_ver.oem_valid) { 10270 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10271 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10272 nvm_ver.oem_release); 10273 return; 10274 } 10275 10276 ixgbe_get_etk_id(hw, &nvm_ver); 10277 ixgbe_get_orom_version(hw, &nvm_ver); 10278 10279 if (nvm_ver.or_valid) { 10280 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10281 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10282 nvm_ver.or_build, nvm_ver.or_patch); 10283 return; 10284 } 10285 10286 /* Set ETrack ID format */ 10287 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10288 "0x%08x", nvm_ver.etk_id); 10289 } 10290 10291 /** 10292 * ixgbe_probe - Device Initialization Routine 10293 * @pdev: PCI device information struct 10294 * @ent: entry in ixgbe_pci_tbl 10295 * 10296 * Returns 0 on success, negative on failure 10297 * 10298 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10299 * The OS initialization, configuring of the adapter private structure, 10300 * and a hardware reset occur. 10301 **/ 10302 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10303 { 10304 struct net_device *netdev; 10305 struct ixgbe_adapter *adapter = NULL; 10306 struct ixgbe_hw *hw; 10307 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10308 int i, err, pci_using_dac, expected_gts; 10309 unsigned int indices = MAX_TX_QUEUES; 10310 u8 part_str[IXGBE_PBANUM_LENGTH]; 10311 bool disable_dev = false; 10312 #ifdef IXGBE_FCOE 10313 u16 device_caps; 10314 #endif 10315 u32 eec; 10316 10317 /* Catch broken hardware that put the wrong VF device ID in 10318 * the PCIe SR-IOV capability. 10319 */ 10320 if (pdev->is_virtfn) { 10321 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10322 pci_name(pdev), pdev->vendor, pdev->device); 10323 return -EINVAL; 10324 } 10325 10326 err = pci_enable_device_mem(pdev); 10327 if (err) 10328 return err; 10329 10330 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10331 pci_using_dac = 1; 10332 } else { 10333 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10334 if (err) { 10335 dev_err(&pdev->dev, 10336 "No usable DMA configuration, aborting\n"); 10337 goto err_dma; 10338 } 10339 pci_using_dac = 0; 10340 } 10341 10342 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10343 if (err) { 10344 dev_err(&pdev->dev, 10345 "pci_request_selected_regions failed 0x%x\n", err); 10346 goto err_pci_reg; 10347 } 10348 10349 pci_enable_pcie_error_reporting(pdev); 10350 10351 pci_set_master(pdev); 10352 pci_save_state(pdev); 10353 10354 if (ii->mac == ixgbe_mac_82598EB) { 10355 #ifdef CONFIG_IXGBE_DCB 10356 /* 8 TC w/ 4 queues per TC */ 10357 indices = 4 * MAX_TRAFFIC_CLASS; 10358 #else 10359 indices = IXGBE_MAX_RSS_INDICES; 10360 #endif 10361 } 10362 10363 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10364 if (!netdev) { 10365 err = -ENOMEM; 10366 goto err_alloc_etherdev; 10367 } 10368 10369 SET_NETDEV_DEV(netdev, &pdev->dev); 10370 10371 adapter = netdev_priv(netdev); 10372 10373 adapter->netdev = netdev; 10374 adapter->pdev = pdev; 10375 hw = &adapter->hw; 10376 hw->back = adapter; 10377 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10378 10379 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10380 pci_resource_len(pdev, 0)); 10381 adapter->io_addr = hw->hw_addr; 10382 if (!hw->hw_addr) { 10383 err = -EIO; 10384 goto err_ioremap; 10385 } 10386 10387 netdev->netdev_ops = &ixgbe_netdev_ops; 10388 ixgbe_set_ethtool_ops(netdev); 10389 netdev->watchdog_timeo = 5 * HZ; 10390 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10391 10392 /* Setup hw api */ 10393 hw->mac.ops = *ii->mac_ops; 10394 hw->mac.type = ii->mac; 10395 hw->mvals = ii->mvals; 10396 if (ii->link_ops) 10397 hw->link.ops = *ii->link_ops; 10398 10399 /* EEPROM */ 10400 hw->eeprom.ops = *ii->eeprom_ops; 10401 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10402 if (ixgbe_removed(hw->hw_addr)) { 10403 err = -EIO; 10404 goto err_ioremap; 10405 } 10406 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10407 if (!(eec & BIT(8))) 10408 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10409 10410 /* PHY */ 10411 hw->phy.ops = *ii->phy_ops; 10412 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10413 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10414 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10415 hw->phy.mdio.mmds = 0; 10416 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10417 hw->phy.mdio.dev = netdev; 10418 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10419 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10420 10421 /* setup the private structure */ 10422 err = ixgbe_sw_init(adapter, ii); 10423 if (err) 10424 goto err_sw_init; 10425 10426 /* Make sure the SWFW semaphore is in a valid state */ 10427 if (hw->mac.ops.init_swfw_sync) 10428 hw->mac.ops.init_swfw_sync(hw); 10429 10430 /* Make it possible the adapter to be woken up via WOL */ 10431 switch (adapter->hw.mac.type) { 10432 case ixgbe_mac_82599EB: 10433 case ixgbe_mac_X540: 10434 case ixgbe_mac_X550: 10435 case ixgbe_mac_X550EM_x: 10436 case ixgbe_mac_x550em_a: 10437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10438 break; 10439 default: 10440 break; 10441 } 10442 10443 /* 10444 * If there is a fan on this device and it has failed log the 10445 * failure. 10446 */ 10447 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10448 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10449 if (esdp & IXGBE_ESDP_SDP1) 10450 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10451 } 10452 10453 if (allow_unsupported_sfp) 10454 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10455 10456 /* reset_hw fills in the perm_addr as well */ 10457 hw->phy.reset_if_overtemp = true; 10458 err = hw->mac.ops.reset_hw(hw); 10459 hw->phy.reset_if_overtemp = false; 10460 ixgbe_set_eee_capable(adapter); 10461 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10462 err = 0; 10463 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10464 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10465 e_dev_err("Reload the driver after installing a supported module.\n"); 10466 goto err_sw_init; 10467 } else if (err) { 10468 e_dev_err("HW Init failed: %d\n", err); 10469 goto err_sw_init; 10470 } 10471 10472 #ifdef CONFIG_PCI_IOV 10473 /* SR-IOV not supported on the 82598 */ 10474 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10475 goto skip_sriov; 10476 /* Mailbox */ 10477 ixgbe_init_mbx_params_pf(hw); 10478 hw->mbx.ops = ii->mbx_ops; 10479 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10480 ixgbe_enable_sriov(adapter, max_vfs); 10481 skip_sriov: 10482 10483 #endif 10484 netdev->features = NETIF_F_SG | 10485 NETIF_F_TSO | 10486 NETIF_F_TSO6 | 10487 NETIF_F_RXHASH | 10488 NETIF_F_RXCSUM | 10489 NETIF_F_HW_CSUM; 10490 10491 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10492 NETIF_F_GSO_GRE_CSUM | \ 10493 NETIF_F_GSO_IPXIP4 | \ 10494 NETIF_F_GSO_IPXIP6 | \ 10495 NETIF_F_GSO_UDP_TUNNEL | \ 10496 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10497 10498 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10499 netdev->features |= NETIF_F_GSO_PARTIAL | 10500 IXGBE_GSO_PARTIAL_FEATURES; 10501 10502 if (hw->mac.type >= ixgbe_mac_82599EB) 10503 netdev->features |= NETIF_F_SCTP_CRC; 10504 10505 /* copy netdev features into list of user selectable features */ 10506 netdev->hw_features |= netdev->features | 10507 NETIF_F_HW_VLAN_CTAG_FILTER | 10508 NETIF_F_HW_VLAN_CTAG_RX | 10509 NETIF_F_HW_VLAN_CTAG_TX | 10510 NETIF_F_RXALL | 10511 NETIF_F_HW_L2FW_DOFFLOAD; 10512 10513 if (hw->mac.type >= ixgbe_mac_82599EB) 10514 netdev->hw_features |= NETIF_F_NTUPLE | 10515 NETIF_F_HW_TC; 10516 10517 if (pci_using_dac) 10518 netdev->features |= NETIF_F_HIGHDMA; 10519 10520 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10521 netdev->hw_enc_features |= netdev->vlan_features; 10522 netdev->mpls_features |= NETIF_F_SG | 10523 NETIF_F_TSO | 10524 NETIF_F_TSO6 | 10525 NETIF_F_HW_CSUM; 10526 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10527 10528 /* set this bit last since it cannot be part of vlan_features */ 10529 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10530 NETIF_F_HW_VLAN_CTAG_RX | 10531 NETIF_F_HW_VLAN_CTAG_TX; 10532 10533 netdev->priv_flags |= IFF_UNICAST_FLT; 10534 netdev->priv_flags |= IFF_SUPP_NOFCS; 10535 10536 /* MTU range: 68 - 9710 */ 10537 netdev->min_mtu = ETH_MIN_MTU; 10538 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10539 10540 #ifdef CONFIG_IXGBE_DCB 10541 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10542 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10543 #endif 10544 10545 #ifdef IXGBE_FCOE 10546 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10547 unsigned int fcoe_l; 10548 10549 if (hw->mac.ops.get_device_caps) { 10550 hw->mac.ops.get_device_caps(hw, &device_caps); 10551 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10552 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10553 } 10554 10555 10556 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10557 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10558 10559 netdev->features |= NETIF_F_FSO | 10560 NETIF_F_FCOE_CRC; 10561 10562 netdev->vlan_features |= NETIF_F_FSO | 10563 NETIF_F_FCOE_CRC | 10564 NETIF_F_FCOE_MTU; 10565 } 10566 #endif /* IXGBE_FCOE */ 10567 ixgbe_init_ipsec_offload(adapter); 10568 10569 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10570 netdev->hw_features |= NETIF_F_LRO; 10571 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10572 netdev->features |= NETIF_F_LRO; 10573 10574 /* make sure the EEPROM is good */ 10575 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10576 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10577 err = -EIO; 10578 goto err_sw_init; 10579 } 10580 10581 eth_platform_get_mac_address(&adapter->pdev->dev, 10582 adapter->hw.mac.perm_addr); 10583 10584 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10585 10586 if (!is_valid_ether_addr(netdev->dev_addr)) { 10587 e_dev_err("invalid MAC address\n"); 10588 err = -EIO; 10589 goto err_sw_init; 10590 } 10591 10592 /* Set hw->mac.addr to permanent MAC address */ 10593 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10594 ixgbe_mac_set_default_filter(adapter); 10595 10596 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10597 10598 if (ixgbe_removed(hw->hw_addr)) { 10599 err = -EIO; 10600 goto err_sw_init; 10601 } 10602 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10603 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10604 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10605 10606 err = ixgbe_init_interrupt_scheme(adapter); 10607 if (err) 10608 goto err_sw_init; 10609 10610 for (i = 0; i < adapter->num_rx_queues; i++) 10611 u64_stats_init(&adapter->rx_ring[i]->syncp); 10612 for (i = 0; i < adapter->num_tx_queues; i++) 10613 u64_stats_init(&adapter->tx_ring[i]->syncp); 10614 for (i = 0; i < adapter->num_xdp_queues; i++) 10615 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10616 10617 /* WOL not supported for all devices */ 10618 adapter->wol = 0; 10619 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10620 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10621 pdev->subsystem_device); 10622 if (hw->wol_enabled) 10623 adapter->wol = IXGBE_WUFC_MAG; 10624 10625 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10626 10627 /* save off EEPROM version number */ 10628 ixgbe_set_fw_version(adapter); 10629 10630 /* pick up the PCI bus settings for reporting later */ 10631 if (ixgbe_pcie_from_parent(hw)) 10632 ixgbe_get_parent_bus_info(adapter); 10633 else 10634 hw->mac.ops.get_bus_info(hw); 10635 10636 /* calculate the expected PCIe bandwidth required for optimal 10637 * performance. Note that some older parts will never have enough 10638 * bandwidth due to being older generation PCIe parts. We clamp these 10639 * parts to ensure no warning is displayed if it can't be fixed. 10640 */ 10641 switch (hw->mac.type) { 10642 case ixgbe_mac_82598EB: 10643 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10644 break; 10645 default: 10646 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10647 break; 10648 } 10649 10650 /* don't check link if we failed to enumerate functions */ 10651 if (expected_gts > 0) 10652 ixgbe_check_minimum_link(adapter, expected_gts); 10653 10654 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10655 if (err) 10656 strlcpy(part_str, "Unknown", sizeof(part_str)); 10657 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10658 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10659 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10660 part_str); 10661 else 10662 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10663 hw->mac.type, hw->phy.type, part_str); 10664 10665 e_dev_info("%pM\n", netdev->dev_addr); 10666 10667 /* reset the hardware with the new settings */ 10668 err = hw->mac.ops.start_hw(hw); 10669 if (err == IXGBE_ERR_EEPROM_VERSION) { 10670 /* We are running on a pre-production device, log a warning */ 10671 e_dev_warn("This device is a pre-production adapter/LOM. " 10672 "Please be aware there may be issues associated " 10673 "with your hardware. If you are experiencing " 10674 "problems please contact your Intel or hardware " 10675 "representative who provided you with this " 10676 "hardware.\n"); 10677 } 10678 strcpy(netdev->name, "eth%d"); 10679 pci_set_drvdata(pdev, adapter); 10680 err = register_netdev(netdev); 10681 if (err) 10682 goto err_register; 10683 10684 10685 /* power down the optics for 82599 SFP+ fiber */ 10686 if (hw->mac.ops.disable_tx_laser) 10687 hw->mac.ops.disable_tx_laser(hw); 10688 10689 /* carrier off reporting is important to ethtool even BEFORE open */ 10690 netif_carrier_off(netdev); 10691 10692 #ifdef CONFIG_IXGBE_DCA 10693 if (dca_add_requester(&pdev->dev) == 0) { 10694 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10695 ixgbe_setup_dca(adapter); 10696 } 10697 #endif 10698 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10699 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10700 for (i = 0; i < adapter->num_vfs; i++) 10701 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10702 } 10703 10704 /* firmware requires driver version to be 0xFFFFFFFF 10705 * since os does not support feature 10706 */ 10707 if (hw->mac.ops.set_fw_drv_ver) 10708 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10709 sizeof(ixgbe_driver_version) - 1, 10710 ixgbe_driver_version); 10711 10712 /* add san mac addr to netdev */ 10713 ixgbe_add_sanmac_netdev(netdev); 10714 10715 e_dev_info("%s\n", ixgbe_default_device_descr); 10716 10717 #ifdef CONFIG_IXGBE_HWMON 10718 if (ixgbe_sysfs_init(adapter)) 10719 e_err(probe, "failed to allocate sysfs resources\n"); 10720 #endif /* CONFIG_IXGBE_HWMON */ 10721 10722 ixgbe_dbg_adapter_init(adapter); 10723 10724 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10725 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10726 hw->mac.ops.setup_link(hw, 10727 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10728 true); 10729 10730 return 0; 10731 10732 err_register: 10733 ixgbe_release_hw_control(adapter); 10734 ixgbe_clear_interrupt_scheme(adapter); 10735 err_sw_init: 10736 ixgbe_disable_sriov(adapter); 10737 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10738 iounmap(adapter->io_addr); 10739 kfree(adapter->jump_tables[0]); 10740 kfree(adapter->mac_table); 10741 kfree(adapter->rss_key); 10742 err_ioremap: 10743 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10744 free_netdev(netdev); 10745 err_alloc_etherdev: 10746 pci_release_mem_regions(pdev); 10747 err_pci_reg: 10748 err_dma: 10749 if (!adapter || disable_dev) 10750 pci_disable_device(pdev); 10751 return err; 10752 } 10753 10754 /** 10755 * ixgbe_remove - Device Removal Routine 10756 * @pdev: PCI device information struct 10757 * 10758 * ixgbe_remove is called by the PCI subsystem to alert the driver 10759 * that it should release a PCI device. The could be caused by a 10760 * Hot-Plug event, or because the driver is going to be removed from 10761 * memory. 10762 **/ 10763 static void ixgbe_remove(struct pci_dev *pdev) 10764 { 10765 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10766 struct net_device *netdev; 10767 bool disable_dev; 10768 int i; 10769 10770 /* if !adapter then we already cleaned up in probe */ 10771 if (!adapter) 10772 return; 10773 10774 netdev = adapter->netdev; 10775 ixgbe_dbg_adapter_exit(adapter); 10776 10777 set_bit(__IXGBE_REMOVING, &adapter->state); 10778 cancel_work_sync(&adapter->service_task); 10779 10780 10781 #ifdef CONFIG_IXGBE_DCA 10782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10783 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10784 dca_remove_requester(&pdev->dev); 10785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10786 IXGBE_DCA_CTRL_DCA_DISABLE); 10787 } 10788 10789 #endif 10790 #ifdef CONFIG_IXGBE_HWMON 10791 ixgbe_sysfs_exit(adapter); 10792 #endif /* CONFIG_IXGBE_HWMON */ 10793 10794 /* remove the added san mac */ 10795 ixgbe_del_sanmac_netdev(netdev); 10796 10797 #ifdef CONFIG_PCI_IOV 10798 ixgbe_disable_sriov(adapter); 10799 #endif 10800 if (netdev->reg_state == NETREG_REGISTERED) 10801 unregister_netdev(netdev); 10802 10803 ixgbe_stop_ipsec_offload(adapter); 10804 ixgbe_clear_interrupt_scheme(adapter); 10805 10806 ixgbe_release_hw_control(adapter); 10807 10808 #ifdef CONFIG_DCB 10809 kfree(adapter->ixgbe_ieee_pfc); 10810 kfree(adapter->ixgbe_ieee_ets); 10811 10812 #endif 10813 iounmap(adapter->io_addr); 10814 pci_release_mem_regions(pdev); 10815 10816 e_dev_info("complete\n"); 10817 10818 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10819 if (adapter->jump_tables[i]) { 10820 kfree(adapter->jump_tables[i]->input); 10821 kfree(adapter->jump_tables[i]->mask); 10822 } 10823 kfree(adapter->jump_tables[i]); 10824 } 10825 10826 kfree(adapter->mac_table); 10827 kfree(adapter->rss_key); 10828 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10829 free_netdev(netdev); 10830 10831 pci_disable_pcie_error_reporting(pdev); 10832 10833 if (disable_dev) 10834 pci_disable_device(pdev); 10835 } 10836 10837 /** 10838 * ixgbe_io_error_detected - called when PCI error is detected 10839 * @pdev: Pointer to PCI device 10840 * @state: The current pci connection state 10841 * 10842 * This function is called after a PCI bus error affecting 10843 * this device has been detected. 10844 */ 10845 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10846 pci_channel_state_t state) 10847 { 10848 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10849 struct net_device *netdev = adapter->netdev; 10850 10851 #ifdef CONFIG_PCI_IOV 10852 struct ixgbe_hw *hw = &adapter->hw; 10853 struct pci_dev *bdev, *vfdev; 10854 u32 dw0, dw1, dw2, dw3; 10855 int vf, pos; 10856 u16 req_id, pf_func; 10857 10858 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10859 adapter->num_vfs == 0) 10860 goto skip_bad_vf_detection; 10861 10862 bdev = pdev->bus->self; 10863 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10864 bdev = bdev->bus->self; 10865 10866 if (!bdev) 10867 goto skip_bad_vf_detection; 10868 10869 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10870 if (!pos) 10871 goto skip_bad_vf_detection; 10872 10873 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10874 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10875 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10876 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10877 if (ixgbe_removed(hw->hw_addr)) 10878 goto skip_bad_vf_detection; 10879 10880 req_id = dw1 >> 16; 10881 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10882 if (!(req_id & 0x0080)) 10883 goto skip_bad_vf_detection; 10884 10885 pf_func = req_id & 0x01; 10886 if ((pf_func & 1) == (pdev->devfn & 1)) { 10887 unsigned int device_id; 10888 10889 vf = (req_id & 0x7F) >> 1; 10890 e_dev_err("VF %d has caused a PCIe error\n", vf); 10891 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10892 "%8.8x\tdw3: %8.8x\n", 10893 dw0, dw1, dw2, dw3); 10894 switch (adapter->hw.mac.type) { 10895 case ixgbe_mac_82599EB: 10896 device_id = IXGBE_82599_VF_DEVICE_ID; 10897 break; 10898 case ixgbe_mac_X540: 10899 device_id = IXGBE_X540_VF_DEVICE_ID; 10900 break; 10901 case ixgbe_mac_X550: 10902 device_id = IXGBE_DEV_ID_X550_VF; 10903 break; 10904 case ixgbe_mac_X550EM_x: 10905 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10906 break; 10907 case ixgbe_mac_x550em_a: 10908 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10909 break; 10910 default: 10911 device_id = 0; 10912 break; 10913 } 10914 10915 /* Find the pci device of the offending VF */ 10916 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10917 while (vfdev) { 10918 if (vfdev->devfn == (req_id & 0xFF)) 10919 break; 10920 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10921 device_id, vfdev); 10922 } 10923 /* 10924 * There's a slim chance the VF could have been hot plugged, 10925 * so if it is no longer present we don't need to issue the 10926 * VFLR. Just clean up the AER in that case. 10927 */ 10928 if (vfdev) { 10929 pcie_flr(vfdev); 10930 /* Free device reference count */ 10931 pci_dev_put(vfdev); 10932 } 10933 10934 pci_cleanup_aer_uncorrect_error_status(pdev); 10935 } 10936 10937 /* 10938 * Even though the error may have occurred on the other port 10939 * we still need to increment the vf error reference count for 10940 * both ports because the I/O resume function will be called 10941 * for both of them. 10942 */ 10943 adapter->vferr_refcount++; 10944 10945 return PCI_ERS_RESULT_RECOVERED; 10946 10947 skip_bad_vf_detection: 10948 #endif /* CONFIG_PCI_IOV */ 10949 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10950 return PCI_ERS_RESULT_DISCONNECT; 10951 10952 if (!netif_device_present(netdev)) 10953 return PCI_ERS_RESULT_DISCONNECT; 10954 10955 rtnl_lock(); 10956 netif_device_detach(netdev); 10957 10958 if (state == pci_channel_io_perm_failure) { 10959 rtnl_unlock(); 10960 return PCI_ERS_RESULT_DISCONNECT; 10961 } 10962 10963 if (netif_running(netdev)) 10964 ixgbe_close_suspend(adapter); 10965 10966 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10967 pci_disable_device(pdev); 10968 rtnl_unlock(); 10969 10970 /* Request a slot reset. */ 10971 return PCI_ERS_RESULT_NEED_RESET; 10972 } 10973 10974 /** 10975 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10976 * @pdev: Pointer to PCI device 10977 * 10978 * Restart the card from scratch, as if from a cold-boot. 10979 */ 10980 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10981 { 10982 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10983 pci_ers_result_t result; 10984 int err; 10985 10986 if (pci_enable_device_mem(pdev)) { 10987 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10988 result = PCI_ERS_RESULT_DISCONNECT; 10989 } else { 10990 smp_mb__before_atomic(); 10991 clear_bit(__IXGBE_DISABLED, &adapter->state); 10992 adapter->hw.hw_addr = adapter->io_addr; 10993 pci_set_master(pdev); 10994 pci_restore_state(pdev); 10995 pci_save_state(pdev); 10996 10997 pci_wake_from_d3(pdev, false); 10998 10999 ixgbe_reset(adapter); 11000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11001 result = PCI_ERS_RESULT_RECOVERED; 11002 } 11003 11004 err = pci_cleanup_aer_uncorrect_error_status(pdev); 11005 if (err) { 11006 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 11007 "failed 0x%0x\n", err); 11008 /* non-fatal, continue */ 11009 } 11010 11011 return result; 11012 } 11013 11014 /** 11015 * ixgbe_io_resume - called when traffic can start flowing again. 11016 * @pdev: Pointer to PCI device 11017 * 11018 * This callback is called when the error recovery driver tells us that 11019 * its OK to resume normal operation. 11020 */ 11021 static void ixgbe_io_resume(struct pci_dev *pdev) 11022 { 11023 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11024 struct net_device *netdev = adapter->netdev; 11025 11026 #ifdef CONFIG_PCI_IOV 11027 if (adapter->vferr_refcount) { 11028 e_info(drv, "Resuming after VF err\n"); 11029 adapter->vferr_refcount--; 11030 return; 11031 } 11032 11033 #endif 11034 rtnl_lock(); 11035 if (netif_running(netdev)) 11036 ixgbe_open(netdev); 11037 11038 netif_device_attach(netdev); 11039 rtnl_unlock(); 11040 } 11041 11042 static const struct pci_error_handlers ixgbe_err_handler = { 11043 .error_detected = ixgbe_io_error_detected, 11044 .slot_reset = ixgbe_io_slot_reset, 11045 .resume = ixgbe_io_resume, 11046 }; 11047 11048 static struct pci_driver ixgbe_driver = { 11049 .name = ixgbe_driver_name, 11050 .id_table = ixgbe_pci_tbl, 11051 .probe = ixgbe_probe, 11052 .remove = ixgbe_remove, 11053 #ifdef CONFIG_PM 11054 .suspend = ixgbe_suspend, 11055 .resume = ixgbe_resume, 11056 #endif 11057 .shutdown = ixgbe_shutdown, 11058 .sriov_configure = ixgbe_pci_sriov_configure, 11059 .err_handler = &ixgbe_err_handler 11060 }; 11061 11062 /** 11063 * ixgbe_init_module - Driver Registration Routine 11064 * 11065 * ixgbe_init_module is the first routine called when the driver is 11066 * loaded. All it does is register with the PCI subsystem. 11067 **/ 11068 static int __init ixgbe_init_module(void) 11069 { 11070 int ret; 11071 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11072 pr_info("%s\n", ixgbe_copyright); 11073 11074 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11075 if (!ixgbe_wq) { 11076 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11077 return -ENOMEM; 11078 } 11079 11080 ixgbe_dbg_init(); 11081 11082 ret = pci_register_driver(&ixgbe_driver); 11083 if (ret) { 11084 destroy_workqueue(ixgbe_wq); 11085 ixgbe_dbg_exit(); 11086 return ret; 11087 } 11088 11089 #ifdef CONFIG_IXGBE_DCA 11090 dca_register_notify(&dca_notifier); 11091 #endif 11092 11093 return 0; 11094 } 11095 11096 module_init(ixgbe_init_module); 11097 11098 /** 11099 * ixgbe_exit_module - Driver Exit Cleanup Routine 11100 * 11101 * ixgbe_exit_module is called just before the driver is removed 11102 * from memory. 11103 **/ 11104 static void __exit ixgbe_exit_module(void) 11105 { 11106 #ifdef CONFIG_IXGBE_DCA 11107 dca_unregister_notify(&dca_notifier); 11108 #endif 11109 pci_unregister_driver(&ixgbe_driver); 11110 11111 ixgbe_dbg_exit(); 11112 if (ixgbe_wq) { 11113 destroy_workqueue(ixgbe_wq); 11114 ixgbe_wq = NULL; 11115 } 11116 } 11117 11118 #ifdef CONFIG_IXGBE_DCA 11119 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11120 void *p) 11121 { 11122 int ret_val; 11123 11124 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11125 __ixgbe_notify_dca); 11126 11127 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11128 } 11129 11130 #endif /* CONFIG_IXGBE_DCA */ 11131 11132 module_exit(ixgbe_exit_module); 11133 11134 /* ixgbe_main.c */ 11135