1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 #include <net/vxlan.h> 54 55 #ifdef CONFIG_OF 56 #include <linux/of_net.h> 57 #endif 58 59 #ifdef CONFIG_SPARC 60 #include <asm/idprom.h> 61 #include <asm/prom.h> 62 #endif 63 64 #include "ixgbe.h" 65 #include "ixgbe_common.h" 66 #include "ixgbe_dcb_82599.h" 67 #include "ixgbe_sriov.h" 68 #ifdef CONFIG_IXGBE_VXLAN 69 #include <net/vxlan.h> 70 #endif 71 72 char ixgbe_driver_name[] = "ixgbe"; 73 static const char ixgbe_driver_string[] = 74 "Intel(R) 10 Gigabit PCI Express Network Driver"; 75 #ifdef IXGBE_FCOE 76 char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #else 79 static char ixgbe_default_device_descr[] = 80 "Intel(R) 10 Gigabit Network Connection"; 81 #endif 82 #define DRV_VERSION "4.0.1-k" 83 const char ixgbe_driver_version[] = DRV_VERSION; 84 static const char ixgbe_copyright[] = 85 "Copyright (c) 1999-2015 Intel Corporation."; 86 87 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 88 89 static const struct ixgbe_info *ixgbe_info_tbl[] = { 90 [board_82598] = &ixgbe_82598_info, 91 [board_82599] = &ixgbe_82599_info, 92 [board_X540] = &ixgbe_X540_info, 93 [board_X550] = &ixgbe_X550_info, 94 [board_X550EM_x] = &ixgbe_X550EM_x_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 140 /* required last entry */ 141 {0, } 142 }; 143 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 144 145 #ifdef CONFIG_IXGBE_DCA 146 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 147 void *p); 148 static struct notifier_block dca_notifier = { 149 .notifier_call = ixgbe_notify_dca, 150 .next = NULL, 151 .priority = 0 152 }; 153 #endif 154 155 #ifdef CONFIG_PCI_IOV 156 static unsigned int max_vfs; 157 module_param(max_vfs, uint, 0); 158 MODULE_PARM_DESC(max_vfs, 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 160 #endif /* CONFIG_PCI_IOV */ 161 162 static unsigned int allow_unsupported_sfp; 163 module_param(allow_unsupported_sfp, uint, 0); 164 MODULE_PARM_DESC(allow_unsupported_sfp, 165 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 166 167 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 168 static int debug = -1; 169 module_param(debug, int, 0); 170 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 171 172 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 173 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 174 MODULE_LICENSE("GPL"); 175 MODULE_VERSION(DRV_VERSION); 176 177 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 178 179 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 180 u32 reg, u16 *value) 181 { 182 struct pci_dev *parent_dev; 183 struct pci_bus *parent_bus; 184 185 parent_bus = adapter->pdev->bus->parent; 186 if (!parent_bus) 187 return -1; 188 189 parent_dev = parent_bus->self; 190 if (!parent_dev) 191 return -1; 192 193 if (!pci_is_pcie(parent_dev)) 194 return -1; 195 196 pcie_capability_read_word(parent_dev, reg, value); 197 if (*value == IXGBE_FAILED_READ_CFG_WORD && 198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 199 return -1; 200 return 0; 201 } 202 203 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 204 { 205 struct ixgbe_hw *hw = &adapter->hw; 206 u16 link_status = 0; 207 int err; 208 209 hw->bus.type = ixgbe_bus_type_pci_express; 210 211 /* Get the negotiated link width and speed from PCI config space of the 212 * parent, as this device is behind a switch 213 */ 214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 215 216 /* assume caller will handle error case */ 217 if (err) 218 return err; 219 220 hw->bus.width = ixgbe_convert_bus_width(link_status); 221 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 222 223 return 0; 224 } 225 226 /** 227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 228 * @hw: hw specific details 229 * 230 * This function is used by probe to determine whether a device's PCI-Express 231 * bandwidth details should be gathered from the parent bus instead of from the 232 * device. Used to ensure that various locations all have the correct device ID 233 * checks. 234 */ 235 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 236 { 237 switch (hw->device_id) { 238 case IXGBE_DEV_ID_82599_SFP_SF_QP: 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 240 return true; 241 default: 242 return false; 243 } 244 } 245 246 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 247 int expected_gts) 248 { 249 struct ixgbe_hw *hw = &adapter->hw; 250 int max_gts = 0; 251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 253 struct pci_dev *pdev; 254 255 /* Some devices are not connected over PCIe and thus do not negotiate 256 * speed. These devices do not have valid bus info, and thus any report 257 * we generate may not be correct. 258 */ 259 if (hw->bus.type == ixgbe_bus_type_internal) 260 return; 261 262 /* determine whether to use the parent device */ 263 if (ixgbe_pcie_from_parent(&adapter->hw)) 264 pdev = adapter->pdev->bus->parent->self; 265 else 266 pdev = adapter->pdev; 267 268 if (pcie_get_minimum_link(pdev, &speed, &width) || 269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 270 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 271 return; 272 } 273 274 switch (speed) { 275 case PCIE_SPEED_2_5GT: 276 /* 8b/10b encoding reduces max throughput by 20% */ 277 max_gts = 2 * width; 278 break; 279 case PCIE_SPEED_5_0GT: 280 /* 8b/10b encoding reduces max throughput by 20% */ 281 max_gts = 4 * width; 282 break; 283 case PCIE_SPEED_8_0GT: 284 /* 128b/130b encoding reduces throughput by less than 2% */ 285 max_gts = 8 * width; 286 break; 287 default: 288 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 289 return; 290 } 291 292 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 293 max_gts); 294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 298 "Unknown"), 299 width, 300 (speed == PCIE_SPEED_2_5GT ? "20%" : 301 speed == PCIE_SPEED_5_0GT ? "20%" : 302 speed == PCIE_SPEED_8_0GT ? "<2%" : 303 "Unknown")); 304 305 if (max_gts < expected_gts) { 306 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 308 expected_gts); 309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 310 } 311 } 312 313 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 314 { 315 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 316 !test_bit(__IXGBE_REMOVING, &adapter->state) && 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 318 schedule_work(&adapter->service_task); 319 } 320 321 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 322 { 323 struct ixgbe_adapter *adapter = hw->back; 324 325 if (!hw->hw_addr) 326 return; 327 hw->hw_addr = NULL; 328 e_dev_err("Adapter removed\n"); 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 330 ixgbe_service_event_schedule(adapter); 331 } 332 333 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 334 { 335 u32 value; 336 337 /* The following check not only optimizes a bit by not 338 * performing a read on the status register when the 339 * register just read was a status register read that 340 * returned IXGBE_FAILED_READ_REG. It also blocks any 341 * potential recursion. 342 */ 343 if (reg == IXGBE_STATUS) { 344 ixgbe_remove_adapter(hw); 345 return; 346 } 347 value = ixgbe_read_reg(hw, IXGBE_STATUS); 348 if (value == IXGBE_FAILED_READ_REG) 349 ixgbe_remove_adapter(hw); 350 } 351 352 /** 353 * ixgbe_read_reg - Read from device register 354 * @hw: hw specific details 355 * @reg: offset of register to read 356 * 357 * Returns : value read or IXGBE_FAILED_READ_REG if removed 358 * 359 * This function is used to read device registers. It checks for device 360 * removal by confirming any read that returns all ones by checking the 361 * status register value for all ones. This function avoids reading from 362 * the hardware if a removal was previously detected in which case it 363 * returns IXGBE_FAILED_READ_REG (all ones). 364 */ 365 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 366 { 367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 368 u32 value; 369 370 if (ixgbe_removed(reg_addr)) 371 return IXGBE_FAILED_READ_REG; 372 value = readl(reg_addr + reg); 373 if (unlikely(value == IXGBE_FAILED_READ_REG)) 374 ixgbe_check_remove(hw, reg); 375 return value; 376 } 377 378 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 379 { 380 u16 value; 381 382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 383 if (value == IXGBE_FAILED_READ_CFG_WORD) { 384 ixgbe_remove_adapter(hw); 385 return true; 386 } 387 return false; 388 } 389 390 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 391 { 392 struct ixgbe_adapter *adapter = hw->back; 393 u16 value; 394 395 if (ixgbe_removed(hw->hw_addr)) 396 return IXGBE_FAILED_READ_CFG_WORD; 397 pci_read_config_word(adapter->pdev, reg, &value); 398 if (value == IXGBE_FAILED_READ_CFG_WORD && 399 ixgbe_check_cfg_remove(hw, adapter->pdev)) 400 return IXGBE_FAILED_READ_CFG_WORD; 401 return value; 402 } 403 404 #ifdef CONFIG_PCI_IOV 405 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 406 { 407 struct ixgbe_adapter *adapter = hw->back; 408 u32 value; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return IXGBE_FAILED_READ_CFG_DWORD; 412 pci_read_config_dword(adapter->pdev, reg, &value); 413 if (value == IXGBE_FAILED_READ_CFG_DWORD && 414 ixgbe_check_cfg_remove(hw, adapter->pdev)) 415 return IXGBE_FAILED_READ_CFG_DWORD; 416 return value; 417 } 418 #endif /* CONFIG_PCI_IOV */ 419 420 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 421 { 422 struct ixgbe_adapter *adapter = hw->back; 423 424 if (ixgbe_removed(hw->hw_addr)) 425 return; 426 pci_write_config_word(adapter->pdev, reg, value); 427 } 428 429 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 430 { 431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 432 433 /* flush memory to make sure state is correct before next watchdog */ 434 smp_mb__before_atomic(); 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 436 } 437 438 struct ixgbe_reg_info { 439 u32 ofs; 440 char *name; 441 }; 442 443 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 444 445 /* General Registers */ 446 {IXGBE_CTRL, "CTRL"}, 447 {IXGBE_STATUS, "STATUS"}, 448 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 449 450 /* Interrupt Registers */ 451 {IXGBE_EICR, "EICR"}, 452 453 /* RX Registers */ 454 {IXGBE_SRRCTL(0), "SRRCTL"}, 455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 456 {IXGBE_RDLEN(0), "RDLEN"}, 457 {IXGBE_RDH(0), "RDH"}, 458 {IXGBE_RDT(0), "RDT"}, 459 {IXGBE_RXDCTL(0), "RXDCTL"}, 460 {IXGBE_RDBAL(0), "RDBAL"}, 461 {IXGBE_RDBAH(0), "RDBAH"}, 462 463 /* TX Registers */ 464 {IXGBE_TDBAL(0), "TDBAL"}, 465 {IXGBE_TDBAH(0), "TDBAH"}, 466 {IXGBE_TDLEN(0), "TDLEN"}, 467 {IXGBE_TDH(0), "TDH"}, 468 {IXGBE_TDT(0), "TDT"}, 469 {IXGBE_TXDCTL(0), "TXDCTL"}, 470 471 /* List Terminator */ 472 { .name = NULL } 473 }; 474 475 476 /* 477 * ixgbe_regdump - register printout routine 478 */ 479 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 480 { 481 int i = 0, j = 0; 482 char rname[16]; 483 u32 regs[64]; 484 485 switch (reginfo->ofs) { 486 case IXGBE_SRRCTL(0): 487 for (i = 0; i < 64; i++) 488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 489 break; 490 case IXGBE_DCA_RXCTRL(0): 491 for (i = 0; i < 64; i++) 492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 493 break; 494 case IXGBE_RDLEN(0): 495 for (i = 0; i < 64; i++) 496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 497 break; 498 case IXGBE_RDH(0): 499 for (i = 0; i < 64; i++) 500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 501 break; 502 case IXGBE_RDT(0): 503 for (i = 0; i < 64; i++) 504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 505 break; 506 case IXGBE_RXDCTL(0): 507 for (i = 0; i < 64; i++) 508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 509 break; 510 case IXGBE_RDBAL(0): 511 for (i = 0; i < 64; i++) 512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 513 break; 514 case IXGBE_RDBAH(0): 515 for (i = 0; i < 64; i++) 516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 517 break; 518 case IXGBE_TDBAL(0): 519 for (i = 0; i < 64; i++) 520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 521 break; 522 case IXGBE_TDBAH(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 525 break; 526 case IXGBE_TDLEN(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 529 break; 530 case IXGBE_TDH(0): 531 for (i = 0; i < 64; i++) 532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 533 break; 534 case IXGBE_TDT(0): 535 for (i = 0; i < 64; i++) 536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 537 break; 538 case IXGBE_TXDCTL(0): 539 for (i = 0; i < 64; i++) 540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 541 break; 542 default: 543 pr_info("%-15s %08x\n", reginfo->name, 544 IXGBE_READ_REG(hw, reginfo->ofs)); 545 return; 546 } 547 548 for (i = 0; i < 8; i++) { 549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 550 pr_err("%-15s", rname); 551 for (j = 0; j < 8; j++) 552 pr_cont(" %08x", regs[i*8+j]); 553 pr_cont("\n"); 554 } 555 556 } 557 558 /* 559 * ixgbe_dump - Print registers, tx-rings and rx-rings 560 */ 561 static void ixgbe_dump(struct ixgbe_adapter *adapter) 562 { 563 struct net_device *netdev = adapter->netdev; 564 struct ixgbe_hw *hw = &adapter->hw; 565 struct ixgbe_reg_info *reginfo; 566 int n = 0; 567 struct ixgbe_ring *tx_ring; 568 struct ixgbe_tx_buffer *tx_buffer; 569 union ixgbe_adv_tx_desc *tx_desc; 570 struct my_u0 { u64 a; u64 b; } *u0; 571 struct ixgbe_ring *rx_ring; 572 union ixgbe_adv_rx_desc *rx_desc; 573 struct ixgbe_rx_buffer *rx_buffer_info; 574 u32 staterr; 575 int i = 0; 576 577 if (!netif_msg_hw(adapter)) 578 return; 579 580 /* Print netdevice Info */ 581 if (netdev) { 582 dev_info(&adapter->pdev->dev, "Net device Info\n"); 583 pr_info("Device Name state " 584 "trans_start last_rx\n"); 585 pr_info("%-15s %016lX %016lX %016lX\n", 586 netdev->name, 587 netdev->state, 588 netdev->trans_start, 589 netdev->last_rx); 590 } 591 592 /* Print Registers */ 593 dev_info(&adapter->pdev->dev, "Register Dump\n"); 594 pr_info(" Register Name Value\n"); 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 596 reginfo->name; reginfo++) { 597 ixgbe_regdump(hw, reginfo); 598 } 599 600 /* Print TX Ring Summary */ 601 if (!netdev || !netif_running(netdev)) 602 return; 603 604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 605 pr_info(" %s %s %s %s\n", 606 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 607 "leng", "ntw", "timestamp"); 608 for (n = 0; n < adapter->num_tx_queues; n++) { 609 tx_ring = adapter->tx_ring[n]; 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 612 n, tx_ring->next_to_use, tx_ring->next_to_clean, 613 (u64)dma_unmap_addr(tx_buffer, dma), 614 dma_unmap_len(tx_buffer, len), 615 tx_buffer->next_to_watch, 616 (u64)tx_buffer->time_stamp); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 tx_ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(tx_ring, i); 672 tx_buffer = &tx_ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 676 i, 677 le64_to_cpu(u0->a), 678 le64_to_cpu(u0->b), 679 (u64)dma_unmap_addr(tx_buffer, dma), 680 dma_unmap_len(tx_buffer, len), 681 tx_buffer->next_to_watch, 682 (u64)tx_buffer->time_stamp, 683 tx_buffer->skb); 684 if (i == tx_ring->next_to_use && 685 i == tx_ring->next_to_clean) 686 pr_cont(" NTC/U\n"); 687 else if (i == tx_ring->next_to_use) 688 pr_cont(" NTU\n"); 689 else if (i == tx_ring->next_to_clean) 690 pr_cont(" NTC\n"); 691 else 692 pr_cont("\n"); 693 694 if (netif_msg_pktdata(adapter) && 695 tx_buffer->skb) 696 print_hex_dump(KERN_INFO, "", 697 DUMP_PREFIX_ADDRESS, 16, 1, 698 tx_buffer->skb->data, 699 dma_unmap_len(tx_buffer, len), 700 true); 701 } 702 } 703 } 704 705 /* Print RX Rings Summary */ 706 rx_ring_summary: 707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 708 pr_info("Queue [NTU] [NTC]\n"); 709 for (n = 0; n < adapter->num_rx_queues; n++) { 710 rx_ring = adapter->rx_ring[n]; 711 pr_info("%5d %5X %5X\n", 712 n, rx_ring->next_to_use, rx_ring->next_to_clean); 713 } 714 715 /* Print RX Rings */ 716 if (!netif_msg_rx_status(adapter)) 717 return; 718 719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 720 721 /* Receive Descriptor Formats 722 * 723 * 82598 Advanced Receive Descriptor (Read) Format 724 * 63 1 0 725 * +-----------------------------------------------------+ 726 * 0 | Packet Buffer Address [63:1] |A0/NSE| 727 * +----------------------------------------------+------+ 728 * 8 | Header Buffer Address [63:1] | DD | 729 * +-----------------------------------------------------+ 730 * 731 * 732 * 82598 Advanced Receive Descriptor (Write-Back) Format 733 * 734 * 63 48 47 32 31 30 21 20 16 15 4 3 0 735 * +------------------------------------------------------+ 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 737 * | Packet | IP | | | | Type | Type | 738 * | Checksum | Ident | | | | | | 739 * +------------------------------------------------------+ 740 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 741 * +------------------------------------------------------+ 742 * 63 48 47 32 31 20 19 0 743 * 744 * 82599+ Advanced Receive Descriptor (Read) Format 745 * 63 1 0 746 * +-----------------------------------------------------+ 747 * 0 | Packet Buffer Address [63:1] |A0/NSE| 748 * +----------------------------------------------+------+ 749 * 8 | Header Buffer Address [63:1] | DD | 750 * +-----------------------------------------------------+ 751 * 752 * 753 * 82599+ Advanced Receive Descriptor (Write-Back) Format 754 * 755 * 63 48 47 32 31 30 21 20 17 16 4 3 0 756 * +------------------------------------------------------+ 757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 759 * |/ Flow Dir Flt ID | | | | | | 760 * +------------------------------------------------------+ 761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 762 * +------------------------------------------------------+ 763 * 63 48 47 32 31 20 19 0 764 */ 765 766 for (n = 0; n < adapter->num_rx_queues; n++) { 767 rx_ring = adapter->rx_ring[n]; 768 pr_info("------------------------------------\n"); 769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 770 pr_info("------------------------------------\n"); 771 pr_info("%s%s%s", 772 "R [desc] [ PktBuf A0] ", 773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 774 "<-- Adv Rx Read format\n"); 775 pr_info("%s%s%s", 776 "RWB[desc] [PcsmIpSHl PtRs] ", 777 "[vl er S cks ln] ---------------- [bi->skb ] ", 778 "<-- Adv Rx Write-Back format\n"); 779 780 for (i = 0; i < rx_ring->count; i++) { 781 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 782 rx_desc = IXGBE_RX_DESC(rx_ring, i); 783 u0 = (struct my_u0 *)rx_desc; 784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 785 if (staterr & IXGBE_RXD_STAT_DD) { 786 /* Descriptor Done */ 787 pr_info("RWB[0x%03X] %016llX " 788 "%016llX ---------------- %p", i, 789 le64_to_cpu(u0->a), 790 le64_to_cpu(u0->b), 791 rx_buffer_info->skb); 792 } else { 793 pr_info("R [0x%03X] %016llX " 794 "%016llX %016llX %p", i, 795 le64_to_cpu(u0->a), 796 le64_to_cpu(u0->b), 797 (u64)rx_buffer_info->dma, 798 rx_buffer_info->skb); 799 800 if (netif_msg_pktdata(adapter) && 801 rx_buffer_info->dma) { 802 print_hex_dump(KERN_INFO, "", 803 DUMP_PREFIX_ADDRESS, 16, 1, 804 page_address(rx_buffer_info->page) + 805 rx_buffer_info->page_offset, 806 ixgbe_rx_bufsz(rx_ring), true); 807 } 808 } 809 810 if (i == rx_ring->next_to_use) 811 pr_cont(" NTU\n"); 812 else if (i == rx_ring->next_to_clean) 813 pr_cont(" NTC\n"); 814 else 815 pr_cont("\n"); 816 817 } 818 } 819 } 820 821 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 822 { 823 u32 ctrl_ext; 824 825 /* Let firmware take over control of h/w */ 826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 829 } 830 831 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 832 { 833 u32 ctrl_ext; 834 835 /* Let firmware know the driver has taken over */ 836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 839 } 840 841 /** 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 843 * @adapter: pointer to adapter struct 844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 845 * @queue: queue to map the corresponding interrupt to 846 * @msix_vector: the vector to map to the corresponding queue 847 * 848 */ 849 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 850 u8 queue, u8 msix_vector) 851 { 852 u32 ivar, index; 853 struct ixgbe_hw *hw = &adapter->hw; 854 switch (hw->mac.type) { 855 case ixgbe_mac_82598EB: 856 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 857 if (direction == -1) 858 direction = 0; 859 index = (((direction * 64) + queue) >> 2) & 0x1F; 860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 861 ivar &= ~(0xFF << (8 * (queue & 0x3))); 862 ivar |= (msix_vector << (8 * (queue & 0x3))); 863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 864 break; 865 case ixgbe_mac_82599EB: 866 case ixgbe_mac_X540: 867 case ixgbe_mac_X550: 868 case ixgbe_mac_X550EM_x: 869 if (direction == -1) { 870 /* other causes */ 871 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 872 index = ((queue & 1) * 8); 873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 874 ivar &= ~(0xFF << index); 875 ivar |= (msix_vector << index); 876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 877 break; 878 } else { 879 /* tx or rx causes */ 880 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 881 index = ((16 * (queue & 1)) + (8 * direction)); 882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 883 ivar &= ~(0xFF << index); 884 ivar |= (msix_vector << index); 885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 886 break; 887 } 888 default: 889 break; 890 } 891 } 892 893 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 894 u64 qmask) 895 { 896 u32 mask; 897 898 switch (adapter->hw.mac.type) { 899 case ixgbe_mac_82598EB: 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 902 break; 903 case ixgbe_mac_82599EB: 904 case ixgbe_mac_X540: 905 case ixgbe_mac_X550: 906 case ixgbe_mac_X550EM_x: 907 mask = (qmask & 0xFFFFFFFF); 908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 909 mask = (qmask >> 32); 910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 911 break; 912 default: 913 break; 914 } 915 } 916 917 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 918 struct ixgbe_tx_buffer *tx_buffer) 919 { 920 if (tx_buffer->skb) { 921 dev_kfree_skb_any(tx_buffer->skb); 922 if (dma_unmap_len(tx_buffer, len)) 923 dma_unmap_single(ring->dev, 924 dma_unmap_addr(tx_buffer, dma), 925 dma_unmap_len(tx_buffer, len), 926 DMA_TO_DEVICE); 927 } else if (dma_unmap_len(tx_buffer, len)) { 928 dma_unmap_page(ring->dev, 929 dma_unmap_addr(tx_buffer, dma), 930 dma_unmap_len(tx_buffer, len), 931 DMA_TO_DEVICE); 932 } 933 tx_buffer->next_to_watch = NULL; 934 tx_buffer->skb = NULL; 935 dma_unmap_len_set(tx_buffer, len, 0); 936 /* tx_buffer must be completely set up in the transmit path */ 937 } 938 939 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 940 { 941 struct ixgbe_hw *hw = &adapter->hw; 942 struct ixgbe_hw_stats *hwstats = &adapter->stats; 943 int i; 944 u32 data; 945 946 if ((hw->fc.current_mode != ixgbe_fc_full) && 947 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 948 return; 949 950 switch (hw->mac.type) { 951 case ixgbe_mac_82598EB: 952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 953 break; 954 default: 955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 956 } 957 hwstats->lxoffrxc += data; 958 959 /* refill credits (no tx hang) if we received xoff */ 960 if (!data) 961 return; 962 963 for (i = 0; i < adapter->num_tx_queues; i++) 964 clear_bit(__IXGBE_HANG_CHECK_ARMED, 965 &adapter->tx_ring[i]->state); 966 } 967 968 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 969 { 970 struct ixgbe_hw *hw = &adapter->hw; 971 struct ixgbe_hw_stats *hwstats = &adapter->stats; 972 u32 xoff[8] = {0}; 973 u8 tc; 974 int i; 975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 976 977 if (adapter->ixgbe_ieee_pfc) 978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 979 980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 981 ixgbe_update_xoff_rx_lfc(adapter); 982 return; 983 } 984 985 /* update stats for each tc, only valid with PFC enabled */ 986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 987 u32 pxoffrxc; 988 989 switch (hw->mac.type) { 990 case ixgbe_mac_82598EB: 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 992 break; 993 default: 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 995 } 996 hwstats->pxoffrxc[i] += pxoffrxc; 997 /* Get the TC for given UP */ 998 tc = netdev_get_prio_tc_map(adapter->netdev, i); 999 xoff[tc] += pxoffrxc; 1000 } 1001 1002 /* disarm tx queues that have received xoff frames */ 1003 for (i = 0; i < adapter->num_tx_queues; i++) { 1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1005 1006 tc = tx_ring->dcb_tc; 1007 if (xoff[tc]) 1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1009 } 1010 } 1011 1012 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1013 { 1014 return ring->stats.packets; 1015 } 1016 1017 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1018 { 1019 struct ixgbe_adapter *adapter; 1020 struct ixgbe_hw *hw; 1021 u32 head, tail; 1022 1023 if (ring->l2_accel_priv) 1024 adapter = ring->l2_accel_priv->real_adapter; 1025 else 1026 adapter = netdev_priv(ring->netdev); 1027 1028 hw = &adapter->hw; 1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1031 1032 if (head != tail) 1033 return (head < tail) ? 1034 tail - head : (tail + ring->count - head); 1035 1036 return 0; 1037 } 1038 1039 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1040 { 1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1044 1045 clear_check_for_tx_hang(tx_ring); 1046 1047 /* 1048 * Check for a hung queue, but be thorough. This verifies 1049 * that a transmit has been completed since the previous 1050 * check AND there is at least one packet pending. The 1051 * ARMED bit is set to indicate a potential hang. The 1052 * bit is cleared if a pause frame is received to remove 1053 * false hang detection due to PFC or 802.3x frames. By 1054 * requiring this to fail twice we avoid races with 1055 * pfc clearing the ARMED bit and conditions where we 1056 * run the check_tx_hang logic with a transmit completion 1057 * pending but without time to complete it yet. 1058 */ 1059 if (tx_done_old == tx_done && tx_pending) 1060 /* make sure it is true for two checks in a row */ 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1062 &tx_ring->state); 1063 /* update completed stats and continue */ 1064 tx_ring->tx_stats.tx_done_old = tx_done; 1065 /* reset the countdown */ 1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1067 1068 return false; 1069 } 1070 1071 /** 1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1073 * @adapter: driver private struct 1074 **/ 1075 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1076 { 1077 1078 /* Do the reset outside of interrupt context */ 1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1081 e_warn(drv, "initiating reset due to tx timeout\n"); 1082 ixgbe_service_event_schedule(adapter); 1083 } 1084 } 1085 1086 /** 1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1088 * @q_vector: structure containing interrupt and ring information 1089 * @tx_ring: tx ring to clean 1090 **/ 1091 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1092 struct ixgbe_ring *tx_ring) 1093 { 1094 struct ixgbe_adapter *adapter = q_vector->adapter; 1095 struct ixgbe_tx_buffer *tx_buffer; 1096 union ixgbe_adv_tx_desc *tx_desc; 1097 unsigned int total_bytes = 0, total_packets = 0; 1098 unsigned int budget = q_vector->tx.work_limit; 1099 unsigned int i = tx_ring->next_to_clean; 1100 1101 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1102 return true; 1103 1104 tx_buffer = &tx_ring->tx_buffer_info[i]; 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1106 i -= tx_ring->count; 1107 1108 do { 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1110 1111 /* if next_to_watch is not set then there is no work pending */ 1112 if (!eop_desc) 1113 break; 1114 1115 /* prevent any other reads prior to eop_desc */ 1116 read_barrier_depends(); 1117 1118 /* if DD is not set pending work has not been completed */ 1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1120 break; 1121 1122 /* clear next_to_watch to prevent false hangs */ 1123 tx_buffer->next_to_watch = NULL; 1124 1125 /* update the statistics for this packet */ 1126 total_bytes += tx_buffer->bytecount; 1127 total_packets += tx_buffer->gso_segs; 1128 1129 /* free the skb */ 1130 dev_consume_skb_any(tx_buffer->skb); 1131 1132 /* unmap skb header data */ 1133 dma_unmap_single(tx_ring->dev, 1134 dma_unmap_addr(tx_buffer, dma), 1135 dma_unmap_len(tx_buffer, len), 1136 DMA_TO_DEVICE); 1137 1138 /* clear tx_buffer data */ 1139 tx_buffer->skb = NULL; 1140 dma_unmap_len_set(tx_buffer, len, 0); 1141 1142 /* unmap remaining buffers */ 1143 while (tx_desc != eop_desc) { 1144 tx_buffer++; 1145 tx_desc++; 1146 i++; 1147 if (unlikely(!i)) { 1148 i -= tx_ring->count; 1149 tx_buffer = tx_ring->tx_buffer_info; 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1151 } 1152 1153 /* unmap any remaining paged data */ 1154 if (dma_unmap_len(tx_buffer, len)) { 1155 dma_unmap_page(tx_ring->dev, 1156 dma_unmap_addr(tx_buffer, dma), 1157 dma_unmap_len(tx_buffer, len), 1158 DMA_TO_DEVICE); 1159 dma_unmap_len_set(tx_buffer, len, 0); 1160 } 1161 } 1162 1163 /* move us one more past the eop_desc for start of next pkt */ 1164 tx_buffer++; 1165 tx_desc++; 1166 i++; 1167 if (unlikely(!i)) { 1168 i -= tx_ring->count; 1169 tx_buffer = tx_ring->tx_buffer_info; 1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1171 } 1172 1173 /* issue prefetch for next Tx descriptor */ 1174 prefetch(tx_desc); 1175 1176 /* update budget accounting */ 1177 budget--; 1178 } while (likely(budget)); 1179 1180 i += tx_ring->count; 1181 tx_ring->next_to_clean = i; 1182 u64_stats_update_begin(&tx_ring->syncp); 1183 tx_ring->stats.bytes += total_bytes; 1184 tx_ring->stats.packets += total_packets; 1185 u64_stats_update_end(&tx_ring->syncp); 1186 q_vector->tx.total_bytes += total_bytes; 1187 q_vector->tx.total_packets += total_packets; 1188 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1190 /* schedule immediate reset if we believe we hung */ 1191 struct ixgbe_hw *hw = &adapter->hw; 1192 e_err(drv, "Detected Tx Unit Hang\n" 1193 " Tx Queue <%d>\n" 1194 " TDH, TDT <%x>, <%x>\n" 1195 " next_to_use <%x>\n" 1196 " next_to_clean <%x>\n" 1197 "tx_buffer_info[next_to_clean]\n" 1198 " time_stamp <%lx>\n" 1199 " jiffies <%lx>\n", 1200 tx_ring->queue_index, 1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1203 tx_ring->next_to_use, i, 1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1205 1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1207 1208 e_info(probe, 1209 "tx hang %d detected on queue %d, resetting adapter\n", 1210 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1211 1212 /* schedule immediate reset if we believe we hung */ 1213 ixgbe_tx_timeout_reset(adapter); 1214 1215 /* the adapter is about to reset, no point in enabling stuff */ 1216 return true; 1217 } 1218 1219 netdev_tx_completed_queue(txring_txq(tx_ring), 1220 total_packets, total_bytes); 1221 1222 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1225 /* Make sure that anybody stopping the queue after this 1226 * sees the new next_to_clean. 1227 */ 1228 smp_mb(); 1229 if (__netif_subqueue_stopped(tx_ring->netdev, 1230 tx_ring->queue_index) 1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1232 netif_wake_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 ++tx_ring->tx_stats.restart_queue; 1235 } 1236 } 1237 1238 return !!budget; 1239 } 1240 1241 #ifdef CONFIG_IXGBE_DCA 1242 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1243 struct ixgbe_ring *tx_ring, 1244 int cpu) 1245 { 1246 struct ixgbe_hw *hw = &adapter->hw; 1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1248 u16 reg_offset; 1249 1250 switch (hw->mac.type) { 1251 case ixgbe_mac_82598EB: 1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1253 break; 1254 case ixgbe_mac_82599EB: 1255 case ixgbe_mac_X540: 1256 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1257 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1258 break; 1259 default: 1260 /* for unknown hardware do not write register */ 1261 return; 1262 } 1263 1264 /* 1265 * We can enable relaxed ordering for reads, but not writes when 1266 * DCA is enabled. This is due to a known issue in some chipsets 1267 * which will cause the DCA tag to be cleared. 1268 */ 1269 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1270 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1271 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1272 1273 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1274 } 1275 1276 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1277 struct ixgbe_ring *rx_ring, 1278 int cpu) 1279 { 1280 struct ixgbe_hw *hw = &adapter->hw; 1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1282 u8 reg_idx = rx_ring->reg_idx; 1283 1284 1285 switch (hw->mac.type) { 1286 case ixgbe_mac_82599EB: 1287 case ixgbe_mac_X540: 1288 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 /* 1295 * We can enable relaxed ordering for reads, but not writes when 1296 * DCA is enabled. This is due to a known issue in some chipsets 1297 * which will cause the DCA tag to be cleared. 1298 */ 1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1301 1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1303 } 1304 1305 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1306 { 1307 struct ixgbe_adapter *adapter = q_vector->adapter; 1308 struct ixgbe_ring *ring; 1309 int cpu = get_cpu(); 1310 1311 if (q_vector->cpu == cpu) 1312 goto out_no_update; 1313 1314 ixgbe_for_each_ring(ring, q_vector->tx) 1315 ixgbe_update_tx_dca(adapter, ring, cpu); 1316 1317 ixgbe_for_each_ring(ring, q_vector->rx) 1318 ixgbe_update_rx_dca(adapter, ring, cpu); 1319 1320 q_vector->cpu = cpu; 1321 out_no_update: 1322 put_cpu(); 1323 } 1324 1325 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1326 { 1327 int i; 1328 1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1330 return; 1331 1332 /* always use CB2 mode, difference is masked in the CB driver */ 1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1334 1335 for (i = 0; i < adapter->num_q_vectors; i++) { 1336 adapter->q_vector[i]->cpu = -1; 1337 ixgbe_update_dca(adapter->q_vector[i]); 1338 } 1339 } 1340 1341 static int __ixgbe_notify_dca(struct device *dev, void *data) 1342 { 1343 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1344 unsigned long event = *(unsigned long *)data; 1345 1346 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1347 return 0; 1348 1349 switch (event) { 1350 case DCA_PROVIDER_ADD: 1351 /* if we're already enabled, don't do it again */ 1352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1353 break; 1354 if (dca_add_requester(dev) == 0) { 1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1356 ixgbe_setup_dca(adapter); 1357 break; 1358 } 1359 /* Fall Through since DCA is disabled. */ 1360 case DCA_PROVIDER_REMOVE: 1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1362 dca_remove_requester(dev); 1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1365 } 1366 break; 1367 } 1368 1369 return 0; 1370 } 1371 1372 #endif /* CONFIG_IXGBE_DCA */ 1373 1374 #define IXGBE_RSS_L4_TYPES_MASK \ 1375 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1376 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1377 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1378 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1379 1380 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1381 union ixgbe_adv_rx_desc *rx_desc, 1382 struct sk_buff *skb) 1383 { 1384 u16 rss_type; 1385 1386 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1387 return; 1388 1389 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1390 IXGBE_RXDADV_RSSTYPE_MASK; 1391 1392 if (!rss_type) 1393 return; 1394 1395 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1396 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1397 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1398 } 1399 1400 #ifdef IXGBE_FCOE 1401 /** 1402 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1403 * @ring: structure containing ring specific data 1404 * @rx_desc: advanced rx descriptor 1405 * 1406 * Returns : true if it is FCoE pkt 1407 */ 1408 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1409 union ixgbe_adv_rx_desc *rx_desc) 1410 { 1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1412 1413 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1414 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1415 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1416 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1417 } 1418 1419 #endif /* IXGBE_FCOE */ 1420 /** 1421 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1422 * @ring: structure containing ring specific data 1423 * @rx_desc: current Rx descriptor being processed 1424 * @skb: skb currently being received and modified 1425 **/ 1426 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1427 union ixgbe_adv_rx_desc *rx_desc, 1428 struct sk_buff *skb) 1429 { 1430 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1431 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; 1432 bool encap_pkt = false; 1433 1434 skb_checksum_none_assert(skb); 1435 1436 /* Rx csum disabled */ 1437 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1438 return; 1439 1440 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && 1441 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { 1442 encap_pkt = true; 1443 skb->encapsulation = 1; 1444 } 1445 1446 /* if IP and error */ 1447 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1448 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1449 ring->rx_stats.csum_err++; 1450 return; 1451 } 1452 1453 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1454 return; 1455 1456 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1457 /* 1458 * 82599 errata, UDP frames with a 0 checksum can be marked as 1459 * checksum errors. 1460 */ 1461 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1462 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1463 return; 1464 1465 ring->rx_stats.csum_err++; 1466 return; 1467 } 1468 1469 /* It must be a TCP or UDP packet with a valid checksum */ 1470 skb->ip_summed = CHECKSUM_UNNECESSARY; 1471 if (encap_pkt) { 1472 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1473 return; 1474 1475 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1476 ring->rx_stats.csum_err++; 1477 return; 1478 } 1479 /* If we checked the outer header let the stack know */ 1480 skb->csum_level = 1; 1481 } 1482 } 1483 1484 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1485 struct ixgbe_rx_buffer *bi) 1486 { 1487 struct page *page = bi->page; 1488 dma_addr_t dma; 1489 1490 /* since we are recycling buffers we should seldom need to alloc */ 1491 if (likely(page)) 1492 return true; 1493 1494 /* alloc new page for storage */ 1495 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1496 if (unlikely(!page)) { 1497 rx_ring->rx_stats.alloc_rx_page_failed++; 1498 return false; 1499 } 1500 1501 /* map page for use */ 1502 dma = dma_map_page(rx_ring->dev, page, 0, 1503 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1504 1505 /* 1506 * if mapping failed free memory back to system since 1507 * there isn't much point in holding memory we can't use 1508 */ 1509 if (dma_mapping_error(rx_ring->dev, dma)) { 1510 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1511 1512 rx_ring->rx_stats.alloc_rx_page_failed++; 1513 return false; 1514 } 1515 1516 bi->dma = dma; 1517 bi->page = page; 1518 bi->page_offset = 0; 1519 1520 return true; 1521 } 1522 1523 /** 1524 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1525 * @rx_ring: ring to place buffers on 1526 * @cleaned_count: number of buffers to replace 1527 **/ 1528 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1529 { 1530 union ixgbe_adv_rx_desc *rx_desc; 1531 struct ixgbe_rx_buffer *bi; 1532 u16 i = rx_ring->next_to_use; 1533 1534 /* nothing to do */ 1535 if (!cleaned_count) 1536 return; 1537 1538 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1539 bi = &rx_ring->rx_buffer_info[i]; 1540 i -= rx_ring->count; 1541 1542 do { 1543 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1544 break; 1545 1546 /* 1547 * Refresh the desc even if buffer_addrs didn't change 1548 * because each write-back erases this info. 1549 */ 1550 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1551 1552 rx_desc++; 1553 bi++; 1554 i++; 1555 if (unlikely(!i)) { 1556 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1557 bi = rx_ring->rx_buffer_info; 1558 i -= rx_ring->count; 1559 } 1560 1561 /* clear the status bits for the next_to_use descriptor */ 1562 rx_desc->wb.upper.status_error = 0; 1563 1564 cleaned_count--; 1565 } while (cleaned_count); 1566 1567 i += rx_ring->count; 1568 1569 if (rx_ring->next_to_use != i) { 1570 rx_ring->next_to_use = i; 1571 1572 /* update next to alloc since we have filled the ring */ 1573 rx_ring->next_to_alloc = i; 1574 1575 /* Force memory writes to complete before letting h/w 1576 * know there are new descriptors to fetch. (Only 1577 * applicable for weak-ordered memory model archs, 1578 * such as IA-64). 1579 */ 1580 wmb(); 1581 writel(i, rx_ring->tail); 1582 } 1583 } 1584 1585 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1586 struct sk_buff *skb) 1587 { 1588 u16 hdr_len = skb_headlen(skb); 1589 1590 /* set gso_size to avoid messing up TCP MSS */ 1591 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1592 IXGBE_CB(skb)->append_cnt); 1593 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1594 } 1595 1596 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1597 struct sk_buff *skb) 1598 { 1599 /* if append_cnt is 0 then frame is not RSC */ 1600 if (!IXGBE_CB(skb)->append_cnt) 1601 return; 1602 1603 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1604 rx_ring->rx_stats.rsc_flush++; 1605 1606 ixgbe_set_rsc_gso_size(rx_ring, skb); 1607 1608 /* gso_size is computed using append_cnt so always clear it last */ 1609 IXGBE_CB(skb)->append_cnt = 0; 1610 } 1611 1612 /** 1613 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1614 * @rx_ring: rx descriptor ring packet is being transacted on 1615 * @rx_desc: pointer to the EOP Rx descriptor 1616 * @skb: pointer to current skb being populated 1617 * 1618 * This function checks the ring, descriptor, and packet information in 1619 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1620 * other fields within the skb. 1621 **/ 1622 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1623 union ixgbe_adv_rx_desc *rx_desc, 1624 struct sk_buff *skb) 1625 { 1626 struct net_device *dev = rx_ring->netdev; 1627 1628 ixgbe_update_rsc_stats(rx_ring, skb); 1629 1630 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1631 1632 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1633 1634 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1635 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1636 1637 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1638 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1639 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1641 } 1642 1643 skb_record_rx_queue(skb, rx_ring->queue_index); 1644 1645 skb->protocol = eth_type_trans(skb, dev); 1646 } 1647 1648 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1649 struct sk_buff *skb) 1650 { 1651 if (ixgbe_qv_busy_polling(q_vector)) 1652 netif_receive_skb(skb); 1653 else 1654 napi_gro_receive(&q_vector->napi, skb); 1655 } 1656 1657 /** 1658 * ixgbe_is_non_eop - process handling of non-EOP buffers 1659 * @rx_ring: Rx ring being processed 1660 * @rx_desc: Rx descriptor for current buffer 1661 * @skb: Current socket buffer containing buffer in progress 1662 * 1663 * This function updates next to clean. If the buffer is an EOP buffer 1664 * this function exits returning false, otherwise it will place the 1665 * sk_buff in the next buffer to be chained and return true indicating 1666 * that this is in fact a non-EOP buffer. 1667 **/ 1668 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1669 union ixgbe_adv_rx_desc *rx_desc, 1670 struct sk_buff *skb) 1671 { 1672 u32 ntc = rx_ring->next_to_clean + 1; 1673 1674 /* fetch, update, and store next to clean */ 1675 ntc = (ntc < rx_ring->count) ? ntc : 0; 1676 rx_ring->next_to_clean = ntc; 1677 1678 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1679 1680 /* update RSC append count if present */ 1681 if (ring_is_rsc_enabled(rx_ring)) { 1682 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1683 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1684 1685 if (unlikely(rsc_enabled)) { 1686 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1687 1688 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1689 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1690 1691 /* update ntc based on RSC value */ 1692 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1693 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1694 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1695 } 1696 } 1697 1698 /* if we are the last buffer then there is nothing else to do */ 1699 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1700 return false; 1701 1702 /* place skb in next buffer to be received */ 1703 rx_ring->rx_buffer_info[ntc].skb = skb; 1704 rx_ring->rx_stats.non_eop_descs++; 1705 1706 return true; 1707 } 1708 1709 /** 1710 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1711 * @rx_ring: rx descriptor ring packet is being transacted on 1712 * @skb: pointer to current skb being adjusted 1713 * 1714 * This function is an ixgbe specific version of __pskb_pull_tail. The 1715 * main difference between this version and the original function is that 1716 * this function can make several assumptions about the state of things 1717 * that allow for significant optimizations versus the standard function. 1718 * As a result we can do things like drop a frag and maintain an accurate 1719 * truesize for the skb. 1720 */ 1721 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1722 struct sk_buff *skb) 1723 { 1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1725 unsigned char *va; 1726 unsigned int pull_len; 1727 1728 /* 1729 * it is valid to use page_address instead of kmap since we are 1730 * working with pages allocated out of the lomem pool per 1731 * alloc_page(GFP_ATOMIC) 1732 */ 1733 va = skb_frag_address(frag); 1734 1735 /* 1736 * we need the header to contain the greater of either ETH_HLEN or 1737 * 60 bytes if the skb->len is less than 60 for skb_pad. 1738 */ 1739 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1740 1741 /* align pull length to size of long to optimize memcpy performance */ 1742 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1743 1744 /* update all of the pointers */ 1745 skb_frag_size_sub(frag, pull_len); 1746 frag->page_offset += pull_len; 1747 skb->data_len -= pull_len; 1748 skb->tail += pull_len; 1749 } 1750 1751 /** 1752 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1753 * @rx_ring: rx descriptor ring packet is being transacted on 1754 * @skb: pointer to current skb being updated 1755 * 1756 * This function provides a basic DMA sync up for the first fragment of an 1757 * skb. The reason for doing this is that the first fragment cannot be 1758 * unmapped until we have reached the end of packet descriptor for a buffer 1759 * chain. 1760 */ 1761 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1762 struct sk_buff *skb) 1763 { 1764 /* if the page was released unmap it, else just sync our portion */ 1765 if (unlikely(IXGBE_CB(skb)->page_released)) { 1766 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1767 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1768 IXGBE_CB(skb)->page_released = false; 1769 } else { 1770 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1771 1772 dma_sync_single_range_for_cpu(rx_ring->dev, 1773 IXGBE_CB(skb)->dma, 1774 frag->page_offset, 1775 ixgbe_rx_bufsz(rx_ring), 1776 DMA_FROM_DEVICE); 1777 } 1778 IXGBE_CB(skb)->dma = 0; 1779 } 1780 1781 /** 1782 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1783 * @rx_ring: rx descriptor ring packet is being transacted on 1784 * @rx_desc: pointer to the EOP Rx descriptor 1785 * @skb: pointer to current skb being fixed 1786 * 1787 * Check for corrupted packet headers caused by senders on the local L2 1788 * embedded NIC switch not setting up their Tx Descriptors right. These 1789 * should be very rare. 1790 * 1791 * Also address the case where we are pulling data in on pages only 1792 * and as such no data is present in the skb header. 1793 * 1794 * In addition if skb is not at least 60 bytes we need to pad it so that 1795 * it is large enough to qualify as a valid Ethernet frame. 1796 * 1797 * Returns true if an error was encountered and skb was freed. 1798 **/ 1799 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1800 union ixgbe_adv_rx_desc *rx_desc, 1801 struct sk_buff *skb) 1802 { 1803 struct net_device *netdev = rx_ring->netdev; 1804 1805 /* verify that the packet does not have any known errors */ 1806 if (unlikely(ixgbe_test_staterr(rx_desc, 1807 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1808 !(netdev->features & NETIF_F_RXALL))) { 1809 dev_kfree_skb_any(skb); 1810 return true; 1811 } 1812 1813 /* place header in linear portion of buffer */ 1814 if (skb_is_nonlinear(skb)) 1815 ixgbe_pull_tail(rx_ring, skb); 1816 1817 #ifdef IXGBE_FCOE 1818 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1819 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1820 return false; 1821 1822 #endif 1823 /* if eth_skb_pad returns an error the skb was freed */ 1824 if (eth_skb_pad(skb)) 1825 return true; 1826 1827 return false; 1828 } 1829 1830 /** 1831 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1832 * @rx_ring: rx descriptor ring to store buffers on 1833 * @old_buff: donor buffer to have page reused 1834 * 1835 * Synchronizes page for reuse by the adapter 1836 **/ 1837 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1838 struct ixgbe_rx_buffer *old_buff) 1839 { 1840 struct ixgbe_rx_buffer *new_buff; 1841 u16 nta = rx_ring->next_to_alloc; 1842 1843 new_buff = &rx_ring->rx_buffer_info[nta]; 1844 1845 /* update, and store next to alloc */ 1846 nta++; 1847 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1848 1849 /* transfer page from old buffer to new buffer */ 1850 *new_buff = *old_buff; 1851 1852 /* sync the buffer for use by the device */ 1853 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1854 new_buff->page_offset, 1855 ixgbe_rx_bufsz(rx_ring), 1856 DMA_FROM_DEVICE); 1857 } 1858 1859 static inline bool ixgbe_page_is_reserved(struct page *page) 1860 { 1861 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1862 } 1863 1864 /** 1865 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1866 * @rx_ring: rx descriptor ring to transact packets on 1867 * @rx_buffer: buffer containing page to add 1868 * @rx_desc: descriptor containing length of buffer written by hardware 1869 * @skb: sk_buff to place the data into 1870 * 1871 * This function will add the data contained in rx_buffer->page to the skb. 1872 * This is done either through a direct copy if the data in the buffer is 1873 * less than the skb header size, otherwise it will just attach the page as 1874 * a frag to the skb. 1875 * 1876 * The function will then update the page offset if necessary and return 1877 * true if the buffer can be reused by the adapter. 1878 **/ 1879 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1880 struct ixgbe_rx_buffer *rx_buffer, 1881 union ixgbe_adv_rx_desc *rx_desc, 1882 struct sk_buff *skb) 1883 { 1884 struct page *page = rx_buffer->page; 1885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1886 #if (PAGE_SIZE < 8192) 1887 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1888 #else 1889 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1890 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1891 ixgbe_rx_bufsz(rx_ring); 1892 #endif 1893 1894 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1895 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1896 1897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1898 1899 /* page is not reserved, we can reuse buffer as-is */ 1900 if (likely(!ixgbe_page_is_reserved(page))) 1901 return true; 1902 1903 /* this page cannot be reused so discard it */ 1904 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1905 return false; 1906 } 1907 1908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1909 rx_buffer->page_offset, size, truesize); 1910 1911 /* avoid re-using remote pages */ 1912 if (unlikely(ixgbe_page_is_reserved(page))) 1913 return false; 1914 1915 #if (PAGE_SIZE < 8192) 1916 /* if we are only owner of page we can reuse it */ 1917 if (unlikely(page_count(page) != 1)) 1918 return false; 1919 1920 /* flip page offset to other buffer */ 1921 rx_buffer->page_offset ^= truesize; 1922 #else 1923 /* move offset up to the next cache line */ 1924 rx_buffer->page_offset += truesize; 1925 1926 if (rx_buffer->page_offset > last_offset) 1927 return false; 1928 #endif 1929 1930 /* Even if we own the page, we are not allowed to use atomic_set() 1931 * This would break get_page_unless_zero() users. 1932 */ 1933 atomic_inc(&page->_count); 1934 1935 return true; 1936 } 1937 1938 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1939 union ixgbe_adv_rx_desc *rx_desc) 1940 { 1941 struct ixgbe_rx_buffer *rx_buffer; 1942 struct sk_buff *skb; 1943 struct page *page; 1944 1945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1946 page = rx_buffer->page; 1947 prefetchw(page); 1948 1949 skb = rx_buffer->skb; 1950 1951 if (likely(!skb)) { 1952 void *page_addr = page_address(page) + 1953 rx_buffer->page_offset; 1954 1955 /* prefetch first cache line of first page */ 1956 prefetch(page_addr); 1957 #if L1_CACHE_BYTES < 128 1958 prefetch(page_addr + L1_CACHE_BYTES); 1959 #endif 1960 1961 /* allocate a skb to store the frags */ 1962 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1963 IXGBE_RX_HDR_SIZE); 1964 if (unlikely(!skb)) { 1965 rx_ring->rx_stats.alloc_rx_buff_failed++; 1966 return NULL; 1967 } 1968 1969 /* 1970 * we will be copying header into skb->data in 1971 * pskb_may_pull so it is in our interest to prefetch 1972 * it now to avoid a possible cache miss 1973 */ 1974 prefetchw(skb->data); 1975 1976 /* 1977 * Delay unmapping of the first packet. It carries the 1978 * header information, HW may still access the header 1979 * after the writeback. Only unmap it when EOP is 1980 * reached 1981 */ 1982 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1983 goto dma_sync; 1984 1985 IXGBE_CB(skb)->dma = rx_buffer->dma; 1986 } else { 1987 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1988 ixgbe_dma_sync_frag(rx_ring, skb); 1989 1990 dma_sync: 1991 /* we are reusing so sync this buffer for CPU use */ 1992 dma_sync_single_range_for_cpu(rx_ring->dev, 1993 rx_buffer->dma, 1994 rx_buffer->page_offset, 1995 ixgbe_rx_bufsz(rx_ring), 1996 DMA_FROM_DEVICE); 1997 1998 rx_buffer->skb = NULL; 1999 } 2000 2001 /* pull page into skb */ 2002 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 2003 /* hand second half of page back to the ring */ 2004 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2005 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 2006 /* the page has been released from the ring */ 2007 IXGBE_CB(skb)->page_released = true; 2008 } else { 2009 /* we are not reusing the buffer so unmap it */ 2010 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 2011 ixgbe_rx_pg_size(rx_ring), 2012 DMA_FROM_DEVICE); 2013 } 2014 2015 /* clear contents of buffer_info */ 2016 rx_buffer->page = NULL; 2017 2018 return skb; 2019 } 2020 2021 /** 2022 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2023 * @q_vector: structure containing interrupt and ring information 2024 * @rx_ring: rx descriptor ring to transact packets on 2025 * @budget: Total limit on number of packets to process 2026 * 2027 * This function provides a "bounce buffer" approach to Rx interrupt 2028 * processing. The advantage to this is that on systems that have 2029 * expensive overhead for IOMMU access this provides a means of avoiding 2030 * it by maintaining the mapping of the page to the syste. 2031 * 2032 * Returns amount of work completed 2033 **/ 2034 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2035 struct ixgbe_ring *rx_ring, 2036 const int budget) 2037 { 2038 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2039 #ifdef IXGBE_FCOE 2040 struct ixgbe_adapter *adapter = q_vector->adapter; 2041 int ddp_bytes; 2042 unsigned int mss = 0; 2043 #endif /* IXGBE_FCOE */ 2044 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2045 2046 while (likely(total_rx_packets < budget)) { 2047 union ixgbe_adv_rx_desc *rx_desc; 2048 struct sk_buff *skb; 2049 2050 /* return some buffers to hardware, one at a time is too slow */ 2051 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2052 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2053 cleaned_count = 0; 2054 } 2055 2056 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2057 2058 if (!rx_desc->wb.upper.status_error) 2059 break; 2060 2061 /* This memory barrier is needed to keep us from reading 2062 * any other fields out of the rx_desc until we know the 2063 * descriptor has been written back 2064 */ 2065 dma_rmb(); 2066 2067 /* retrieve a buffer from the ring */ 2068 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2069 2070 /* exit if we failed to retrieve a buffer */ 2071 if (!skb) 2072 break; 2073 2074 cleaned_count++; 2075 2076 /* place incomplete frames back on ring for completion */ 2077 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2078 continue; 2079 2080 /* verify the packet layout is correct */ 2081 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2082 continue; 2083 2084 /* probably a little skewed due to removing CRC */ 2085 total_rx_bytes += skb->len; 2086 2087 /* populate checksum, timestamp, VLAN, and protocol */ 2088 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2089 2090 #ifdef IXGBE_FCOE 2091 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2092 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2093 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2094 /* include DDPed FCoE data */ 2095 if (ddp_bytes > 0) { 2096 if (!mss) { 2097 mss = rx_ring->netdev->mtu - 2098 sizeof(struct fcoe_hdr) - 2099 sizeof(struct fc_frame_header) - 2100 sizeof(struct fcoe_crc_eof); 2101 if (mss > 512) 2102 mss &= ~511; 2103 } 2104 total_rx_bytes += ddp_bytes; 2105 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2106 mss); 2107 } 2108 if (!ddp_bytes) { 2109 dev_kfree_skb_any(skb); 2110 continue; 2111 } 2112 } 2113 2114 #endif /* IXGBE_FCOE */ 2115 skb_mark_napi_id(skb, &q_vector->napi); 2116 ixgbe_rx_skb(q_vector, skb); 2117 2118 /* update budget accounting */ 2119 total_rx_packets++; 2120 } 2121 2122 u64_stats_update_begin(&rx_ring->syncp); 2123 rx_ring->stats.packets += total_rx_packets; 2124 rx_ring->stats.bytes += total_rx_bytes; 2125 u64_stats_update_end(&rx_ring->syncp); 2126 q_vector->rx.total_packets += total_rx_packets; 2127 q_vector->rx.total_bytes += total_rx_bytes; 2128 2129 return total_rx_packets; 2130 } 2131 2132 #ifdef CONFIG_NET_RX_BUSY_POLL 2133 /* must be called with local_bh_disable()d */ 2134 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2135 { 2136 struct ixgbe_q_vector *q_vector = 2137 container_of(napi, struct ixgbe_q_vector, napi); 2138 struct ixgbe_adapter *adapter = q_vector->adapter; 2139 struct ixgbe_ring *ring; 2140 int found = 0; 2141 2142 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2143 return LL_FLUSH_FAILED; 2144 2145 if (!ixgbe_qv_lock_poll(q_vector)) 2146 return LL_FLUSH_BUSY; 2147 2148 ixgbe_for_each_ring(ring, q_vector->rx) { 2149 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2150 #ifdef BP_EXTENDED_STATS 2151 if (found) 2152 ring->stats.cleaned += found; 2153 else 2154 ring->stats.misses++; 2155 #endif 2156 if (found) 2157 break; 2158 } 2159 2160 ixgbe_qv_unlock_poll(q_vector); 2161 2162 return found; 2163 } 2164 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2165 2166 /** 2167 * ixgbe_configure_msix - Configure MSI-X hardware 2168 * @adapter: board private structure 2169 * 2170 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2171 * interrupts. 2172 **/ 2173 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2174 { 2175 struct ixgbe_q_vector *q_vector; 2176 int v_idx; 2177 u32 mask; 2178 2179 /* Populate MSIX to EITR Select */ 2180 if (adapter->num_vfs > 32) { 2181 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2183 } 2184 2185 /* 2186 * Populate the IVAR table and set the ITR values to the 2187 * corresponding register. 2188 */ 2189 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2190 struct ixgbe_ring *ring; 2191 q_vector = adapter->q_vector[v_idx]; 2192 2193 ixgbe_for_each_ring(ring, q_vector->rx) 2194 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2195 2196 ixgbe_for_each_ring(ring, q_vector->tx) 2197 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2198 2199 ixgbe_write_eitr(q_vector); 2200 } 2201 2202 switch (adapter->hw.mac.type) { 2203 case ixgbe_mac_82598EB: 2204 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2205 v_idx); 2206 break; 2207 case ixgbe_mac_82599EB: 2208 case ixgbe_mac_X540: 2209 case ixgbe_mac_X550: 2210 case ixgbe_mac_X550EM_x: 2211 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2212 break; 2213 default: 2214 break; 2215 } 2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2217 2218 /* set up to autoclear timer, and the vectors */ 2219 mask = IXGBE_EIMS_ENABLE_MASK; 2220 mask &= ~(IXGBE_EIMS_OTHER | 2221 IXGBE_EIMS_MAILBOX | 2222 IXGBE_EIMS_LSC); 2223 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2225 } 2226 2227 enum latency_range { 2228 lowest_latency = 0, 2229 low_latency = 1, 2230 bulk_latency = 2, 2231 latency_invalid = 255 2232 }; 2233 2234 /** 2235 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2236 * @q_vector: structure containing interrupt and ring information 2237 * @ring_container: structure containing ring performance data 2238 * 2239 * Stores a new ITR value based on packets and byte 2240 * counts during the last interrupt. The advantage of per interrupt 2241 * computation is faster updates and more accurate ITR for the current 2242 * traffic pattern. Constants in this function were computed 2243 * based on theoretical maximum wire speed and thresholds were set based 2244 * on testing data as well as attempting to minimize response time 2245 * while increasing bulk throughput. 2246 * this functionality is controlled by the InterruptThrottleRate module 2247 * parameter (see ixgbe_param.c) 2248 **/ 2249 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2250 struct ixgbe_ring_container *ring_container) 2251 { 2252 int bytes = ring_container->total_bytes; 2253 int packets = ring_container->total_packets; 2254 u32 timepassed_us; 2255 u64 bytes_perint; 2256 u8 itr_setting = ring_container->itr; 2257 2258 if (packets == 0) 2259 return; 2260 2261 /* simple throttlerate management 2262 * 0-10MB/s lowest (100000 ints/s) 2263 * 10-20MB/s low (20000 ints/s) 2264 * 20-1249MB/s bulk (8000 ints/s) 2265 */ 2266 /* what was last interrupt timeslice? */ 2267 timepassed_us = q_vector->itr >> 2; 2268 if (timepassed_us == 0) 2269 return; 2270 2271 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2272 2273 switch (itr_setting) { 2274 case lowest_latency: 2275 if (bytes_perint > 10) 2276 itr_setting = low_latency; 2277 break; 2278 case low_latency: 2279 if (bytes_perint > 20) 2280 itr_setting = bulk_latency; 2281 else if (bytes_perint <= 10) 2282 itr_setting = lowest_latency; 2283 break; 2284 case bulk_latency: 2285 if (bytes_perint <= 20) 2286 itr_setting = low_latency; 2287 break; 2288 } 2289 2290 /* clear work counters since we have the values we need */ 2291 ring_container->total_bytes = 0; 2292 ring_container->total_packets = 0; 2293 2294 /* write updated itr to ring container */ 2295 ring_container->itr = itr_setting; 2296 } 2297 2298 /** 2299 * ixgbe_write_eitr - write EITR register in hardware specific way 2300 * @q_vector: structure containing interrupt and ring information 2301 * 2302 * This function is made to be called by ethtool and by the driver 2303 * when it needs to update EITR registers at runtime. Hardware 2304 * specific quirks/differences are taken care of here. 2305 */ 2306 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2307 { 2308 struct ixgbe_adapter *adapter = q_vector->adapter; 2309 struct ixgbe_hw *hw = &adapter->hw; 2310 int v_idx = q_vector->v_idx; 2311 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2312 2313 switch (adapter->hw.mac.type) { 2314 case ixgbe_mac_82598EB: 2315 /* must write high and low 16 bits to reset counter */ 2316 itr_reg |= (itr_reg << 16); 2317 break; 2318 case ixgbe_mac_82599EB: 2319 case ixgbe_mac_X540: 2320 case ixgbe_mac_X550: 2321 case ixgbe_mac_X550EM_x: 2322 /* 2323 * set the WDIS bit to not clear the timer bits and cause an 2324 * immediate assertion of the interrupt 2325 */ 2326 itr_reg |= IXGBE_EITR_CNT_WDIS; 2327 break; 2328 default: 2329 break; 2330 } 2331 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2332 } 2333 2334 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2335 { 2336 u32 new_itr = q_vector->itr; 2337 u8 current_itr; 2338 2339 ixgbe_update_itr(q_vector, &q_vector->tx); 2340 ixgbe_update_itr(q_vector, &q_vector->rx); 2341 2342 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2343 2344 switch (current_itr) { 2345 /* counts and packets in update_itr are dependent on these numbers */ 2346 case lowest_latency: 2347 new_itr = IXGBE_100K_ITR; 2348 break; 2349 case low_latency: 2350 new_itr = IXGBE_20K_ITR; 2351 break; 2352 case bulk_latency: 2353 new_itr = IXGBE_8K_ITR; 2354 break; 2355 default: 2356 break; 2357 } 2358 2359 if (new_itr != q_vector->itr) { 2360 /* do an exponential smoothing */ 2361 new_itr = (10 * new_itr * q_vector->itr) / 2362 ((9 * new_itr) + q_vector->itr); 2363 2364 /* save the algorithm value here */ 2365 q_vector->itr = new_itr; 2366 2367 ixgbe_write_eitr(q_vector); 2368 } 2369 } 2370 2371 /** 2372 * ixgbe_check_overtemp_subtask - check for over temperature 2373 * @adapter: pointer to adapter 2374 **/ 2375 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2376 { 2377 struct ixgbe_hw *hw = &adapter->hw; 2378 u32 eicr = adapter->interrupt_event; 2379 2380 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2381 return; 2382 2383 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2384 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2385 return; 2386 2387 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2388 2389 switch (hw->device_id) { 2390 case IXGBE_DEV_ID_82599_T3_LOM: 2391 /* 2392 * Since the warning interrupt is for both ports 2393 * we don't have to check if: 2394 * - This interrupt wasn't for our port. 2395 * - We may have missed the interrupt so always have to 2396 * check if we got a LSC 2397 */ 2398 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2399 !(eicr & IXGBE_EICR_LSC)) 2400 return; 2401 2402 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2403 u32 speed; 2404 bool link_up = false; 2405 2406 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2407 2408 if (link_up) 2409 return; 2410 } 2411 2412 /* Check if this is not due to overtemp */ 2413 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2414 return; 2415 2416 break; 2417 default: 2418 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2419 return; 2420 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2421 return; 2422 break; 2423 } 2424 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2425 2426 adapter->interrupt_event = 0; 2427 } 2428 2429 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2430 { 2431 struct ixgbe_hw *hw = &adapter->hw; 2432 2433 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2434 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2435 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2436 /* write to clear the interrupt */ 2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2438 } 2439 } 2440 2441 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2442 { 2443 struct ixgbe_hw *hw = &adapter->hw; 2444 2445 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2446 return; 2447 2448 switch (adapter->hw.mac.type) { 2449 case ixgbe_mac_82599EB: 2450 /* 2451 * Need to check link state so complete overtemp check 2452 * on service task 2453 */ 2454 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2455 (eicr & IXGBE_EICR_LSC)) && 2456 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2457 adapter->interrupt_event = eicr; 2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2459 ixgbe_service_event_schedule(adapter); 2460 return; 2461 } 2462 return; 2463 case ixgbe_mac_X540: 2464 if (!(eicr & IXGBE_EICR_TS)) 2465 return; 2466 break; 2467 default: 2468 return; 2469 } 2470 2471 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2472 } 2473 2474 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2475 { 2476 switch (hw->mac.type) { 2477 case ixgbe_mac_82598EB: 2478 if (hw->phy.type == ixgbe_phy_nl) 2479 return true; 2480 return false; 2481 case ixgbe_mac_82599EB: 2482 case ixgbe_mac_X550EM_x: 2483 switch (hw->mac.ops.get_media_type(hw)) { 2484 case ixgbe_media_type_fiber: 2485 case ixgbe_media_type_fiber_qsfp: 2486 return true; 2487 default: 2488 return false; 2489 } 2490 default: 2491 return false; 2492 } 2493 } 2494 2495 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2496 { 2497 struct ixgbe_hw *hw = &adapter->hw; 2498 2499 if (eicr & IXGBE_EICR_GPI_SDP2(hw)) { 2500 /* Clear the interrupt */ 2501 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2(hw)); 2502 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2503 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2504 ixgbe_service_event_schedule(adapter); 2505 } 2506 } 2507 2508 if (eicr & IXGBE_EICR_GPI_SDP1(hw)) { 2509 /* Clear the interrupt */ 2510 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2511 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2512 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2513 ixgbe_service_event_schedule(adapter); 2514 } 2515 } 2516 } 2517 2518 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2519 { 2520 struct ixgbe_hw *hw = &adapter->hw; 2521 2522 adapter->lsc_int++; 2523 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2524 adapter->link_check_timeout = jiffies; 2525 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2526 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2527 IXGBE_WRITE_FLUSH(hw); 2528 ixgbe_service_event_schedule(adapter); 2529 } 2530 } 2531 2532 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2533 u64 qmask) 2534 { 2535 u32 mask; 2536 struct ixgbe_hw *hw = &adapter->hw; 2537 2538 switch (hw->mac.type) { 2539 case ixgbe_mac_82598EB: 2540 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2541 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2542 break; 2543 case ixgbe_mac_82599EB: 2544 case ixgbe_mac_X540: 2545 case ixgbe_mac_X550: 2546 case ixgbe_mac_X550EM_x: 2547 mask = (qmask & 0xFFFFFFFF); 2548 if (mask) 2549 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2550 mask = (qmask >> 32); 2551 if (mask) 2552 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2553 break; 2554 default: 2555 break; 2556 } 2557 /* skip the flush */ 2558 } 2559 2560 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2561 u64 qmask) 2562 { 2563 u32 mask; 2564 struct ixgbe_hw *hw = &adapter->hw; 2565 2566 switch (hw->mac.type) { 2567 case ixgbe_mac_82598EB: 2568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2569 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2570 break; 2571 case ixgbe_mac_82599EB: 2572 case ixgbe_mac_X540: 2573 case ixgbe_mac_X550: 2574 case ixgbe_mac_X550EM_x: 2575 mask = (qmask & 0xFFFFFFFF); 2576 if (mask) 2577 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2578 mask = (qmask >> 32); 2579 if (mask) 2580 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2581 break; 2582 default: 2583 break; 2584 } 2585 /* skip the flush */ 2586 } 2587 2588 /** 2589 * ixgbe_irq_enable - Enable default interrupt generation settings 2590 * @adapter: board private structure 2591 **/ 2592 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2593 bool flush) 2594 { 2595 struct ixgbe_hw *hw = &adapter->hw; 2596 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2597 2598 /* don't reenable LSC while waiting for link */ 2599 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2600 mask &= ~IXGBE_EIMS_LSC; 2601 2602 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2603 switch (adapter->hw.mac.type) { 2604 case ixgbe_mac_82599EB: 2605 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2606 break; 2607 case ixgbe_mac_X540: 2608 case ixgbe_mac_X550: 2609 case ixgbe_mac_X550EM_x: 2610 mask |= IXGBE_EIMS_TS; 2611 break; 2612 default: 2613 break; 2614 } 2615 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2616 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2617 switch (adapter->hw.mac.type) { 2618 case ixgbe_mac_82599EB: 2619 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2620 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2621 /* fall through */ 2622 case ixgbe_mac_X540: 2623 case ixgbe_mac_X550: 2624 case ixgbe_mac_X550EM_x: 2625 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2626 mask |= IXGBE_EICR_GPI_SDP0_X540; 2627 mask |= IXGBE_EIMS_ECC; 2628 mask |= IXGBE_EIMS_MAILBOX; 2629 break; 2630 default: 2631 break; 2632 } 2633 2634 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2635 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2636 mask |= IXGBE_EIMS_FLOW_DIR; 2637 2638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2639 if (queues) 2640 ixgbe_irq_enable_queues(adapter, ~0); 2641 if (flush) 2642 IXGBE_WRITE_FLUSH(&adapter->hw); 2643 } 2644 2645 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2646 { 2647 struct ixgbe_adapter *adapter = data; 2648 struct ixgbe_hw *hw = &adapter->hw; 2649 u32 eicr; 2650 2651 /* 2652 * Workaround for Silicon errata. Use clear-by-write instead 2653 * of clear-by-read. Reading with EICS will return the 2654 * interrupt causes without clearing, which later be done 2655 * with the write to EICR. 2656 */ 2657 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2658 2659 /* The lower 16bits of the EICR register are for the queue interrupts 2660 * which should be masked here in order to not accidentally clear them if 2661 * the bits are high when ixgbe_msix_other is called. There is a race 2662 * condition otherwise which results in possible performance loss 2663 * especially if the ixgbe_msix_other interrupt is triggering 2664 * consistently (as it would when PPS is turned on for the X540 device) 2665 */ 2666 eicr &= 0xFFFF0000; 2667 2668 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2669 2670 if (eicr & IXGBE_EICR_LSC) 2671 ixgbe_check_lsc(adapter); 2672 2673 if (eicr & IXGBE_EICR_MAILBOX) 2674 ixgbe_msg_task(adapter); 2675 2676 switch (hw->mac.type) { 2677 case ixgbe_mac_82599EB: 2678 case ixgbe_mac_X540: 2679 case ixgbe_mac_X550: 2680 case ixgbe_mac_X550EM_x: 2681 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 2682 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2683 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 2684 ixgbe_service_event_schedule(adapter); 2685 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2686 IXGBE_EICR_GPI_SDP0_X540); 2687 } 2688 if (eicr & IXGBE_EICR_ECC) { 2689 e_info(link, "Received ECC Err, initiating reset\n"); 2690 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2691 ixgbe_service_event_schedule(adapter); 2692 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2693 } 2694 /* Handle Flow Director Full threshold interrupt */ 2695 if (eicr & IXGBE_EICR_FLOW_DIR) { 2696 int reinit_count = 0; 2697 int i; 2698 for (i = 0; i < adapter->num_tx_queues; i++) { 2699 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2700 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2701 &ring->state)) 2702 reinit_count++; 2703 } 2704 if (reinit_count) { 2705 /* no more flow director interrupts until after init */ 2706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2707 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2708 ixgbe_service_event_schedule(adapter); 2709 } 2710 } 2711 ixgbe_check_sfp_event(adapter, eicr); 2712 ixgbe_check_overtemp_event(adapter, eicr); 2713 break; 2714 default: 2715 break; 2716 } 2717 2718 ixgbe_check_fan_failure(adapter, eicr); 2719 2720 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2721 ixgbe_ptp_check_pps_event(adapter, eicr); 2722 2723 /* re-enable the original interrupt state, no lsc, no queues */ 2724 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2725 ixgbe_irq_enable(adapter, false, false); 2726 2727 return IRQ_HANDLED; 2728 } 2729 2730 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2731 { 2732 struct ixgbe_q_vector *q_vector = data; 2733 2734 /* EIAM disabled interrupts (on this vector) for us */ 2735 2736 if (q_vector->rx.ring || q_vector->tx.ring) 2737 napi_schedule(&q_vector->napi); 2738 2739 return IRQ_HANDLED; 2740 } 2741 2742 /** 2743 * ixgbe_poll - NAPI Rx polling callback 2744 * @napi: structure for representing this polling device 2745 * @budget: how many packets driver is allowed to clean 2746 * 2747 * This function is used for legacy and MSI, NAPI mode 2748 **/ 2749 int ixgbe_poll(struct napi_struct *napi, int budget) 2750 { 2751 struct ixgbe_q_vector *q_vector = 2752 container_of(napi, struct ixgbe_q_vector, napi); 2753 struct ixgbe_adapter *adapter = q_vector->adapter; 2754 struct ixgbe_ring *ring; 2755 int per_ring_budget; 2756 bool clean_complete = true; 2757 2758 #ifdef CONFIG_IXGBE_DCA 2759 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2760 ixgbe_update_dca(q_vector); 2761 #endif 2762 2763 ixgbe_for_each_ring(ring, q_vector->tx) 2764 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2765 2766 if (!ixgbe_qv_lock_napi(q_vector)) 2767 return budget; 2768 2769 /* attempt to distribute budget to each queue fairly, but don't allow 2770 * the budget to go below 1 because we'll exit polling */ 2771 if (q_vector->rx.count > 1) 2772 per_ring_budget = max(budget/q_vector->rx.count, 1); 2773 else 2774 per_ring_budget = budget; 2775 2776 ixgbe_for_each_ring(ring, q_vector->rx) 2777 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2778 per_ring_budget) < per_ring_budget); 2779 2780 ixgbe_qv_unlock_napi(q_vector); 2781 /* If all work not completed, return budget and keep polling */ 2782 if (!clean_complete) 2783 return budget; 2784 2785 /* all work done, exit the polling mode */ 2786 napi_complete(napi); 2787 if (adapter->rx_itr_setting & 1) 2788 ixgbe_set_itr(q_vector); 2789 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2790 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2791 2792 return 0; 2793 } 2794 2795 /** 2796 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2797 * @adapter: board private structure 2798 * 2799 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2800 * interrupts from the kernel. 2801 **/ 2802 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2803 { 2804 struct net_device *netdev = adapter->netdev; 2805 int vector, err; 2806 int ri = 0, ti = 0; 2807 2808 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2809 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2810 struct msix_entry *entry = &adapter->msix_entries[vector]; 2811 2812 if (q_vector->tx.ring && q_vector->rx.ring) { 2813 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2814 "%s-%s-%d", netdev->name, "TxRx", ri++); 2815 ti++; 2816 } else if (q_vector->rx.ring) { 2817 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2818 "%s-%s-%d", netdev->name, "rx", ri++); 2819 } else if (q_vector->tx.ring) { 2820 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2821 "%s-%s-%d", netdev->name, "tx", ti++); 2822 } else { 2823 /* skip this unused q_vector */ 2824 continue; 2825 } 2826 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2827 q_vector->name, q_vector); 2828 if (err) { 2829 e_err(probe, "request_irq failed for MSIX interrupt " 2830 "Error: %d\n", err); 2831 goto free_queue_irqs; 2832 } 2833 /* If Flow Director is enabled, set interrupt affinity */ 2834 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2835 /* assign the mask for this irq */ 2836 irq_set_affinity_hint(entry->vector, 2837 &q_vector->affinity_mask); 2838 } 2839 } 2840 2841 err = request_irq(adapter->msix_entries[vector].vector, 2842 ixgbe_msix_other, 0, netdev->name, adapter); 2843 if (err) { 2844 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2845 goto free_queue_irqs; 2846 } 2847 2848 return 0; 2849 2850 free_queue_irqs: 2851 while (vector) { 2852 vector--; 2853 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2854 NULL); 2855 free_irq(adapter->msix_entries[vector].vector, 2856 adapter->q_vector[vector]); 2857 } 2858 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2859 pci_disable_msix(adapter->pdev); 2860 kfree(adapter->msix_entries); 2861 adapter->msix_entries = NULL; 2862 return err; 2863 } 2864 2865 /** 2866 * ixgbe_intr - legacy mode Interrupt Handler 2867 * @irq: interrupt number 2868 * @data: pointer to a network interface device structure 2869 **/ 2870 static irqreturn_t ixgbe_intr(int irq, void *data) 2871 { 2872 struct ixgbe_adapter *adapter = data; 2873 struct ixgbe_hw *hw = &adapter->hw; 2874 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2875 u32 eicr; 2876 2877 /* 2878 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2879 * before the read of EICR. 2880 */ 2881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2882 2883 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2884 * therefore no explicit interrupt disable is necessary */ 2885 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2886 if (!eicr) { 2887 /* 2888 * shared interrupt alert! 2889 * make sure interrupts are enabled because the read will 2890 * have disabled interrupts due to EIAM 2891 * finish the workaround of silicon errata on 82598. Unmask 2892 * the interrupt that we masked before the EICR read. 2893 */ 2894 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2895 ixgbe_irq_enable(adapter, true, true); 2896 return IRQ_NONE; /* Not our interrupt */ 2897 } 2898 2899 if (eicr & IXGBE_EICR_LSC) 2900 ixgbe_check_lsc(adapter); 2901 2902 switch (hw->mac.type) { 2903 case ixgbe_mac_82599EB: 2904 ixgbe_check_sfp_event(adapter, eicr); 2905 /* Fall through */ 2906 case ixgbe_mac_X540: 2907 case ixgbe_mac_X550: 2908 case ixgbe_mac_X550EM_x: 2909 if (eicr & IXGBE_EICR_ECC) { 2910 e_info(link, "Received ECC Err, initiating reset\n"); 2911 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2912 ixgbe_service_event_schedule(adapter); 2913 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2914 } 2915 ixgbe_check_overtemp_event(adapter, eicr); 2916 break; 2917 default: 2918 break; 2919 } 2920 2921 ixgbe_check_fan_failure(adapter, eicr); 2922 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2923 ixgbe_ptp_check_pps_event(adapter, eicr); 2924 2925 /* would disable interrupts here but EIAM disabled it */ 2926 napi_schedule(&q_vector->napi); 2927 2928 /* 2929 * re-enable link(maybe) and non-queue interrupts, no flush. 2930 * ixgbe_poll will re-enable the queue interrupts 2931 */ 2932 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2933 ixgbe_irq_enable(adapter, false, false); 2934 2935 return IRQ_HANDLED; 2936 } 2937 2938 /** 2939 * ixgbe_request_irq - initialize interrupts 2940 * @adapter: board private structure 2941 * 2942 * Attempts to configure interrupts using the best available 2943 * capabilities of the hardware and kernel. 2944 **/ 2945 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2946 { 2947 struct net_device *netdev = adapter->netdev; 2948 int err; 2949 2950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2951 err = ixgbe_request_msix_irqs(adapter); 2952 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2953 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2954 netdev->name, adapter); 2955 else 2956 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2957 netdev->name, adapter); 2958 2959 if (err) 2960 e_err(probe, "request_irq failed, Error %d\n", err); 2961 2962 return err; 2963 } 2964 2965 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2966 { 2967 int vector; 2968 2969 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2970 free_irq(adapter->pdev->irq, adapter); 2971 return; 2972 } 2973 2974 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2975 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2976 struct msix_entry *entry = &adapter->msix_entries[vector]; 2977 2978 /* free only the irqs that were actually requested */ 2979 if (!q_vector->rx.ring && !q_vector->tx.ring) 2980 continue; 2981 2982 /* clear the affinity_mask in the IRQ descriptor */ 2983 irq_set_affinity_hint(entry->vector, NULL); 2984 2985 free_irq(entry->vector, q_vector); 2986 } 2987 2988 free_irq(adapter->msix_entries[vector++].vector, adapter); 2989 } 2990 2991 /** 2992 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2993 * @adapter: board private structure 2994 **/ 2995 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2996 { 2997 switch (adapter->hw.mac.type) { 2998 case ixgbe_mac_82598EB: 2999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3000 break; 3001 case ixgbe_mac_82599EB: 3002 case ixgbe_mac_X540: 3003 case ixgbe_mac_X550: 3004 case ixgbe_mac_X550EM_x: 3005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3008 break; 3009 default: 3010 break; 3011 } 3012 IXGBE_WRITE_FLUSH(&adapter->hw); 3013 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3014 int vector; 3015 3016 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3017 synchronize_irq(adapter->msix_entries[vector].vector); 3018 3019 synchronize_irq(adapter->msix_entries[vector++].vector); 3020 } else { 3021 synchronize_irq(adapter->pdev->irq); 3022 } 3023 } 3024 3025 /** 3026 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3027 * 3028 **/ 3029 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3030 { 3031 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3032 3033 ixgbe_write_eitr(q_vector); 3034 3035 ixgbe_set_ivar(adapter, 0, 0, 0); 3036 ixgbe_set_ivar(adapter, 1, 0, 0); 3037 3038 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3039 } 3040 3041 /** 3042 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3043 * @adapter: board private structure 3044 * @ring: structure containing ring specific data 3045 * 3046 * Configure the Tx descriptor ring after a reset. 3047 **/ 3048 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3049 struct ixgbe_ring *ring) 3050 { 3051 struct ixgbe_hw *hw = &adapter->hw; 3052 u64 tdba = ring->dma; 3053 int wait_loop = 10; 3054 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3055 u8 reg_idx = ring->reg_idx; 3056 3057 /* disable queue to avoid issues while updating state */ 3058 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3059 IXGBE_WRITE_FLUSH(hw); 3060 3061 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3062 (tdba & DMA_BIT_MASK(32))); 3063 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3064 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3065 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3066 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3067 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3068 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3069 3070 /* 3071 * set WTHRESH to encourage burst writeback, it should not be set 3072 * higher than 1 when: 3073 * - ITR is 0 as it could cause false TX hangs 3074 * - ITR is set to > 100k int/sec and BQL is enabled 3075 * 3076 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3077 * to or less than the number of on chip descriptors, which is 3078 * currently 40. 3079 */ 3080 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3081 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3082 else 3083 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3084 3085 /* 3086 * Setting PTHRESH to 32 both improves performance 3087 * and avoids a TX hang with DFP enabled 3088 */ 3089 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3090 32; /* PTHRESH = 32 */ 3091 3092 /* reinitialize flowdirector state */ 3093 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3094 ring->atr_sample_rate = adapter->atr_sample_rate; 3095 ring->atr_count = 0; 3096 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3097 } else { 3098 ring->atr_sample_rate = 0; 3099 } 3100 3101 /* initialize XPS */ 3102 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3103 struct ixgbe_q_vector *q_vector = ring->q_vector; 3104 3105 if (q_vector) 3106 netif_set_xps_queue(ring->netdev, 3107 &q_vector->affinity_mask, 3108 ring->queue_index); 3109 } 3110 3111 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3112 3113 /* enable queue */ 3114 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3115 3116 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3117 if (hw->mac.type == ixgbe_mac_82598EB && 3118 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3119 return; 3120 3121 /* poll to verify queue is enabled */ 3122 do { 3123 usleep_range(1000, 2000); 3124 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3125 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3126 if (!wait_loop) 3127 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3128 } 3129 3130 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3131 { 3132 struct ixgbe_hw *hw = &adapter->hw; 3133 u32 rttdcs, mtqc; 3134 u8 tcs = netdev_get_num_tc(adapter->netdev); 3135 3136 if (hw->mac.type == ixgbe_mac_82598EB) 3137 return; 3138 3139 /* disable the arbiter while setting MTQC */ 3140 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3141 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3142 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3143 3144 /* set transmit pool layout */ 3145 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3146 mtqc = IXGBE_MTQC_VT_ENA; 3147 if (tcs > 4) 3148 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3149 else if (tcs > 1) 3150 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3151 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3152 mtqc |= IXGBE_MTQC_32VF; 3153 else 3154 mtqc |= IXGBE_MTQC_64VF; 3155 } else { 3156 if (tcs > 4) 3157 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3158 else if (tcs > 1) 3159 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3160 else 3161 mtqc = IXGBE_MTQC_64Q_1PB; 3162 } 3163 3164 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3165 3166 /* Enable Security TX Buffer IFG for multiple pb */ 3167 if (tcs) { 3168 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3169 sectx |= IXGBE_SECTX_DCB; 3170 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3171 } 3172 3173 /* re-enable the arbiter */ 3174 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3175 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3176 } 3177 3178 /** 3179 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3180 * @adapter: board private structure 3181 * 3182 * Configure the Tx unit of the MAC after a reset. 3183 **/ 3184 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3185 { 3186 struct ixgbe_hw *hw = &adapter->hw; 3187 u32 dmatxctl; 3188 u32 i; 3189 3190 ixgbe_setup_mtqc(adapter); 3191 3192 if (hw->mac.type != ixgbe_mac_82598EB) { 3193 /* DMATXCTL.EN must be before Tx queues are enabled */ 3194 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3195 dmatxctl |= IXGBE_DMATXCTL_TE; 3196 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3197 } 3198 3199 /* Setup the HW Tx Head and Tail descriptor pointers */ 3200 for (i = 0; i < adapter->num_tx_queues; i++) 3201 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3202 } 3203 3204 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3205 struct ixgbe_ring *ring) 3206 { 3207 struct ixgbe_hw *hw = &adapter->hw; 3208 u8 reg_idx = ring->reg_idx; 3209 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3210 3211 srrctl |= IXGBE_SRRCTL_DROP_EN; 3212 3213 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3214 } 3215 3216 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3217 struct ixgbe_ring *ring) 3218 { 3219 struct ixgbe_hw *hw = &adapter->hw; 3220 u8 reg_idx = ring->reg_idx; 3221 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3222 3223 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3224 3225 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3226 } 3227 3228 #ifdef CONFIG_IXGBE_DCB 3229 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3230 #else 3231 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3232 #endif 3233 { 3234 int i; 3235 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3236 3237 if (adapter->ixgbe_ieee_pfc) 3238 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3239 3240 /* 3241 * We should set the drop enable bit if: 3242 * SR-IOV is enabled 3243 * or 3244 * Number of Rx queues > 1 and flow control is disabled 3245 * 3246 * This allows us to avoid head of line blocking for security 3247 * and performance reasons. 3248 */ 3249 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3250 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3251 for (i = 0; i < adapter->num_rx_queues; i++) 3252 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3253 } else { 3254 for (i = 0; i < adapter->num_rx_queues; i++) 3255 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3256 } 3257 } 3258 3259 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3260 3261 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3262 struct ixgbe_ring *rx_ring) 3263 { 3264 struct ixgbe_hw *hw = &adapter->hw; 3265 u32 srrctl; 3266 u8 reg_idx = rx_ring->reg_idx; 3267 3268 if (hw->mac.type == ixgbe_mac_82598EB) { 3269 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3270 3271 /* 3272 * if VMDq is not active we must program one srrctl register 3273 * per RSS queue since we have enabled RDRXCTL.MVMEN 3274 */ 3275 reg_idx &= mask; 3276 } 3277 3278 /* configure header buffer length, needed for RSC */ 3279 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3280 3281 /* configure the packet buffer length */ 3282 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3283 3284 /* configure descriptor type */ 3285 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3286 3287 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3288 } 3289 3290 /** 3291 * Return a number of entries in the RSS indirection table 3292 * 3293 * @adapter: device handle 3294 * 3295 * - 82598/82599/X540: 128 3296 * - X550(non-SRIOV mode): 512 3297 * - X550(SRIOV mode): 64 3298 */ 3299 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3300 { 3301 if (adapter->hw.mac.type < ixgbe_mac_X550) 3302 return 128; 3303 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3304 return 64; 3305 else 3306 return 512; 3307 } 3308 3309 /** 3310 * Write the RETA table to HW 3311 * 3312 * @adapter: device handle 3313 * 3314 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3315 */ 3316 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3317 { 3318 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3319 struct ixgbe_hw *hw = &adapter->hw; 3320 u32 reta = 0; 3321 u32 indices_multi; 3322 u8 *indir_tbl = adapter->rss_indir_tbl; 3323 3324 /* Fill out the redirection table as follows: 3325 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3326 * indices. 3327 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3328 * - X550: 8 bit wide entries containing 6 bit RSS index 3329 */ 3330 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3331 indices_multi = 0x11; 3332 else 3333 indices_multi = 0x1; 3334 3335 /* Write redirection table to HW */ 3336 for (i = 0; i < reta_entries; i++) { 3337 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3338 if ((i & 3) == 3) { 3339 if (i < 128) 3340 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3341 else 3342 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3343 reta); 3344 reta = 0; 3345 } 3346 } 3347 } 3348 3349 /** 3350 * Write the RETA table to HW (for x550 devices in SRIOV mode) 3351 * 3352 * @adapter: device handle 3353 * 3354 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3355 */ 3356 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3357 { 3358 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3359 struct ixgbe_hw *hw = &adapter->hw; 3360 u32 vfreta = 0; 3361 unsigned int pf_pool = adapter->num_vfs; 3362 3363 /* Write redirection table to HW */ 3364 for (i = 0; i < reta_entries; i++) { 3365 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3366 if ((i & 3) == 3) { 3367 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3368 vfreta); 3369 vfreta = 0; 3370 } 3371 } 3372 } 3373 3374 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3375 { 3376 struct ixgbe_hw *hw = &adapter->hw; 3377 u32 i, j; 3378 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3379 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3380 3381 /* Program table for at least 2 queues w/ SR-IOV so that VFs can 3382 * make full use of any rings they may have. We will use the 3383 * PSRTYPE register to control how many rings we use within the PF. 3384 */ 3385 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3386 rss_i = 2; 3387 3388 /* Fill out hash function seeds */ 3389 for (i = 0; i < 10; i++) 3390 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3391 3392 /* Fill out redirection table */ 3393 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3394 3395 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3396 if (j == rss_i) 3397 j = 0; 3398 3399 adapter->rss_indir_tbl[i] = j; 3400 } 3401 3402 ixgbe_store_reta(adapter); 3403 } 3404 3405 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3406 { 3407 struct ixgbe_hw *hw = &adapter->hw; 3408 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3409 unsigned int pf_pool = adapter->num_vfs; 3410 int i, j; 3411 3412 /* Fill out hash function seeds */ 3413 for (i = 0; i < 10; i++) 3414 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3415 adapter->rss_key[i]); 3416 3417 /* Fill out the redirection table */ 3418 for (i = 0, j = 0; i < 64; i++, j++) { 3419 if (j == rss_i) 3420 j = 0; 3421 3422 adapter->rss_indir_tbl[i] = j; 3423 } 3424 3425 ixgbe_store_vfreta(adapter); 3426 } 3427 3428 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3429 { 3430 struct ixgbe_hw *hw = &adapter->hw; 3431 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3432 u32 rxcsum; 3433 3434 /* Disable indicating checksum in descriptor, enables RSS hash */ 3435 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3436 rxcsum |= IXGBE_RXCSUM_PCSD; 3437 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3438 3439 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3440 if (adapter->ring_feature[RING_F_RSS].mask) 3441 mrqc = IXGBE_MRQC_RSSEN; 3442 } else { 3443 u8 tcs = netdev_get_num_tc(adapter->netdev); 3444 3445 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3446 if (tcs > 4) 3447 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3448 else if (tcs > 1) 3449 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3450 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3451 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3452 else 3453 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3454 } else { 3455 if (tcs > 4) 3456 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3457 else if (tcs > 1) 3458 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3459 else 3460 mrqc = IXGBE_MRQC_RSSEN; 3461 } 3462 } 3463 3464 /* Perform hash on these packet types */ 3465 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3466 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3467 IXGBE_MRQC_RSS_FIELD_IPV6 | 3468 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3469 3470 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3471 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3472 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3473 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3474 3475 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key)); 3476 if ((hw->mac.type >= ixgbe_mac_X550) && 3477 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3478 unsigned int pf_pool = adapter->num_vfs; 3479 3480 /* Enable VF RSS mode */ 3481 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3482 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3483 3484 /* Setup RSS through the VF registers */ 3485 ixgbe_setup_vfreta(adapter); 3486 vfmrqc = IXGBE_MRQC_RSSEN; 3487 vfmrqc |= rss_field; 3488 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3489 } else { 3490 ixgbe_setup_reta(adapter); 3491 mrqc |= rss_field; 3492 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3493 } 3494 } 3495 3496 /** 3497 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3498 * @adapter: address of board private structure 3499 * @index: index of ring to set 3500 **/ 3501 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3502 struct ixgbe_ring *ring) 3503 { 3504 struct ixgbe_hw *hw = &adapter->hw; 3505 u32 rscctrl; 3506 u8 reg_idx = ring->reg_idx; 3507 3508 if (!ring_is_rsc_enabled(ring)) 3509 return; 3510 3511 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3512 rscctrl |= IXGBE_RSCCTL_RSCEN; 3513 /* 3514 * we must limit the number of descriptors so that the 3515 * total size of max desc * buf_len is not greater 3516 * than 65536 3517 */ 3518 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3519 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3520 } 3521 3522 #define IXGBE_MAX_RX_DESC_POLL 10 3523 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3524 struct ixgbe_ring *ring) 3525 { 3526 struct ixgbe_hw *hw = &adapter->hw; 3527 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3528 u32 rxdctl; 3529 u8 reg_idx = ring->reg_idx; 3530 3531 if (ixgbe_removed(hw->hw_addr)) 3532 return; 3533 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3534 if (hw->mac.type == ixgbe_mac_82598EB && 3535 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3536 return; 3537 3538 do { 3539 usleep_range(1000, 2000); 3540 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3541 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3542 3543 if (!wait_loop) { 3544 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3545 "the polling period\n", reg_idx); 3546 } 3547 } 3548 3549 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3550 struct ixgbe_ring *ring) 3551 { 3552 struct ixgbe_hw *hw = &adapter->hw; 3553 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3554 u32 rxdctl; 3555 u8 reg_idx = ring->reg_idx; 3556 3557 if (ixgbe_removed(hw->hw_addr)) 3558 return; 3559 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3560 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3561 3562 /* write value back with RXDCTL.ENABLE bit cleared */ 3563 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3564 3565 if (hw->mac.type == ixgbe_mac_82598EB && 3566 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3567 return; 3568 3569 /* the hardware may take up to 100us to really disable the rx queue */ 3570 do { 3571 udelay(10); 3572 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3573 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3574 3575 if (!wait_loop) { 3576 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3577 "the polling period\n", reg_idx); 3578 } 3579 } 3580 3581 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3582 struct ixgbe_ring *ring) 3583 { 3584 struct ixgbe_hw *hw = &adapter->hw; 3585 u64 rdba = ring->dma; 3586 u32 rxdctl; 3587 u8 reg_idx = ring->reg_idx; 3588 3589 /* disable queue to avoid issues while updating state */ 3590 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3591 ixgbe_disable_rx_queue(adapter, ring); 3592 3593 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3594 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3595 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3596 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3597 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3598 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3599 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3600 3601 ixgbe_configure_srrctl(adapter, ring); 3602 ixgbe_configure_rscctl(adapter, ring); 3603 3604 if (hw->mac.type == ixgbe_mac_82598EB) { 3605 /* 3606 * enable cache line friendly hardware writes: 3607 * PTHRESH=32 descriptors (half the internal cache), 3608 * this also removes ugly rx_no_buffer_count increment 3609 * HTHRESH=4 descriptors (to minimize latency on fetch) 3610 * WTHRESH=8 burst writeback up to two cache lines 3611 */ 3612 rxdctl &= ~0x3FFFFF; 3613 rxdctl |= 0x080420; 3614 } 3615 3616 /* enable receive descriptor ring */ 3617 rxdctl |= IXGBE_RXDCTL_ENABLE; 3618 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3619 3620 ixgbe_rx_desc_queue_enable(adapter, ring); 3621 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3622 } 3623 3624 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3625 { 3626 struct ixgbe_hw *hw = &adapter->hw; 3627 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3628 u16 pool; 3629 3630 /* PSRTYPE must be initialized in non 82598 adapters */ 3631 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3632 IXGBE_PSRTYPE_UDPHDR | 3633 IXGBE_PSRTYPE_IPV4HDR | 3634 IXGBE_PSRTYPE_L2HDR | 3635 IXGBE_PSRTYPE_IPV6HDR; 3636 3637 if (hw->mac.type == ixgbe_mac_82598EB) 3638 return; 3639 3640 if (rss_i > 3) 3641 psrtype |= 2 << 29; 3642 else if (rss_i > 1) 3643 psrtype |= 1 << 29; 3644 3645 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3646 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3647 } 3648 3649 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3650 { 3651 struct ixgbe_hw *hw = &adapter->hw; 3652 u32 reg_offset, vf_shift; 3653 u32 gcr_ext, vmdctl; 3654 int i; 3655 3656 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3657 return; 3658 3659 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3660 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3661 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3662 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3663 vmdctl |= IXGBE_VT_CTL_REPLEN; 3664 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3665 3666 vf_shift = VMDQ_P(0) % 32; 3667 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3668 3669 /* Enable only the PF's pool for Tx/Rx */ 3670 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3671 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3672 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3673 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3674 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 3675 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3676 3677 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3678 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3679 3680 /* 3681 * Set up VF register offsets for selected VT Mode, 3682 * i.e. 32 or 64 VFs for SR-IOV 3683 */ 3684 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3685 case IXGBE_82599_VMDQ_8Q_MASK: 3686 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3687 break; 3688 case IXGBE_82599_VMDQ_4Q_MASK: 3689 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3690 break; 3691 default: 3692 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3693 break; 3694 } 3695 3696 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3697 3698 3699 /* Enable MAC Anti-Spoofing */ 3700 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3701 adapter->num_vfs); 3702 3703 /* Ensure LLDP is set for Ethertype Antispoofing if we will be 3704 * calling set_ethertype_anti_spoofing for each VF in loop below 3705 */ 3706 if (hw->mac.ops.set_ethertype_anti_spoofing) 3707 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 3708 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 3709 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */ 3710 IXGBE_ETH_P_LLDP)); /* LLDP eth type */ 3711 3712 /* For VFs that have spoof checking turned off */ 3713 for (i = 0; i < adapter->num_vfs; i++) { 3714 if (!adapter->vfinfo[i].spoofchk_enabled) 3715 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3716 3717 /* enable ethertype anti spoofing if hw supports it */ 3718 if (hw->mac.ops.set_ethertype_anti_spoofing) 3719 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 3720 3721 /* Enable/Disable RSS query feature */ 3722 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 3723 adapter->vfinfo[i].rss_query_enabled); 3724 } 3725 } 3726 3727 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3728 { 3729 struct ixgbe_hw *hw = &adapter->hw; 3730 struct net_device *netdev = adapter->netdev; 3731 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3732 struct ixgbe_ring *rx_ring; 3733 int i; 3734 u32 mhadd, hlreg0; 3735 3736 #ifdef IXGBE_FCOE 3737 /* adjust max frame to be able to do baby jumbo for FCoE */ 3738 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3739 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3740 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3741 3742 #endif /* IXGBE_FCOE */ 3743 3744 /* adjust max frame to be at least the size of a standard frame */ 3745 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3746 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3747 3748 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3749 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3750 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3751 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3752 3753 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3754 } 3755 3756 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3757 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3758 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3759 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3760 3761 /* 3762 * Setup the HW Rx Head and Tail Descriptor Pointers and 3763 * the Base and Length of the Rx Descriptor Ring 3764 */ 3765 for (i = 0; i < adapter->num_rx_queues; i++) { 3766 rx_ring = adapter->rx_ring[i]; 3767 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3768 set_ring_rsc_enabled(rx_ring); 3769 else 3770 clear_ring_rsc_enabled(rx_ring); 3771 } 3772 } 3773 3774 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3775 { 3776 struct ixgbe_hw *hw = &adapter->hw; 3777 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3778 3779 switch (hw->mac.type) { 3780 case ixgbe_mac_X550: 3781 case ixgbe_mac_X550EM_x: 3782 case ixgbe_mac_82598EB: 3783 /* 3784 * For VMDq support of different descriptor types or 3785 * buffer sizes through the use of multiple SRRCTL 3786 * registers, RDRXCTL.MVMEN must be set to 1 3787 * 3788 * also, the manual doesn't mention it clearly but DCA hints 3789 * will only use queue 0's tags unless this bit is set. Side 3790 * effects of setting this bit are only that SRRCTL must be 3791 * fully programmed [0..15] 3792 */ 3793 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3794 break; 3795 case ixgbe_mac_82599EB: 3796 case ixgbe_mac_X540: 3797 /* Disable RSC for ACK packets */ 3798 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3799 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3800 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3801 /* hardware requires some bits to be set by default */ 3802 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3803 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3804 break; 3805 default: 3806 /* We should do nothing since we don't know this hardware */ 3807 return; 3808 } 3809 3810 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3811 } 3812 3813 /** 3814 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3815 * @adapter: board private structure 3816 * 3817 * Configure the Rx unit of the MAC after a reset. 3818 **/ 3819 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3820 { 3821 struct ixgbe_hw *hw = &adapter->hw; 3822 int i; 3823 u32 rxctrl, rfctl; 3824 3825 /* disable receives while setting up the descriptors */ 3826 hw->mac.ops.disable_rx(hw); 3827 3828 ixgbe_setup_psrtype(adapter); 3829 ixgbe_setup_rdrxctl(adapter); 3830 3831 /* RSC Setup */ 3832 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3833 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3834 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3835 rfctl |= IXGBE_RFCTL_RSC_DIS; 3836 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3837 3838 /* Program registers for the distribution of queues */ 3839 ixgbe_setup_mrqc(adapter); 3840 3841 /* set_rx_buffer_len must be called before ring initialization */ 3842 ixgbe_set_rx_buffer_len(adapter); 3843 3844 /* 3845 * Setup the HW Rx Head and Tail Descriptor Pointers and 3846 * the Base and Length of the Rx Descriptor Ring 3847 */ 3848 for (i = 0; i < adapter->num_rx_queues; i++) 3849 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3850 3851 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3852 /* disable drop enable for 82598 parts */ 3853 if (hw->mac.type == ixgbe_mac_82598EB) 3854 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3855 3856 /* enable all receives */ 3857 rxctrl |= IXGBE_RXCTRL_RXEN; 3858 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3859 } 3860 3861 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3862 __be16 proto, u16 vid) 3863 { 3864 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3865 struct ixgbe_hw *hw = &adapter->hw; 3866 3867 /* add VID to filter table */ 3868 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3869 set_bit(vid, adapter->active_vlans); 3870 3871 return 0; 3872 } 3873 3874 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3875 __be16 proto, u16 vid) 3876 { 3877 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3878 struct ixgbe_hw *hw = &adapter->hw; 3879 3880 /* remove VID from filter table */ 3881 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3882 clear_bit(vid, adapter->active_vlans); 3883 3884 return 0; 3885 } 3886 3887 /** 3888 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3889 * @adapter: driver data 3890 */ 3891 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3892 { 3893 struct ixgbe_hw *hw = &adapter->hw; 3894 u32 vlnctrl; 3895 int i, j; 3896 3897 switch (hw->mac.type) { 3898 case ixgbe_mac_82598EB: 3899 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3900 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3901 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3902 break; 3903 case ixgbe_mac_82599EB: 3904 case ixgbe_mac_X540: 3905 case ixgbe_mac_X550: 3906 case ixgbe_mac_X550EM_x: 3907 for (i = 0; i < adapter->num_rx_queues; i++) { 3908 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3909 3910 if (ring->l2_accel_priv) 3911 continue; 3912 j = ring->reg_idx; 3913 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3914 vlnctrl &= ~IXGBE_RXDCTL_VME; 3915 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3916 } 3917 break; 3918 default: 3919 break; 3920 } 3921 } 3922 3923 /** 3924 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3925 * @adapter: driver data 3926 */ 3927 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3928 { 3929 struct ixgbe_hw *hw = &adapter->hw; 3930 u32 vlnctrl; 3931 int i, j; 3932 3933 switch (hw->mac.type) { 3934 case ixgbe_mac_82598EB: 3935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3936 vlnctrl |= IXGBE_VLNCTRL_VME; 3937 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3938 break; 3939 case ixgbe_mac_82599EB: 3940 case ixgbe_mac_X540: 3941 case ixgbe_mac_X550: 3942 case ixgbe_mac_X550EM_x: 3943 for (i = 0; i < adapter->num_rx_queues; i++) { 3944 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3945 3946 if (ring->l2_accel_priv) 3947 continue; 3948 j = ring->reg_idx; 3949 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3950 vlnctrl |= IXGBE_RXDCTL_VME; 3951 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3952 } 3953 break; 3954 default: 3955 break; 3956 } 3957 } 3958 3959 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3960 { 3961 u16 vid; 3962 3963 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3964 3965 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3966 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3967 } 3968 3969 /** 3970 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3971 * @netdev: network interface device structure 3972 * 3973 * Writes multicast address list to the MTA hash table. 3974 * Returns: -ENOMEM on failure 3975 * 0 on no addresses written 3976 * X on writing X addresses to MTA 3977 **/ 3978 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3979 { 3980 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3981 struct ixgbe_hw *hw = &adapter->hw; 3982 3983 if (!netif_running(netdev)) 3984 return 0; 3985 3986 if (hw->mac.ops.update_mc_addr_list) 3987 hw->mac.ops.update_mc_addr_list(hw, netdev); 3988 else 3989 return -ENOMEM; 3990 3991 #ifdef CONFIG_PCI_IOV 3992 ixgbe_restore_vf_multicasts(adapter); 3993 #endif 3994 3995 return netdev_mc_count(netdev); 3996 } 3997 3998 #ifdef CONFIG_PCI_IOV 3999 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4000 { 4001 struct ixgbe_hw *hw = &adapter->hw; 4002 int i; 4003 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4004 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 4005 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 4006 adapter->mac_table[i].queue, 4007 IXGBE_RAH_AV); 4008 else 4009 hw->mac.ops.clear_rar(hw, i); 4010 4011 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 4012 } 4013 } 4014 #endif 4015 4016 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4017 { 4018 struct ixgbe_hw *hw = &adapter->hw; 4019 int i; 4020 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4021 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 4022 if (adapter->mac_table[i].state & 4023 IXGBE_MAC_STATE_IN_USE) 4024 hw->mac.ops.set_rar(hw, i, 4025 adapter->mac_table[i].addr, 4026 adapter->mac_table[i].queue, 4027 IXGBE_RAH_AV); 4028 else 4029 hw->mac.ops.clear_rar(hw, i); 4030 4031 adapter->mac_table[i].state &= 4032 ~(IXGBE_MAC_STATE_MODIFIED); 4033 } 4034 } 4035 } 4036 4037 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4038 { 4039 int i; 4040 struct ixgbe_hw *hw = &adapter->hw; 4041 4042 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4043 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 4044 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 4045 eth_zero_addr(adapter->mac_table[i].addr); 4046 adapter->mac_table[i].queue = 0; 4047 } 4048 ixgbe_sync_mac_table(adapter); 4049 } 4050 4051 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 4052 { 4053 struct ixgbe_hw *hw = &adapter->hw; 4054 int i, count = 0; 4055 4056 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4057 if (adapter->mac_table[i].state == 0) 4058 count++; 4059 } 4060 return count; 4061 } 4062 4063 /* this function destroys the first RAR entry */ 4064 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 4065 u8 *addr) 4066 { 4067 struct ixgbe_hw *hw = &adapter->hw; 4068 4069 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 4070 adapter->mac_table[0].queue = VMDQ_P(0); 4071 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 4072 IXGBE_MAC_STATE_IN_USE); 4073 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 4074 adapter->mac_table[0].queue, 4075 IXGBE_RAH_AV); 4076 } 4077 4078 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 4079 { 4080 struct ixgbe_hw *hw = &adapter->hw; 4081 int i; 4082 4083 if (is_zero_ether_addr(addr)) 4084 return -EINVAL; 4085 4086 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4087 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 4088 continue; 4089 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 4090 IXGBE_MAC_STATE_IN_USE); 4091 ether_addr_copy(adapter->mac_table[i].addr, addr); 4092 adapter->mac_table[i].queue = queue; 4093 ixgbe_sync_mac_table(adapter); 4094 return i; 4095 } 4096 return -ENOMEM; 4097 } 4098 4099 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 4100 { 4101 /* search table for addr, if found, set to 0 and sync */ 4102 int i; 4103 struct ixgbe_hw *hw = &adapter->hw; 4104 4105 if (is_zero_ether_addr(addr)) 4106 return -EINVAL; 4107 4108 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4109 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 4110 adapter->mac_table[i].queue == queue) { 4111 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 4112 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 4113 eth_zero_addr(adapter->mac_table[i].addr); 4114 adapter->mac_table[i].queue = 0; 4115 ixgbe_sync_mac_table(adapter); 4116 return 0; 4117 } 4118 } 4119 return -ENOMEM; 4120 } 4121 /** 4122 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4123 * @netdev: network interface device structure 4124 * 4125 * Writes unicast address list to the RAR table. 4126 * Returns: -ENOMEM on failure/insufficient address space 4127 * 0 on no addresses written 4128 * X on writing X addresses to the RAR table 4129 **/ 4130 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4131 { 4132 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4133 int count = 0; 4134 4135 /* return ENOMEM indicating insufficient memory for addresses */ 4136 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 4137 return -ENOMEM; 4138 4139 if (!netdev_uc_empty(netdev)) { 4140 struct netdev_hw_addr *ha; 4141 netdev_for_each_uc_addr(ha, netdev) { 4142 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4143 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4144 count++; 4145 } 4146 } 4147 return count; 4148 } 4149 4150 /** 4151 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4152 * @netdev: network interface device structure 4153 * 4154 * The set_rx_method entry point is called whenever the unicast/multicast 4155 * address list or the network interface flags are updated. This routine is 4156 * responsible for configuring the hardware for proper unicast, multicast and 4157 * promiscuous mode. 4158 **/ 4159 void ixgbe_set_rx_mode(struct net_device *netdev) 4160 { 4161 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4162 struct ixgbe_hw *hw = &adapter->hw; 4163 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4164 u32 vlnctrl; 4165 int count; 4166 4167 /* Check for Promiscuous and All Multicast modes */ 4168 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4169 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4170 4171 /* set all bits that we expect to always be set */ 4172 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4173 fctrl |= IXGBE_FCTRL_BAM; 4174 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4175 fctrl |= IXGBE_FCTRL_PMCF; 4176 4177 /* clear the bits we are changing the status of */ 4178 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4179 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4180 if (netdev->flags & IFF_PROMISC) { 4181 hw->addr_ctrl.user_set_promisc = true; 4182 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4183 vmolr |= IXGBE_VMOLR_MPE; 4184 /* Only disable hardware filter vlans in promiscuous mode 4185 * if SR-IOV and VMDQ are disabled - otherwise ensure 4186 * that hardware VLAN filters remain enabled. 4187 */ 4188 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4189 IXGBE_FLAG_SRIOV_ENABLED)) 4190 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4191 } else { 4192 if (netdev->flags & IFF_ALLMULTI) { 4193 fctrl |= IXGBE_FCTRL_MPE; 4194 vmolr |= IXGBE_VMOLR_MPE; 4195 } 4196 vlnctrl |= IXGBE_VLNCTRL_VFE; 4197 hw->addr_ctrl.user_set_promisc = false; 4198 } 4199 4200 /* 4201 * Write addresses to available RAR registers, if there is not 4202 * sufficient space to store all the addresses then enable 4203 * unicast promiscuous mode 4204 */ 4205 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4206 if (count < 0) { 4207 fctrl |= IXGBE_FCTRL_UPE; 4208 vmolr |= IXGBE_VMOLR_ROPE; 4209 } 4210 4211 /* Write addresses to the MTA, if the attempt fails 4212 * then we should just turn on promiscuous mode so 4213 * that we can at least receive multicast traffic 4214 */ 4215 count = ixgbe_write_mc_addr_list(netdev); 4216 if (count < 0) { 4217 fctrl |= IXGBE_FCTRL_MPE; 4218 vmolr |= IXGBE_VMOLR_MPE; 4219 } else if (count) { 4220 vmolr |= IXGBE_VMOLR_ROMPE; 4221 } 4222 4223 if (hw->mac.type != ixgbe_mac_82598EB) { 4224 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4225 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4226 IXGBE_VMOLR_ROPE); 4227 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4228 } 4229 4230 /* This is useful for sniffing bad packets. */ 4231 if (adapter->netdev->features & NETIF_F_RXALL) { 4232 /* UPE and MPE will be handled by normal PROMISC logic 4233 * in e1000e_set_rx_mode */ 4234 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4235 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4236 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4237 4238 fctrl &= ~(IXGBE_FCTRL_DPF); 4239 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4240 } 4241 4242 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4243 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4244 4245 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4246 ixgbe_vlan_strip_enable(adapter); 4247 else 4248 ixgbe_vlan_strip_disable(adapter); 4249 } 4250 4251 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4252 { 4253 int q_idx; 4254 4255 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4256 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4257 napi_enable(&adapter->q_vector[q_idx]->napi); 4258 } 4259 } 4260 4261 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4262 { 4263 int q_idx; 4264 4265 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4266 napi_disable(&adapter->q_vector[q_idx]->napi); 4267 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4268 pr_info("QV %d locked\n", q_idx); 4269 usleep_range(1000, 20000); 4270 } 4271 } 4272 } 4273 4274 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter) 4275 { 4276 switch (adapter->hw.mac.type) { 4277 case ixgbe_mac_X550: 4278 case ixgbe_mac_X550EM_x: 4279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0); 4280 #ifdef CONFIG_IXGBE_VXLAN 4281 adapter->vxlan_port = 0; 4282 #endif 4283 break; 4284 default: 4285 break; 4286 } 4287 } 4288 4289 #ifdef CONFIG_IXGBE_DCB 4290 /** 4291 * ixgbe_configure_dcb - Configure DCB hardware 4292 * @adapter: ixgbe adapter struct 4293 * 4294 * This is called by the driver on open to configure the DCB hardware. 4295 * This is also called by the gennetlink interface when reconfiguring 4296 * the DCB state. 4297 */ 4298 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4299 { 4300 struct ixgbe_hw *hw = &adapter->hw; 4301 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4302 4303 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4304 if (hw->mac.type == ixgbe_mac_82598EB) 4305 netif_set_gso_max_size(adapter->netdev, 65536); 4306 return; 4307 } 4308 4309 if (hw->mac.type == ixgbe_mac_82598EB) 4310 netif_set_gso_max_size(adapter->netdev, 32768); 4311 4312 #ifdef IXGBE_FCOE 4313 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4314 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4315 #endif 4316 4317 /* reconfigure the hardware */ 4318 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4319 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4320 DCB_TX_CONFIG); 4321 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4322 DCB_RX_CONFIG); 4323 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4324 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4325 ixgbe_dcb_hw_ets(&adapter->hw, 4326 adapter->ixgbe_ieee_ets, 4327 max_frame); 4328 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4329 adapter->ixgbe_ieee_pfc->pfc_en, 4330 adapter->ixgbe_ieee_ets->prio_tc); 4331 } 4332 4333 /* Enable RSS Hash per TC */ 4334 if (hw->mac.type != ixgbe_mac_82598EB) { 4335 u32 msb = 0; 4336 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4337 4338 while (rss_i) { 4339 msb++; 4340 rss_i >>= 1; 4341 } 4342 4343 /* write msb to all 8 TCs in one write */ 4344 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4345 } 4346 } 4347 #endif 4348 4349 /* Additional bittime to account for IXGBE framing */ 4350 #define IXGBE_ETH_FRAMING 20 4351 4352 /** 4353 * ixgbe_hpbthresh - calculate high water mark for flow control 4354 * 4355 * @adapter: board private structure to calculate for 4356 * @pb: packet buffer to calculate 4357 */ 4358 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4359 { 4360 struct ixgbe_hw *hw = &adapter->hw; 4361 struct net_device *dev = adapter->netdev; 4362 int link, tc, kb, marker; 4363 u32 dv_id, rx_pba; 4364 4365 /* Calculate max LAN frame size */ 4366 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4367 4368 #ifdef IXGBE_FCOE 4369 /* FCoE traffic class uses FCOE jumbo frames */ 4370 if ((dev->features & NETIF_F_FCOE_MTU) && 4371 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4372 (pb == ixgbe_fcoe_get_tc(adapter))) 4373 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4374 #endif 4375 4376 /* Calculate delay value for device */ 4377 switch (hw->mac.type) { 4378 case ixgbe_mac_X540: 4379 case ixgbe_mac_X550: 4380 case ixgbe_mac_X550EM_x: 4381 dv_id = IXGBE_DV_X540(link, tc); 4382 break; 4383 default: 4384 dv_id = IXGBE_DV(link, tc); 4385 break; 4386 } 4387 4388 /* Loopback switch introduces additional latency */ 4389 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4390 dv_id += IXGBE_B2BT(tc); 4391 4392 /* Delay value is calculated in bit times convert to KB */ 4393 kb = IXGBE_BT2KB(dv_id); 4394 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4395 4396 marker = rx_pba - kb; 4397 4398 /* It is possible that the packet buffer is not large enough 4399 * to provide required headroom. In this case throw an error 4400 * to user and a do the best we can. 4401 */ 4402 if (marker < 0) { 4403 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4404 "headroom to support flow control." 4405 "Decrease MTU or number of traffic classes\n", pb); 4406 marker = tc + 1; 4407 } 4408 4409 return marker; 4410 } 4411 4412 /** 4413 * ixgbe_lpbthresh - calculate low water mark for for flow control 4414 * 4415 * @adapter: board private structure to calculate for 4416 * @pb: packet buffer to calculate 4417 */ 4418 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4419 { 4420 struct ixgbe_hw *hw = &adapter->hw; 4421 struct net_device *dev = adapter->netdev; 4422 int tc; 4423 u32 dv_id; 4424 4425 /* Calculate max LAN frame size */ 4426 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4427 4428 #ifdef IXGBE_FCOE 4429 /* FCoE traffic class uses FCOE jumbo frames */ 4430 if ((dev->features & NETIF_F_FCOE_MTU) && 4431 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4432 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4433 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4434 #endif 4435 4436 /* Calculate delay value for device */ 4437 switch (hw->mac.type) { 4438 case ixgbe_mac_X540: 4439 case ixgbe_mac_X550: 4440 case ixgbe_mac_X550EM_x: 4441 dv_id = IXGBE_LOW_DV_X540(tc); 4442 break; 4443 default: 4444 dv_id = IXGBE_LOW_DV(tc); 4445 break; 4446 } 4447 4448 /* Delay value is calculated in bit times convert to KB */ 4449 return IXGBE_BT2KB(dv_id); 4450 } 4451 4452 /* 4453 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4454 */ 4455 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4456 { 4457 struct ixgbe_hw *hw = &adapter->hw; 4458 int num_tc = netdev_get_num_tc(adapter->netdev); 4459 int i; 4460 4461 if (!num_tc) 4462 num_tc = 1; 4463 4464 for (i = 0; i < num_tc; i++) { 4465 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4466 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4467 4468 /* Low water marks must not be larger than high water marks */ 4469 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4470 hw->fc.low_water[i] = 0; 4471 } 4472 4473 for (; i < MAX_TRAFFIC_CLASS; i++) 4474 hw->fc.high_water[i] = 0; 4475 } 4476 4477 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4478 { 4479 struct ixgbe_hw *hw = &adapter->hw; 4480 int hdrm; 4481 u8 tc = netdev_get_num_tc(adapter->netdev); 4482 4483 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4484 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4485 hdrm = 32 << adapter->fdir_pballoc; 4486 else 4487 hdrm = 0; 4488 4489 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4490 ixgbe_pbthresh_setup(adapter); 4491 } 4492 4493 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4494 { 4495 struct ixgbe_hw *hw = &adapter->hw; 4496 struct hlist_node *node2; 4497 struct ixgbe_fdir_filter *filter; 4498 4499 spin_lock(&adapter->fdir_perfect_lock); 4500 4501 if (!hlist_empty(&adapter->fdir_filter_list)) 4502 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4503 4504 hlist_for_each_entry_safe(filter, node2, 4505 &adapter->fdir_filter_list, fdir_node) { 4506 ixgbe_fdir_write_perfect_filter_82599(hw, 4507 &filter->filter, 4508 filter->sw_idx, 4509 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4510 IXGBE_FDIR_DROP_QUEUE : 4511 adapter->rx_ring[filter->action]->reg_idx); 4512 } 4513 4514 spin_unlock(&adapter->fdir_perfect_lock); 4515 } 4516 4517 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4518 struct ixgbe_adapter *adapter) 4519 { 4520 struct ixgbe_hw *hw = &adapter->hw; 4521 u32 vmolr; 4522 4523 /* No unicast promiscuous support for VMDQ devices. */ 4524 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4525 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4526 4527 /* clear the affected bit */ 4528 vmolr &= ~IXGBE_VMOLR_MPE; 4529 4530 if (dev->flags & IFF_ALLMULTI) { 4531 vmolr |= IXGBE_VMOLR_MPE; 4532 } else { 4533 vmolr |= IXGBE_VMOLR_ROMPE; 4534 hw->mac.ops.update_mc_addr_list(hw, dev); 4535 } 4536 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4537 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4538 } 4539 4540 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4541 { 4542 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4543 int rss_i = adapter->num_rx_queues_per_pool; 4544 struct ixgbe_hw *hw = &adapter->hw; 4545 u16 pool = vadapter->pool; 4546 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4547 IXGBE_PSRTYPE_UDPHDR | 4548 IXGBE_PSRTYPE_IPV4HDR | 4549 IXGBE_PSRTYPE_L2HDR | 4550 IXGBE_PSRTYPE_IPV6HDR; 4551 4552 if (hw->mac.type == ixgbe_mac_82598EB) 4553 return; 4554 4555 if (rss_i > 3) 4556 psrtype |= 2 << 29; 4557 else if (rss_i > 1) 4558 psrtype |= 1 << 29; 4559 4560 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4561 } 4562 4563 /** 4564 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4565 * @rx_ring: ring to free buffers from 4566 **/ 4567 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4568 { 4569 struct device *dev = rx_ring->dev; 4570 unsigned long size; 4571 u16 i; 4572 4573 /* ring already cleared, nothing to do */ 4574 if (!rx_ring->rx_buffer_info) 4575 return; 4576 4577 /* Free all the Rx ring sk_buffs */ 4578 for (i = 0; i < rx_ring->count; i++) { 4579 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4580 4581 if (rx_buffer->skb) { 4582 struct sk_buff *skb = rx_buffer->skb; 4583 if (IXGBE_CB(skb)->page_released) 4584 dma_unmap_page(dev, 4585 IXGBE_CB(skb)->dma, 4586 ixgbe_rx_bufsz(rx_ring), 4587 DMA_FROM_DEVICE); 4588 dev_kfree_skb(skb); 4589 rx_buffer->skb = NULL; 4590 } 4591 4592 if (!rx_buffer->page) 4593 continue; 4594 4595 dma_unmap_page(dev, rx_buffer->dma, 4596 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4597 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4598 4599 rx_buffer->page = NULL; 4600 } 4601 4602 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4603 memset(rx_ring->rx_buffer_info, 0, size); 4604 4605 /* Zero out the descriptor ring */ 4606 memset(rx_ring->desc, 0, rx_ring->size); 4607 4608 rx_ring->next_to_alloc = 0; 4609 rx_ring->next_to_clean = 0; 4610 rx_ring->next_to_use = 0; 4611 } 4612 4613 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4614 struct ixgbe_ring *rx_ring) 4615 { 4616 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4617 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4618 4619 /* shutdown specific queue receive and wait for dma to settle */ 4620 ixgbe_disable_rx_queue(adapter, rx_ring); 4621 usleep_range(10000, 20000); 4622 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4623 ixgbe_clean_rx_ring(rx_ring); 4624 rx_ring->l2_accel_priv = NULL; 4625 } 4626 4627 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4628 struct ixgbe_fwd_adapter *accel) 4629 { 4630 struct ixgbe_adapter *adapter = accel->real_adapter; 4631 unsigned int rxbase = accel->rx_base_queue; 4632 unsigned int txbase = accel->tx_base_queue; 4633 int i; 4634 4635 netif_tx_stop_all_queues(vdev); 4636 4637 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4638 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4639 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4640 } 4641 4642 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4643 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4644 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4645 } 4646 4647 4648 return 0; 4649 } 4650 4651 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4652 struct ixgbe_fwd_adapter *accel) 4653 { 4654 struct ixgbe_adapter *adapter = accel->real_adapter; 4655 unsigned int rxbase, txbase, queues; 4656 int i, baseq, err = 0; 4657 4658 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4659 return 0; 4660 4661 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4662 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4663 accel->pool, adapter->num_rx_pools, 4664 baseq, baseq + adapter->num_rx_queues_per_pool, 4665 adapter->fwd_bitmask); 4666 4667 accel->netdev = vdev; 4668 accel->rx_base_queue = rxbase = baseq; 4669 accel->tx_base_queue = txbase = baseq; 4670 4671 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4672 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4673 4674 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4675 adapter->rx_ring[rxbase + i]->netdev = vdev; 4676 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4677 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4678 } 4679 4680 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4681 adapter->tx_ring[txbase + i]->netdev = vdev; 4682 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4683 } 4684 4685 queues = min_t(unsigned int, 4686 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4687 err = netif_set_real_num_tx_queues(vdev, queues); 4688 if (err) 4689 goto fwd_queue_err; 4690 4691 err = netif_set_real_num_rx_queues(vdev, queues); 4692 if (err) 4693 goto fwd_queue_err; 4694 4695 if (is_valid_ether_addr(vdev->dev_addr)) 4696 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4697 4698 ixgbe_fwd_psrtype(accel); 4699 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4700 return err; 4701 fwd_queue_err: 4702 ixgbe_fwd_ring_down(vdev, accel); 4703 return err; 4704 } 4705 4706 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4707 { 4708 struct net_device *upper; 4709 struct list_head *iter; 4710 int err; 4711 4712 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4713 if (netif_is_macvlan(upper)) { 4714 struct macvlan_dev *dfwd = netdev_priv(upper); 4715 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4716 4717 if (dfwd->fwd_priv) { 4718 err = ixgbe_fwd_ring_up(upper, vadapter); 4719 if (err) 4720 continue; 4721 } 4722 } 4723 } 4724 } 4725 4726 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4727 { 4728 struct ixgbe_hw *hw = &adapter->hw; 4729 4730 ixgbe_configure_pb(adapter); 4731 #ifdef CONFIG_IXGBE_DCB 4732 ixgbe_configure_dcb(adapter); 4733 #endif 4734 /* 4735 * We must restore virtualization before VLANs or else 4736 * the VLVF registers will not be populated 4737 */ 4738 ixgbe_configure_virtualization(adapter); 4739 4740 ixgbe_set_rx_mode(adapter->netdev); 4741 ixgbe_restore_vlan(adapter); 4742 4743 switch (hw->mac.type) { 4744 case ixgbe_mac_82599EB: 4745 case ixgbe_mac_X540: 4746 hw->mac.ops.disable_rx_buff(hw); 4747 break; 4748 default: 4749 break; 4750 } 4751 4752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4753 ixgbe_init_fdir_signature_82599(&adapter->hw, 4754 adapter->fdir_pballoc); 4755 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4756 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4757 adapter->fdir_pballoc); 4758 ixgbe_fdir_filter_restore(adapter); 4759 } 4760 4761 switch (hw->mac.type) { 4762 case ixgbe_mac_82599EB: 4763 case ixgbe_mac_X540: 4764 hw->mac.ops.enable_rx_buff(hw); 4765 break; 4766 default: 4767 break; 4768 } 4769 4770 #ifdef IXGBE_FCOE 4771 /* configure FCoE L2 filters, redirection table, and Rx control */ 4772 ixgbe_configure_fcoe(adapter); 4773 4774 #endif /* IXGBE_FCOE */ 4775 ixgbe_configure_tx(adapter); 4776 ixgbe_configure_rx(adapter); 4777 ixgbe_configure_dfwd(adapter); 4778 } 4779 4780 /** 4781 * ixgbe_sfp_link_config - set up SFP+ link 4782 * @adapter: pointer to private adapter struct 4783 **/ 4784 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4785 { 4786 /* 4787 * We are assuming the worst case scenario here, and that 4788 * is that an SFP was inserted/removed after the reset 4789 * but before SFP detection was enabled. As such the best 4790 * solution is to just start searching as soon as we start 4791 */ 4792 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4793 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4794 4795 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4796 } 4797 4798 /** 4799 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4800 * @hw: pointer to private hardware struct 4801 * 4802 * Returns 0 on success, negative on failure 4803 **/ 4804 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4805 { 4806 u32 speed; 4807 bool autoneg, link_up = false; 4808 int ret = IXGBE_ERR_LINK_SETUP; 4809 4810 if (hw->mac.ops.check_link) 4811 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4812 4813 if (ret) 4814 return ret; 4815 4816 speed = hw->phy.autoneg_advertised; 4817 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4818 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4819 &autoneg); 4820 if (ret) 4821 return ret; 4822 4823 if (hw->mac.ops.setup_link) 4824 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4825 4826 return ret; 4827 } 4828 4829 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4830 { 4831 struct ixgbe_hw *hw = &adapter->hw; 4832 u32 gpie = 0; 4833 4834 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4835 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4836 IXGBE_GPIE_OCD; 4837 gpie |= IXGBE_GPIE_EIAME; 4838 /* 4839 * use EIAM to auto-mask when MSI-X interrupt is asserted 4840 * this saves a register write for every interrupt 4841 */ 4842 switch (hw->mac.type) { 4843 case ixgbe_mac_82598EB: 4844 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4845 break; 4846 case ixgbe_mac_82599EB: 4847 case ixgbe_mac_X540: 4848 case ixgbe_mac_X550: 4849 case ixgbe_mac_X550EM_x: 4850 default: 4851 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4852 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4853 break; 4854 } 4855 } else { 4856 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4857 * specifically only auto mask tx and rx interrupts */ 4858 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4859 } 4860 4861 /* XXX: to interrupt immediately for EICS writes, enable this */ 4862 /* gpie |= IXGBE_GPIE_EIMEN; */ 4863 4864 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4865 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4866 4867 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4868 case IXGBE_82599_VMDQ_8Q_MASK: 4869 gpie |= IXGBE_GPIE_VTMODE_16; 4870 break; 4871 case IXGBE_82599_VMDQ_4Q_MASK: 4872 gpie |= IXGBE_GPIE_VTMODE_32; 4873 break; 4874 default: 4875 gpie |= IXGBE_GPIE_VTMODE_64; 4876 break; 4877 } 4878 } 4879 4880 /* Enable Thermal over heat sensor interrupt */ 4881 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4882 switch (adapter->hw.mac.type) { 4883 case ixgbe_mac_82599EB: 4884 gpie |= IXGBE_SDP0_GPIEN_8259X; 4885 break; 4886 case ixgbe_mac_X540: 4887 gpie |= IXGBE_EIMS_TS; 4888 break; 4889 default: 4890 break; 4891 } 4892 } 4893 4894 /* Enable fan failure interrupt */ 4895 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4896 gpie |= IXGBE_SDP1_GPIEN(hw); 4897 4898 if (hw->mac.type == ixgbe_mac_82599EB) { 4899 gpie |= IXGBE_SDP1_GPIEN_8259X; 4900 gpie |= IXGBE_SDP2_GPIEN_8259X; 4901 } 4902 4903 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4904 } 4905 4906 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4907 { 4908 struct ixgbe_hw *hw = &adapter->hw; 4909 int err; 4910 u32 ctrl_ext; 4911 4912 ixgbe_get_hw_control(adapter); 4913 ixgbe_setup_gpie(adapter); 4914 4915 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4916 ixgbe_configure_msix(adapter); 4917 else 4918 ixgbe_configure_msi_and_legacy(adapter); 4919 4920 /* enable the optics for 82599 SFP+ fiber */ 4921 if (hw->mac.ops.enable_tx_laser) 4922 hw->mac.ops.enable_tx_laser(hw); 4923 4924 if (hw->phy.ops.set_phy_power) 4925 hw->phy.ops.set_phy_power(hw, true); 4926 4927 smp_mb__before_atomic(); 4928 clear_bit(__IXGBE_DOWN, &adapter->state); 4929 ixgbe_napi_enable_all(adapter); 4930 4931 if (ixgbe_is_sfp(hw)) { 4932 ixgbe_sfp_link_config(adapter); 4933 } else { 4934 err = ixgbe_non_sfp_link_config(hw); 4935 if (err) 4936 e_err(probe, "link_config FAILED %d\n", err); 4937 } 4938 4939 /* clear any pending interrupts, may auto mask */ 4940 IXGBE_READ_REG(hw, IXGBE_EICR); 4941 ixgbe_irq_enable(adapter, true, true); 4942 4943 /* 4944 * If this adapter has a fan, check to see if we had a failure 4945 * before we enabled the interrupt. 4946 */ 4947 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4948 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4949 if (esdp & IXGBE_ESDP_SDP1) 4950 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4951 } 4952 4953 /* bring the link up in the watchdog, this could race with our first 4954 * link up interrupt but shouldn't be a problem */ 4955 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4956 adapter->link_check_timeout = jiffies; 4957 mod_timer(&adapter->service_timer, jiffies); 4958 4959 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4960 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4961 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4962 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4963 } 4964 4965 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4966 { 4967 WARN_ON(in_interrupt()); 4968 /* put off any impending NetWatchDogTimeout */ 4969 adapter->netdev->trans_start = jiffies; 4970 4971 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4972 usleep_range(1000, 2000); 4973 ixgbe_down(adapter); 4974 /* 4975 * If SR-IOV enabled then wait a bit before bringing the adapter 4976 * back up to give the VFs time to respond to the reset. The 4977 * two second wait is based upon the watchdog timer cycle in 4978 * the VF driver. 4979 */ 4980 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4981 msleep(2000); 4982 ixgbe_up(adapter); 4983 clear_bit(__IXGBE_RESETTING, &adapter->state); 4984 } 4985 4986 void ixgbe_up(struct ixgbe_adapter *adapter) 4987 { 4988 /* hardware has been reset, we need to reload some things */ 4989 ixgbe_configure(adapter); 4990 4991 ixgbe_up_complete(adapter); 4992 } 4993 4994 void ixgbe_reset(struct ixgbe_adapter *adapter) 4995 { 4996 struct ixgbe_hw *hw = &adapter->hw; 4997 struct net_device *netdev = adapter->netdev; 4998 int err; 4999 u8 old_addr[ETH_ALEN]; 5000 5001 if (ixgbe_removed(hw->hw_addr)) 5002 return; 5003 /* lock SFP init bit to prevent race conditions with the watchdog */ 5004 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5005 usleep_range(1000, 2000); 5006 5007 /* clear all SFP and link config related flags while holding SFP_INIT */ 5008 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5009 IXGBE_FLAG2_SFP_NEEDS_RESET); 5010 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5011 5012 err = hw->mac.ops.init_hw(hw); 5013 switch (err) { 5014 case 0: 5015 case IXGBE_ERR_SFP_NOT_PRESENT: 5016 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5017 break; 5018 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5019 e_dev_err("master disable timed out\n"); 5020 break; 5021 case IXGBE_ERR_EEPROM_VERSION: 5022 /* We are running on a pre-production device, log a warning */ 5023 e_dev_warn("This device is a pre-production adapter/LOM. " 5024 "Please be aware there may be issues associated with " 5025 "your hardware. If you are experiencing problems " 5026 "please contact your Intel or hardware " 5027 "representative who provided you with this " 5028 "hardware.\n"); 5029 break; 5030 default: 5031 e_dev_err("Hardware Error: %d\n", err); 5032 } 5033 5034 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5035 /* do not flush user set addresses */ 5036 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 5037 ixgbe_flush_sw_mac_table(adapter); 5038 ixgbe_mac_set_default_filter(adapter, old_addr); 5039 5040 /* update SAN MAC vmdq pool selection */ 5041 if (hw->mac.san_mac_rar_index) 5042 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5043 5044 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5045 ixgbe_ptp_reset(adapter); 5046 5047 if (hw->phy.ops.set_phy_power) { 5048 if (!netif_running(adapter->netdev) && !adapter->wol) 5049 hw->phy.ops.set_phy_power(hw, false); 5050 else 5051 hw->phy.ops.set_phy_power(hw, true); 5052 } 5053 } 5054 5055 /** 5056 * ixgbe_clean_tx_ring - Free Tx Buffers 5057 * @tx_ring: ring to be cleaned 5058 **/ 5059 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5060 { 5061 struct ixgbe_tx_buffer *tx_buffer_info; 5062 unsigned long size; 5063 u16 i; 5064 5065 /* ring already cleared, nothing to do */ 5066 if (!tx_ring->tx_buffer_info) 5067 return; 5068 5069 /* Free all the Tx ring sk_buffs */ 5070 for (i = 0; i < tx_ring->count; i++) { 5071 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 5072 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 5073 } 5074 5075 netdev_tx_reset_queue(txring_txq(tx_ring)); 5076 5077 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5078 memset(tx_ring->tx_buffer_info, 0, size); 5079 5080 /* Zero out the descriptor ring */ 5081 memset(tx_ring->desc, 0, tx_ring->size); 5082 5083 tx_ring->next_to_use = 0; 5084 tx_ring->next_to_clean = 0; 5085 } 5086 5087 /** 5088 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5089 * @adapter: board private structure 5090 **/ 5091 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5092 { 5093 int i; 5094 5095 for (i = 0; i < adapter->num_rx_queues; i++) 5096 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5097 } 5098 5099 /** 5100 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5101 * @adapter: board private structure 5102 **/ 5103 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5104 { 5105 int i; 5106 5107 for (i = 0; i < adapter->num_tx_queues; i++) 5108 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5109 } 5110 5111 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5112 { 5113 struct hlist_node *node2; 5114 struct ixgbe_fdir_filter *filter; 5115 5116 spin_lock(&adapter->fdir_perfect_lock); 5117 5118 hlist_for_each_entry_safe(filter, node2, 5119 &adapter->fdir_filter_list, fdir_node) { 5120 hlist_del(&filter->fdir_node); 5121 kfree(filter); 5122 } 5123 adapter->fdir_filter_count = 0; 5124 5125 spin_unlock(&adapter->fdir_perfect_lock); 5126 } 5127 5128 void ixgbe_down(struct ixgbe_adapter *adapter) 5129 { 5130 struct net_device *netdev = adapter->netdev; 5131 struct ixgbe_hw *hw = &adapter->hw; 5132 struct net_device *upper; 5133 struct list_head *iter; 5134 int i; 5135 5136 /* signal that we are down to the interrupt handler */ 5137 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5138 return; /* do nothing if already down */ 5139 5140 /* disable receives */ 5141 hw->mac.ops.disable_rx(hw); 5142 5143 /* disable all enabled rx queues */ 5144 for (i = 0; i < adapter->num_rx_queues; i++) 5145 /* this call also flushes the previous write */ 5146 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5147 5148 usleep_range(10000, 20000); 5149 5150 netif_tx_stop_all_queues(netdev); 5151 5152 /* call carrier off first to avoid false dev_watchdog timeouts */ 5153 netif_carrier_off(netdev); 5154 netif_tx_disable(netdev); 5155 5156 /* disable any upper devices */ 5157 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5158 if (netif_is_macvlan(upper)) { 5159 struct macvlan_dev *vlan = netdev_priv(upper); 5160 5161 if (vlan->fwd_priv) { 5162 netif_tx_stop_all_queues(upper); 5163 netif_carrier_off(upper); 5164 netif_tx_disable(upper); 5165 } 5166 } 5167 } 5168 5169 ixgbe_irq_disable(adapter); 5170 5171 ixgbe_napi_disable_all(adapter); 5172 5173 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5174 IXGBE_FLAG2_RESET_REQUESTED); 5175 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5176 5177 del_timer_sync(&adapter->service_timer); 5178 5179 if (adapter->num_vfs) { 5180 /* Clear EITR Select mapping */ 5181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5182 5183 /* Mark all the VFs as inactive */ 5184 for (i = 0 ; i < adapter->num_vfs; i++) 5185 adapter->vfinfo[i].clear_to_send = false; 5186 5187 /* ping all the active vfs to let them know we are going down */ 5188 ixgbe_ping_all_vfs(adapter); 5189 5190 /* Disable all VFTE/VFRE TX/RX */ 5191 ixgbe_disable_tx_rx(adapter); 5192 } 5193 5194 /* disable transmits in the hardware now that interrupts are off */ 5195 for (i = 0; i < adapter->num_tx_queues; i++) { 5196 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5197 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5198 } 5199 5200 /* Disable the Tx DMA engine on 82599 and later MAC */ 5201 switch (hw->mac.type) { 5202 case ixgbe_mac_82599EB: 5203 case ixgbe_mac_X540: 5204 case ixgbe_mac_X550: 5205 case ixgbe_mac_X550EM_x: 5206 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5207 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5208 ~IXGBE_DMATXCTL_TE)); 5209 break; 5210 default: 5211 break; 5212 } 5213 5214 if (!pci_channel_offline(adapter->pdev)) 5215 ixgbe_reset(adapter); 5216 5217 /* power down the optics for 82599 SFP+ fiber */ 5218 if (hw->mac.ops.disable_tx_laser) 5219 hw->mac.ops.disable_tx_laser(hw); 5220 5221 ixgbe_clean_all_tx_rings(adapter); 5222 ixgbe_clean_all_rx_rings(adapter); 5223 5224 #ifdef CONFIG_IXGBE_DCA 5225 /* since we reset the hardware DCA settings were cleared */ 5226 ixgbe_setup_dca(adapter); 5227 #endif 5228 } 5229 5230 /** 5231 * ixgbe_tx_timeout - Respond to a Tx Hang 5232 * @netdev: network interface device structure 5233 **/ 5234 static void ixgbe_tx_timeout(struct net_device *netdev) 5235 { 5236 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5237 5238 /* Do the reset outside of interrupt context */ 5239 ixgbe_tx_timeout_reset(adapter); 5240 } 5241 5242 /** 5243 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5244 * @adapter: board private structure to initialize 5245 * 5246 * ixgbe_sw_init initializes the Adapter private data structure. 5247 * Fields are initialized based on PCI device information and 5248 * OS network device settings (MTU size). 5249 **/ 5250 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5251 { 5252 struct ixgbe_hw *hw = &adapter->hw; 5253 struct pci_dev *pdev = adapter->pdev; 5254 unsigned int rss, fdir; 5255 u32 fwsm; 5256 #ifdef CONFIG_IXGBE_DCB 5257 int j; 5258 struct tc_configuration *tc; 5259 #endif 5260 5261 /* PCI config space info */ 5262 5263 hw->vendor_id = pdev->vendor; 5264 hw->device_id = pdev->device; 5265 hw->revision_id = pdev->revision; 5266 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5267 hw->subsystem_device_id = pdev->subsystem_device; 5268 5269 /* Set common capability flags and settings */ 5270 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5271 adapter->ring_feature[RING_F_RSS].limit = rss; 5272 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5273 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5274 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5275 adapter->atr_sample_rate = 20; 5276 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5277 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5278 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5279 #ifdef CONFIG_IXGBE_DCA 5280 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5281 #endif 5282 #ifdef IXGBE_FCOE 5283 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5284 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5285 #ifdef CONFIG_IXGBE_DCB 5286 /* Default traffic class to use for FCoE */ 5287 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5288 #endif /* CONFIG_IXGBE_DCB */ 5289 #endif /* IXGBE_FCOE */ 5290 5291 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5292 hw->mac.num_rar_entries, 5293 GFP_ATOMIC); 5294 5295 /* Set MAC specific capability flags and exceptions */ 5296 switch (hw->mac.type) { 5297 case ixgbe_mac_82598EB: 5298 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5299 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5300 5301 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5302 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5303 5304 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5305 adapter->ring_feature[RING_F_FDIR].limit = 0; 5306 adapter->atr_sample_rate = 0; 5307 adapter->fdir_pballoc = 0; 5308 #ifdef IXGBE_FCOE 5309 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5310 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5311 #ifdef CONFIG_IXGBE_DCB 5312 adapter->fcoe.up = 0; 5313 #endif /* IXGBE_DCB */ 5314 #endif /* IXGBE_FCOE */ 5315 break; 5316 case ixgbe_mac_82599EB: 5317 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5318 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5319 break; 5320 case ixgbe_mac_X540: 5321 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 5322 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5323 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5324 break; 5325 case ixgbe_mac_X550EM_x: 5326 case ixgbe_mac_X550: 5327 #ifdef CONFIG_IXGBE_DCA 5328 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5329 #endif 5330 #ifdef CONFIG_IXGBE_VXLAN 5331 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 5332 #endif 5333 break; 5334 default: 5335 break; 5336 } 5337 5338 #ifdef IXGBE_FCOE 5339 /* FCoE support exists, always init the FCoE lock */ 5340 spin_lock_init(&adapter->fcoe.lock); 5341 5342 #endif 5343 /* n-tuple support exists, always init our spinlock */ 5344 spin_lock_init(&adapter->fdir_perfect_lock); 5345 5346 #ifdef CONFIG_IXGBE_DCB 5347 switch (hw->mac.type) { 5348 case ixgbe_mac_X540: 5349 case ixgbe_mac_X550: 5350 case ixgbe_mac_X550EM_x: 5351 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5352 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5353 break; 5354 default: 5355 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5356 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5357 break; 5358 } 5359 5360 /* Configure DCB traffic classes */ 5361 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5362 tc = &adapter->dcb_cfg.tc_config[j]; 5363 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5364 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5365 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5366 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5367 tc->dcb_pfc = pfc_disabled; 5368 } 5369 5370 /* Initialize default user to priority mapping, UPx->TC0 */ 5371 tc = &adapter->dcb_cfg.tc_config[0]; 5372 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5373 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5374 5375 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5376 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5377 adapter->dcb_cfg.pfc_mode_enable = false; 5378 adapter->dcb_set_bitmap = 0x00; 5379 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5380 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5381 sizeof(adapter->temp_dcb_cfg)); 5382 5383 #endif 5384 5385 /* default flow control settings */ 5386 hw->fc.requested_mode = ixgbe_fc_full; 5387 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5388 ixgbe_pbthresh_setup(adapter); 5389 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5390 hw->fc.send_xon = true; 5391 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5392 5393 #ifdef CONFIG_PCI_IOV 5394 if (max_vfs > 0) 5395 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5396 5397 /* assign number of SR-IOV VFs */ 5398 if (hw->mac.type != ixgbe_mac_82598EB) { 5399 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5400 adapter->num_vfs = 0; 5401 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5402 } else { 5403 adapter->num_vfs = max_vfs; 5404 } 5405 } 5406 #endif /* CONFIG_PCI_IOV */ 5407 5408 /* enable itr by default in dynamic mode */ 5409 adapter->rx_itr_setting = 1; 5410 adapter->tx_itr_setting = 1; 5411 5412 /* set default ring sizes */ 5413 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5414 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5415 5416 /* set default work limits */ 5417 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5418 5419 /* initialize eeprom parameters */ 5420 if (ixgbe_init_eeprom_params_generic(hw)) { 5421 e_dev_err("EEPROM initialization failed\n"); 5422 return -EIO; 5423 } 5424 5425 /* PF holds first pool slot */ 5426 set_bit(0, &adapter->fwd_bitmask); 5427 set_bit(__IXGBE_DOWN, &adapter->state); 5428 5429 return 0; 5430 } 5431 5432 /** 5433 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5434 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5435 * 5436 * Return 0 on success, negative on failure 5437 **/ 5438 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5439 { 5440 struct device *dev = tx_ring->dev; 5441 int orig_node = dev_to_node(dev); 5442 int ring_node = -1; 5443 int size; 5444 5445 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5446 5447 if (tx_ring->q_vector) 5448 ring_node = tx_ring->q_vector->numa_node; 5449 5450 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5451 if (!tx_ring->tx_buffer_info) 5452 tx_ring->tx_buffer_info = vzalloc(size); 5453 if (!tx_ring->tx_buffer_info) 5454 goto err; 5455 5456 u64_stats_init(&tx_ring->syncp); 5457 5458 /* round up to nearest 4K */ 5459 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5460 tx_ring->size = ALIGN(tx_ring->size, 4096); 5461 5462 set_dev_node(dev, ring_node); 5463 tx_ring->desc = dma_alloc_coherent(dev, 5464 tx_ring->size, 5465 &tx_ring->dma, 5466 GFP_KERNEL); 5467 set_dev_node(dev, orig_node); 5468 if (!tx_ring->desc) 5469 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5470 &tx_ring->dma, GFP_KERNEL); 5471 if (!tx_ring->desc) 5472 goto err; 5473 5474 tx_ring->next_to_use = 0; 5475 tx_ring->next_to_clean = 0; 5476 return 0; 5477 5478 err: 5479 vfree(tx_ring->tx_buffer_info); 5480 tx_ring->tx_buffer_info = NULL; 5481 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5482 return -ENOMEM; 5483 } 5484 5485 /** 5486 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5487 * @adapter: board private structure 5488 * 5489 * If this function returns with an error, then it's possible one or 5490 * more of the rings is populated (while the rest are not). It is the 5491 * callers duty to clean those orphaned rings. 5492 * 5493 * Return 0 on success, negative on failure 5494 **/ 5495 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5496 { 5497 int i, err = 0; 5498 5499 for (i = 0; i < adapter->num_tx_queues; i++) { 5500 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5501 if (!err) 5502 continue; 5503 5504 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5505 goto err_setup_tx; 5506 } 5507 5508 return 0; 5509 err_setup_tx: 5510 /* rewind the index freeing the rings as we go */ 5511 while (i--) 5512 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5513 return err; 5514 } 5515 5516 /** 5517 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5518 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5519 * 5520 * Returns 0 on success, negative on failure 5521 **/ 5522 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5523 { 5524 struct device *dev = rx_ring->dev; 5525 int orig_node = dev_to_node(dev); 5526 int ring_node = -1; 5527 int size; 5528 5529 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5530 5531 if (rx_ring->q_vector) 5532 ring_node = rx_ring->q_vector->numa_node; 5533 5534 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5535 if (!rx_ring->rx_buffer_info) 5536 rx_ring->rx_buffer_info = vzalloc(size); 5537 if (!rx_ring->rx_buffer_info) 5538 goto err; 5539 5540 u64_stats_init(&rx_ring->syncp); 5541 5542 /* Round up to nearest 4K */ 5543 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5544 rx_ring->size = ALIGN(rx_ring->size, 4096); 5545 5546 set_dev_node(dev, ring_node); 5547 rx_ring->desc = dma_alloc_coherent(dev, 5548 rx_ring->size, 5549 &rx_ring->dma, 5550 GFP_KERNEL); 5551 set_dev_node(dev, orig_node); 5552 if (!rx_ring->desc) 5553 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5554 &rx_ring->dma, GFP_KERNEL); 5555 if (!rx_ring->desc) 5556 goto err; 5557 5558 rx_ring->next_to_clean = 0; 5559 rx_ring->next_to_use = 0; 5560 5561 return 0; 5562 err: 5563 vfree(rx_ring->rx_buffer_info); 5564 rx_ring->rx_buffer_info = NULL; 5565 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5566 return -ENOMEM; 5567 } 5568 5569 /** 5570 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5571 * @adapter: board private structure 5572 * 5573 * If this function returns with an error, then it's possible one or 5574 * more of the rings is populated (while the rest are not). It is the 5575 * callers duty to clean those orphaned rings. 5576 * 5577 * Return 0 on success, negative on failure 5578 **/ 5579 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5580 { 5581 int i, err = 0; 5582 5583 for (i = 0; i < adapter->num_rx_queues; i++) { 5584 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5585 if (!err) 5586 continue; 5587 5588 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5589 goto err_setup_rx; 5590 } 5591 5592 #ifdef IXGBE_FCOE 5593 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5594 if (!err) 5595 #endif 5596 return 0; 5597 err_setup_rx: 5598 /* rewind the index freeing the rings as we go */ 5599 while (i--) 5600 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5601 return err; 5602 } 5603 5604 /** 5605 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5606 * @tx_ring: Tx descriptor ring for a specific queue 5607 * 5608 * Free all transmit software resources 5609 **/ 5610 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5611 { 5612 ixgbe_clean_tx_ring(tx_ring); 5613 5614 vfree(tx_ring->tx_buffer_info); 5615 tx_ring->tx_buffer_info = NULL; 5616 5617 /* if not set, then don't free */ 5618 if (!tx_ring->desc) 5619 return; 5620 5621 dma_free_coherent(tx_ring->dev, tx_ring->size, 5622 tx_ring->desc, tx_ring->dma); 5623 5624 tx_ring->desc = NULL; 5625 } 5626 5627 /** 5628 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5629 * @adapter: board private structure 5630 * 5631 * Free all transmit software resources 5632 **/ 5633 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5634 { 5635 int i; 5636 5637 for (i = 0; i < adapter->num_tx_queues; i++) 5638 if (adapter->tx_ring[i]->desc) 5639 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5640 } 5641 5642 /** 5643 * ixgbe_free_rx_resources - Free Rx Resources 5644 * @rx_ring: ring to clean the resources from 5645 * 5646 * Free all receive software resources 5647 **/ 5648 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5649 { 5650 ixgbe_clean_rx_ring(rx_ring); 5651 5652 vfree(rx_ring->rx_buffer_info); 5653 rx_ring->rx_buffer_info = NULL; 5654 5655 /* if not set, then don't free */ 5656 if (!rx_ring->desc) 5657 return; 5658 5659 dma_free_coherent(rx_ring->dev, rx_ring->size, 5660 rx_ring->desc, rx_ring->dma); 5661 5662 rx_ring->desc = NULL; 5663 } 5664 5665 /** 5666 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5667 * @adapter: board private structure 5668 * 5669 * Free all receive software resources 5670 **/ 5671 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5672 { 5673 int i; 5674 5675 #ifdef IXGBE_FCOE 5676 ixgbe_free_fcoe_ddp_resources(adapter); 5677 5678 #endif 5679 for (i = 0; i < adapter->num_rx_queues; i++) 5680 if (adapter->rx_ring[i]->desc) 5681 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5682 } 5683 5684 /** 5685 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5686 * @netdev: network interface device structure 5687 * @new_mtu: new value for maximum frame size 5688 * 5689 * Returns 0 on success, negative on failure 5690 **/ 5691 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5692 { 5693 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5694 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5695 5696 /* MTU < 68 is an error and causes problems on some kernels */ 5697 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5698 return -EINVAL; 5699 5700 /* 5701 * For 82599EB we cannot allow legacy VFs to enable their receive 5702 * paths when MTU greater than 1500 is configured. So display a 5703 * warning that legacy VFs will be disabled. 5704 */ 5705 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5706 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5707 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5708 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5709 5710 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5711 5712 /* must set new MTU before calling down or up */ 5713 netdev->mtu = new_mtu; 5714 5715 if (netif_running(netdev)) 5716 ixgbe_reinit_locked(adapter); 5717 5718 return 0; 5719 } 5720 5721 /** 5722 * ixgbe_open - Called when a network interface is made active 5723 * @netdev: network interface device structure 5724 * 5725 * Returns 0 on success, negative value on failure 5726 * 5727 * The open entry point is called when a network interface is made 5728 * active by the system (IFF_UP). At this point all resources needed 5729 * for transmit and receive operations are allocated, the interrupt 5730 * handler is registered with the OS, the watchdog timer is started, 5731 * and the stack is notified that the interface is ready. 5732 **/ 5733 static int ixgbe_open(struct net_device *netdev) 5734 { 5735 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5736 struct ixgbe_hw *hw = &adapter->hw; 5737 int err, queues; 5738 5739 /* disallow open during test */ 5740 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5741 return -EBUSY; 5742 5743 netif_carrier_off(netdev); 5744 5745 /* allocate transmit descriptors */ 5746 err = ixgbe_setup_all_tx_resources(adapter); 5747 if (err) 5748 goto err_setup_tx; 5749 5750 /* allocate receive descriptors */ 5751 err = ixgbe_setup_all_rx_resources(adapter); 5752 if (err) 5753 goto err_setup_rx; 5754 5755 ixgbe_configure(adapter); 5756 5757 err = ixgbe_request_irq(adapter); 5758 if (err) 5759 goto err_req_irq; 5760 5761 /* Notify the stack of the actual queue counts. */ 5762 if (adapter->num_rx_pools > 1) 5763 queues = adapter->num_rx_queues_per_pool; 5764 else 5765 queues = adapter->num_tx_queues; 5766 5767 err = netif_set_real_num_tx_queues(netdev, queues); 5768 if (err) 5769 goto err_set_queues; 5770 5771 if (adapter->num_rx_pools > 1 && 5772 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5773 queues = IXGBE_MAX_L2A_QUEUES; 5774 else 5775 queues = adapter->num_rx_queues; 5776 err = netif_set_real_num_rx_queues(netdev, queues); 5777 if (err) 5778 goto err_set_queues; 5779 5780 ixgbe_ptp_init(adapter); 5781 5782 ixgbe_up_complete(adapter); 5783 5784 ixgbe_clear_vxlan_port(adapter); 5785 #ifdef CONFIG_IXGBE_VXLAN 5786 vxlan_get_rx_port(netdev); 5787 #endif 5788 5789 return 0; 5790 5791 err_set_queues: 5792 ixgbe_free_irq(adapter); 5793 err_req_irq: 5794 ixgbe_free_all_rx_resources(adapter); 5795 if (hw->phy.ops.set_phy_power && !adapter->wol) 5796 hw->phy.ops.set_phy_power(&adapter->hw, false); 5797 err_setup_rx: 5798 ixgbe_free_all_tx_resources(adapter); 5799 err_setup_tx: 5800 ixgbe_reset(adapter); 5801 5802 return err; 5803 } 5804 5805 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5806 { 5807 ixgbe_ptp_suspend(adapter); 5808 5809 if (adapter->hw.phy.ops.enter_lplu) { 5810 adapter->hw.phy.reset_disable = true; 5811 ixgbe_down(adapter); 5812 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 5813 adapter->hw.phy.reset_disable = false; 5814 } else { 5815 ixgbe_down(adapter); 5816 } 5817 5818 ixgbe_free_irq(adapter); 5819 5820 ixgbe_free_all_tx_resources(adapter); 5821 ixgbe_free_all_rx_resources(adapter); 5822 } 5823 5824 /** 5825 * ixgbe_close - Disables a network interface 5826 * @netdev: network interface device structure 5827 * 5828 * Returns 0, this is not allowed to fail 5829 * 5830 * The close entry point is called when an interface is de-activated 5831 * by the OS. The hardware is still under the drivers control, but 5832 * needs to be disabled. A global MAC reset is issued to stop the 5833 * hardware, and all transmit and receive resources are freed. 5834 **/ 5835 static int ixgbe_close(struct net_device *netdev) 5836 { 5837 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5838 5839 ixgbe_ptp_stop(adapter); 5840 5841 ixgbe_close_suspend(adapter); 5842 5843 ixgbe_fdir_filter_exit(adapter); 5844 5845 ixgbe_release_hw_control(adapter); 5846 5847 return 0; 5848 } 5849 5850 #ifdef CONFIG_PM 5851 static int ixgbe_resume(struct pci_dev *pdev) 5852 { 5853 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5854 struct net_device *netdev = adapter->netdev; 5855 u32 err; 5856 5857 adapter->hw.hw_addr = adapter->io_addr; 5858 pci_set_power_state(pdev, PCI_D0); 5859 pci_restore_state(pdev); 5860 /* 5861 * pci_restore_state clears dev->state_saved so call 5862 * pci_save_state to restore it. 5863 */ 5864 pci_save_state(pdev); 5865 5866 err = pci_enable_device_mem(pdev); 5867 if (err) { 5868 e_dev_err("Cannot enable PCI device from suspend\n"); 5869 return err; 5870 } 5871 smp_mb__before_atomic(); 5872 clear_bit(__IXGBE_DISABLED, &adapter->state); 5873 pci_set_master(pdev); 5874 5875 pci_wake_from_d3(pdev, false); 5876 5877 ixgbe_reset(adapter); 5878 5879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5880 5881 rtnl_lock(); 5882 err = ixgbe_init_interrupt_scheme(adapter); 5883 if (!err && netif_running(netdev)) 5884 err = ixgbe_open(netdev); 5885 5886 rtnl_unlock(); 5887 5888 if (err) 5889 return err; 5890 5891 netif_device_attach(netdev); 5892 5893 return 0; 5894 } 5895 #endif /* CONFIG_PM */ 5896 5897 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5898 { 5899 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5900 struct net_device *netdev = adapter->netdev; 5901 struct ixgbe_hw *hw = &adapter->hw; 5902 u32 ctrl, fctrl; 5903 u32 wufc = adapter->wol; 5904 #ifdef CONFIG_PM 5905 int retval = 0; 5906 #endif 5907 5908 netif_device_detach(netdev); 5909 5910 rtnl_lock(); 5911 if (netif_running(netdev)) 5912 ixgbe_close_suspend(adapter); 5913 rtnl_unlock(); 5914 5915 ixgbe_clear_interrupt_scheme(adapter); 5916 5917 #ifdef CONFIG_PM 5918 retval = pci_save_state(pdev); 5919 if (retval) 5920 return retval; 5921 5922 #endif 5923 if (hw->mac.ops.stop_link_on_d3) 5924 hw->mac.ops.stop_link_on_d3(hw); 5925 5926 if (wufc) { 5927 ixgbe_set_rx_mode(netdev); 5928 5929 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5930 if (hw->mac.ops.enable_tx_laser) 5931 hw->mac.ops.enable_tx_laser(hw); 5932 5933 /* turn on all-multi mode if wake on multicast is enabled */ 5934 if (wufc & IXGBE_WUFC_MC) { 5935 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5936 fctrl |= IXGBE_FCTRL_MPE; 5937 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5938 } 5939 5940 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5941 ctrl |= IXGBE_CTRL_GIO_DIS; 5942 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5943 5944 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5945 } else { 5946 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5947 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5948 } 5949 5950 switch (hw->mac.type) { 5951 case ixgbe_mac_82598EB: 5952 pci_wake_from_d3(pdev, false); 5953 break; 5954 case ixgbe_mac_82599EB: 5955 case ixgbe_mac_X540: 5956 case ixgbe_mac_X550: 5957 case ixgbe_mac_X550EM_x: 5958 pci_wake_from_d3(pdev, !!wufc); 5959 break; 5960 default: 5961 break; 5962 } 5963 5964 *enable_wake = !!wufc; 5965 if (hw->phy.ops.set_phy_power && !*enable_wake) 5966 hw->phy.ops.set_phy_power(hw, false); 5967 5968 ixgbe_release_hw_control(adapter); 5969 5970 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5971 pci_disable_device(pdev); 5972 5973 return 0; 5974 } 5975 5976 #ifdef CONFIG_PM 5977 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5978 { 5979 int retval; 5980 bool wake; 5981 5982 retval = __ixgbe_shutdown(pdev, &wake); 5983 if (retval) 5984 return retval; 5985 5986 if (wake) { 5987 pci_prepare_to_sleep(pdev); 5988 } else { 5989 pci_wake_from_d3(pdev, false); 5990 pci_set_power_state(pdev, PCI_D3hot); 5991 } 5992 5993 return 0; 5994 } 5995 #endif /* CONFIG_PM */ 5996 5997 static void ixgbe_shutdown(struct pci_dev *pdev) 5998 { 5999 bool wake; 6000 6001 __ixgbe_shutdown(pdev, &wake); 6002 6003 if (system_state == SYSTEM_POWER_OFF) { 6004 pci_wake_from_d3(pdev, wake); 6005 pci_set_power_state(pdev, PCI_D3hot); 6006 } 6007 } 6008 6009 /** 6010 * ixgbe_update_stats - Update the board statistics counters. 6011 * @adapter: board private structure 6012 **/ 6013 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6014 { 6015 struct net_device *netdev = adapter->netdev; 6016 struct ixgbe_hw *hw = &adapter->hw; 6017 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6018 u64 total_mpc = 0; 6019 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6020 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6021 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6022 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6023 6024 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6025 test_bit(__IXGBE_RESETTING, &adapter->state)) 6026 return; 6027 6028 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6029 u64 rsc_count = 0; 6030 u64 rsc_flush = 0; 6031 for (i = 0; i < adapter->num_rx_queues; i++) { 6032 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6033 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6034 } 6035 adapter->rsc_total_count = rsc_count; 6036 adapter->rsc_total_flush = rsc_flush; 6037 } 6038 6039 for (i = 0; i < adapter->num_rx_queues; i++) { 6040 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6041 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6042 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6043 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6044 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6045 bytes += rx_ring->stats.bytes; 6046 packets += rx_ring->stats.packets; 6047 } 6048 adapter->non_eop_descs = non_eop_descs; 6049 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6050 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6051 adapter->hw_csum_rx_error = hw_csum_rx_error; 6052 netdev->stats.rx_bytes = bytes; 6053 netdev->stats.rx_packets = packets; 6054 6055 bytes = 0; 6056 packets = 0; 6057 /* gather some stats to the adapter struct that are per queue */ 6058 for (i = 0; i < adapter->num_tx_queues; i++) { 6059 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6060 restart_queue += tx_ring->tx_stats.restart_queue; 6061 tx_busy += tx_ring->tx_stats.tx_busy; 6062 bytes += tx_ring->stats.bytes; 6063 packets += tx_ring->stats.packets; 6064 } 6065 adapter->restart_queue = restart_queue; 6066 adapter->tx_busy = tx_busy; 6067 netdev->stats.tx_bytes = bytes; 6068 netdev->stats.tx_packets = packets; 6069 6070 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6071 6072 /* 8 register reads */ 6073 for (i = 0; i < 8; i++) { 6074 /* for packet buffers not used, the register should read 0 */ 6075 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6076 missed_rx += mpc; 6077 hwstats->mpc[i] += mpc; 6078 total_mpc += hwstats->mpc[i]; 6079 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6080 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6081 switch (hw->mac.type) { 6082 case ixgbe_mac_82598EB: 6083 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6084 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6085 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6086 hwstats->pxonrxc[i] += 6087 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6088 break; 6089 case ixgbe_mac_82599EB: 6090 case ixgbe_mac_X540: 6091 case ixgbe_mac_X550: 6092 case ixgbe_mac_X550EM_x: 6093 hwstats->pxonrxc[i] += 6094 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6095 break; 6096 default: 6097 break; 6098 } 6099 } 6100 6101 /*16 register reads */ 6102 for (i = 0; i < 16; i++) { 6103 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6104 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6105 if ((hw->mac.type == ixgbe_mac_82599EB) || 6106 (hw->mac.type == ixgbe_mac_X540) || 6107 (hw->mac.type == ixgbe_mac_X550) || 6108 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6109 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6110 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6111 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6112 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6113 } 6114 } 6115 6116 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6117 /* work around hardware counting issue */ 6118 hwstats->gprc -= missed_rx; 6119 6120 ixgbe_update_xoff_received(adapter); 6121 6122 /* 82598 hardware only has a 32 bit counter in the high register */ 6123 switch (hw->mac.type) { 6124 case ixgbe_mac_82598EB: 6125 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6126 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6127 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6128 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6129 break; 6130 case ixgbe_mac_X540: 6131 case ixgbe_mac_X550: 6132 case ixgbe_mac_X550EM_x: 6133 /* OS2BMC stats are X540 and later */ 6134 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6135 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6136 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6137 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6138 case ixgbe_mac_82599EB: 6139 for (i = 0; i < 16; i++) 6140 adapter->hw_rx_no_dma_resources += 6141 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6142 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6143 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6144 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6145 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6146 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6147 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6148 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6149 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6150 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6151 #ifdef IXGBE_FCOE 6152 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6153 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6154 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6155 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6156 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6157 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6158 /* Add up per cpu counters for total ddp aloc fail */ 6159 if (adapter->fcoe.ddp_pool) { 6160 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6161 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6162 unsigned int cpu; 6163 u64 noddp = 0, noddp_ext_buff = 0; 6164 for_each_possible_cpu(cpu) { 6165 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6166 noddp += ddp_pool->noddp; 6167 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6168 } 6169 hwstats->fcoe_noddp = noddp; 6170 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6171 } 6172 #endif /* IXGBE_FCOE */ 6173 break; 6174 default: 6175 break; 6176 } 6177 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6178 hwstats->bprc += bprc; 6179 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6180 if (hw->mac.type == ixgbe_mac_82598EB) 6181 hwstats->mprc -= bprc; 6182 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6183 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6184 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6185 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6186 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6187 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6188 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6189 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6190 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6191 hwstats->lxontxc += lxon; 6192 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6193 hwstats->lxofftxc += lxoff; 6194 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6195 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6196 /* 6197 * 82598 errata - tx of flow control packets is included in tx counters 6198 */ 6199 xon_off_tot = lxon + lxoff; 6200 hwstats->gptc -= xon_off_tot; 6201 hwstats->mptc -= xon_off_tot; 6202 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6203 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6204 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6205 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6206 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6207 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6208 hwstats->ptc64 -= xon_off_tot; 6209 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6210 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6211 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6212 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6213 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6214 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6215 6216 /* Fill out the OS statistics structure */ 6217 netdev->stats.multicast = hwstats->mprc; 6218 6219 /* Rx Errors */ 6220 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6221 netdev->stats.rx_dropped = 0; 6222 netdev->stats.rx_length_errors = hwstats->rlec; 6223 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6224 netdev->stats.rx_missed_errors = total_mpc; 6225 } 6226 6227 /** 6228 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6229 * @adapter: pointer to the device adapter structure 6230 **/ 6231 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6232 { 6233 struct ixgbe_hw *hw = &adapter->hw; 6234 int i; 6235 6236 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6237 return; 6238 6239 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6240 6241 /* if interface is down do nothing */ 6242 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6243 return; 6244 6245 /* do nothing if we are not using signature filters */ 6246 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6247 return; 6248 6249 adapter->fdir_overflow++; 6250 6251 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6252 for (i = 0; i < adapter->num_tx_queues; i++) 6253 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6254 &(adapter->tx_ring[i]->state)); 6255 /* re-enable flow director interrupts */ 6256 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6257 } else { 6258 e_err(probe, "failed to finish FDIR re-initialization, " 6259 "ignored adding FDIR ATR filters\n"); 6260 } 6261 } 6262 6263 /** 6264 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6265 * @adapter: pointer to the device adapter structure 6266 * 6267 * This function serves two purposes. First it strobes the interrupt lines 6268 * in order to make certain interrupts are occurring. Secondly it sets the 6269 * bits needed to check for TX hangs. As a result we should immediately 6270 * determine if a hang has occurred. 6271 */ 6272 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6273 { 6274 struct ixgbe_hw *hw = &adapter->hw; 6275 u64 eics = 0; 6276 int i; 6277 6278 /* If we're down, removing or resetting, just bail */ 6279 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6280 test_bit(__IXGBE_REMOVING, &adapter->state) || 6281 test_bit(__IXGBE_RESETTING, &adapter->state)) 6282 return; 6283 6284 /* Force detection of hung controller */ 6285 if (netif_carrier_ok(adapter->netdev)) { 6286 for (i = 0; i < adapter->num_tx_queues; i++) 6287 set_check_for_tx_hang(adapter->tx_ring[i]); 6288 } 6289 6290 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6291 /* 6292 * for legacy and MSI interrupts don't set any bits 6293 * that are enabled for EIAM, because this operation 6294 * would set *both* EIMS and EICS for any bit in EIAM 6295 */ 6296 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6297 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6298 } else { 6299 /* get one bit for every active tx/rx interrupt vector */ 6300 for (i = 0; i < adapter->num_q_vectors; i++) { 6301 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6302 if (qv->rx.ring || qv->tx.ring) 6303 eics |= ((u64)1 << i); 6304 } 6305 } 6306 6307 /* Cause software interrupt to ensure rings are cleaned */ 6308 ixgbe_irq_rearm_queues(adapter, eics); 6309 } 6310 6311 /** 6312 * ixgbe_watchdog_update_link - update the link status 6313 * @adapter: pointer to the device adapter structure 6314 * @link_speed: pointer to a u32 to store the link_speed 6315 **/ 6316 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6317 { 6318 struct ixgbe_hw *hw = &adapter->hw; 6319 u32 link_speed = adapter->link_speed; 6320 bool link_up = adapter->link_up; 6321 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6322 6323 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6324 return; 6325 6326 if (hw->mac.ops.check_link) { 6327 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6328 } else { 6329 /* always assume link is up, if no check link function */ 6330 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6331 link_up = true; 6332 } 6333 6334 if (adapter->ixgbe_ieee_pfc) 6335 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6336 6337 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6338 hw->mac.ops.fc_enable(hw); 6339 ixgbe_set_rx_drop_en(adapter); 6340 } 6341 6342 if (link_up || 6343 time_after(jiffies, (adapter->link_check_timeout + 6344 IXGBE_TRY_LINK_TIMEOUT))) { 6345 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6346 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6347 IXGBE_WRITE_FLUSH(hw); 6348 } 6349 6350 adapter->link_up = link_up; 6351 adapter->link_speed = link_speed; 6352 } 6353 6354 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6355 { 6356 #ifdef CONFIG_IXGBE_DCB 6357 struct net_device *netdev = adapter->netdev; 6358 struct dcb_app app = { 6359 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6360 .protocol = 0, 6361 }; 6362 u8 up = 0; 6363 6364 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6365 up = dcb_ieee_getapp_mask(netdev, &app); 6366 6367 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6368 #endif 6369 } 6370 6371 /** 6372 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6373 * print link up message 6374 * @adapter: pointer to the device adapter structure 6375 **/ 6376 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6377 { 6378 struct net_device *netdev = adapter->netdev; 6379 struct ixgbe_hw *hw = &adapter->hw; 6380 struct net_device *upper; 6381 struct list_head *iter; 6382 u32 link_speed = adapter->link_speed; 6383 const char *speed_str; 6384 bool flow_rx, flow_tx; 6385 6386 /* only continue if link was previously down */ 6387 if (netif_carrier_ok(netdev)) 6388 return; 6389 6390 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6391 6392 switch (hw->mac.type) { 6393 case ixgbe_mac_82598EB: { 6394 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6395 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6396 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6397 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6398 } 6399 break; 6400 case ixgbe_mac_X540: 6401 case ixgbe_mac_X550: 6402 case ixgbe_mac_X550EM_x: 6403 case ixgbe_mac_82599EB: { 6404 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6405 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6406 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6407 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6408 } 6409 break; 6410 default: 6411 flow_tx = false; 6412 flow_rx = false; 6413 break; 6414 } 6415 6416 adapter->last_rx_ptp_check = jiffies; 6417 6418 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6419 ixgbe_ptp_start_cyclecounter(adapter); 6420 6421 switch (link_speed) { 6422 case IXGBE_LINK_SPEED_10GB_FULL: 6423 speed_str = "10 Gbps"; 6424 break; 6425 case IXGBE_LINK_SPEED_2_5GB_FULL: 6426 speed_str = "2.5 Gbps"; 6427 break; 6428 case IXGBE_LINK_SPEED_1GB_FULL: 6429 speed_str = "1 Gbps"; 6430 break; 6431 case IXGBE_LINK_SPEED_100_FULL: 6432 speed_str = "100 Mbps"; 6433 break; 6434 default: 6435 speed_str = "unknown speed"; 6436 break; 6437 } 6438 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 6439 ((flow_rx && flow_tx) ? "RX/TX" : 6440 (flow_rx ? "RX" : 6441 (flow_tx ? "TX" : "None")))); 6442 6443 netif_carrier_on(netdev); 6444 ixgbe_check_vf_rate_limit(adapter); 6445 6446 /* enable transmits */ 6447 netif_tx_wake_all_queues(adapter->netdev); 6448 6449 /* enable any upper devices */ 6450 rtnl_lock(); 6451 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6452 if (netif_is_macvlan(upper)) { 6453 struct macvlan_dev *vlan = netdev_priv(upper); 6454 6455 if (vlan->fwd_priv) 6456 netif_tx_wake_all_queues(upper); 6457 } 6458 } 6459 rtnl_unlock(); 6460 6461 /* update the default user priority for VFs */ 6462 ixgbe_update_default_up(adapter); 6463 6464 /* ping all the active vfs to let them know link has changed */ 6465 ixgbe_ping_all_vfs(adapter); 6466 } 6467 6468 /** 6469 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6470 * print link down message 6471 * @adapter: pointer to the adapter structure 6472 **/ 6473 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6474 { 6475 struct net_device *netdev = adapter->netdev; 6476 struct ixgbe_hw *hw = &adapter->hw; 6477 6478 adapter->link_up = false; 6479 adapter->link_speed = 0; 6480 6481 /* only continue if link was up previously */ 6482 if (!netif_carrier_ok(netdev)) 6483 return; 6484 6485 /* poll for SFP+ cable when link is down */ 6486 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6487 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6488 6489 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6490 ixgbe_ptp_start_cyclecounter(adapter); 6491 6492 e_info(drv, "NIC Link is Down\n"); 6493 netif_carrier_off(netdev); 6494 6495 /* ping all the active vfs to let them know link has changed */ 6496 ixgbe_ping_all_vfs(adapter); 6497 } 6498 6499 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6500 { 6501 int i; 6502 6503 for (i = 0; i < adapter->num_tx_queues; i++) { 6504 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6505 6506 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6507 return true; 6508 } 6509 6510 return false; 6511 } 6512 6513 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6514 { 6515 struct ixgbe_hw *hw = &adapter->hw; 6516 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6517 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6518 6519 int i, j; 6520 6521 if (!adapter->num_vfs) 6522 return false; 6523 6524 /* resetting the PF is only needed for MAC before X550 */ 6525 if (hw->mac.type >= ixgbe_mac_X550) 6526 return false; 6527 6528 for (i = 0; i < adapter->num_vfs; i++) { 6529 for (j = 0; j < q_per_pool; j++) { 6530 u32 h, t; 6531 6532 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6533 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6534 6535 if (h != t) 6536 return true; 6537 } 6538 } 6539 6540 return false; 6541 } 6542 6543 /** 6544 * ixgbe_watchdog_flush_tx - flush queues on link down 6545 * @adapter: pointer to the device adapter structure 6546 **/ 6547 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6548 { 6549 if (!netif_carrier_ok(adapter->netdev)) { 6550 if (ixgbe_ring_tx_pending(adapter) || 6551 ixgbe_vf_tx_pending(adapter)) { 6552 /* We've lost link, so the controller stops DMA, 6553 * but we've got queued Tx work that's never going 6554 * to get done, so reset controller to flush Tx. 6555 * (Do the reset outside of interrupt context). 6556 */ 6557 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6558 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6559 } 6560 } 6561 } 6562 6563 #ifdef CONFIG_PCI_IOV 6564 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6565 struct pci_dev *vfdev) 6566 { 6567 if (!pci_wait_for_pending_transaction(vfdev)) 6568 e_dev_warn("Issuing VFLR with pending transactions\n"); 6569 6570 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6571 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6572 6573 msleep(100); 6574 } 6575 6576 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6577 { 6578 struct ixgbe_hw *hw = &adapter->hw; 6579 struct pci_dev *pdev = adapter->pdev; 6580 struct pci_dev *vfdev; 6581 u32 gpc; 6582 int pos; 6583 unsigned short vf_id; 6584 6585 if (!(netif_carrier_ok(adapter->netdev))) 6586 return; 6587 6588 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6589 if (gpc) /* If incrementing then no need for the check below */ 6590 return; 6591 /* Check to see if a bad DMA write target from an errant or 6592 * malicious VF has caused a PCIe error. If so then we can 6593 * issue a VFLR to the offending VF(s) and then resume without 6594 * requesting a full slot reset. 6595 */ 6596 6597 if (!pdev) 6598 return; 6599 6600 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6601 if (!pos) 6602 return; 6603 6604 /* get the device ID for the VF */ 6605 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6606 6607 /* check status reg for all VFs owned by this PF */ 6608 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6609 while (vfdev) { 6610 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6611 u16 status_reg; 6612 6613 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6614 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6615 /* issue VFLR */ 6616 ixgbe_issue_vf_flr(adapter, vfdev); 6617 } 6618 6619 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6620 } 6621 } 6622 6623 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6624 { 6625 u32 ssvpc; 6626 6627 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6628 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6629 adapter->num_vfs == 0) 6630 return; 6631 6632 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6633 6634 /* 6635 * ssvpc register is cleared on read, if zero then no 6636 * spoofed packets in the last interval. 6637 */ 6638 if (!ssvpc) 6639 return; 6640 6641 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6642 } 6643 #else 6644 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6645 { 6646 } 6647 6648 static void 6649 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6650 { 6651 } 6652 #endif /* CONFIG_PCI_IOV */ 6653 6654 6655 /** 6656 * ixgbe_watchdog_subtask - check and bring link up 6657 * @adapter: pointer to the device adapter structure 6658 **/ 6659 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6660 { 6661 /* if interface is down, removing or resetting, do nothing */ 6662 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6663 test_bit(__IXGBE_REMOVING, &adapter->state) || 6664 test_bit(__IXGBE_RESETTING, &adapter->state)) 6665 return; 6666 6667 ixgbe_watchdog_update_link(adapter); 6668 6669 if (adapter->link_up) 6670 ixgbe_watchdog_link_is_up(adapter); 6671 else 6672 ixgbe_watchdog_link_is_down(adapter); 6673 6674 ixgbe_check_for_bad_vf(adapter); 6675 ixgbe_spoof_check(adapter); 6676 ixgbe_update_stats(adapter); 6677 6678 ixgbe_watchdog_flush_tx(adapter); 6679 } 6680 6681 /** 6682 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6683 * @adapter: the ixgbe adapter structure 6684 **/ 6685 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6686 { 6687 struct ixgbe_hw *hw = &adapter->hw; 6688 s32 err; 6689 6690 /* not searching for SFP so there is nothing to do here */ 6691 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6692 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6693 return; 6694 6695 /* someone else is in init, wait until next service event */ 6696 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6697 return; 6698 6699 err = hw->phy.ops.identify_sfp(hw); 6700 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6701 goto sfp_out; 6702 6703 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6704 /* If no cable is present, then we need to reset 6705 * the next time we find a good cable. */ 6706 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6707 } 6708 6709 /* exit on error */ 6710 if (err) 6711 goto sfp_out; 6712 6713 /* exit if reset not needed */ 6714 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6715 goto sfp_out; 6716 6717 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6718 6719 /* 6720 * A module may be identified correctly, but the EEPROM may not have 6721 * support for that module. setup_sfp() will fail in that case, so 6722 * we should not allow that module to load. 6723 */ 6724 if (hw->mac.type == ixgbe_mac_82598EB) 6725 err = hw->phy.ops.reset(hw); 6726 else 6727 err = hw->mac.ops.setup_sfp(hw); 6728 6729 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6730 goto sfp_out; 6731 6732 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6733 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6734 6735 sfp_out: 6736 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6737 6738 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6739 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6740 e_dev_err("failed to initialize because an unsupported " 6741 "SFP+ module type was detected.\n"); 6742 e_dev_err("Reload the driver after installing a " 6743 "supported module.\n"); 6744 unregister_netdev(adapter->netdev); 6745 } 6746 } 6747 6748 /** 6749 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6750 * @adapter: the ixgbe adapter structure 6751 **/ 6752 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6753 { 6754 struct ixgbe_hw *hw = &adapter->hw; 6755 u32 speed; 6756 bool autoneg = false; 6757 6758 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6759 return; 6760 6761 /* someone else is in init, wait until next service event */ 6762 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6763 return; 6764 6765 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6766 6767 speed = hw->phy.autoneg_advertised; 6768 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6769 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6770 6771 /* setup the highest link when no autoneg */ 6772 if (!autoneg) { 6773 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6774 speed = IXGBE_LINK_SPEED_10GB_FULL; 6775 } 6776 } 6777 6778 if (hw->mac.ops.setup_link) 6779 hw->mac.ops.setup_link(hw, speed, true); 6780 6781 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6782 adapter->link_check_timeout = jiffies; 6783 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6784 } 6785 6786 /** 6787 * ixgbe_service_timer - Timer Call-back 6788 * @data: pointer to adapter cast into an unsigned long 6789 **/ 6790 static void ixgbe_service_timer(unsigned long data) 6791 { 6792 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6793 unsigned long next_event_offset; 6794 6795 /* poll faster when waiting for link */ 6796 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6797 next_event_offset = HZ / 10; 6798 else 6799 next_event_offset = HZ * 2; 6800 6801 /* Reset the timer */ 6802 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6803 6804 ixgbe_service_event_schedule(adapter); 6805 } 6806 6807 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 6808 { 6809 struct ixgbe_hw *hw = &adapter->hw; 6810 u32 status; 6811 6812 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 6813 return; 6814 6815 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 6816 6817 if (!hw->phy.ops.handle_lasi) 6818 return; 6819 6820 status = hw->phy.ops.handle_lasi(&adapter->hw); 6821 if (status != IXGBE_ERR_OVERTEMP) 6822 return; 6823 6824 e_crit(drv, "%s\n", ixgbe_overheat_msg); 6825 } 6826 6827 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6828 { 6829 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6830 return; 6831 6832 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6833 6834 /* If we're already down, removing or resetting, just bail */ 6835 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6836 test_bit(__IXGBE_REMOVING, &adapter->state) || 6837 test_bit(__IXGBE_RESETTING, &adapter->state)) 6838 return; 6839 6840 ixgbe_dump(adapter); 6841 netdev_err(adapter->netdev, "Reset adapter\n"); 6842 adapter->tx_timeout_count++; 6843 6844 rtnl_lock(); 6845 ixgbe_reinit_locked(adapter); 6846 rtnl_unlock(); 6847 } 6848 6849 /** 6850 * ixgbe_service_task - manages and runs subtasks 6851 * @work: pointer to work_struct containing our data 6852 **/ 6853 static void ixgbe_service_task(struct work_struct *work) 6854 { 6855 struct ixgbe_adapter *adapter = container_of(work, 6856 struct ixgbe_adapter, 6857 service_task); 6858 if (ixgbe_removed(adapter->hw.hw_addr)) { 6859 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6860 rtnl_lock(); 6861 ixgbe_down(adapter); 6862 rtnl_unlock(); 6863 } 6864 ixgbe_service_event_complete(adapter); 6865 return; 6866 } 6867 #ifdef CONFIG_IXGBE_VXLAN 6868 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) { 6869 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED; 6870 vxlan_get_rx_port(adapter->netdev); 6871 } 6872 #endif /* CONFIG_IXGBE_VXLAN */ 6873 ixgbe_reset_subtask(adapter); 6874 ixgbe_phy_interrupt_subtask(adapter); 6875 ixgbe_sfp_detection_subtask(adapter); 6876 ixgbe_sfp_link_config_subtask(adapter); 6877 ixgbe_check_overtemp_subtask(adapter); 6878 ixgbe_watchdog_subtask(adapter); 6879 ixgbe_fdir_reinit_subtask(adapter); 6880 ixgbe_check_hang_subtask(adapter); 6881 6882 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6883 ixgbe_ptp_overflow_check(adapter); 6884 ixgbe_ptp_rx_hang(adapter); 6885 } 6886 6887 ixgbe_service_event_complete(adapter); 6888 } 6889 6890 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6891 struct ixgbe_tx_buffer *first, 6892 u8 *hdr_len) 6893 { 6894 struct sk_buff *skb = first->skb; 6895 u32 vlan_macip_lens, type_tucmd; 6896 u32 mss_l4len_idx, l4len; 6897 int err; 6898 6899 if (skb->ip_summed != CHECKSUM_PARTIAL) 6900 return 0; 6901 6902 if (!skb_is_gso(skb)) 6903 return 0; 6904 6905 err = skb_cow_head(skb, 0); 6906 if (err < 0) 6907 return err; 6908 6909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6910 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6911 6912 if (first->protocol == htons(ETH_P_IP)) { 6913 struct iphdr *iph = ip_hdr(skb); 6914 iph->tot_len = 0; 6915 iph->check = 0; 6916 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6917 iph->daddr, 0, 6918 IPPROTO_TCP, 6919 0); 6920 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6921 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6922 IXGBE_TX_FLAGS_CSUM | 6923 IXGBE_TX_FLAGS_IPV4; 6924 } else if (skb_is_gso_v6(skb)) { 6925 ipv6_hdr(skb)->payload_len = 0; 6926 tcp_hdr(skb)->check = 6927 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6928 &ipv6_hdr(skb)->daddr, 6929 0, IPPROTO_TCP, 0); 6930 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6931 IXGBE_TX_FLAGS_CSUM; 6932 } 6933 6934 /* compute header lengths */ 6935 l4len = tcp_hdrlen(skb); 6936 *hdr_len = skb_transport_offset(skb) + l4len; 6937 6938 /* update gso size and bytecount with header size */ 6939 first->gso_segs = skb_shinfo(skb)->gso_segs; 6940 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6941 6942 /* mss_l4len_id: use 0 as index for TSO */ 6943 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6944 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6945 6946 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6947 vlan_macip_lens = skb_network_header_len(skb); 6948 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6949 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6950 6951 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6952 mss_l4len_idx); 6953 6954 return 1; 6955 } 6956 6957 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6958 struct ixgbe_tx_buffer *first) 6959 { 6960 struct sk_buff *skb = first->skb; 6961 u32 vlan_macip_lens = 0; 6962 u32 mss_l4len_idx = 0; 6963 u32 type_tucmd = 0; 6964 6965 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6966 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6967 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6968 return; 6969 vlan_macip_lens = skb_network_offset(skb) << 6970 IXGBE_ADVTXD_MACLEN_SHIFT; 6971 } else { 6972 u8 l4_hdr = 0; 6973 union { 6974 struct iphdr *ipv4; 6975 struct ipv6hdr *ipv6; 6976 u8 *raw; 6977 } network_hdr; 6978 union { 6979 struct tcphdr *tcphdr; 6980 u8 *raw; 6981 } transport_hdr; 6982 6983 if (skb->encapsulation) { 6984 network_hdr.raw = skb_inner_network_header(skb); 6985 transport_hdr.raw = skb_inner_transport_header(skb); 6986 vlan_macip_lens = skb_inner_network_offset(skb) << 6987 IXGBE_ADVTXD_MACLEN_SHIFT; 6988 } else { 6989 network_hdr.raw = skb_network_header(skb); 6990 transport_hdr.raw = skb_transport_header(skb); 6991 vlan_macip_lens = skb_network_offset(skb) << 6992 IXGBE_ADVTXD_MACLEN_SHIFT; 6993 } 6994 6995 /* use first 4 bits to determine IP version */ 6996 switch (network_hdr.ipv4->version) { 6997 case IPVERSION: 6998 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; 6999 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7000 l4_hdr = network_hdr.ipv4->protocol; 7001 break; 7002 case 6: 7003 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; 7004 l4_hdr = network_hdr.ipv6->nexthdr; 7005 break; 7006 default: 7007 if (unlikely(net_ratelimit())) { 7008 dev_warn(tx_ring->dev, 7009 "partial checksum but version=%d\n", 7010 network_hdr.ipv4->version); 7011 } 7012 } 7013 7014 switch (l4_hdr) { 7015 case IPPROTO_TCP: 7016 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 7017 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 7018 IXGBE_ADVTXD_L4LEN_SHIFT; 7019 break; 7020 case IPPROTO_SCTP: 7021 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7022 mss_l4len_idx = sizeof(struct sctphdr) << 7023 IXGBE_ADVTXD_L4LEN_SHIFT; 7024 break; 7025 case IPPROTO_UDP: 7026 mss_l4len_idx = sizeof(struct udphdr) << 7027 IXGBE_ADVTXD_L4LEN_SHIFT; 7028 break; 7029 default: 7030 if (unlikely(net_ratelimit())) { 7031 dev_warn(tx_ring->dev, 7032 "partial checksum but l4 proto=%x!\n", 7033 l4_hdr); 7034 } 7035 break; 7036 } 7037 7038 /* update TX checksum flag */ 7039 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7040 } 7041 7042 /* vlan_macip_lens: MACLEN, VLAN tag */ 7043 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7044 7045 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 7046 type_tucmd, mss_l4len_idx); 7047 } 7048 7049 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7050 ((_flag <= _result) ? \ 7051 ((u32)(_input & _flag) * (_result / _flag)) : \ 7052 ((u32)(_input & _flag) / (_flag / _result))) 7053 7054 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7055 { 7056 /* set type for advanced descriptor with frame checksum insertion */ 7057 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7058 IXGBE_ADVTXD_DCMD_DEXT | 7059 IXGBE_ADVTXD_DCMD_IFCS; 7060 7061 /* set HW vlan bit if vlan is present */ 7062 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7063 IXGBE_ADVTXD_DCMD_VLE); 7064 7065 /* set segmentation enable bits for TSO/FSO */ 7066 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7067 IXGBE_ADVTXD_DCMD_TSE); 7068 7069 /* set timestamp bit if present */ 7070 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7071 IXGBE_ADVTXD_MAC_TSTAMP); 7072 7073 /* insert frame checksum */ 7074 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7075 7076 return cmd_type; 7077 } 7078 7079 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7080 u32 tx_flags, unsigned int paylen) 7081 { 7082 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7083 7084 /* enable L4 checksum for TSO and TX checksum offload */ 7085 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7086 IXGBE_TX_FLAGS_CSUM, 7087 IXGBE_ADVTXD_POPTS_TXSM); 7088 7089 /* enble IPv4 checksum for TSO */ 7090 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7091 IXGBE_TX_FLAGS_IPV4, 7092 IXGBE_ADVTXD_POPTS_IXSM); 7093 7094 /* 7095 * Check Context must be set if Tx switch is enabled, which it 7096 * always is for case where virtual functions are running 7097 */ 7098 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7099 IXGBE_TX_FLAGS_CC, 7100 IXGBE_ADVTXD_CC); 7101 7102 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7103 } 7104 7105 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7106 { 7107 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7108 7109 /* Herbert's original patch had: 7110 * smp_mb__after_netif_stop_queue(); 7111 * but since that doesn't exist yet, just open code it. 7112 */ 7113 smp_mb(); 7114 7115 /* We need to check again in a case another CPU has just 7116 * made room available. 7117 */ 7118 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7119 return -EBUSY; 7120 7121 /* A reprieve! - use start_queue because it doesn't call schedule */ 7122 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7123 ++tx_ring->tx_stats.restart_queue; 7124 return 0; 7125 } 7126 7127 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7128 { 7129 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7130 return 0; 7131 7132 return __ixgbe_maybe_stop_tx(tx_ring, size); 7133 } 7134 7135 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7136 IXGBE_TXD_CMD_RS) 7137 7138 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7139 struct ixgbe_tx_buffer *first, 7140 const u8 hdr_len) 7141 { 7142 struct sk_buff *skb = first->skb; 7143 struct ixgbe_tx_buffer *tx_buffer; 7144 union ixgbe_adv_tx_desc *tx_desc; 7145 struct skb_frag_struct *frag; 7146 dma_addr_t dma; 7147 unsigned int data_len, size; 7148 u32 tx_flags = first->tx_flags; 7149 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7150 u16 i = tx_ring->next_to_use; 7151 7152 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7153 7154 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7155 7156 size = skb_headlen(skb); 7157 data_len = skb->data_len; 7158 7159 #ifdef IXGBE_FCOE 7160 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7161 if (data_len < sizeof(struct fcoe_crc_eof)) { 7162 size -= sizeof(struct fcoe_crc_eof) - data_len; 7163 data_len = 0; 7164 } else { 7165 data_len -= sizeof(struct fcoe_crc_eof); 7166 } 7167 } 7168 7169 #endif 7170 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7171 7172 tx_buffer = first; 7173 7174 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7175 if (dma_mapping_error(tx_ring->dev, dma)) 7176 goto dma_error; 7177 7178 /* record length, and DMA address */ 7179 dma_unmap_len_set(tx_buffer, len, size); 7180 dma_unmap_addr_set(tx_buffer, dma, dma); 7181 7182 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7183 7184 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7185 tx_desc->read.cmd_type_len = 7186 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7187 7188 i++; 7189 tx_desc++; 7190 if (i == tx_ring->count) { 7191 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7192 i = 0; 7193 } 7194 tx_desc->read.olinfo_status = 0; 7195 7196 dma += IXGBE_MAX_DATA_PER_TXD; 7197 size -= IXGBE_MAX_DATA_PER_TXD; 7198 7199 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7200 } 7201 7202 if (likely(!data_len)) 7203 break; 7204 7205 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7206 7207 i++; 7208 tx_desc++; 7209 if (i == tx_ring->count) { 7210 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7211 i = 0; 7212 } 7213 tx_desc->read.olinfo_status = 0; 7214 7215 #ifdef IXGBE_FCOE 7216 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7217 #else 7218 size = skb_frag_size(frag); 7219 #endif 7220 data_len -= size; 7221 7222 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7223 DMA_TO_DEVICE); 7224 7225 tx_buffer = &tx_ring->tx_buffer_info[i]; 7226 } 7227 7228 /* write last descriptor with RS and EOP bits */ 7229 cmd_type |= size | IXGBE_TXD_CMD; 7230 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7231 7232 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7233 7234 /* set the timestamp */ 7235 first->time_stamp = jiffies; 7236 7237 /* 7238 * Force memory writes to complete before letting h/w know there 7239 * are new descriptors to fetch. (Only applicable for weak-ordered 7240 * memory model archs, such as IA-64). 7241 * 7242 * We also need this memory barrier to make certain all of the 7243 * status bits have been updated before next_to_watch is written. 7244 */ 7245 wmb(); 7246 7247 /* set next_to_watch value indicating a packet is present */ 7248 first->next_to_watch = tx_desc; 7249 7250 i++; 7251 if (i == tx_ring->count) 7252 i = 0; 7253 7254 tx_ring->next_to_use = i; 7255 7256 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7257 7258 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7259 writel(i, tx_ring->tail); 7260 7261 /* we need this if more than one processor can write to our tail 7262 * at a time, it synchronizes IO on IA64/Altix systems 7263 */ 7264 mmiowb(); 7265 } 7266 7267 return; 7268 dma_error: 7269 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7270 7271 /* clear dma mappings for failed tx_buffer_info map */ 7272 for (;;) { 7273 tx_buffer = &tx_ring->tx_buffer_info[i]; 7274 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7275 if (tx_buffer == first) 7276 break; 7277 if (i == 0) 7278 i = tx_ring->count; 7279 i--; 7280 } 7281 7282 tx_ring->next_to_use = i; 7283 } 7284 7285 static void ixgbe_atr(struct ixgbe_ring *ring, 7286 struct ixgbe_tx_buffer *first) 7287 { 7288 struct ixgbe_q_vector *q_vector = ring->q_vector; 7289 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7290 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7291 union { 7292 unsigned char *network; 7293 struct iphdr *ipv4; 7294 struct ipv6hdr *ipv6; 7295 } hdr; 7296 struct tcphdr *th; 7297 struct sk_buff *skb; 7298 #ifdef CONFIG_IXGBE_VXLAN 7299 u8 encap = false; 7300 #endif /* CONFIG_IXGBE_VXLAN */ 7301 __be16 vlan_id; 7302 7303 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7304 if (!q_vector) 7305 return; 7306 7307 /* do nothing if sampling is disabled */ 7308 if (!ring->atr_sample_rate) 7309 return; 7310 7311 ring->atr_count++; 7312 7313 /* snag network header to get L4 type and address */ 7314 skb = first->skb; 7315 hdr.network = skb_network_header(skb); 7316 if (skb->encapsulation) { 7317 #ifdef CONFIG_IXGBE_VXLAN 7318 struct ixgbe_adapter *adapter = q_vector->adapter; 7319 7320 if (!adapter->vxlan_port) 7321 return; 7322 if (first->protocol != htons(ETH_P_IP) || 7323 hdr.ipv4->version != IPVERSION || 7324 hdr.ipv4->protocol != IPPROTO_UDP) { 7325 return; 7326 } 7327 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port) 7328 return; 7329 encap = true; 7330 hdr.network = skb_inner_network_header(skb); 7331 th = inner_tcp_hdr(skb); 7332 #else 7333 return; 7334 #endif /* CONFIG_IXGBE_VXLAN */ 7335 } else { 7336 /* Currently only IPv4/IPv6 with TCP is supported */ 7337 if ((first->protocol != htons(ETH_P_IPV6) || 7338 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7339 (first->protocol != htons(ETH_P_IP) || 7340 hdr.ipv4->protocol != IPPROTO_TCP)) 7341 return; 7342 th = tcp_hdr(skb); 7343 } 7344 7345 /* skip this packet since it is invalid or the socket is closing */ 7346 if (!th || th->fin) 7347 return; 7348 7349 /* sample on all syn packets or once every atr sample count */ 7350 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7351 return; 7352 7353 /* reset sample count */ 7354 ring->atr_count = 0; 7355 7356 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7357 7358 /* 7359 * src and dst are inverted, think how the receiver sees them 7360 * 7361 * The input is broken into two sections, a non-compressed section 7362 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7363 * is XORed together and stored in the compressed dword. 7364 */ 7365 input.formatted.vlan_id = vlan_id; 7366 7367 /* 7368 * since src port and flex bytes occupy the same word XOR them together 7369 * and write the value to source port portion of compressed dword 7370 */ 7371 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7372 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7373 else 7374 common.port.src ^= th->dest ^ first->protocol; 7375 common.port.dst ^= th->source; 7376 7377 if (first->protocol == htons(ETH_P_IP)) { 7378 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7379 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7380 } else { 7381 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7382 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7383 hdr.ipv6->saddr.s6_addr32[1] ^ 7384 hdr.ipv6->saddr.s6_addr32[2] ^ 7385 hdr.ipv6->saddr.s6_addr32[3] ^ 7386 hdr.ipv6->daddr.s6_addr32[0] ^ 7387 hdr.ipv6->daddr.s6_addr32[1] ^ 7388 hdr.ipv6->daddr.s6_addr32[2] ^ 7389 hdr.ipv6->daddr.s6_addr32[3]; 7390 } 7391 7392 #ifdef CONFIG_IXGBE_VXLAN 7393 if (encap) 7394 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 7395 #endif /* CONFIG_IXGBE_VXLAN */ 7396 7397 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7398 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7399 input, common, ring->queue_index); 7400 } 7401 7402 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7403 void *accel_priv, select_queue_fallback_t fallback) 7404 { 7405 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7406 #ifdef IXGBE_FCOE 7407 struct ixgbe_adapter *adapter; 7408 struct ixgbe_ring_feature *f; 7409 int txq; 7410 #endif 7411 7412 if (fwd_adapter) 7413 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7414 7415 #ifdef IXGBE_FCOE 7416 7417 /* 7418 * only execute the code below if protocol is FCoE 7419 * or FIP and we have FCoE enabled on the adapter 7420 */ 7421 switch (vlan_get_protocol(skb)) { 7422 case htons(ETH_P_FCOE): 7423 case htons(ETH_P_FIP): 7424 adapter = netdev_priv(dev); 7425 7426 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7427 break; 7428 default: 7429 return fallback(dev, skb); 7430 } 7431 7432 f = &adapter->ring_feature[RING_F_FCOE]; 7433 7434 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7435 smp_processor_id(); 7436 7437 while (txq >= f->indices) 7438 txq -= f->indices; 7439 7440 return txq + f->offset; 7441 #else 7442 return fallback(dev, skb); 7443 #endif 7444 } 7445 7446 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7447 struct ixgbe_adapter *adapter, 7448 struct ixgbe_ring *tx_ring) 7449 { 7450 struct ixgbe_tx_buffer *first; 7451 int tso; 7452 u32 tx_flags = 0; 7453 unsigned short f; 7454 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7455 __be16 protocol = skb->protocol; 7456 u8 hdr_len = 0; 7457 7458 /* 7459 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7460 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7461 * + 2 desc gap to keep tail from touching head, 7462 * + 1 desc for context descriptor, 7463 * otherwise try next time 7464 */ 7465 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7466 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7467 7468 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7469 tx_ring->tx_stats.tx_busy++; 7470 return NETDEV_TX_BUSY; 7471 } 7472 7473 /* record the location of the first descriptor for this packet */ 7474 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7475 first->skb = skb; 7476 first->bytecount = skb->len; 7477 first->gso_segs = 1; 7478 7479 /* if we have a HW VLAN tag being added default to the HW one */ 7480 if (skb_vlan_tag_present(skb)) { 7481 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7482 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7483 /* else if it is a SW VLAN check the next protocol and store the tag */ 7484 } else if (protocol == htons(ETH_P_8021Q)) { 7485 struct vlan_hdr *vhdr, _vhdr; 7486 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7487 if (!vhdr) 7488 goto out_drop; 7489 7490 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7491 IXGBE_TX_FLAGS_VLAN_SHIFT; 7492 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7493 } 7494 protocol = vlan_get_protocol(skb); 7495 7496 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7497 adapter->ptp_clock && 7498 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7499 &adapter->state)) { 7500 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7501 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7502 7503 /* schedule check for Tx timestamp */ 7504 adapter->ptp_tx_skb = skb_get(skb); 7505 adapter->ptp_tx_start = jiffies; 7506 schedule_work(&adapter->ptp_tx_work); 7507 } 7508 7509 skb_tx_timestamp(skb); 7510 7511 #ifdef CONFIG_PCI_IOV 7512 /* 7513 * Use the l2switch_enable flag - would be false if the DMA 7514 * Tx switch had been disabled. 7515 */ 7516 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7517 tx_flags |= IXGBE_TX_FLAGS_CC; 7518 7519 #endif 7520 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7521 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7522 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7523 (skb->priority != TC_PRIO_CONTROL))) { 7524 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7525 tx_flags |= (skb->priority & 0x7) << 7526 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7527 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7528 struct vlan_ethhdr *vhdr; 7529 7530 if (skb_cow_head(skb, 0)) 7531 goto out_drop; 7532 vhdr = (struct vlan_ethhdr *)skb->data; 7533 vhdr->h_vlan_TCI = htons(tx_flags >> 7534 IXGBE_TX_FLAGS_VLAN_SHIFT); 7535 } else { 7536 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7537 } 7538 } 7539 7540 /* record initial flags and protocol */ 7541 first->tx_flags = tx_flags; 7542 first->protocol = protocol; 7543 7544 #ifdef IXGBE_FCOE 7545 /* setup tx offload for FCoE */ 7546 if ((protocol == htons(ETH_P_FCOE)) && 7547 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7548 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7549 if (tso < 0) 7550 goto out_drop; 7551 7552 goto xmit_fcoe; 7553 } 7554 7555 #endif /* IXGBE_FCOE */ 7556 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7557 if (tso < 0) 7558 goto out_drop; 7559 else if (!tso) 7560 ixgbe_tx_csum(tx_ring, first); 7561 7562 /* add the ATR filter if ATR is on */ 7563 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7564 ixgbe_atr(tx_ring, first); 7565 7566 #ifdef IXGBE_FCOE 7567 xmit_fcoe: 7568 #endif /* IXGBE_FCOE */ 7569 ixgbe_tx_map(tx_ring, first, hdr_len); 7570 7571 return NETDEV_TX_OK; 7572 7573 out_drop: 7574 dev_kfree_skb_any(first->skb); 7575 first->skb = NULL; 7576 7577 return NETDEV_TX_OK; 7578 } 7579 7580 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7581 struct net_device *netdev, 7582 struct ixgbe_ring *ring) 7583 { 7584 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7585 struct ixgbe_ring *tx_ring; 7586 7587 /* 7588 * The minimum packet size for olinfo paylen is 17 so pad the skb 7589 * in order to meet this minimum size requirement. 7590 */ 7591 if (skb_put_padto(skb, 17)) 7592 return NETDEV_TX_OK; 7593 7594 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7595 7596 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7597 } 7598 7599 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7600 struct net_device *netdev) 7601 { 7602 return __ixgbe_xmit_frame(skb, netdev, NULL); 7603 } 7604 7605 /** 7606 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7607 * @netdev: network interface device structure 7608 * @p: pointer to an address structure 7609 * 7610 * Returns 0 on success, negative on failure 7611 **/ 7612 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7613 { 7614 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7615 struct ixgbe_hw *hw = &adapter->hw; 7616 struct sockaddr *addr = p; 7617 int ret; 7618 7619 if (!is_valid_ether_addr(addr->sa_data)) 7620 return -EADDRNOTAVAIL; 7621 7622 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7623 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7624 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7625 7626 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7627 return ret > 0 ? 0 : ret; 7628 } 7629 7630 static int 7631 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7632 { 7633 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7634 struct ixgbe_hw *hw = &adapter->hw; 7635 u16 value; 7636 int rc; 7637 7638 if (prtad != hw->phy.mdio.prtad) 7639 return -EINVAL; 7640 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7641 if (!rc) 7642 rc = value; 7643 return rc; 7644 } 7645 7646 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7647 u16 addr, u16 value) 7648 { 7649 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7650 struct ixgbe_hw *hw = &adapter->hw; 7651 7652 if (prtad != hw->phy.mdio.prtad) 7653 return -EINVAL; 7654 return hw->phy.ops.write_reg(hw, addr, devad, value); 7655 } 7656 7657 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7658 { 7659 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7660 7661 switch (cmd) { 7662 case SIOCSHWTSTAMP: 7663 return ixgbe_ptp_set_ts_config(adapter, req); 7664 case SIOCGHWTSTAMP: 7665 return ixgbe_ptp_get_ts_config(adapter, req); 7666 default: 7667 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7668 } 7669 } 7670 7671 /** 7672 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7673 * netdev->dev_addrs 7674 * @netdev: network interface device structure 7675 * 7676 * Returns non-zero on failure 7677 **/ 7678 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7679 { 7680 int err = 0; 7681 struct ixgbe_adapter *adapter = netdev_priv(dev); 7682 struct ixgbe_hw *hw = &adapter->hw; 7683 7684 if (is_valid_ether_addr(hw->mac.san_addr)) { 7685 rtnl_lock(); 7686 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7687 rtnl_unlock(); 7688 7689 /* update SAN MAC vmdq pool selection */ 7690 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7691 } 7692 return err; 7693 } 7694 7695 /** 7696 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7697 * netdev->dev_addrs 7698 * @netdev: network interface device structure 7699 * 7700 * Returns non-zero on failure 7701 **/ 7702 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7703 { 7704 int err = 0; 7705 struct ixgbe_adapter *adapter = netdev_priv(dev); 7706 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7707 7708 if (is_valid_ether_addr(mac->san_addr)) { 7709 rtnl_lock(); 7710 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7711 rtnl_unlock(); 7712 } 7713 return err; 7714 } 7715 7716 #ifdef CONFIG_NET_POLL_CONTROLLER 7717 /* 7718 * Polling 'interrupt' - used by things like netconsole to send skbs 7719 * without having to re-enable interrupts. It's not called while 7720 * the interrupt routine is executing. 7721 */ 7722 static void ixgbe_netpoll(struct net_device *netdev) 7723 { 7724 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7725 int i; 7726 7727 /* if interface is down do nothing */ 7728 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7729 return; 7730 7731 /* loop through and schedule all active queues */ 7732 for (i = 0; i < adapter->num_q_vectors; i++) 7733 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7734 } 7735 7736 #endif 7737 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7738 struct rtnl_link_stats64 *stats) 7739 { 7740 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7741 int i; 7742 7743 rcu_read_lock(); 7744 for (i = 0; i < adapter->num_rx_queues; i++) { 7745 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7746 u64 bytes, packets; 7747 unsigned int start; 7748 7749 if (ring) { 7750 do { 7751 start = u64_stats_fetch_begin_irq(&ring->syncp); 7752 packets = ring->stats.packets; 7753 bytes = ring->stats.bytes; 7754 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7755 stats->rx_packets += packets; 7756 stats->rx_bytes += bytes; 7757 } 7758 } 7759 7760 for (i = 0; i < adapter->num_tx_queues; i++) { 7761 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7762 u64 bytes, packets; 7763 unsigned int start; 7764 7765 if (ring) { 7766 do { 7767 start = u64_stats_fetch_begin_irq(&ring->syncp); 7768 packets = ring->stats.packets; 7769 bytes = ring->stats.bytes; 7770 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7771 stats->tx_packets += packets; 7772 stats->tx_bytes += bytes; 7773 } 7774 } 7775 rcu_read_unlock(); 7776 /* following stats updated by ixgbe_watchdog_task() */ 7777 stats->multicast = netdev->stats.multicast; 7778 stats->rx_errors = netdev->stats.rx_errors; 7779 stats->rx_length_errors = netdev->stats.rx_length_errors; 7780 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7781 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7782 return stats; 7783 } 7784 7785 #ifdef CONFIG_IXGBE_DCB 7786 /** 7787 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7788 * @adapter: pointer to ixgbe_adapter 7789 * @tc: number of traffic classes currently enabled 7790 * 7791 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7792 * 802.1Q priority maps to a packet buffer that exists. 7793 */ 7794 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7795 { 7796 struct ixgbe_hw *hw = &adapter->hw; 7797 u32 reg, rsave; 7798 int i; 7799 7800 /* 82598 have a static priority to TC mapping that can not 7801 * be changed so no validation is needed. 7802 */ 7803 if (hw->mac.type == ixgbe_mac_82598EB) 7804 return; 7805 7806 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7807 rsave = reg; 7808 7809 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7810 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7811 7812 /* If up2tc is out of bounds default to zero */ 7813 if (up2tc > tc) 7814 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7815 } 7816 7817 if (reg != rsave) 7818 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7819 7820 return; 7821 } 7822 7823 /** 7824 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7825 * @adapter: Pointer to adapter struct 7826 * 7827 * Populate the netdev user priority to tc map 7828 */ 7829 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7830 { 7831 struct net_device *dev = adapter->netdev; 7832 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7833 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7834 u8 prio; 7835 7836 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7837 u8 tc = 0; 7838 7839 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7840 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7841 else if (ets) 7842 tc = ets->prio_tc[prio]; 7843 7844 netdev_set_prio_tc_map(dev, prio, tc); 7845 } 7846 } 7847 7848 #endif /* CONFIG_IXGBE_DCB */ 7849 /** 7850 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7851 * 7852 * @netdev: net device to configure 7853 * @tc: number of traffic classes to enable 7854 */ 7855 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7856 { 7857 struct ixgbe_adapter *adapter = netdev_priv(dev); 7858 struct ixgbe_hw *hw = &adapter->hw; 7859 bool pools; 7860 7861 /* Hardware supports up to 8 traffic classes */ 7862 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 7863 return -EINVAL; 7864 7865 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 7866 return -EINVAL; 7867 7868 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7869 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7870 return -EBUSY; 7871 7872 /* Hardware has to reinitialize queues and interrupts to 7873 * match packet buffer alignment. Unfortunately, the 7874 * hardware is not flexible enough to do this dynamically. 7875 */ 7876 if (netif_running(dev)) 7877 ixgbe_close(dev); 7878 ixgbe_clear_interrupt_scheme(adapter); 7879 7880 #ifdef CONFIG_IXGBE_DCB 7881 if (tc) { 7882 netdev_set_num_tc(dev, tc); 7883 ixgbe_set_prio_tc_map(adapter); 7884 7885 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7886 7887 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7888 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7889 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7890 } 7891 } else { 7892 netdev_reset_tc(dev); 7893 7894 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7895 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7896 7897 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7898 7899 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7900 adapter->dcb_cfg.pfc_mode_enable = false; 7901 } 7902 7903 ixgbe_validate_rtr(adapter, tc); 7904 7905 #endif /* CONFIG_IXGBE_DCB */ 7906 ixgbe_init_interrupt_scheme(adapter); 7907 7908 if (netif_running(dev)) 7909 return ixgbe_open(dev); 7910 7911 return 0; 7912 } 7913 7914 #ifdef CONFIG_PCI_IOV 7915 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7916 { 7917 struct net_device *netdev = adapter->netdev; 7918 7919 rtnl_lock(); 7920 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7921 rtnl_unlock(); 7922 } 7923 7924 #endif 7925 void ixgbe_do_reset(struct net_device *netdev) 7926 { 7927 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7928 7929 if (netif_running(netdev)) 7930 ixgbe_reinit_locked(adapter); 7931 else 7932 ixgbe_reset(adapter); 7933 } 7934 7935 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7936 netdev_features_t features) 7937 { 7938 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7939 7940 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7941 if (!(features & NETIF_F_RXCSUM)) 7942 features &= ~NETIF_F_LRO; 7943 7944 /* Turn off LRO if not RSC capable */ 7945 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7946 features &= ~NETIF_F_LRO; 7947 7948 return features; 7949 } 7950 7951 static int ixgbe_set_features(struct net_device *netdev, 7952 netdev_features_t features) 7953 { 7954 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7955 netdev_features_t changed = netdev->features ^ features; 7956 bool need_reset = false; 7957 7958 /* Make sure RSC matches LRO, reset if change */ 7959 if (!(features & NETIF_F_LRO)) { 7960 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7961 need_reset = true; 7962 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7963 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7964 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7965 if (adapter->rx_itr_setting == 1 || 7966 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7967 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7968 need_reset = true; 7969 } else if ((changed ^ features) & NETIF_F_LRO) { 7970 e_info(probe, "rx-usecs set too low, " 7971 "disabling RSC\n"); 7972 } 7973 } 7974 7975 /* 7976 * Check if Flow Director n-tuple support was enabled or disabled. If 7977 * the state changed, we need to reset. 7978 */ 7979 switch (features & NETIF_F_NTUPLE) { 7980 case NETIF_F_NTUPLE: 7981 /* turn off ATR, enable perfect filters and reset */ 7982 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7983 need_reset = true; 7984 7985 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7986 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7987 break; 7988 default: 7989 /* turn off perfect filters, enable ATR and reset */ 7990 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 7991 need_reset = true; 7992 7993 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7994 7995 /* We cannot enable ATR if SR-IOV is enabled */ 7996 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7997 break; 7998 7999 /* We cannot enable ATR if we have 2 or more traffic classes */ 8000 if (netdev_get_num_tc(netdev) > 1) 8001 break; 8002 8003 /* We cannot enable ATR if RSS is disabled */ 8004 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 8005 break; 8006 8007 /* A sample rate of 0 indicates ATR disabled */ 8008 if (!adapter->atr_sample_rate) 8009 break; 8010 8011 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 8012 break; 8013 } 8014 8015 if (features & NETIF_F_HW_VLAN_CTAG_RX) 8016 ixgbe_vlan_strip_enable(adapter); 8017 else 8018 ixgbe_vlan_strip_disable(adapter); 8019 8020 if (changed & NETIF_F_RXALL) 8021 need_reset = true; 8022 8023 netdev->features = features; 8024 8025 #ifdef CONFIG_IXGBE_VXLAN 8026 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 8027 if (features & NETIF_F_RXCSUM) 8028 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; 8029 else 8030 ixgbe_clear_vxlan_port(adapter); 8031 } 8032 #endif /* CONFIG_IXGBE_VXLAN */ 8033 8034 if (need_reset) 8035 ixgbe_do_reset(netdev); 8036 8037 return 0; 8038 } 8039 8040 #ifdef CONFIG_IXGBE_VXLAN 8041 /** 8042 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up 8043 * @dev: The port's netdev 8044 * @sa_family: Socket Family that VXLAN is notifiying us about 8045 * @port: New UDP port number that VXLAN started listening to 8046 **/ 8047 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, 8048 __be16 port) 8049 { 8050 struct ixgbe_adapter *adapter = netdev_priv(dev); 8051 struct ixgbe_hw *hw = &adapter->hw; 8052 u16 new_port = ntohs(port); 8053 8054 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8055 return; 8056 8057 if (sa_family == AF_INET6) 8058 return; 8059 8060 if (adapter->vxlan_port == new_port) 8061 return; 8062 8063 if (adapter->vxlan_port) { 8064 netdev_info(dev, 8065 "Hit Max num of VXLAN ports, not adding port %d\n", 8066 new_port); 8067 return; 8068 } 8069 8070 adapter->vxlan_port = new_port; 8071 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port); 8072 } 8073 8074 /** 8075 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away 8076 * @dev: The port's netdev 8077 * @sa_family: Socket Family that VXLAN is notifying us about 8078 * @port: UDP port number that VXLAN stopped listening to 8079 **/ 8080 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, 8081 __be16 port) 8082 { 8083 struct ixgbe_adapter *adapter = netdev_priv(dev); 8084 u16 new_port = ntohs(port); 8085 8086 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8087 return; 8088 8089 if (sa_family == AF_INET6) 8090 return; 8091 8092 if (adapter->vxlan_port != new_port) { 8093 netdev_info(dev, "Port %d was not found, not deleting\n", 8094 new_port); 8095 return; 8096 } 8097 8098 ixgbe_clear_vxlan_port(adapter); 8099 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; 8100 } 8101 #endif /* CONFIG_IXGBE_VXLAN */ 8102 8103 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 8104 struct net_device *dev, 8105 const unsigned char *addr, u16 vid, 8106 u16 flags) 8107 { 8108 /* guarantee we can provide a unique filter for the unicast address */ 8109 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 8110 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 8111 return -ENOMEM; 8112 } 8113 8114 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 8115 } 8116 8117 /** 8118 * ixgbe_configure_bridge_mode - set various bridge modes 8119 * @adapter - the private structure 8120 * @mode - requested bridge mode 8121 * 8122 * Configure some settings require for various bridge modes. 8123 **/ 8124 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 8125 __u16 mode) 8126 { 8127 struct ixgbe_hw *hw = &adapter->hw; 8128 unsigned int p, num_pools; 8129 u32 vmdctl; 8130 8131 switch (mode) { 8132 case BRIDGE_MODE_VEPA: 8133 /* disable Tx loopback, rely on switch hairpin mode */ 8134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 8135 8136 /* must enable Rx switching replication to allow multicast 8137 * packet reception on all VFs, and to enable source address 8138 * pruning. 8139 */ 8140 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 8141 vmdctl |= IXGBE_VT_CTL_REPLEN; 8142 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 8143 8144 /* enable Rx source address pruning. Note, this requires 8145 * replication to be enabled or else it does nothing. 8146 */ 8147 num_pools = adapter->num_vfs + adapter->num_rx_pools; 8148 for (p = 0; p < num_pools; p++) { 8149 if (hw->mac.ops.set_source_address_pruning) 8150 hw->mac.ops.set_source_address_pruning(hw, 8151 true, 8152 p); 8153 } 8154 break; 8155 case BRIDGE_MODE_VEB: 8156 /* enable Tx loopback for internal VF/PF communication */ 8157 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 8158 IXGBE_PFDTXGSWC_VT_LBEN); 8159 8160 /* disable Rx switching replication unless we have SR-IOV 8161 * virtual functions 8162 */ 8163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 8164 if (!adapter->num_vfs) 8165 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 8166 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 8167 8168 /* disable Rx source address pruning, since we don't expect to 8169 * be receiving external loopback of our transmitted frames. 8170 */ 8171 num_pools = adapter->num_vfs + adapter->num_rx_pools; 8172 for (p = 0; p < num_pools; p++) { 8173 if (hw->mac.ops.set_source_address_pruning) 8174 hw->mac.ops.set_source_address_pruning(hw, 8175 false, 8176 p); 8177 } 8178 break; 8179 default: 8180 return -EINVAL; 8181 } 8182 8183 adapter->bridge_mode = mode; 8184 8185 e_info(drv, "enabling bridge mode: %s\n", 8186 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 8187 8188 return 0; 8189 } 8190 8191 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 8192 struct nlmsghdr *nlh, u16 flags) 8193 { 8194 struct ixgbe_adapter *adapter = netdev_priv(dev); 8195 struct nlattr *attr, *br_spec; 8196 int rem; 8197 8198 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 8199 return -EOPNOTSUPP; 8200 8201 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 8202 if (!br_spec) 8203 return -EINVAL; 8204 8205 nla_for_each_nested(attr, br_spec, rem) { 8206 int status; 8207 __u16 mode; 8208 8209 if (nla_type(attr) != IFLA_BRIDGE_MODE) 8210 continue; 8211 8212 if (nla_len(attr) < sizeof(mode)) 8213 return -EINVAL; 8214 8215 mode = nla_get_u16(attr); 8216 status = ixgbe_configure_bridge_mode(adapter, mode); 8217 if (status) 8218 return status; 8219 8220 break; 8221 } 8222 8223 return 0; 8224 } 8225 8226 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 8227 struct net_device *dev, 8228 u32 filter_mask, int nlflags) 8229 { 8230 struct ixgbe_adapter *adapter = netdev_priv(dev); 8231 8232 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 8233 return 0; 8234 8235 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 8236 adapter->bridge_mode, 0, 0, nlflags, 8237 filter_mask, NULL); 8238 } 8239 8240 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 8241 { 8242 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 8243 struct ixgbe_adapter *adapter = netdev_priv(pdev); 8244 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 8245 unsigned int limit; 8246 int pool, err; 8247 8248 /* Hardware has a limited number of available pools. Each VF, and the 8249 * PF require a pool. Check to ensure we don't attempt to use more 8250 * then the available number of pools. 8251 */ 8252 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 8253 return ERR_PTR(-EINVAL); 8254 8255 #ifdef CONFIG_RPS 8256 if (vdev->num_rx_queues != vdev->num_tx_queues) { 8257 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 8258 vdev->name); 8259 return ERR_PTR(-EINVAL); 8260 } 8261 #endif 8262 /* Check for hardware restriction on number of rx/tx queues */ 8263 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 8264 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 8265 netdev_info(pdev, 8266 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 8267 pdev->name); 8268 return ERR_PTR(-EINVAL); 8269 } 8270 8271 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8272 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 8273 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 8274 return ERR_PTR(-EBUSY); 8275 8276 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 8277 if (!fwd_adapter) 8278 return ERR_PTR(-ENOMEM); 8279 8280 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 8281 adapter->num_rx_pools++; 8282 set_bit(pool, &adapter->fwd_bitmask); 8283 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8284 8285 /* Enable VMDq flag so device will be set in VM mode */ 8286 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 8287 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8288 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 8289 8290 /* Force reinit of ring allocation with VMDQ enabled */ 8291 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8292 if (err) 8293 goto fwd_add_err; 8294 fwd_adapter->pool = pool; 8295 fwd_adapter->real_adapter = adapter; 8296 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 8297 if (err) 8298 goto fwd_add_err; 8299 netif_tx_start_all_queues(vdev); 8300 return fwd_adapter; 8301 fwd_add_err: 8302 /* unwind counter and free adapter struct */ 8303 netdev_info(pdev, 8304 "%s: dfwd hardware acceleration failed\n", vdev->name); 8305 clear_bit(pool, &adapter->fwd_bitmask); 8306 adapter->num_rx_pools--; 8307 kfree(fwd_adapter); 8308 return ERR_PTR(err); 8309 } 8310 8311 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 8312 { 8313 struct ixgbe_fwd_adapter *fwd_adapter = priv; 8314 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 8315 unsigned int limit; 8316 8317 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 8318 adapter->num_rx_pools--; 8319 8320 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8321 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8322 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 8323 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8324 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 8325 fwd_adapter->pool, adapter->num_rx_pools, 8326 fwd_adapter->rx_base_queue, 8327 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 8328 adapter->fwd_bitmask); 8329 kfree(fwd_adapter); 8330 } 8331 8332 #define IXGBE_MAX_TUNNEL_HDR_LEN 80 8333 static netdev_features_t 8334 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 8335 netdev_features_t features) 8336 { 8337 if (!skb->encapsulation) 8338 return features; 8339 8340 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 8341 IXGBE_MAX_TUNNEL_HDR_LEN)) 8342 return features & ~NETIF_F_ALL_CSUM; 8343 8344 return features; 8345 } 8346 8347 static const struct net_device_ops ixgbe_netdev_ops = { 8348 .ndo_open = ixgbe_open, 8349 .ndo_stop = ixgbe_close, 8350 .ndo_start_xmit = ixgbe_xmit_frame, 8351 .ndo_select_queue = ixgbe_select_queue, 8352 .ndo_set_rx_mode = ixgbe_set_rx_mode, 8353 .ndo_validate_addr = eth_validate_addr, 8354 .ndo_set_mac_address = ixgbe_set_mac, 8355 .ndo_change_mtu = ixgbe_change_mtu, 8356 .ndo_tx_timeout = ixgbe_tx_timeout, 8357 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 8358 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 8359 .ndo_do_ioctl = ixgbe_ioctl, 8360 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 8361 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 8362 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 8363 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 8364 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 8365 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 8366 .ndo_get_stats64 = ixgbe_get_stats64, 8367 #ifdef CONFIG_IXGBE_DCB 8368 .ndo_setup_tc = ixgbe_setup_tc, 8369 #endif 8370 #ifdef CONFIG_NET_POLL_CONTROLLER 8371 .ndo_poll_controller = ixgbe_netpoll, 8372 #endif 8373 #ifdef CONFIG_NET_RX_BUSY_POLL 8374 .ndo_busy_poll = ixgbe_low_latency_recv, 8375 #endif 8376 #ifdef IXGBE_FCOE 8377 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 8378 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 8379 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 8380 .ndo_fcoe_enable = ixgbe_fcoe_enable, 8381 .ndo_fcoe_disable = ixgbe_fcoe_disable, 8382 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 8383 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 8384 #endif /* IXGBE_FCOE */ 8385 .ndo_set_features = ixgbe_set_features, 8386 .ndo_fix_features = ixgbe_fix_features, 8387 .ndo_fdb_add = ixgbe_ndo_fdb_add, 8388 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 8389 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 8390 .ndo_dfwd_add_station = ixgbe_fwd_add, 8391 .ndo_dfwd_del_station = ixgbe_fwd_del, 8392 #ifdef CONFIG_IXGBE_VXLAN 8393 .ndo_add_vxlan_port = ixgbe_add_vxlan_port, 8394 .ndo_del_vxlan_port = ixgbe_del_vxlan_port, 8395 #endif /* CONFIG_IXGBE_VXLAN */ 8396 .ndo_features_check = ixgbe_features_check, 8397 }; 8398 8399 /** 8400 * ixgbe_enumerate_functions - Get the number of ports this device has 8401 * @adapter: adapter structure 8402 * 8403 * This function enumerates the phsyical functions co-located on a single slot, 8404 * in order to determine how many ports a device has. This is most useful in 8405 * determining the required GT/s of PCIe bandwidth necessary for optimal 8406 * performance. 8407 **/ 8408 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 8409 { 8410 struct pci_dev *entry, *pdev = adapter->pdev; 8411 int physfns = 0; 8412 8413 /* Some cards can not use the generic count PCIe functions method, 8414 * because they are behind a parent switch, so we hardcode these with 8415 * the correct number of functions. 8416 */ 8417 if (ixgbe_pcie_from_parent(&adapter->hw)) 8418 physfns = 4; 8419 8420 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8421 /* don't count virtual functions */ 8422 if (entry->is_virtfn) 8423 continue; 8424 8425 /* When the devices on the bus don't all match our device ID, 8426 * we can't reliably determine the correct number of 8427 * functions. This can occur if a function has been direct 8428 * attached to a virtual machine using VT-d, for example. In 8429 * this case, simply return -1 to indicate this. 8430 */ 8431 if ((entry->vendor != pdev->vendor) || 8432 (entry->device != pdev->device)) 8433 return -1; 8434 8435 physfns++; 8436 } 8437 8438 return physfns; 8439 } 8440 8441 /** 8442 * ixgbe_wol_supported - Check whether device supports WoL 8443 * @hw: hw specific details 8444 * @device_id: the device ID 8445 * @subdev_id: the subsystem device ID 8446 * 8447 * This function is used by probe and ethtool to determine 8448 * which devices have WoL support 8449 * 8450 **/ 8451 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8452 u16 subdevice_id) 8453 { 8454 struct ixgbe_hw *hw = &adapter->hw; 8455 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8456 int is_wol_supported = 0; 8457 8458 switch (device_id) { 8459 case IXGBE_DEV_ID_82599_SFP: 8460 /* Only these subdevices could supports WOL */ 8461 switch (subdevice_id) { 8462 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8463 case IXGBE_SUBDEV_ID_82599_560FLR: 8464 /* only support first port */ 8465 if (hw->bus.func != 0) 8466 break; 8467 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8468 case IXGBE_SUBDEV_ID_82599_SFP: 8469 case IXGBE_SUBDEV_ID_82599_RNDC: 8470 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8471 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8472 is_wol_supported = 1; 8473 break; 8474 } 8475 break; 8476 case IXGBE_DEV_ID_82599EN_SFP: 8477 /* Only this subdevice supports WOL */ 8478 switch (subdevice_id) { 8479 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8480 is_wol_supported = 1; 8481 break; 8482 } 8483 break; 8484 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8485 /* All except this subdevice support WOL */ 8486 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8487 is_wol_supported = 1; 8488 break; 8489 case IXGBE_DEV_ID_82599_KX4: 8490 is_wol_supported = 1; 8491 break; 8492 case IXGBE_DEV_ID_X540T: 8493 case IXGBE_DEV_ID_X540T1: 8494 case IXGBE_DEV_ID_X550T: 8495 case IXGBE_DEV_ID_X550EM_X_KX4: 8496 case IXGBE_DEV_ID_X550EM_X_KR: 8497 case IXGBE_DEV_ID_X550EM_X_10G_T: 8498 /* check eeprom to see if enabled wol */ 8499 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8500 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8501 (hw->bus.func == 0))) { 8502 is_wol_supported = 1; 8503 } 8504 break; 8505 } 8506 8507 return is_wol_supported; 8508 } 8509 8510 /** 8511 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8512 * @adapter: Pointer to adapter struct 8513 */ 8514 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8515 { 8516 #ifdef CONFIG_OF 8517 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8518 struct ixgbe_hw *hw = &adapter->hw; 8519 const unsigned char *addr; 8520 8521 addr = of_get_mac_address(dp); 8522 if (addr) { 8523 ether_addr_copy(hw->mac.perm_addr, addr); 8524 return; 8525 } 8526 #endif /* CONFIG_OF */ 8527 8528 #ifdef CONFIG_SPARC 8529 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8530 #endif /* CONFIG_SPARC */ 8531 } 8532 8533 /** 8534 * ixgbe_probe - Device Initialization Routine 8535 * @pdev: PCI device information struct 8536 * @ent: entry in ixgbe_pci_tbl 8537 * 8538 * Returns 0 on success, negative on failure 8539 * 8540 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8541 * The OS initialization, configuring of the adapter private structure, 8542 * and a hardware reset occur. 8543 **/ 8544 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8545 { 8546 struct net_device *netdev; 8547 struct ixgbe_adapter *adapter = NULL; 8548 struct ixgbe_hw *hw; 8549 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8550 int i, err, pci_using_dac, expected_gts; 8551 unsigned int indices = MAX_TX_QUEUES; 8552 u8 part_str[IXGBE_PBANUM_LENGTH]; 8553 bool disable_dev = false; 8554 #ifdef IXGBE_FCOE 8555 u16 device_caps; 8556 #endif 8557 u32 eec; 8558 8559 /* Catch broken hardware that put the wrong VF device ID in 8560 * the PCIe SR-IOV capability. 8561 */ 8562 if (pdev->is_virtfn) { 8563 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8564 pci_name(pdev), pdev->vendor, pdev->device); 8565 return -EINVAL; 8566 } 8567 8568 err = pci_enable_device_mem(pdev); 8569 if (err) 8570 return err; 8571 8572 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8573 pci_using_dac = 1; 8574 } else { 8575 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8576 if (err) { 8577 dev_err(&pdev->dev, 8578 "No usable DMA configuration, aborting\n"); 8579 goto err_dma; 8580 } 8581 pci_using_dac = 0; 8582 } 8583 8584 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8585 IORESOURCE_MEM), ixgbe_driver_name); 8586 if (err) { 8587 dev_err(&pdev->dev, 8588 "pci_request_selected_regions failed 0x%x\n", err); 8589 goto err_pci_reg; 8590 } 8591 8592 pci_enable_pcie_error_reporting(pdev); 8593 8594 pci_set_master(pdev); 8595 pci_save_state(pdev); 8596 8597 if (ii->mac == ixgbe_mac_82598EB) { 8598 #ifdef CONFIG_IXGBE_DCB 8599 /* 8 TC w/ 4 queues per TC */ 8600 indices = 4 * MAX_TRAFFIC_CLASS; 8601 #else 8602 indices = IXGBE_MAX_RSS_INDICES; 8603 #endif 8604 } 8605 8606 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8607 if (!netdev) { 8608 err = -ENOMEM; 8609 goto err_alloc_etherdev; 8610 } 8611 8612 SET_NETDEV_DEV(netdev, &pdev->dev); 8613 8614 adapter = netdev_priv(netdev); 8615 8616 adapter->netdev = netdev; 8617 adapter->pdev = pdev; 8618 hw = &adapter->hw; 8619 hw->back = adapter; 8620 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8621 8622 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8623 pci_resource_len(pdev, 0)); 8624 adapter->io_addr = hw->hw_addr; 8625 if (!hw->hw_addr) { 8626 err = -EIO; 8627 goto err_ioremap; 8628 } 8629 8630 netdev->netdev_ops = &ixgbe_netdev_ops; 8631 ixgbe_set_ethtool_ops(netdev); 8632 netdev->watchdog_timeo = 5 * HZ; 8633 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8634 8635 /* Setup hw api */ 8636 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8637 hw->mac.type = ii->mac; 8638 hw->mvals = ii->mvals; 8639 8640 /* EEPROM */ 8641 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8642 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 8643 if (ixgbe_removed(hw->hw_addr)) { 8644 err = -EIO; 8645 goto err_ioremap; 8646 } 8647 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8648 if (!(eec & (1 << 8))) 8649 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8650 8651 /* PHY */ 8652 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8653 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8654 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8655 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8656 hw->phy.mdio.mmds = 0; 8657 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8658 hw->phy.mdio.dev = netdev; 8659 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8660 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8661 8662 ii->get_invariants(hw); 8663 8664 /* setup the private structure */ 8665 err = ixgbe_sw_init(adapter); 8666 if (err) 8667 goto err_sw_init; 8668 8669 /* Make it possible the adapter to be woken up via WOL */ 8670 switch (adapter->hw.mac.type) { 8671 case ixgbe_mac_82599EB: 8672 case ixgbe_mac_X540: 8673 case ixgbe_mac_X550: 8674 case ixgbe_mac_X550EM_x: 8675 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8676 break; 8677 default: 8678 break; 8679 } 8680 8681 /* 8682 * If there is a fan on this device and it has failed log the 8683 * failure. 8684 */ 8685 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8686 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8687 if (esdp & IXGBE_ESDP_SDP1) 8688 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8689 } 8690 8691 if (allow_unsupported_sfp) 8692 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8693 8694 /* reset_hw fills in the perm_addr as well */ 8695 hw->phy.reset_if_overtemp = true; 8696 err = hw->mac.ops.reset_hw(hw); 8697 hw->phy.reset_if_overtemp = false; 8698 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8699 hw->mac.type == ixgbe_mac_82598EB) { 8700 err = 0; 8701 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8702 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8703 e_dev_err("Reload the driver after installing a supported module.\n"); 8704 goto err_sw_init; 8705 } else if (err) { 8706 e_dev_err("HW Init failed: %d\n", err); 8707 goto err_sw_init; 8708 } 8709 8710 #ifdef CONFIG_PCI_IOV 8711 /* SR-IOV not supported on the 82598 */ 8712 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8713 goto skip_sriov; 8714 /* Mailbox */ 8715 ixgbe_init_mbx_params_pf(hw); 8716 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8717 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8718 ixgbe_enable_sriov(adapter); 8719 skip_sriov: 8720 8721 #endif 8722 netdev->features = NETIF_F_SG | 8723 NETIF_F_IP_CSUM | 8724 NETIF_F_IPV6_CSUM | 8725 NETIF_F_HW_VLAN_CTAG_TX | 8726 NETIF_F_HW_VLAN_CTAG_RX | 8727 NETIF_F_TSO | 8728 NETIF_F_TSO6 | 8729 NETIF_F_RXHASH | 8730 NETIF_F_RXCSUM; 8731 8732 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8733 8734 switch (adapter->hw.mac.type) { 8735 case ixgbe_mac_82599EB: 8736 case ixgbe_mac_X540: 8737 case ixgbe_mac_X550: 8738 case ixgbe_mac_X550EM_x: 8739 netdev->features |= NETIF_F_SCTP_CSUM; 8740 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8741 NETIF_F_NTUPLE; 8742 break; 8743 default: 8744 break; 8745 } 8746 8747 netdev->hw_features |= NETIF_F_RXALL; 8748 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 8749 8750 netdev->vlan_features |= NETIF_F_TSO; 8751 netdev->vlan_features |= NETIF_F_TSO6; 8752 netdev->vlan_features |= NETIF_F_IP_CSUM; 8753 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8754 netdev->vlan_features |= NETIF_F_SG; 8755 8756 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 8757 NETIF_F_IPV6_CSUM; 8758 8759 netdev->priv_flags |= IFF_UNICAST_FLT; 8760 netdev->priv_flags |= IFF_SUPP_NOFCS; 8761 8762 #ifdef CONFIG_IXGBE_VXLAN 8763 switch (adapter->hw.mac.type) { 8764 case ixgbe_mac_X550: 8765 case ixgbe_mac_X550EM_x: 8766 netdev->hw_enc_features |= NETIF_F_RXCSUM | 8767 NETIF_F_IP_CSUM | 8768 NETIF_F_IPV6_CSUM; 8769 break; 8770 default: 8771 break; 8772 } 8773 #endif /* CONFIG_IXGBE_VXLAN */ 8774 8775 #ifdef CONFIG_IXGBE_DCB 8776 netdev->dcbnl_ops = &dcbnl_ops; 8777 #endif 8778 8779 #ifdef IXGBE_FCOE 8780 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8781 unsigned int fcoe_l; 8782 8783 if (hw->mac.ops.get_device_caps) { 8784 hw->mac.ops.get_device_caps(hw, &device_caps); 8785 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8786 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8787 } 8788 8789 8790 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8791 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8792 8793 netdev->features |= NETIF_F_FSO | 8794 NETIF_F_FCOE_CRC; 8795 8796 netdev->vlan_features |= NETIF_F_FSO | 8797 NETIF_F_FCOE_CRC | 8798 NETIF_F_FCOE_MTU; 8799 } 8800 #endif /* IXGBE_FCOE */ 8801 if (pci_using_dac) { 8802 netdev->features |= NETIF_F_HIGHDMA; 8803 netdev->vlan_features |= NETIF_F_HIGHDMA; 8804 } 8805 8806 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8807 netdev->hw_features |= NETIF_F_LRO; 8808 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8809 netdev->features |= NETIF_F_LRO; 8810 8811 /* make sure the EEPROM is good */ 8812 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8813 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8814 err = -EIO; 8815 goto err_sw_init; 8816 } 8817 8818 ixgbe_get_platform_mac_addr(adapter); 8819 8820 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8821 8822 if (!is_valid_ether_addr(netdev->dev_addr)) { 8823 e_dev_err("invalid MAC address\n"); 8824 err = -EIO; 8825 goto err_sw_init; 8826 } 8827 8828 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8829 8830 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8831 (unsigned long) adapter); 8832 8833 if (ixgbe_removed(hw->hw_addr)) { 8834 err = -EIO; 8835 goto err_sw_init; 8836 } 8837 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8838 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8839 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8840 8841 err = ixgbe_init_interrupt_scheme(adapter); 8842 if (err) 8843 goto err_sw_init; 8844 8845 /* WOL not supported for all devices */ 8846 adapter->wol = 0; 8847 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8848 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8849 pdev->subsystem_device); 8850 if (hw->wol_enabled) 8851 adapter->wol = IXGBE_WUFC_MAG; 8852 8853 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8854 8855 /* save off EEPROM version number */ 8856 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8857 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8858 8859 /* pick up the PCI bus settings for reporting later */ 8860 if (ixgbe_pcie_from_parent(hw)) 8861 ixgbe_get_parent_bus_info(adapter); 8862 else 8863 hw->mac.ops.get_bus_info(hw); 8864 8865 /* calculate the expected PCIe bandwidth required for optimal 8866 * performance. Note that some older parts will never have enough 8867 * bandwidth due to being older generation PCIe parts. We clamp these 8868 * parts to ensure no warning is displayed if it can't be fixed. 8869 */ 8870 switch (hw->mac.type) { 8871 case ixgbe_mac_82598EB: 8872 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8873 break; 8874 default: 8875 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8876 break; 8877 } 8878 8879 /* don't check link if we failed to enumerate functions */ 8880 if (expected_gts > 0) 8881 ixgbe_check_minimum_link(adapter, expected_gts); 8882 8883 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8884 if (err) 8885 strlcpy(part_str, "Unknown", sizeof(part_str)); 8886 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8887 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8888 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8889 part_str); 8890 else 8891 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8892 hw->mac.type, hw->phy.type, part_str); 8893 8894 e_dev_info("%pM\n", netdev->dev_addr); 8895 8896 /* reset the hardware with the new settings */ 8897 err = hw->mac.ops.start_hw(hw); 8898 if (err == IXGBE_ERR_EEPROM_VERSION) { 8899 /* We are running on a pre-production device, log a warning */ 8900 e_dev_warn("This device is a pre-production adapter/LOM. " 8901 "Please be aware there may be issues associated " 8902 "with your hardware. If you are experiencing " 8903 "problems please contact your Intel or hardware " 8904 "representative who provided you with this " 8905 "hardware.\n"); 8906 } 8907 strcpy(netdev->name, "eth%d"); 8908 err = register_netdev(netdev); 8909 if (err) 8910 goto err_register; 8911 8912 pci_set_drvdata(pdev, adapter); 8913 8914 /* power down the optics for 82599 SFP+ fiber */ 8915 if (hw->mac.ops.disable_tx_laser) 8916 hw->mac.ops.disable_tx_laser(hw); 8917 8918 /* carrier off reporting is important to ethtool even BEFORE open */ 8919 netif_carrier_off(netdev); 8920 8921 #ifdef CONFIG_IXGBE_DCA 8922 if (dca_add_requester(&pdev->dev) == 0) { 8923 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8924 ixgbe_setup_dca(adapter); 8925 } 8926 #endif 8927 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8928 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8929 for (i = 0; i < adapter->num_vfs; i++) 8930 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8931 } 8932 8933 /* firmware requires driver version to be 0xFFFFFFFF 8934 * since os does not support feature 8935 */ 8936 if (hw->mac.ops.set_fw_drv_ver) 8937 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8938 0xFF); 8939 8940 /* add san mac addr to netdev */ 8941 ixgbe_add_sanmac_netdev(netdev); 8942 8943 e_dev_info("%s\n", ixgbe_default_device_descr); 8944 8945 #ifdef CONFIG_IXGBE_HWMON 8946 if (ixgbe_sysfs_init(adapter)) 8947 e_err(probe, "failed to allocate sysfs resources\n"); 8948 #endif /* CONFIG_IXGBE_HWMON */ 8949 8950 ixgbe_dbg_adapter_init(adapter); 8951 8952 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8953 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8954 hw->mac.ops.setup_link(hw, 8955 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8956 true); 8957 8958 return 0; 8959 8960 err_register: 8961 ixgbe_release_hw_control(adapter); 8962 ixgbe_clear_interrupt_scheme(adapter); 8963 err_sw_init: 8964 ixgbe_disable_sriov(adapter); 8965 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8966 iounmap(adapter->io_addr); 8967 kfree(adapter->mac_table); 8968 err_ioremap: 8969 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8970 free_netdev(netdev); 8971 err_alloc_etherdev: 8972 pci_release_selected_regions(pdev, 8973 pci_select_bars(pdev, IORESOURCE_MEM)); 8974 err_pci_reg: 8975 err_dma: 8976 if (!adapter || disable_dev) 8977 pci_disable_device(pdev); 8978 return err; 8979 } 8980 8981 /** 8982 * ixgbe_remove - Device Removal Routine 8983 * @pdev: PCI device information struct 8984 * 8985 * ixgbe_remove is called by the PCI subsystem to alert the driver 8986 * that it should release a PCI device. The could be caused by a 8987 * Hot-Plug event, or because the driver is going to be removed from 8988 * memory. 8989 **/ 8990 static void ixgbe_remove(struct pci_dev *pdev) 8991 { 8992 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8993 struct net_device *netdev; 8994 bool disable_dev; 8995 8996 /* if !adapter then we already cleaned up in probe */ 8997 if (!adapter) 8998 return; 8999 9000 netdev = adapter->netdev; 9001 ixgbe_dbg_adapter_exit(adapter); 9002 9003 set_bit(__IXGBE_REMOVING, &adapter->state); 9004 cancel_work_sync(&adapter->service_task); 9005 9006 9007 #ifdef CONFIG_IXGBE_DCA 9008 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 9009 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 9010 dca_remove_requester(&pdev->dev); 9011 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 9012 } 9013 9014 #endif 9015 #ifdef CONFIG_IXGBE_HWMON 9016 ixgbe_sysfs_exit(adapter); 9017 #endif /* CONFIG_IXGBE_HWMON */ 9018 9019 /* remove the added san mac */ 9020 ixgbe_del_sanmac_netdev(netdev); 9021 9022 if (netdev->reg_state == NETREG_REGISTERED) 9023 unregister_netdev(netdev); 9024 9025 #ifdef CONFIG_PCI_IOV 9026 ixgbe_disable_sriov(adapter); 9027 #endif 9028 ixgbe_clear_interrupt_scheme(adapter); 9029 9030 ixgbe_release_hw_control(adapter); 9031 9032 #ifdef CONFIG_DCB 9033 kfree(adapter->ixgbe_ieee_pfc); 9034 kfree(adapter->ixgbe_ieee_ets); 9035 9036 #endif 9037 iounmap(adapter->io_addr); 9038 pci_release_selected_regions(pdev, pci_select_bars(pdev, 9039 IORESOURCE_MEM)); 9040 9041 e_dev_info("complete\n"); 9042 9043 kfree(adapter->mac_table); 9044 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 9045 free_netdev(netdev); 9046 9047 pci_disable_pcie_error_reporting(pdev); 9048 9049 if (disable_dev) 9050 pci_disable_device(pdev); 9051 } 9052 9053 /** 9054 * ixgbe_io_error_detected - called when PCI error is detected 9055 * @pdev: Pointer to PCI device 9056 * @state: The current pci connection state 9057 * 9058 * This function is called after a PCI bus error affecting 9059 * this device has been detected. 9060 */ 9061 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 9062 pci_channel_state_t state) 9063 { 9064 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9065 struct net_device *netdev = adapter->netdev; 9066 9067 #ifdef CONFIG_PCI_IOV 9068 struct ixgbe_hw *hw = &adapter->hw; 9069 struct pci_dev *bdev, *vfdev; 9070 u32 dw0, dw1, dw2, dw3; 9071 int vf, pos; 9072 u16 req_id, pf_func; 9073 9074 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 9075 adapter->num_vfs == 0) 9076 goto skip_bad_vf_detection; 9077 9078 bdev = pdev->bus->self; 9079 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 9080 bdev = bdev->bus->self; 9081 9082 if (!bdev) 9083 goto skip_bad_vf_detection; 9084 9085 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 9086 if (!pos) 9087 goto skip_bad_vf_detection; 9088 9089 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 9090 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 9091 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 9092 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 9093 if (ixgbe_removed(hw->hw_addr)) 9094 goto skip_bad_vf_detection; 9095 9096 req_id = dw1 >> 16; 9097 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 9098 if (!(req_id & 0x0080)) 9099 goto skip_bad_vf_detection; 9100 9101 pf_func = req_id & 0x01; 9102 if ((pf_func & 1) == (pdev->devfn & 1)) { 9103 unsigned int device_id; 9104 9105 vf = (req_id & 0x7F) >> 1; 9106 e_dev_err("VF %d has caused a PCIe error\n", vf); 9107 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 9108 "%8.8x\tdw3: %8.8x\n", 9109 dw0, dw1, dw2, dw3); 9110 switch (adapter->hw.mac.type) { 9111 case ixgbe_mac_82599EB: 9112 device_id = IXGBE_82599_VF_DEVICE_ID; 9113 break; 9114 case ixgbe_mac_X540: 9115 device_id = IXGBE_X540_VF_DEVICE_ID; 9116 break; 9117 case ixgbe_mac_X550: 9118 device_id = IXGBE_DEV_ID_X550_VF; 9119 break; 9120 case ixgbe_mac_X550EM_x: 9121 device_id = IXGBE_DEV_ID_X550EM_X_VF; 9122 break; 9123 default: 9124 device_id = 0; 9125 break; 9126 } 9127 9128 /* Find the pci device of the offending VF */ 9129 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 9130 while (vfdev) { 9131 if (vfdev->devfn == (req_id & 0xFF)) 9132 break; 9133 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 9134 device_id, vfdev); 9135 } 9136 /* 9137 * There's a slim chance the VF could have been hot plugged, 9138 * so if it is no longer present we don't need to issue the 9139 * VFLR. Just clean up the AER in that case. 9140 */ 9141 if (vfdev) { 9142 ixgbe_issue_vf_flr(adapter, vfdev); 9143 /* Free device reference count */ 9144 pci_dev_put(vfdev); 9145 } 9146 9147 pci_cleanup_aer_uncorrect_error_status(pdev); 9148 } 9149 9150 /* 9151 * Even though the error may have occurred on the other port 9152 * we still need to increment the vf error reference count for 9153 * both ports because the I/O resume function will be called 9154 * for both of them. 9155 */ 9156 adapter->vferr_refcount++; 9157 9158 return PCI_ERS_RESULT_RECOVERED; 9159 9160 skip_bad_vf_detection: 9161 #endif /* CONFIG_PCI_IOV */ 9162 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 9163 return PCI_ERS_RESULT_DISCONNECT; 9164 9165 rtnl_lock(); 9166 netif_device_detach(netdev); 9167 9168 if (state == pci_channel_io_perm_failure) { 9169 rtnl_unlock(); 9170 return PCI_ERS_RESULT_DISCONNECT; 9171 } 9172 9173 if (netif_running(netdev)) 9174 ixgbe_down(adapter); 9175 9176 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 9177 pci_disable_device(pdev); 9178 rtnl_unlock(); 9179 9180 /* Request a slot reset. */ 9181 return PCI_ERS_RESULT_NEED_RESET; 9182 } 9183 9184 /** 9185 * ixgbe_io_slot_reset - called after the pci bus has been reset. 9186 * @pdev: Pointer to PCI device 9187 * 9188 * Restart the card from scratch, as if from a cold-boot. 9189 */ 9190 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 9191 { 9192 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9193 pci_ers_result_t result; 9194 int err; 9195 9196 if (pci_enable_device_mem(pdev)) { 9197 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 9198 result = PCI_ERS_RESULT_DISCONNECT; 9199 } else { 9200 smp_mb__before_atomic(); 9201 clear_bit(__IXGBE_DISABLED, &adapter->state); 9202 adapter->hw.hw_addr = adapter->io_addr; 9203 pci_set_master(pdev); 9204 pci_restore_state(pdev); 9205 pci_save_state(pdev); 9206 9207 pci_wake_from_d3(pdev, false); 9208 9209 ixgbe_reset(adapter); 9210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 9211 result = PCI_ERS_RESULT_RECOVERED; 9212 } 9213 9214 err = pci_cleanup_aer_uncorrect_error_status(pdev); 9215 if (err) { 9216 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 9217 "failed 0x%0x\n", err); 9218 /* non-fatal, continue */ 9219 } 9220 9221 return result; 9222 } 9223 9224 /** 9225 * ixgbe_io_resume - called when traffic can start flowing again. 9226 * @pdev: Pointer to PCI device 9227 * 9228 * This callback is called when the error recovery driver tells us that 9229 * its OK to resume normal operation. 9230 */ 9231 static void ixgbe_io_resume(struct pci_dev *pdev) 9232 { 9233 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9234 struct net_device *netdev = adapter->netdev; 9235 9236 #ifdef CONFIG_PCI_IOV 9237 if (adapter->vferr_refcount) { 9238 e_info(drv, "Resuming after VF err\n"); 9239 adapter->vferr_refcount--; 9240 return; 9241 } 9242 9243 #endif 9244 if (netif_running(netdev)) 9245 ixgbe_up(adapter); 9246 9247 netif_device_attach(netdev); 9248 } 9249 9250 static const struct pci_error_handlers ixgbe_err_handler = { 9251 .error_detected = ixgbe_io_error_detected, 9252 .slot_reset = ixgbe_io_slot_reset, 9253 .resume = ixgbe_io_resume, 9254 }; 9255 9256 static struct pci_driver ixgbe_driver = { 9257 .name = ixgbe_driver_name, 9258 .id_table = ixgbe_pci_tbl, 9259 .probe = ixgbe_probe, 9260 .remove = ixgbe_remove, 9261 #ifdef CONFIG_PM 9262 .suspend = ixgbe_suspend, 9263 .resume = ixgbe_resume, 9264 #endif 9265 .shutdown = ixgbe_shutdown, 9266 .sriov_configure = ixgbe_pci_sriov_configure, 9267 .err_handler = &ixgbe_err_handler 9268 }; 9269 9270 /** 9271 * ixgbe_init_module - Driver Registration Routine 9272 * 9273 * ixgbe_init_module is the first routine called when the driver is 9274 * loaded. All it does is register with the PCI subsystem. 9275 **/ 9276 static int __init ixgbe_init_module(void) 9277 { 9278 int ret; 9279 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 9280 pr_info("%s\n", ixgbe_copyright); 9281 9282 ixgbe_dbg_init(); 9283 9284 ret = pci_register_driver(&ixgbe_driver); 9285 if (ret) { 9286 ixgbe_dbg_exit(); 9287 return ret; 9288 } 9289 9290 #ifdef CONFIG_IXGBE_DCA 9291 dca_register_notify(&dca_notifier); 9292 #endif 9293 9294 return 0; 9295 } 9296 9297 module_init(ixgbe_init_module); 9298 9299 /** 9300 * ixgbe_exit_module - Driver Exit Cleanup Routine 9301 * 9302 * ixgbe_exit_module is called just before the driver is removed 9303 * from memory. 9304 **/ 9305 static void __exit ixgbe_exit_module(void) 9306 { 9307 #ifdef CONFIG_IXGBE_DCA 9308 dca_unregister_notify(&dca_notifier); 9309 #endif 9310 pci_unregister_driver(&ixgbe_driver); 9311 9312 ixgbe_dbg_exit(); 9313 } 9314 9315 #ifdef CONFIG_IXGBE_DCA 9316 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 9317 void *p) 9318 { 9319 int ret_val; 9320 9321 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 9322 __ixgbe_notify_dca); 9323 9324 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 9325 } 9326 9327 #endif /* CONFIG_IXGBE_DCA */ 9328 9329 module_exit(ixgbe_exit_module); 9330 9331 /* ixgbe_main.c */ 9332